WO2022209561A1

WO2022209561A1 - Frequency dividing circuit

Info

Publication number: WO2022209561A1
Application number: PCT/JP2022/009164
Authority: WO
Inventors: 暁新家; 慧吉澤
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2021-03-31
Filing date: 2022-03-03
Publication date: 2022-10-06
Also published as: JPWO2022209561A1

Abstract

[Problem] To achieve frequency division with respect to an analog signal. [Solution] This frequency dividing circuit is provided with an inverter and an input circuit. The inverter includes a transistor. The input circuit converts a first signal, which is an analog differential signal, to a second signal which is a differential analog signal for driving the transistor.

Description

frequency divider

The present disclosure relates to a frequency dividing circuit.

A frequency divider is a circuit that converts a high-frequency signal into a low-frequency signal, and is widely used in electronic devices that use high-frequency signals. For example, it is widely used for processing high-frequency received signals in wireless communication, and for processing clock signals in processors such as CPUs (Central Processing Units).

Generally, the clock signal of the frequency divider is a square wave (digital signal). Therefore, when a clock signal is oscillated by a sine wave oscillator, a buffer amplifier is required to convert the sine wave into a rectangular wave. However, there is a desire to reduce the power consumption of various circuits and to reduce the circuit area, and in some cases it is not preferable to install a buffer amplifier.

Japanese Patent Publication No. 2012-503443 WO 10/134257 JP 2019-180000

Therefore, the present disclosure provides a frequency divider circuit that can handle analog signals.

According to one embodiment, the divider circuit includes an inverter and an input circuit. The inverter has a transistor. The input circuit converts a first signal, which is an analog differential signal, into a second signal, which is a differential analog signal for driving the transistors.

The transistor may be a MOSFET, and the input circuit superimposes a bias voltage on the AC component of the first signal to obtain a voltage lower than the threshold voltage of the transistor and a threshold voltage of the transistor. may be converted to the second signal oscillating between a voltage higher than .

The inverter may include an nMOS and a pMOS, and the input circuit may include a signal obtained by superimposing a threshold voltage of the nMOS and an AC component of the differential signal, and a threshold voltage of the pMOS. A signal obtained by superimposing a voltage and an AC component of the differential signal may be generated.

The input circuit includes a capacitor for extracting an AC component of a first differential signal, which is one of the signals forming the differential signal, and an AC component of a second differential signal, which is the other signal forming the differential signal. and a capacitor for extracting the component.

A latch circuit may be further provided.

The inverter is a first transistor, which is a p-type MOSFET and whose source is connected to a positive power supply voltage; a second transistor, which is a p-type MOSFET and whose source is connected to the drain of the first transistor; a third transistor, which is an n-type MOSFET and whose drain is connected to the drain of the second transistor; and an n-type MOSFET, whose drain is connected to the source of the third transistor and whose source is connected to the negative power supply voltage. a fourth transistor having a gate connected to the gate of the first transistor;
The latch circuit is a fifth transistor, a p-type MOSFET whose source is connected to the positive power supply voltage, and a p-type MOSFET whose source is connected to the positive power supply voltage and whose drain is the fifth transistor. a sixth transistor connected to the gate of the transistor, the gate of which is connected to the drain of the fifth transistor; and an n-type MOSFET, the drain of which is connected to the drain of the fifth transistor, and the source of which is the negative power supply voltage. and an n-type MOSFET, the drain of which is connected to the drain of the sixth transistor and the gate of the seventh transistor, the source of which is connected to the negative power supply voltage, and the gate of which is connected to the first an eighth transistor connected to the drain of the seven transistor;
The frequency dividing circuit includes a first inverter, a second inverter, a third inverter and a fourth inverter, a first latch circuit and a second latch circuit, a first output terminal, a second output terminal, a third output terminal and a third inverter. 4 output terminals, and
The first output terminal is connected to the gate of the first transistor of the first inverter, the drain of the second transistor of the fourth inverter, and the drain of the sixth transistor of the second latch circuit. , outputs the first output signal,
The second output terminal is connected to the gate of the first transistor of the second inverter, the drain of the second transistor of the third inverter, and the drain of the fifth transistor of the second latch circuit. , outputting a second output signal forming a differential signal with the first output signal;
The third output terminal is connected to the gate of the first transistor of the fourth inverter, the drain of the second transistor of the second inverter, and the drain of the sixth transistor of the first latch circuit. , outputting a third output signal having a predetermined phase shift from the first output signal,
The fourth output terminal is connected to the gate of the first transistor of the third inverter, the drain of the second transistor of the first inverter, and the drain of the fifth transistor of the first latch circuit. , may output a fourth output signal forming a differential signal with the third output signal.

The input circuit includes a first input terminal to which one of the first signals is input, a second input terminal to which the other of the first signals is input, the first input terminal, and the first inverter. and the gate of the second transistor of the third inverter; the second input terminal; and the second transistor of the second inverter. a second capacitor connected between a gate and a terminal connected to the gate of the second transistor of the fourth inverter; the first input terminal; and the gate of the third transistor of the first inverter. and a terminal connected to the gate of the third transistor of the third inverter; a third capacitor connected between the second input terminal; the gate of the third transistor of the second inverter; and a fourth capacitor connected between a terminal connected to the gate of the third transistor of the fourth inverter.

The input circuit includes: a first bias circuit that applies a first bias voltage to the output of the first capacitor; a second bias circuit that applies a second bias voltage to the output of the second capacitor; A third bias circuit that applies a third bias voltage to the output of the third capacitor, and a fourth bias circuit that applies a fourth bias voltage to the output of the fourth capacitor may be provided.

The first bias voltage and the second bias voltage may be threshold voltages of the second transistor, and the third bias voltage and the fourth bias voltage may be threshold voltages of the third transistor. may be

The input circuit may comprise a first steady voltage source connected to the positive power supply voltage and a second steady voltage source connected to the negative power supply voltage,
The first bias circuit may comprise the first steady voltage source and a first resistor connected to the first steady voltage source,
The second bias circuit may comprise the first steady voltage source and a second resistor connected to the first steady voltage source,
The third bias circuit may comprise the second steady voltage source and a third resistor connected to the second steady voltage source,
The fourth bias circuit may include the second constant voltage source and a fourth resistor connected to the second constant voltage source.

The voltages of the first bias circuit, the second bias circuit, the third bias circuit, and the fourth bias circuit may be variably controlled.

The first bias circuit, the second bias circuit, the third bias circuit, and the fourth bias circuit output currents depending on the fluctuation of at least one of the positive power supply voltage and the negative power supply voltage. may include at least one current source with a varying .

The current source may include a transistor whose gate is connected to the positive power supply voltage or the negative power supply voltage.

The current source may include a resistor connected to the positive power supply voltage or the negative power supply voltage.

A power gate transistor may be provided between the source of the fourth transistor, the source of the seventh transistor, the source of the eighth transistor, and the negative power supply voltage.

The predetermined phase may be π/2.

A signal may be generated by dividing the first signal by n (where n is an integer equal to or greater than 2).

FIG. 2 is a diagram showing a frequency dividing circuit according to one embodiment; FIG. 4 is a diagram showing a frequency divider according to one embodiment; 1 is a circuit diagram of an inverter according to one embodiment; FIG. FIG. 2 is a circuit diagram showing a frequency divider according to one embodiment using MOSFETs; 1 is a circuit diagram of an input circuit according to one embodiment; FIG. 4 is a timing chart of input/output signals of an input circuit according to one embodiment; 4 is a timing chart of input/output signals of the frequency divider according to one embodiment; 1 is a circuit diagram of an input circuit according to one embodiment; FIG. 1 is a circuit diagram of a frequency dividing circuit according to one embodiment; FIG. 1 is a circuit diagram of a frequency dividing circuit according to one embodiment; FIG. 1 is a circuit diagram of an input circuit according to one embodiment; FIG. 1 is a circuit diagram of an input circuit according to one embodiment; FIG. 1 is a circuit diagram of an input circuit according to one embodiment; FIG. 1 is a circuit diagram of an input circuit according to one embodiment; FIG. 1 is a circuit diagram of a current source according to one embodiment; FIG. 1 is a circuit diagram of a current source according to one embodiment; FIG. 1 is a circuit diagram of a current source according to one embodiment; FIG.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation, and it is not necessary that the shapes, sizes, ratios, etc. of the configuration of each part in the actual apparatus are as shown in the drawings. In addition, since the drawings are drawn in a simplified manner, it is assumed that configurations necessary for mounting other than those shown in the drawings are appropriately provided.

FIG. 1 is a diagram schematically showing an example of a frequency dividing circuit according to an embodiment of the present disclosure. A frequency dividing circuit 1 includes an input circuit 10 and a frequency dividing section 20 .

The input circuit 10 receives an analog differential signal IN (first signal) and converts the differential signal IN into an analog signal Vdr (second signal) for driving the transistors provided in the frequency divider 20. This is a circuit that outputs Hereinafter, differential signals may be denoted by adding + or - as appropriate. For example, the analog differential signals described above may be represented as signals IN+, IN-.

The frequency divider 20 outputs a digital signal obtained by frequency-dividing the differential signal IN. This frequency dividing section 20 may be a general frequency dividing circuit. As an example, the frequency dividing circuit 1 outputs a digital differential clock signal Q and a differential clock signal I having a predetermined phase shift from the clock signal Q from the frequency dividing unit 20 . For example, when the frequency divider 1 operates as a divide-by-two circuit, the differential clock signals Q+/Q- and the differential clock signals I+/I- shifted by π/2 from these signals are Output.

Fig. 2 is a schematic diagram showing an example of a general frequency divider circuit. Using FIG. 2, first, the frequency divider 20, which is a basic configuration, will be described.

In a general frequency dividing circuit, frequency-divided signals Q and I are output by inputting a digital differential clock signal Vdr to an inverter. However, this frequency dividing circuit requires a large amplitude when inputting a differential signal represented by an analog sine wave. In the present embodiment, the input circuit 10 generates an analog signal Vdr capable of appropriately driving the frequency divider 20 as a drive signal, and divides the sine wave differential signal IN.

A combination of two inverters between signals Q+ and Q- and a combination of two inverters between signals I+ and I- each form a latch circuit. With this latch circuit, it is possible to generate and output a differential signal in each combination even while the output from the inverter is stopped.

FIG. 3 is a circuit diagram showing the inverter circuit in FIG. 2 using MOSFETs. FIG. 3 is, for example, a circuit showing an inverter that receives the signal I+ and outputs the signal Q+ in FIG.

The inverter includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4.

The first transistor M1 is, for example, a pMOS, has a source connected to the positive power supply voltage Vdd, and a gate to which I+ is applied.

The second transistor M2 is, for example, a pMOS, has a source connected to the drain of the first transistor M1, and a gate to which Vdr- is applied.

The third transistor M3 is, for example, nMOS, its drain is connected to the drain of the second transistor M2, and Vdr+ is applied to its gate.

The fourth transistor M4 is, for example, an nMOS, has a drain connected to the source of the third transistor M3, a source connected to the negative power supply voltage Vss, and a gate connected to the gate of the first transistor M1.

The input signal is applied to the gate of the first transistor M1 and the gate of the fourth transistor M4. The output signal is output from the drain of the second transistor M2 and the drain of the third transistor M3.

The signal Q+ outputs a value that is the negation of the signal I+ at the timing when the second transistor M2 and the third transistor M3 are driven.

The driving signals Vdr+/Vdr- are analog signals each having a value that crosses the threshold values of the second transistor M2 and the third transistor M3. In the frequency dividing circuit 1 according to the present embodiment, the input circuit 10 controls the analog differential signal IN such that the drive signal appropriately oscillates based on the threshold of each transistor.

The power supply voltage is described as positive and negative, but this can be understood as general power supply voltages Vdd and Vss. For example, more generally, the negative power supply voltage Vss may be connected to a ground point.

The order of each transistor is not limited to the above. For example, the positive power supply voltage Vdd is connected to the second transistor M2, the first transistor M1, the fourth transistor M4, and the third transistor M3, and the source of the third transistor M3 is connected to the negative power supply voltage Vss. There may be.

FIG. 4 is a diagram in which the configuration of the frequency divider 20 is rewritten using MOSFETs using the configuration of the inverter in FIG. The latch circuit is similarly rewritten with MOSFET.

As shown in FIG. 4, the frequency divider 20 according to the present embodiment includes a first inverter 200, a second inverter 202, a third inverter 204, a fourth inverter 206, a first latch circuit 210, a first 2 latch circuit 212; When the analog signals Vn and Vp are input, the frequency divider 20 generates and outputs frequency-divided signals I and Q based on the frequencies of the analog signals. The analog signals Vn and Vp are signals generated by the input circuit 10 based on the analog differential signal IN. The generation of this signal will be described later in detail.

The first inverter 200 includes a first transistor M11, a second transistor M12, a third transistor M13, and a fourth transistor M14, which are connected in the same manner as in FIG. Similarly, the second inverter 202 comprises a first transistor M21, a second transistor M22, a third transistor M23 and a fourth transistor M24. The third inverter 204 includes a first transistor M31, a second transistor M32, a third transistor M33, and a fourth transistor M34. The fourth inverter 206 includes a first transistor M41, a second transistor M42, a third transistor M43, and a fourth transistor M44.

The latch circuit includes pMOS fifth and sixth transistors, and nMOS seventh and eighth transistors. The fifth transistor has a source connected to the positive power supply voltage Vdd. The sixth transistor has a source connected to the positive power supply voltage Vdd, a drain connected to the gate of the fifth transistor, and a gate connected to the drain of the fifth transistor. The seventh transistor has a source connected to the negative power supply voltage Vss and a drain connected to the drain of the fifth transistor. The eighth transistor has a source connected to the negative power supply voltage Vss, a drain connected to the drain of the sixth transistor and the gate of the seventh transistor, and a gate connected to the drain of the seventh transistor. By adopting such a form, the outputs from the drains of the fifth and seventh transistors and the outputs from the drains of the sixth and eighth transistors have inverted values regardless of the clock signal.

The connection of each transistor in Fig. 4 will be explained based on the connection in Fig. 2. The first inverter 200, the second inverter 202, the third inverter 204, and the fourth inverter 206 correspond to the inverters positioned at the lower left, upper left, lower right, and upper right of FIG. 2, respectively. The first latch circuit and the second latch circuit correspond to the latch circuits located on the left and right sides of FIG. 2, respectively.

The connection in Fig. 4 will be explained.

Vp-, Vp+, Vn-, and Vn+ are signals obtained by superimposing a bias voltage on the AC component of the analog differential signal to be divided, and are signals output from the input circuit 10 . Q+, Q-, I+, and I- are frequency-divided clock signals that are outputs of the frequency divider circuit 1, as described above. Here, for convenience, the terminal that outputs Q+ is the first output terminal, the terminal that outputs Q- is the second output terminal, the terminal that outputs I+ is the third output terminal, and the terminal that outputs I- is the fourth output terminal. call. In the context of communications, Q and I are concepts that may need to be distinguished, but in this disclosure, they are only used as symbols, and the names of signals in particular are restricted. is not. However, Q+ and Q-, and I+ and I- each constitute a differential signal.

The first output terminal is the drain of the second transistor M42 and the drain of the third transistor M43 of the fourth inverter 206, the gate of the first transistor M11 and the gate of the fourth transistor M14 of the first inverter 200, and the second latch circuit. 212 is connected to the drain of the sixth transistor M26 and the drain of the eighth transistor M28. Based on the input Vp- and Vn+ signals, the Q+ signal output from the fourth inverter 206 is input to the first inverter 200 and the second latch circuit 212, and is output via the first output terminal. be done. When the second transistor M42 and the third transistor M43 of the fourth inverter 206 are turned off by the signals of Vp- and Vn+, the signal of Q+ held in the second latch circuit 212 is output.

The second output terminal is the drain of the second transistor M32 and the drain of the third transistor M33 of the third inverter 204, the gate of the first transistor M21 and the gate of the fourth transistor M24 of the second inverter 202, and the second latch circuit. 212 is connected to the drain of the fifth transistor M25 and the drain of the seventh transistor M27. Based on the input Vp- and Vn+ signals, the Q- signal output from the third inverter 204 is input to the second inverter 202 and the second latch circuit 212 and via the second output terminal. output. When the second transistor M32 and the third transistor M33 of the third inverter 204 are turned off by the signals of Vp- and Vn+, the signal of Q- held in the second latch circuit 212 is output.

The third output terminal is the drain of the second transistor M22 and the drain of the third transistor M23 of the second inverter 202, the gate of the first transistor M41 and the gate of the fourth transistor M44 of the fourth inverter 206, and the first latch circuit. 210 is connected to the drain of the sixth transistor M16 and the drain of the eighth transistor M18. Based on the input Vp+ and Vn- signals, the I+ signal output from the second inverter 202 is input to the fourth inverter 206 and the first latch circuit 210, and is output via the third output terminal. be done. When the second transistor M22 and the third transistor M23 of the second inverter 202 are turned off by the signals of Vp+ and Vn-, the signal of I+ held in the first latch circuit 210 is output.

The fourth output terminal is the drain of the second transistor M12 and the drain of the third transistor M13 of the first inverter 200, the gate of the first transistor M31 and the gate of the fourth transistor M34 of the third inverter 204, and the first latch circuit. 210 is connected to the drain of the fifth transistor M15 and the drain of the seventh transistor M17. Based on the input Vp+ and Vn- signals, the I- signal output from the first inverter 200 is input to the third inverter 204 and the first latch circuit 210, and through the fourth output terminal. output. When the second transistor M12 and the third transistor M13 of the second inverter 202 are turned off by the signals of Vp+ and Vn-, the signal of I- held in the first latch circuit 210 is output.

Thus, the frequency divider 20 is controlled by the input signals Vp-, Vp+ and Vn-, Vn+.

Vp- is a signal whose voltage value oscillates across the threshold voltages of the second transistor M32 of the third inverter 204 and the second transistor M42 of the fourth inverter 206. Vp+ is a signal whose voltage value oscillates across the threshold voltages of the second transistor M12 of the first inverter 200 and the second transistor M22 of the second inverter 202. FIG. The alternating components of Vp- and Vp+ constitute a differential signal. If the second transistor Mx2 in each inverter is the same element, for example, Vp− and Vp+ are generated as signals obtained by superimposing the threshold voltage of the second transistor Mx2 on the AC component of the differential clock signal.

Vn- is a signal whose voltage value oscillates across the threshold voltages of the third transistor M13 of the first inverter 200 and the third transistor M23 of the second inverter 202. Vn+ is a signal whose voltage value oscillates across the threshold voltages of the third transistor M33 of the third inverter 204 and the third transistor M43 of the fourth inverter 206. FIG. The alternating components of Vn- and Vn+ constitute a differential signal. If the third transistor Mx3 in each inverter is the same element, for example, Vn− and Vn+ are generated as signals obtained by superimposing the threshold voltage of the third transistor Mx3 on the AC component of the differential clock signal.

Note that the form in the present disclosure is not limited to the form of FIG. 4, and other general frequency dividing circuit inverters, latch circuits, etc. can be used as long as they are circuits that can be appropriately divided by analog drive signals. can also be used as the frequency divider 20.

In the embodiment of the present disclosure, the input circuit 10 appropriately generates these analog AC signals Vn-, Vn+, Vp-, and Vp+, so that the analog signal is converted through a buffer for A/D conversion. A divided signal can be obtained without Several specific embodiments of the input circuit 10 are described below.

(First embodiment)
FIG. 5 is a diagram showing an example of the input circuit 10. As shown in FIG. The input circuit 10 includes capacitors C1, C2, C3, C4, constant voltage sources E1, E2, and resistors R1, R2, R3, R4. The input circuit 10 has, as input terminals, a first input terminal to which an analog signal IN+ is applied, and a second input terminal to which an analog signal IN- is applied.

The first input terminal is connected to the positive power supply voltage Vdd via a capacitor C1, a resistor R1, and a constant voltage source E1. The positive power supply voltage is controlled to at least the threshold voltage (first bias voltage) of the second transistors M12 and M22 of the first inverter 200 and the second inverter 202 via the constant voltage source E1 and the resistor R1. The analog signal IN+ has its AC component extracted through the capacitor C1, and this AC component is the positive power supply voltage Vdd, the constant voltage source E1, the second transistor M12 which is the first bias voltage generated by the resistor R1, Superimposed on the threshold voltage of M22. Therefore, the input circuit 10 outputs, as Vp+, a signal in which the threshold voltages of the second transistors M12 and M22 and the AC component of the input analog signal IN+ are superimposed.

Also, the first input terminal is connected to the negative power supply voltage Vss via a capacitor C2, a resistor R2, and a constant voltage source E2. The negative power supply voltage is controlled at least to the threshold voltage (second bias voltage) of the third transistors M33 and M43 of the third inverter 204 and the fourth inverter 206 via the constant voltage source E2 and the resistor R2. The AC component of the signal IN+ is extracted through the capacitor C2, and this AC component is the negative power supply voltage Vss, the constant voltage source E2, and the third transistors M33 and M43, which are the second bias voltage generated by the resistor R2. is superimposed with the threshold voltage of Therefore, the input circuit 10 outputs, as Vn-, a signal in which the threshold voltages of the third transistors M33 and M34 and the AC component of the input analog signal IN+ are superimposed.

The second input terminal is connected to the negative power supply voltage Vss via a capacitor C3, a resistor R3, and a constant voltage source E2. The negative power supply voltage is controlled at least to the threshold voltage (third bias voltage) of the third transistors M13 and M23 of the first inverter 200 and the second inverter 202 via the constant voltage source E3 and the resistor R3. The AC component of the signal IN- is extracted through the capacitor C3, and this AC component is the negative power supply voltage Vss, the constant voltage source E3, and the third transistor M13, which is the third bias voltage generated by the resistor R3. Superimposed on the threshold voltage of M23. Therefore, the input circuit 10 outputs, as Vn+, a signal in which the threshold voltages of the third transistors M13 and M23 and the AC component of the input analog signal IN- are superimposed.

Also, the second input terminal is connected to the positive power supply voltage Vdd via a capacitor C4, a resistor R4, and a constant voltage source E1. The positive power supply voltage is controlled to at least the threshold voltage (fourth bias voltage) of the second transistors M32 and M42 of the third inverter 204 and the fourth inverter 206 via the constant voltage source E1 and the resistor R4. The signal IN- has its AC component extracted through the capacitor C4, and this AC component is the positive power supply voltage Vdd, the constant voltage source E1, the fourth bias voltage generated by the resistor R4, the second transistor M32, Superimposed on the threshold voltage of M42. Therefore, the input circuit 10 outputs, as Vp-, a signal in which the threshold voltages of the second transistors M32, M32 and the AC component of the input analog signal IN- are superimposed.

Preferably, the second transistor Mx2 of each inverter uses the same element, and similarly the third transistor Mx3 of each inverter uses the same element. In this preferred form, Vdd - E1 is the threshold voltage of the second transistor and E2 is the threshold voltage of the third transistor. Then, each resistor controls so that the AC component is not propagated to the power supply side. In this case, the first bias voltage and the fourth bias voltage have the same value, and the second bias voltage and the third bias voltage have the same value.

The circuits that generate the bias voltages may be separately provided with, for example, first to fourth bias circuits that generate the first to fourth bias voltages. In another preferred example of the above, it is sufficient to be able to generate a first bias voltage and a second bias, in which case a first bias circuit and a second bias circuit may be provided.

Also, it is desirable that the respective bias voltages and threshold voltages are equal, but this is not the only option. A similar division can be achieved if the value is sufficiently close to the threshold voltage.

FIG. 6 is a timing chart of IN, Vp, and Vn, which are the input/output signals of the input circuit 10. FIG. As shown in FIG. 6, Vn+/- is a signal obtained by increasing the AC component of IN+/- by E2, ie, the threshold voltage of the third transistor. Similarly, Vp+/- is the AC component of IN+/- biased by Vdd-E1, the threshold voltage of the second transistor.

7 is a timing chart of Vp, Vn, Q, and I, which are the input/output signals of the frequency divider 20. FIG. As shown in this figure, Q+, I+, Q-, and I- are converted to a clock signal with a cycle twice that of the original analog signal IN with a phase shift of π/2 for signals Vn and Vp. I know it's done.

As described above, according to this embodiment, the analog signal oscillated by the oscillator can be output as a frequency-divided digital clock signal without undergoing digital conversion before frequency division. This circuit simply adds capacitors and resistors to the conventional divider circuit for analog signals. For this reason, a conversion buffer or the like for converting from analog to digital is not required, so that the area of the circuit and the power consumption can be reduced.

(Second embodiment)
FIG. 8 is a diagram showing another example of the input circuit 10. As shown in FIG. As shown in this figure, instead of the constant voltage sources E1 and E2 used in the input circuit 10, a power source with a variable voltage can be used.

In this embodiment, instead of the constant voltage source of the previous embodiment, variable transistors T1 and T2 are used to make the bias voltage superimposed on IN variable. The current of the constant current source is output by the current mirror circuit arranged on the left side. The gate potential of this current mirror is the same as the gate potential of the variable transistor T1. Therefore, by forming a current mirror together with the variable transistor T1 and changing the element coefficient of the variable transistor T1, the magnification of the output current can be changed. By connecting this output to the positive power supply voltage Vdd via a capacitor, it changes to a variable voltage. This voltage is converted to an appropriate voltage by a diode-connected transistor and superimposed on the AC component output from the input-side capacitor through the corresponding resistors to generate the signal Vn.

The current of the current mirror located on the right is further mirrored in the current mirror circuit located in the next stage. Here, the magnification of the left current mirror can be changed by changing the element coefficient of the variable transistor T2. After that, the signal Vp is generated by the same operation as the operation on the Vn side described above.

As described above, according to this embodiment, it is possible to appropriately change the voltage value superimposed on the AC component of the clock signal. Depending on the performance of the MOSFET in a high frequency band, it may not be able to follow the performance when the gate-source voltage becomes larger or smaller than the threshold voltage. In such a case, stable performance may be obtained by making the voltage value superimposed on the clock signal larger (nMOS) or smaller (pMOS) than the threshold voltage. By controlling the voltage of the signal superimposed in the input circuit 10 with a variable transistor, it becomes possible to deal with clock signals of various frequencies, and in the frequency band in which control can be performed according to the threshold voltage, power consumption can be reduced. It is possible to prevent power from being raised.

Also, if the same elements are used for the same transistors in each inverter, there may be differences between wafers due to process variations. Due to such individual differences, if the constant voltage source is used as the threshold voltage as in the first embodiment, the frequency division operation may not be appropriate. Even in such a case, if the bias voltage can be controlled as in the present embodiment, appropriate frequency division can be achieved regardless of individual differences. Also, even when the coefficient of the element changes due to temperature change, etc., it is possible to realize appropriate frequency division by appropriately controlling the bias voltage.

(Third Embodiment)
FIG. 9 is a diagram showing a frequency dividing circuit 1 in which a power gate is provided in the frequency dividing section 20. As shown in FIG. The transistor T3 has a source connected to the negative power supply voltage Vss, a drain connected to the sources of the fourth transistor of each inverter and the seventh and eighth transistors of each latch circuit, and an enable signal input to its gate. . That is, transistors other than the transistor T3 of the frequency divider 20 are connected to the negative power supply voltage Vss via the transistor T3.

The enable signal EN turns on/off the connection between the frequency divider 20 and the power supply circuit. This makes it possible to stop the function of the frequency dividing circuit 1 when frequency division is not necessary.

Although only the transistor T3 is provided as a power gate in FIG. 9, it is not limited to this, and a plurality of transistors may be provided in parallel with the transistor T3 as power gates.

As described above, according to the present embodiment, by providing a transistor that functions as a power gate, it is possible to suppress leakage current and reduce power consumption when the frequency divider circuit 1 is not in operation.

It should be noted that this embodiment may be used alone or in combination with other embodiments. For example, in the second embodiment described above and each embodiment described later, a power gate can be provided, and the above effects can be obtained.

(Fourth embodiment)
FIG. 10 shows a frequency dividing circuit 1 that summarizes the control of inverters by clock signals. As shown in FIG. 10, the first inverter 200 and the second inverter 202 may share the second transistor M12 and the third transistor M13. Similarly, the third inverter 204 and the fourth inverter 206 may also share the second transistor M32 and the third transistor M33.

In this way, by sharing the transistors to which the signals Vp+/Vp- and Vn+/Vn- are input, the operation can be made faster.

(Fifth embodiment)
When the input circuit 10 of FIG. 8 is used, each inverter is not affected by power supply voltage fluctuations, but each latch circuit is affected by power supply voltage fluctuations. In this embodiment, as compared with the input circuit 10 of FIG. 8, a circuit that is less likely to be affected by the power supply voltage as the overall frequency dividing circuit 1 will be described.

FIG. 11 is a circuit diagram showing the input circuit 10 according to this embodiment. The input circuit 10 includes transistors T4 and T5, to whose gates a power supply voltage is applied, between the current mirror circuit and the transistor that superimposes a DC component on the clock signal. These two transistors T4 and T5 have their drain currents flow according to the power supply voltage, so the bias voltage is also affected by fluctuations in the power supply voltage.

Specifically, the transistor T4 is, for example, a pMOS, has a source connected to the positive power supply voltage Vdd, a drain connected to the drain of the transistor T1, and a gate connected to the negative power supply voltage Vss. By connecting the gate to the negative power supply voltage Vss, the transistor T4 operates as a diode that allows a current to flow in one direction from the source to the drain. The performance of this diode depends on the power supply voltage due to the source and gate connections.

Similarly, the transistor T5 is, for example, an nMOS, has a source connected to the negative power supply voltage Vss, a drain connected to the drain of the transistor T2, and a gate connected to the positive power supply voltage Vdd. By connecting the gate to the positive power supply voltage Vdd, the transistor T5 operates as a diode that allows a current to flow in one direction from the drain to the source. The performance of this diode depends on the power supply voltage due to the source and gate connections.

By setting the bias voltage in the input circuit 10 to be affected by fluctuations in the power supply voltage, the superimposed signal output from the input circuit 10 is affected by the power supply voltage. Since the output of the input circuit 10 becomes the driving voltage of the inverters in the frequency dividing section 20, each inverter is driven under the influence of fluctuations in the power supply voltage.

As described above, according to the input circuit 10 according to the present embodiment, the driving of each circuit in the frequency dividing section 20 is changed with fluctuations in the power supply voltage. That is, both the inverter and the latch circuit in the frequency dividing section 20 are affected by the fluctuation of the power supply voltage to the same degree. As a result, it is possible to increase the resistance of the frequency dividing circuit 1 to fluctuations in the power supply voltage, and to realize more stable operation even when the power supply voltage fluctuates.

For example, if the state of the inverter transistor in the frequency dividing unit 20 is SS, the capability of the latch circuit transistor becomes higher than the capability of the inverter transistor when the temperature is low and the power supply voltage is at a high potential. For this reason, in the inverter circuit, it is necessary to apply a potential that reverses the on/off state of the latch circuit. However, if the drive capability of the inverter circuit is insufficient, it becomes difficult to divide the frequency with a small input amplitude. .

Conversely, if the state of the inverter transistor is FF, the ability of the transistor in the latch circuit is reduced when the temperature is high and the power supply voltage is low, making it difficult to retain the state in the latch circuit. Become. In this case as well, it becomes difficult to divide the frequency at a small input amplitude.

As in the present embodiment, by varying the bias voltage for driving the inverter in the same manner as the power supply voltage on which the latch circuit depends, the inverter and the latch circuit can be controlled even when there is such variation in the power supply voltage. can be operated appropriately, and the operation of the frequency dividing circuit 1 can be stabilized.

(Sixth embodiment)
As a modification of the fifth embodiment described above, a general form in which a circuit that generates a bias voltage depends on voltage fluctuations will be described.

FIG. 12 is a circuit diagram of the input circuit 10 according to this embodiment. The input circuit 10 comprises current sources Id1, Id2 for generating bias voltages. The current sources Id1 and Id2 are current sources that depend on the power supply voltage (they are easily affected by the power supply voltage). For example, it can be seen from the operation of the transistors T4 and T5 in the circuit of FIG. 11 that the input circuit 10 shown in FIG. 11 is an example of the input circuit 10 shown in FIG.

FIG. 13 is a circuit diagram of another example of the input circuit 10 according to this embodiment. The input circuit 10 comprises current sources Id1, Id2 for generating bias voltages, and also current sources Ii1, Ii2. Each of the current sources Ii1 and Ii2 is a current source that does not depend on the power supply voltage (is not easily affected by the power supply voltage). By providing such current sources Ii1 and Ii2, it is possible to control the magnitude of the influence of the power supply voltage on the bias voltage.

FIG. 14 is another example of the input circuit 10 shown in FIG. In addition to current sources Id1, Id2, Ii1 and Ii2, current sources Id3 and Id4 dependent on the power supply voltage and power currents Ii3 and Ii4 independent of the power supply voltage are provided.

In the form of FIG. 14, current sources Id1 and Ii1 are used to generate the bias voltage that generates Vn+. Current sources Id2, Ii2 are used to generate bias voltages that generate Vp+. Power currents Id3, Ii3 are used to generate the bias voltages that generate Vn-. Current sources Id4, Ii4 are used to generate bias voltages that generate Vp-. In each of the above-described embodiments, two types of bias voltages were generated, one for generating Vn+ and Vn-, and the other for generating Vp+ and Vp-. A bias voltage may be generated for each signal output by the input circuit 10 to drive.

FIG. 15 is a diagram showing an example of a current source that depends on the power supply voltage. Shown on the left is the current source for generating the bias voltage for Vn. This is similar to the example shown in FIG. 11, and is configured using a pMOS whose source is connected to the positive power supply voltage Vdd and whose gate is connected to the negative power supply voltage Vss.

Shown on the right is the current source for generating the bias voltage for Vp. This is also the same as the example shown in FIG. 11, and is configured using an nMOS whose source is connected to the negative power supply voltage Vss and whose gate is connected to the positive power supply voltage Vdd.

FIG. 16 is a diagram showing another example of a current source that depends on the power supply voltage. The MOSFETs in FIG. 15 can also be more simply replaced with resistors. As in the case of FIG. 15, it is necessary to increase the circuit area while the structure is simple and the process is simple. Therefore, either one can be appropriately selected according to the purpose.

FIG. 17 is a diagram showing an example of a power flow that does not depend on the power supply voltage. The input circuit 10 may include a circuit using a BGR (Bandgap reference) and two current mirrors as a current source Ii1 or the like that does not depend on the power supply voltage. The BGR is a voltage source that is less dependent on the power supply voltage, and by using the voltage generated from this BGR as an input to the current mirror, a current that is less dependent on the power supply voltage is generated.

More specifically, in the current mirror on the left, the gate voltage is generated by BGR. As a result, the drain current becomes less dependent on the power supply voltage, and this current is mirrored. Since the current that generates the bias voltage on the Vp side is generated based on the current generated by this current mirror, it is a small current that depends on the power supply voltage.

The current generated by the left current mirror becomes the input of the right current mirror. Therefore, it is possible to duplicate a small current that depends on the power supply voltage also from the right current mirror. This generated current generates a bias voltage on the Vn side. Therefore, the current for generating the bias voltage on the Vn side is a small current that depends on the power supply voltage.

As described above, according to the present embodiment, by using at least one current source that depends on the power supply voltage to generate the bias voltages for both p/n, the inverter and the latch circuit in the frequency divider 20 voltage dependence can be reduced. By generating the bias voltage in this way, the input circuit 10 can generate an analog signal with improved stability against fluctuations in the power supply voltage.

　In addition, in the embodiments of Figs. 11 to 14, a noise removing capacitor or the like may be further provided as appropriate. For example, between the drain of the transistor that is the output terminal of the constant voltage source E1 that is the bias voltage and Vdd, and between the drain of the transistor that is the output terminal of the constant voltage source E2 that is the bias voltage and Vss. may be provided.

(Seventh embodiment)
The frequency dividing circuit 1 formed by the input circuit 10 and the frequency dividing section 20 in each of the above-described embodiments is particularly a part of the frequency dividing section 20 (for example, the first inverter 200, the second inverter 202 and the first latch circuit). 210 combinations) can be replaced by D-FF. Therefore, a clock signal for D-FF can be generated as an analog signal using a configuration equivalent to this input circuit 10. FIG.

Therefore, according to the input circuit 10 according to all the embodiments of the present disclosure, an analog signal can be used as the input signal of the frequency dividing circuit that divides the frequency by 3 or more. In each of the above-described embodiments, the circuit for frequency division by 2 has been described, but as described above, the input circuit 10 can also be applied to a frequency divider circuit for frequency division by 3 or more.

The frequency divider circuit according to each of the embodiments described above may be used, for example, for processing high-frequency signals in RF transceiver circuits. It may also be used in an ADPLL (All Digital Phase Locked Loop) that generates a clock signal in an image sensor using CMOS. The present invention is not limited to these uses, and can be used in devices that use frequency division of clock signals.

The above-described embodiment may be in the following form.

(1)
an inverter having a transistor;
an input circuit that converts a first signal that is an analog differential signal to a second signal that is a differential analog signal for driving the transistors;
A divider circuit with

(2)
the transistor is a MOSFET;
The input circuit superimposes a bias voltage on the AC component of the first signal to oscillate between a voltage lower than the threshold voltage of the transistor and a voltage higher than the threshold voltage of the transistor. convert to a second signal,
(1) The divider circuit described in (1).

(3)
the inverter comprises an nMOS and a pMOS;
The input circuit is
a signal obtained by superimposing the threshold voltage of the nMOS and an AC component of the differential signal;
a signal obtained by superimposing the threshold voltage of the pMOS and an AC component of the differential signal;
to generate
(2) The divider circuit described in (2).

(Four)
The input circuit is
a capacitor for extracting an AC component of a first differential signal, which is one of the signals constituting the differential signal;
a capacitor for extracting an AC component of a second differential signal, which is the other signal constituting the differential signal;
comprising
The frequency dividing circuit according to (2) or (3).

(Five)
further comprising a latch circuit;
(2) The divider circuit described in (2).

(6)
The inverter is
a first transistor, which is a p-type MOSFET and whose source is connected to the positive supply voltage;
a second transistor, which is a p-type MOSFET and whose source is connected to the drain of the first transistor;
a third transistor, which is an n-type MOSFET and whose drain is connected to the drain of the second transistor;
a fourth transistor which is an n-type MOSFET and has a drain connected to the source of the third transistor, a source connected to a negative power supply voltage, and a gate connected to the gate of the first transistor;
with
The latch circuit is
a fifth transistor, which is a p-type MOSFET and whose source is connected to the positive power supply voltage;
a sixth transistor which is a p-type MOSFET and has a source connected to the positive power supply voltage, a drain connected to the gate of the fifth transistor, and a gate connected to the drain of the fifth transistor;
a seventh transistor which is an n-type MOSFET and has a drain connected to the drain of the fifth transistor and a source connected to the negative power supply voltage;
an n-type MOSFET having a drain connected to the drain of the sixth transistor and the gate of the seventh transistor, a source connected to the negative power supply voltage, and a gate connected to the drain of the seventh transistor; 8 transistors and
with
The frequency divider circuit
a first inverter, a second inverter, a third inverter and a fourth inverter;
a first latch circuit and a second latch circuit;
a first output terminal, a second output terminal, a third output terminal and a fourth output terminal;
with
The first output terminal is connected to the gate of the first transistor of the first inverter, the drain of the second transistor of the fourth inverter, and the drain of the sixth transistor of the second latch circuit. , outputs the first output signal,
The second output terminal is connected to the gate of the first transistor of the second inverter, the drain of the second transistor of the third inverter, and the drain of the fifth transistor of the second latch circuit. , outputting a second output signal forming a differential signal with the first output signal;
The third output terminal is connected to the gate of the first transistor of the fourth inverter, the drain of the second transistor of the second inverter, and the drain of the sixth transistor of the first latch circuit. , outputting a third output signal having a predetermined phase shift from the first output signal,
The fourth output terminal is connected to the gate of the first transistor of the third inverter, the drain of the second transistor of the first inverter, and the drain of the fifth transistor of the first latch circuit. , outputting a fourth output signal forming a differential signal with the third output signal;
(5) The divider circuit described in (5).

(7)
The input circuit is
a first input terminal to which one of the first signals is input;
a second input terminal to which the other of the first signals is input;
a first capacitor connected between the first input terminal and the gate of the second transistor of the first inverter and the gate of the second transistor of the second inverter;
a second capacitor connected between the second input terminal and a terminal connected to the gate of the second transistor of the third inverter and the gate of the second transistor of the fourth inverter;
a third capacitor connected between the first input terminal and a terminal connected to the gate of the third transistor of the first inverter and the gate of the third transistor of the second inverter;
a fourth capacitor connected between the second input terminal and a terminal connected to the gate of the third transistor of the third inverter and the gate of the third transistor of the fourth inverter;
The divider circuit according to (6), comprising:

(8)
The input circuit is
a first bias circuit that applies a first bias voltage to the output of the first capacitor;
a second bias circuit that applies a second bias voltage to the output of the second capacitor;
a third bias circuit that applies a third bias voltage to the output of the third capacitor;
a fourth bias circuit that applies a fourth bias voltage to the output of the fourth capacitor;
comprising
(7) The divider circuit described in (7).

(9)
the first bias voltage and the second bias voltage are threshold voltages of the second transistor;
wherein the third bias voltage and the fourth bias voltage are threshold voltages of the third transistor;
(8) The divider circuit described in (8).

(Ten)
The input circuit is
a first steady-state voltage source connected to the positive power supply voltage;
a second steady-state voltage source connected to the negative power supply voltage;
with
The first bias circuit includes the first steady voltage source and a first resistor connected to the first steady voltage source,
The second bias circuit comprises the first steady voltage source and a second resistor connected to the first steady voltage source,
the third bias circuit includes the second constant voltage source and a third resistor connected to the second constant voltage source,
The fourth bias circuit comprises the second constant voltage source and a fourth resistor connected to the second constant voltage source,
(8) The divider circuit described in (8).

(11)
The first bias circuit, the second bias circuit, the third bias circuit, and the fourth bias circuit can variably control voltages.
(8) The divider circuit described in (8).

(12)
the first inverter and the second inverter share the second transistor and the third transistor;
the third inverter and the fourth inverter share the second transistor and the third transistor;
A frequency dividing circuit according to any one of (6) to (11).

(13)
The first bias circuit, the second bias circuit, the third bias circuit, and the fourth bias circuit output currents depending on the fluctuation of at least one of the positive power supply voltage and the negative power supply voltage. comprising at least one current source with a varying
The frequency dividing circuit according to any one of (8) to (10).

(14)
the current source comprises a transistor having a gate connected to the positive power supply voltage or the negative power supply voltage;
(13) The divider circuit described in (13).

(15)
The current source comprises a resistor connected to the positive power supply voltage or the negative power supply voltage,
(13) The divider circuit described in (13).

(16)
Further comprising a power gate transistor between the source of the fourth transistor, the source of the seventh transistor and the source of the eighth transistor, and the negative power supply voltage,
A frequency dividing circuit according to any one of (6) to (15).

(17)
The predetermined phase is π/2,
A frequency dividing circuit according to any one of (6) to (16).

(18)
generating a signal by dividing the first signal by n (where n is an integer equal to or greater than 2);
A frequency dividing circuit according to any one of (1) to (17).

Aspects of the present disclosure are not limited to the above-described embodiments, but include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. That is, various additions, changes, and partial deletions are possible without departing from the conceptual idea and spirit of the present disclosure derived from the content defined in the claims and equivalents thereof.

1: divider circuit,
10: input circuit, 20: divider,
200: first inverter, 202: second inverter, 204: third inverter, 206: fourth inverter,
210: first latch circuit, 212: second latch circuit,

Claims

an inverter having a transistor;
an input circuit that converts a first signal that is an analog differential signal to a second signal that is a differential analog signal for driving the transistors;
A divider circuit with
the transistor is a MOSFET;
The input circuit superimposes a bias voltage on the AC component of the first signal to oscillate between a voltage lower than the threshold voltage of the transistor and a voltage higher than the threshold voltage of the transistor. convert to a second signal,
The frequency dividing circuit according to claim 1.
the inverter comprises an nMOS and a pMOS;
The input circuit is
a signal obtained by superimposing the threshold voltage of the nMOS and an AC component of the differential signal;
a signal obtained by superimposing the threshold voltage of the pMOS and an AC component of the differential signal;
to generate
3. The frequency dividing circuit according to claim 2.
The input circuit is
a capacitor for extracting an AC component of a first differential signal, which is one of the signals constituting the differential signal;
a capacitor for extracting an AC component of a second differential signal, which is the other signal constituting the differential signal;
comprising
3. The frequency dividing circuit according to claim 2.
further comprising a latch circuit;
3. The frequency dividing circuit according to claim 2.
The inverter is
a first transistor, which is a p-type MOSFET and whose source is connected to the positive supply voltage;
a second transistor, which is a p-type MOSFET and whose source is connected to the drain of the first transistor;
a third transistor, which is an n-type MOSFET and whose drain is connected to the drain of the second transistor;
a fourth transistor which is an n-type MOSFET and has a drain connected to the source of the third transistor, a source connected to a negative power supply voltage, and a gate connected to the gate of the first transistor;
with
The latch circuit is
a fifth transistor, which is a p-type MOSFET and whose source is connected to the positive power supply voltage;
a sixth transistor which is a p-type MOSFET and has a source connected to the positive power supply voltage, a drain connected to the gate of the fifth transistor, and a gate connected to the drain of the fifth transistor;
a seventh transistor which is an n-type MOSFET and has a drain connected to the drain of the fifth transistor and a source connected to the negative power supply voltage;
an n-type MOSFET having a drain connected to the drain of the sixth transistor and the gate of the seventh transistor, a source connected to the negative power supply voltage, and a gate connected to the drain of the seventh transistor; 8 transistors and
with
The frequency divider circuit
a first inverter, a second inverter, a third inverter and a fourth inverter;
a first latch circuit and a second latch circuit;
a first output terminal, a second output terminal, a third output terminal and a fourth output terminal;
with
The first output terminal is connected to the gate of the first transistor of the first inverter, the drain of the second transistor of the fourth inverter, and the drain of the sixth transistor of the second latch circuit. , outputs the first output signal,
The second output terminal is connected to the gate of the first transistor of the second inverter, the drain of the second transistor of the third inverter, and the drain of the fifth transistor of the second latch circuit. , outputting a second output signal forming a differential signal with the first output signal;
The third output terminal is connected to the gate of the first transistor of the fourth inverter, the drain of the second transistor of the second inverter, and the drain of the sixth transistor of the first latch circuit. , outputting a third output signal having a predetermined phase shift from the first output signal,
The fourth output terminal is connected to the gate of the first transistor of the third inverter, the drain of the second transistor of the first inverter, and the drain of the fifth transistor of the first latch circuit. , outputting a fourth output signal forming a differential signal with the third output signal;
6. The frequency dividing circuit according to claim 5.
The input circuit is
a first input terminal to which one of the first signals is input;
a second input terminal to which the other of the first signals is input;
a first capacitor connected between the first input terminal and the gate of the second transistor of the first inverter and the gate of the second transistor of the second inverter;
a second capacitor connected between the second input terminal and a terminal connected to the gate of the second transistor of the third inverter and the gate of the second transistor of the fourth inverter;
a third capacitor connected between the first input terminal and a terminal connected to the gate of the third transistor of the first inverter and the gate of the third transistor of the second inverter;
a fourth capacitor connected between the second input terminal and a terminal connected to the gate of the third transistor of the third inverter and the gate of the third transistor of the fourth inverter;
7. The divider circuit of claim 6, comprising:
The input circuit is
a first bias circuit that applies a first bias voltage to the output of the first capacitor;
a second bias circuit that applies a second bias voltage to the output of the second capacitor;
a third bias circuit that applies a third bias voltage to the output of the third capacitor;
a fourth bias circuit that applies a fourth bias voltage to the output of the fourth capacitor;
comprising
8. A frequency dividing circuit according to claim 7.
the first bias voltage and the second bias voltage are threshold voltages of the second transistor;
wherein the third bias voltage and the fourth bias voltage are threshold voltages of the third transistor;
9. A frequency dividing circuit according to claim 8.
The input circuit is
a first steady-state voltage source connected to the positive power supply voltage;
a second steady-state voltage source connected to the negative power supply voltage;
with
The first bias circuit includes the first steady voltage source and a first resistor connected to the first steady voltage source,
The second bias circuit includes the first steady voltage source and a second resistor connected to the first steady voltage source,
the third bias circuit includes the second constant voltage source and a third resistor connected to the second constant voltage source,
The fourth bias circuit comprises the second constant voltage source and a fourth resistor connected to the second constant voltage source,
9. A frequency dividing circuit according to claim 8.
The first bias circuit, the second bias circuit, the third bias circuit, and the fourth bias circuit can variably control voltages.
9. A frequency dividing circuit according to claim 8.
the first inverter and the second inverter share the second transistor and the third transistor;
the third inverter and the fourth inverter share the second transistor and the third transistor;
7. The frequency dividing circuit according to claim 6.
The first bias circuit, the second bias circuit, the third bias circuit, and the fourth bias circuit output currents depending on the fluctuation of at least one of the positive power supply voltage and the negative power supply voltage. comprising at least one current source with a varying
9. A frequency dividing circuit according to claim 8.
the current source comprises a transistor having a gate connected to the positive power supply voltage or the negative power supply voltage;
14. A frequency divider circuit as claimed in claim 13.
The current source comprises a resistor connected to the positive power supply voltage or the negative power supply voltage,
14. A frequency divider circuit as claimed in claim 13.
Further comprising a power gate transistor between the source of the fourth transistor, the source of the seventh transistor and the source of the eighth transistor, and the negative power supply voltage,
7. The frequency dividing circuit according to claim 6.
The predetermined phase is π/2,
7. The frequency dividing circuit according to claim 6.
generating a signal by dividing the first signal by n (where n is an integer equal to or greater than 2);
The frequency dividing circuit according to claim 1.