WO2022206885A1 - 一种耦合封装结构及耦合方法 - Google Patents

一种耦合封装结构及耦合方法 Download PDF

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WO2022206885A1
WO2022206885A1 PCT/CN2022/084346 CN2022084346W WO2022206885A1 WO 2022206885 A1 WO2022206885 A1 WO 2022206885A1 CN 2022084346 W CN2022084346 W CN 2022084346W WO 2022206885 A1 WO2022206885 A1 WO 2022206885A1
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packaged
coupling
component
face
protective layer
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PCT/CN2022/084346
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English (en)
French (fr)
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孙杰
孙天博
李忠宇
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北京摩尔芯光半导体技术有限公司
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Publication of WO2022206885A1 publication Critical patent/WO2022206885A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G02B6/262—Optical details of coupling light into, or out of, or between fibre ends, e.g. special fibre end shapes or associated optical elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/25—Preparing the ends of light guides for coupling, e.g. cutting
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements

Definitions

  • the present application relates to the field of chip technology, and more particularly, to a coupling package structure and a coupling method.
  • Photonic Integrated Circuit (PIC) chip refers to a chip made using photonic integration technology, also known as optical chip.
  • Photonic integration technology can be compatible with the existing semiconductor CMOS (Complementary Metal-Oxide-Semiconductor, complementary metal oxide semiconductor) standard technology, and can be integrated with microelectronic integrated circuits. Therefore, integrated optical chips have become a research hotspot. , computing, quantum, biology and other fields have a wide range of applications.
  • CMOS Complementary Metal-Oxide-Semiconductor, complementary metal oxide semiconductor
  • the coupling methods of optical chips and fiber arrays (FA) or other optical chips are divided into end-face coupling and grating vertical coupling.
  • grating vertical coupling is more suitable for rapid chip testing, while end-face coupling is more inclined to make packaged products. Therefore, the integrated optical chips that tend to be commercialized mostly adopt the end-face coupling method.
  • the present application provides a coupling package structure and a coupling method, so as to solve the problem that the coupling package structure will cause high coupling loss during the coupling package.
  • a coupling package structure comprising:
  • the first component to be packaged includes a first optical chip, a first waveguide located in the first optical chip, the first component to be packaged further includes a first coupling end face and a cutting end face, On one side of the first coupling end face, the side surface of the first waveguide is flush with the first coupling end face, and the cutting end face protrudes from the first coupling end face;
  • a second component to be packaged includes a substrate located at the bottom of the second package component, a structure to be coupled located on one side of the substrate, and a first protective layer, the first protective layer located on the The top of the second to-be-packaged element wraps the to-be-coupled structure, and the to-be-coupled structure is disposed protruding from the first protective layer;
  • the second component to be packaged is flip-chip packaged with the first component to be packaged, so that the first waveguide is in contact with the side surface of the structure to be coupled.
  • Both the first component to be packaged and the second component to be packaged are disposed on the same side of the carrier.
  • the height adjustment layer is used for cooperating with the first protective layer to arrange the structure to be coupled and the first waveguide in the same surface.
  • the material of the height adjustment layer includes epoxy resin.
  • the carrier includes a printed circuit board or a ceramic board.
  • the second component to be packaged includes an optical fiber array
  • the substrate includes: a substrate located at the bottom of the second component to be packaged;
  • the first protective layer includes: a cladding layer on top of the second component to be packaged;
  • the structure to be coupled includes: a plurality of optical fibers, and the plurality of optical fibers are wrapped by the first protective layer;
  • One end of the structure to be coupled protrudes from the first protective layer.
  • the distance by which the cleaved end face protrudes from the first coupling end face is smaller than the distance by which one end of the optical fiber protrudes from the cladding of the optical fiber array.
  • the second component to be packaged includes a preset optical chip, and the preset optical chip includes at least an optical fiber array and a PLC chip;
  • the substrate includes a second optical chip
  • the structure to be coupled includes a second waveguide
  • the second waveguide is located between the first protective layer and the second optical chip, and the second waveguide is disposed protruding from the first protective layer.
  • the distance by which the cutting end surface protrudes from the first coupling end surface is smaller than the distance by which the second waveguide protrudes from the first protective layer.
  • a coupling method that includes:
  • a first element to be packaged and a second element to be packaged are provided, wherein the first element to be packaged includes a first optical chip, a first waveguide located in the first optical chip, and the first element to be packaged further includes a first coupling end face and a cutting end face, on the side of the first coupling end face, the side surface of the first waveguide is flush with the first coupling end face, and the cutting end face protrudes from the first coupling end face; the first coupling end face
  • the two components to be packaged include a substrate located at the bottom of the second package component, a structure to be coupled located on one side of the substrate, and a first protective layer.
  • the first protective layer is located on the top of the second package component and wraps the entire component.
  • the second to-be-packaged element is packaged with the first to-be-packaged element in a flip-chip manner, so that the first waveguide is in close contact with the side surface of the to-be-coupled structure.
  • the embodiments of the present application provide a coupling package structure and a coupling method, wherein the to-be-coupled structure of the second to-be-packaged element of the coupled package structure protrudes from the second to-be-packaged element.
  • a first protective layer, and the coupling method is to encapsulate the second component to be packaged with the first component to be packaged in a flip-chip manner, so that the first waveguide is in close contact with the side surface of the structure to be coupled, Large coupling losses due to the large distance between the first waveguide and the structure to be coupled are avoided.
  • FIG. 1 is a schematic structural diagram of an optical chip
  • FIG. 2 is a schematic structural diagram of an optical fiber array
  • FIG. 3 is a schematic diagram of a coupling package structure of an optical chip and an optical fiber array in the prior art
  • FIG. 4 is a schematic diagram of the fiber exiting the fiber to the waveguide
  • FIG. 5 is a schematic cross-sectional structural diagram of a coupling package structure according to an embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional structural diagram of a coupling package structure provided by yet another embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional structural diagram of a coupling package structure provided by another embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional structural diagram of a coupling package structure provided by yet another embodiment of the present application.
  • FIG. 9 is a schematic cross-sectional structural diagram of a coupling package structure according to still another embodiment of the present application.
  • the existing solution is to create a cut trench (usually 100 ⁇ m deep) in the cross-sectional direction of the waveguide by some etching methods (eg deep silicon etching). In this way, a smooth waveguide surface will be produced on the chip to obtain better coupling efficiency. Then, mechanical dicing is performed, and the dicing blade cuts the chip along the dicing groove without touching the waveguide plane to obtain the optical chip as shown in FIG. 1 . Therefore, referring to FIG. 1 , a small step 12 will be formed on the substrate 11 of the optical chip, and the height of the step 12 is set as h and the width is set as s. The small steps 12 protrude from the waveguide 13 and the protective layer 14 .
  • some etching methods eg deep silicon etching
  • the waveguide cannot be in close contact with the fiber or waveguide to be coupled.
  • FIG. 2 shows a schematic structural diagram of an optical fiber array
  • FIG. 3 shows a schematic structural diagram of a coupling package between an optical chip and an optical fiber array.
  • the optical fiber array includes a substrate 21 , a plurality of optical fibers 22 and an optical fiber cladding 23 , the substrate 21 includes a plurality of V-shaped grooves, and a bundle or a single optical fiber 22 is installed on the substrate 21 at a predetermined interval.
  • the optical fibers 22 in the optical fiber array cannot be in close contact with the waveguide 13.
  • the coupling efficiency from the optical fiber 22 to the optical chip is the same as the optical fiber 22 and the optical chip incident waveguide. 13 is proportional to the mode field coincidence integral.
  • the outgoing light of the optical fiber 22 will have a certain divergence angle ⁇ .
  • the mode spot of the optical fiber 22 will also increase accordingly, so the mode field of the optical fiber and the mode field of the incident waveguide 13 will be more mismatched. This results in a decrease in coupling efficiency.
  • embodiments of the present application provide a coupling packaging structure and a coupling method, wherein the coupling packaging structure and the coupling method, wherein the to-be-coupled structure of the second to-be-packaged element of the coupling and packaging structure protrudes beyond the the first protective layer of the second component to be packaged, and the coupling method is to encapsulate the second component to be packaged with the first component to be packaged in a flip-chip manner, so that the first waveguide is connected to the component to be packaged.
  • the side surfaces of the coupling structure are in close contact, which avoids large coupling loss caused by the large distance between the first waveguide and the structure to be coupled.
  • an embodiment of the present application provides a coupling package structure, as shown in FIG. 5 , the coupling package structure includes:
  • a first component to be packaged 100 includes a first optical chip 101, a first waveguide 102 located in the first optical chip 101, and the first component to be packaged 100 further includes a first coupling The end face and the cutting end face, on the side of the first coupling end face, the side surface of the first waveguide 102 is flush with the first coupling end face, and the cutting end face protrudes from the first coupling end face;
  • the second to-be-packaged component 200 includes a substrate 201 located at the bottom of the second packaged component, a to-be-coupled structure 202 located on one side of the substrate 201 , and a first protective layer 203 .
  • a protective layer 203 is located on top of the second to-be-packaged element and wraps the to-be-coupled structure 202, and the to-be-coupled structure 202 is disposed protruding from the first protective layer 203;
  • the second component to be packaged 200 is flip-chip packaged with the first component to be packaged 100 , so that the first waveguide 102 is in contact with the side surface of the structure to be coupled 202 .
  • the second component to be packaged 200 is also an optical chip for illustration as an example, and the optical chip includes but is not limited to a PLC (Planar Lightwave Circuit) chip or a silicon photonics chip.
  • the optical chip includes but is not limited to a PLC (Planar Lightwave Circuit) chip or a silicon photonics chip.
  • PLC is a technology platform for manufacturing integrated optoelectronic devices, which can be applied to different substrate 201 materials, including silicon/glass/silicon dioxide (Silicon/Quartz/Silica), lithium niobate (LiNbO3), insulators Silicon (SOI/SIMOX), silicon oxynitride (SiON), high molecular polymer (Polymer), etc.
  • Devices based on planar optical circuit technology solutions include: Splitter, Arrayed Waveguide Grating (AWG), Variable Optical Attenuator (VOA), Optical switch, etc.
  • a PLC chip is a single chip that is cut from a PLC wafer into bars and polished.
  • the substrate 201 refers to a carrier part for manufacturing semiconductor chips such as planar optical path passive chips (optical splitters, AWGs, etc.), active chips (lasers, detectors, etc.) and integrated optical circuit chips.
  • semiconductor chips such as planar optical path passive chips (optical splitters, AWGs, etc.), active chips (lasers, detectors, etc.) and integrated optical circuit chips.
  • the flip-chip packaging means that the substrate 201 of the second component to be packaged 200 is disposed above (a side away from the first optical chip 101 ), and the first protective layer 203 is disposed below (close to the side of the first optical chip 101 ). the first optical chip 101 side).
  • the to-be-coupled structure 202 in the second to-be-packaged component 200 is disposed protruding from the first protective layer 203 , when the second to-be-packaged component 200 is packaged in a flip-chip manner, the to-be-coupled The protruding part of the structure 202 can make up for the existence of small steps in the first component to be packaged 100 , so that the first waveguide 102 can be in contact with the side surface of the structure to be coupled 202 , thereby solving the problem of large loss on the coupling end face.
  • the first component to be packaged 100 further includes a second protective layer 103 on top of the first optical chip 101 .
  • the first component to be packaged 100 may also not include the second protective layer 103 , which is not limited in the present application.
  • FIG. 7 shows a schematic structural diagram of coupling and packaging between the coupling packaging structure and the optical fiber array.
  • the protruding structure to be coupled 202 due to the protruding structure to be coupled 202 compared to the first protective layer 203 , during the coupling and packaging, the protruding structure to be coupled The structure 202 can make up for the existence of small steps in the first component to be packaged 100 , so that the structure to be coupled 202 can be in close contact with the first waveguide 102 , thereby solving the problem of large loss during coupling and packaging.
  • the second component to be packaged 200 is an optical fiber array or an optical chip
  • the types of the substrate 201 , the first protective layer 203 and the structure to be coupled 202 are different, specifically.
  • the substrate 201 includes: an optical fiber array substrate 201;
  • the first protective layer 203 includes: an optical fiber array cladding
  • the to-be-coupled structure 202 includes: a plurality of optical fibers, and the plurality of optical fibers are wrapped by the fiber array cladding;
  • One end of the optical fiber protrudes from the cladding of the optical fiber array.
  • the distance S1 by which the cleaved end face protrudes from the first coupling end face is smaller than the distance S3 by which one end of the optical fiber protrudes from the cladding of the optical fiber array.
  • the preset optical chip includes at least an optical fiber array, a PLC chip or other types of optical chips,
  • the substrate 201 includes a second optical chip
  • the to-be-coupled structure 202 includes a second waveguide
  • the second waveguide is located between the first protective layer 203 and the second optical chip, and the second waveguide is disposed protruding from the first protective layer 203 .
  • the distance S1 by which the cutting end surface protrudes from the first coupling end surface is smaller than the distance S2 by which the second waveguide protrudes from the first protective layer 203 .
  • the coupling package structure further includes:
  • the first component to be packaged 100 and the second component to be packaged 200 are both disposed on the same side of the carrier 300 , and the first optical chip 101 is disposed toward the carrier 300 , the first protective layer 203 set towards the carrier 300;
  • the height adjustment layer 301 is used to cooperate with the first protective layer 203 to dispose the structure to be coupled 202 and the first waveguide 102 in the same surface.
  • the height adjustment layer 301 includes an epoxy resin layer.
  • the carrier 300 includes a printed circuit board (Printed Circuit Boards, PCB) or a ceramic board.
  • PCB printed Circuit Boards
  • the embodiment of the present application also provides a coupling method, including:
  • S101 Provide a first component to be packaged and a second component to be packaged, wherein the first component to be packaged includes a first optical chip, a first waveguide in the first optical chip, and a first optical chip on top of the first optical chip
  • the second protective layer, the first component to be packaged further includes a first coupling end face and a cutting end face, and on the side of the first coupling end face, the side surface of the first waveguide is flush with the first coupling end face, so The cutting end surface protrudes from the first coupling end surface;
  • the second component to be packaged includes a substrate located at the bottom of the second package component, a structure to be coupled located on one side of the substrate, and a first protective layer.
  • a protective layer is located on top of the second packaging element and wraps the to-be-coupled structure, and the to-be-coupled structure is disposed protruding from the first protective layer;
  • S102 Package the second component to be packaged and the first component to be packaged in a flip-chip manner, so that the first waveguide is in close contact with the side surface of the structure to be coupled.
  • the embodiments of the present application provide a coupling package structure and a coupling method, wherein the to-be-coupled structure of the second to-be-packaged element of the coupled package structure protrudes from the first protection of the second to-be-packaged element layer, and the coupling method is to encapsulate the second component to be packaged with the first component to be packaged in a flip-chip manner, so that the first waveguide is in close contact with the side surface of the structure to be coupled, avoiding There is a large coupling loss due to the large distance between the first waveguide and the structure to be coupled.

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  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optical Couplings Of Light Guides (AREA)

Abstract

一种耦合封装结构及耦合方法。该耦合封装结构包括第一待封装元件(100)和第二待封装元件(200)。第一待封装元件(100)包括第一光芯片(101)、位于第一光芯片(101)中的第一波导(102)，第一待封装元件(100)还包括第一耦合端面和切割端面，在第一耦合端面一侧，第一波导(102)的侧面与第一耦合端面齐平，切割端面突出第一耦合端面。第二待封装元件(200)包括位于第二封装元件底部的衬底(201)、位于衬底(201)一侧的待耦合结构(202)以及第一保护层(203)，第一保护层(203)位于第二待封装元件(200)的顶部且包裹待耦合结构(202)，待耦合结构(202)突出第一保护层(203)设置。第二待封装元件(200)以倒装方式与第一待封装元件(100)封装，以使第一波导(102)与待耦合结构(202)的侧面接触，避免了从第一波导(102)与待耦合结构(202)之间由于存在较大距离而导致的较大耦合损耗。

Description

一种耦合封装结构及耦合方法
本申请要求于2021年03月31日提交中国专利局、申请号为202110349619.3、发明名称为“一种耦合封装结构及耦合方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片技术领域，更具体地说，涉及一种耦合封装结构及耦合方法。
背景技术
光子集成(Photonic Integrated Circuit，PIC)芯片是指使用光子集成技术制成的芯片，也可称为光芯片。光子集成技术能够与现有的半导体CMOS(Complementary Metal-Oxide-Semiconductor，互补金属氧化物半导体)标准技术兼容，可与微电子集成电路集成，因此，集成光学芯片成为研究热点，在通讯、传感、计算、量子、生物等领域有广泛的应用。
光芯片与光纤阵列(Fiber Array，FA)或其他光芯片耦合的方式分为端面耦合和光栅垂直耦合。其中，光栅垂直耦合更适用于芯片快速测试，而端面耦合更偏向于做封装产品。因此趋向于商业化的集成光学芯片多采用端面耦合方式。
但在目前的耦合封装结构中，光纤阵列与光芯片耦合或光芯片与光芯片耦合时，会导致较高的耦合损耗。
发明内容
为解决上述技术问题，本申请提供了一种耦合封装结构及耦合方法，以解决耦合封装结构在耦合封装时会导致较高的耦合损耗的问题。
为实现上述技术目的，本申请实施例提供了如下技术方案：
一种耦合封装结构，包括：
第一待封装元件，所述第一待封装元件包括第一光芯片、位于所述第一光芯片中的第一波导，所述第一待封装元件还包括第一耦合端面和切割 端面，在所述第一耦合端面一侧，所述第一波导的侧面与所述第一耦合端面齐平，所述切割端面突出所述第一耦合端面；
第二待封装元件，所述第二待封装元件包括位于第二封装元件底部的衬底、位于所述衬底一侧的待耦合结构以及第一保护层，所述第一保护层位于所述第二待封装元件的顶部且包裹所述待耦合结构，所述待耦合结构突出所述第一保护层设置；
所述第二待封装元件以倒装方式与所述第一待封装元件封装，以使所述第一波导与所述待耦合结构的侧面接触。
可选的，还包括：
载体；
所述第一待封装元件和所述第二待封装元件均设置于所述载体的同一侧。
可选的，还包括：
位于所述载体与所述第一保护层之间的高度调节层；
所述高度调节层用于配合所述第一保护层将所述待耦合结构与所述第一波导设置在同一表面内。
可选的，所述高度调节层的材料包括环氧树脂。
可选的，所述载体包括印制电路板或陶瓷板。
可选的，所述第二待封装元件包括光纤阵列；
所述衬底包括：位于第二待封装元件底部的衬底；
所述第一保护层包括：位于第二待封装元件顶部的包层；
所述待耦合结构包括：多根光纤，所述多根光纤被所述第一保护层包裹；
所述待耦合结构的一端突出所述第一保护层设置。
可选的，所述切割端面突出所述第一耦合端面的距离小于所述光纤的一端突出所述光纤阵列包层的距离。
可选的，所述第二待封装元件包括预设光芯片，所述预设光芯片至少包括光纤阵列、PLC芯片；
所述衬底包括第二光芯片；
所述待耦合结构包括第二波导；
所述第二波导位于所述第一保护层与所述第二光芯片之间，且所述第二波导突出所述第一保护层设置。
可选的，所述切割端面突出所述第一耦合端面的距离小于所述第二波导突出所述第一保护层的距离。
一种耦合方法，包括：
提供第一待封装元件和第二待封装元件，其中，所述第一待封装元件包括第一光芯片、位于所述第一光芯片中的第一波导，所述第一待封装元件还包括第一耦合端面和切割端面，在所述第一耦合端面一侧，所述第一波导的侧面与所述第一耦合端面齐平，所述切割端面突出所述第一耦合端面；所述第二待封装元件包括位于第二封装元件底部的衬底、位于所述衬底一侧的待耦合结构以及第一保护层，所述第一保护层位于所述第二封装元件的顶部且包裹所述待耦合结构，所述待耦合结构突出所述第一保护层设置；
以倒装方式将第二待封装元件与所述第一待封装元件封装，以使所述第一波导与所述待耦合结构的侧面紧密接触。
从上述技术方案可以看出，本申请实施例提供了一种耦合封装结构及耦合方法，其中，所述耦合封装结构的第二待封装元件的待耦合结构突出于所述第二待封装元件的第一保护层，且耦合方式为将所述第二待封装元件以倒装的方式与所述第一待封装元件封装，从而使得所述第一波导与所述待耦合结构的侧面紧密接触，避免了从第一波导与所述待耦合结构之间由于存在较大距离而导致的较大耦合损耗。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为光芯片的结构示意图；
图2为光纤阵列的结构示意图；
图3为现有技术中光芯片和光纤阵列的耦合封装结构示意图；
图4为光纤出射光纤到波导的示意图；
图5为本申请的一个实施例提供的一种耦合封装结构的剖面结构示意图；
图6为本申请的又一个实施例提供的一种耦合封装结构的剖面结构示意图；
图7为本申请的另一个实施例提供的一种耦合封装结构的剖面结构示意图；
图8为本申请的又一个实施例提供的一种耦合封装结构的剖面结构示意图；
图9为本申请的再一个实施例提供的一种耦合封装结构的剖面结构示意图。
具体实施方式
正如背景技术中所述，现有技术中光芯片与光纤阵列或光芯片与光芯片耦合时存在较大的耦合损耗。
这是因为在经过CMOS工艺加工出来的原始光芯片的端面通常不能直接进行端面耦合，主要原因是传统的机械式的晶圆切割工具会导致两个问题：(1)、芯片边缘凹凸不平，很不光滑，直接进行端面耦合损耗较大(2)、波导区域内缩在芯片的保护层内部，离芯片边缘有一定的距离。因此，在采用边耦合的光子集成芯片(例如硅光芯片)中需要将芯片中波导的边缘端切割露出并切割整齐。
现有的方案是，在波导的横截面方向，通过一些刻蚀方法(例如深硅刻蚀)，产生一个切割沟槽(通常是100μm深)。这样，在芯片上将会产生一个光滑的波导面，获得更好的耦合效率。随后进行机械切割，切割刀片在不触碰波导平面的情况下将芯片沿着切割槽切下来，获得如图1所示的光芯片。因此，参考图1，光芯片的基底11上会形成一个小台阶12，设台阶12的高度为h，宽度为s。小台阶12突出于波导13和保护层14。
在耦合时，由于该小台阶12的存在，使得波导与待耦合的光纤或波导无法紧密接触。
以光纤阵列为例，参考图2和图3，图2示出了光纤阵列的结构示意图， 图3示出了光芯片与光纤阵列的耦合封装结构示意图。光纤阵列包括衬底21、多根光纤22和光纤包层23，衬底21上包括多个V形槽，一束或一根光纤22按照规定间隔安装在衬底21上。
参考图3，由于光芯片上的小台阶12的存在，使得光纤阵列中的光纤22无法与波导13紧密接触，而参考图4，从光纤22到光芯片的耦合效率跟光纤22和光芯片入射波导13的模场重合积分成正比。光纤22的出射光会有一定的发散角α，随着传播距离S的增加，光纤22的模斑也会相应的增大，因此光纤模场和入射波导13的模场就会更加不匹配，从而导致耦合效率的降低。
为了解决这一问题，本申请实施例提供了一种耦合封装结构及耦合方法，其中，耦合封装结构及耦合方法，其中，所述耦合封装结构的第二待封装元件的待耦合结构突出于所述第二待封装元件的第一保护层，且耦合方式为将所述第二待封装元件以倒装的方式与所述第一待封装元件封装，从而使得所述第一波导与所述待耦合结构的侧面紧密接触，避免了从第一波导与所述待耦合结构之间由于存在较大距离而导致的较大耦合损耗。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供了一种耦合封装结构，如图5所示，所述耦合封装结构包括：
第一待封装元件100，所述第一待封装元件100包括第一光芯片101、位于所述第一光芯片101中的第一波导102，所述第一待封装元件100还包括第一耦合端面和切割端面，在所述第一耦合端面一侧，所述第一波导102的侧面与所述第一耦合端面齐平，所述切割端面突出所述第一耦合端面；
第二待封装元件200，所述第二待封装元件200包括位于第二封装元件底部的衬底201、位于所述衬底201一侧的待耦合结构202以及第一保护层203，所述第一保护层203位于第二待封装元件的顶部且包裹所述待 耦合结构202，所述待耦合结构202突出所述第一保护层203设置；
所述第二待封装元件200以倒装方式与所述第一待封装元件100封装，以使所述第一波导102与所述待耦合结构202的侧面接触。
在图5中，以所述第二待封装元件200同样为光芯片为例进行说明，所述光芯片包括但不限于PLC(Planar Lightwave Circuit，平面光路)芯片或硅光芯片。
其中，PLC是用于制造集成光电子器件的一种技术平台，能够应用于不同的衬底201材料，包括硅/玻璃/二氧化硅(Silicon/Quartz/Silica)、铌酸锂(LiNbO3)、绝缘体上的硅(SOI/SIMOX)、氮氧化硅(SiON)、高分子聚合物(Polymer)等。基于平面光路技术解决方案的器件包括：分路器(Splitter)、阵列波导光栅(Arrayed Waveguide Grating，AWG)、可调光衰减器(Variable Optical Attenuator，VOA)、光开关(Optical switch)等。PLC芯片，则是将PLC晶圆经切割成为巴条、抛光后切割成的单个芯片。
在本实施例中，所述衬底201是指制造平面光路无源芯片(光分路器、AWG等)、有源芯片(激光器、探测器等)及集成光路芯片等半导体芯片的承载部分。
在本实施例中，倒装方式进行封装是指第二待封装元件200的衬底201设置在上方(远离所述第一光芯片101一侧)，而第一保护层203设置在下方(靠近所述第一光芯片101一侧)的方式。结合参考图5，由于所述第二待封装元件200中的待耦合结构202突出所述第一保护层203设置，使得所述第二待封装元件200在以倒装方式进行封装时，待耦合结构202突出的部分可以弥补第一待封装元件100中的小台阶的存在，使得第一波导102可以与所述待耦合结构202的侧面接触，解决耦合端面存在较大损耗的问题。
在图5中，所述第一待封装元件100还包括位于第一光芯片101顶部的第二保护层103。在本申请的一些实施例中，参考图6，所述第一待封装元件100也可以不包括所述第二保护层103，本申请对此并不做限定。
参考图7，图7示出了耦合封装结构与光纤阵列进行耦合封装的结构示意图，类似的，由于相较于第一保护层203突出的待耦合结构202，在耦合封装时，突出的待耦合结构202可以弥补第一待封装元件100中的小台阶的存在，使得待耦合结构202可以与第一波导102紧密接触，解决耦合封装时 损耗较大的问题。
相应的，当所述第二待封装元件200为光纤阵列或光芯片时，所述衬底201、第一保护层203和待耦合结构202的类型不同，具体地。
参考图7，当所述第二待封装元件200包括光纤阵列时，所述衬底201包括：光纤阵列衬底201；
所述第一保护层203包括：光纤阵列包层；
所述待耦合结构202包括：多根光纤，所述多根光纤被所述光纤阵列包层包裹；
所述光纤的一端突出所述光纤阵列包层设置。
仍然参考图7，所述切割端面突出所述第一耦合端面的距离S1小于所述光纤的一端突出所述光纤阵列包层的距离S3。
参考图5，当所述第二待封装元件200包括预设光芯片时，所述预设光芯片至少包括光纤阵列、PLC芯片或其他类型的光芯片，
所述衬底201包括第二光芯片；
所述待耦合结构202包括第二波导；
所述第二波导位于所述第一保护层203与所述第二光芯片之间，且所述第二波导突出所述第一保护层203设置。
相应的，所述切割端面突出所述第一耦合端面的距离S1小于所述第二波导突出所述第一保护层203的距离S2。
参考图8或图9，所述耦合封装结构还包括：
载体300；
所述第一待封装元件100和所述第二待封装元件200均设置于所述载体300的同一侧，且所述第一光芯片101朝向所述载体300设置，所述第一保护层203朝向所述载体300设置；
以及位于所述载体300与所述第一保护层203之间的高度调节层301；
所述高度调节层301用于配合所述第一保护层203将所述待耦合结构202与所述第一波导102设置在同一表面内。
可选的，所述高度调节层301包括环氧树脂层。
可选的，所述载体300包括印制电路板(Printed Circuit Boards，PCB)或陶瓷板。
相应的，本申请实施例还提供了一种耦合方法，包括：
S101：提供第一待封装元件和第二待封装元件，其中，所述第一待封装元件包括第一光芯片、位于所述第一光芯片中的第一波导以及位于第一光芯片顶部的第二保护层，所述第一待封装元件还包括第一耦合端面和切割端面，在所述第一耦合端面一侧，所述第一波导的侧面与所述第一耦合端面齐平，所述切割端面突出所述第一耦合端面；所述第二待封装元件包括位于第二封装元件底部的衬底、位于所述衬底一侧的待耦合结构以及第一保护层，所述第一保护层位于所述第二封装元件的顶部且包裹所述待耦合结构，所述待耦合结构突出所述第一保护层设置；
S102：以倒装方式将第二待封装元件与所述第一待封装元件封装，以使所述第一波导与所述待耦合结构的侧面紧密接触。
综上所述，本申请实施例提供了一种耦合封装结构及耦合方法，其中，所述耦合封装结构的第二待封装元件的待耦合结构突出于所述第二待封装元件的第一保护层，且耦合方式为将所述第二待封装元件以倒装的方式与所述第一待封装元件封装，从而使得所述第一波导与所述待耦合结构的侧面紧密接触，避免了从第一波导与所述待耦合结构之间由于存在较大距离而导致的较大耦合损耗。
本说明书中各实施例中记载的特征可以相互替换或者组合，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种耦合封装结构，其特征在于，包括：
    第一待封装元件，所述第一待封装元件包括第一光芯片、位于所述第一光芯片中的第一波导，所述第一待封装元件还包括第一耦合端面和切割端面，在所述第一耦合端面一侧，所述第一波导的侧面与所述第一耦合端面齐平，所述切割端面突出所述第一耦合端面；
    第二待封装元件，所述第二待封装元件包括位于第二封装元件底部的衬底、位于所述衬底一侧的待耦合结构以及第一保护层，所述第一保护层位于所述第二待封装元件的顶部且包裹所述待耦合结构，所述待耦合结构突出所述第一保护层设置；
    所述第二待封装元件以倒装方式与所述第一待封装元件封装，以使所述第一波导与所述待耦合结构的侧面接触。
  2. 根据权利要求1所述的耦合封装结构，其特征在于，还包括：
    载体；
    所述第一待封装元件和所述第二待封装元件均设置于所述载体的同一侧。
  3. 根据权利要求2所述的耦合封装结构，其特征在于，还包括：
    位于所述载体与所述第一保护层之间的高度调节层；
    所述高度调节层用于配合所述第一保护层将所述待耦合结构与所述第一波导设置在同一表面内。
  4. 根据权利要求3所述的耦合封装结构，其特征在于，所述高度调节层的材料包括环氧树脂。
  5. 根据权利要求2所述的耦合封装结构，其特征在于，所述载体包括印制电路板或陶瓷板。
  6. 根据权利要求1所述的耦合封装结构，其特征在于，所述第二待封装元件包括光纤阵列；
    所述衬底包括：位于第二待封装元件底部的衬底；
    所述第一保护层包括：位于第二待封装元件顶部的包层；
    所述待耦合结构包括：多根光纤，所述多根光纤被所述第一保护层包裹；
    所述待耦合结构的一端突出所述第一保护层设置。
  7. 根据权利要求6所述的耦合封装结构，其特征在于，所述切割端面突出所述第一耦合端面的距离小于所述光纤的一端突出所述光纤阵列包层的距离。
  8. 根据权利要求1所述的耦合封装结构，其特征在于，所述第二待封装元件包括预设光芯片，所述预设光芯片至少包括光纤阵列、PLC芯片；
    所述衬底包括第二光芯片；
    所述待耦合结构包括第二波导；
    所述第二波导位于所述第一保护层与所述第二光芯片之间，且所述第二波导突出所述第一保护层设置。
  9. 根据权利要求8所述的耦合封装结构，其特征在于，所述切割端面突出所述第一耦合端面的距离小于所述第二波导突出所述第一保护层的距离。
  10. 一种耦合方法，其特征在于，包括：
    提供第一待封装元件和第二待封装元件，其中，所述第一待封装元件包括第一光芯片、位于所述第一光芯片中的第一波导，所述第一待封装元件还包括第一耦合端面和切割端面，在所述第一耦合端面一侧，所述第一波导的侧面与所述第一耦合端面齐平，所述切割端面突出所述第一耦合端面；所述第二待封装元件包括位于第二封装元件底部的衬底、位于所述衬底一侧的待耦合结构以及第一保护层，所述第一保护层位于所述第二封装元件的顶部且包裹所述待耦合结构，所述待耦合结构突出所述第一保护层设置；
    以倒装方式将第二待封装元件与所述第一待封装元件封装，以使所述第一波导与所述待耦合结构的侧面紧密接触。
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