WO2022206214A1

WO2022206214A1 - Controller and control system adapted to performing motor control

Info

Publication number: WO2022206214A1
Application number: PCT/CN2022/077106
Authority: WO
Inventors: 贺岩; 龚劭秋; 钱进; 冯赟
Original assignee: 实时侠智能控制技术有限公司
Priority date: 2021-03-31
Filing date: 2022-02-21
Publication date: 2022-10-06
Also published as: CN113067527A

Abstract

Provided in the present invention are a controller and a control system which are adapted to performing motor control. The controller comprises: a first processor, which is configured to run a first operating system and motor control, wherein the motor control is run during an interrupt service routine of the first processor; a cache coupled to the first processor; and a cache controller, which is used for loading primitives of the first operating system to the cache and locking the cache. The first processor, the cache, and the cache controller are integrated into the same chip.

Description

Controllers and control systems suitable for performing motor control

technical field

The present invention generally relates to controllers, and more particularly to a controller and control system suitable for performing motor control.

Background technique

Motion control and motor control are core technologies in the field of industrial automation. The motion controller that realizes motion control and the motor controller that realizes motor control are the two key control components on devices that automatically perform complex work commonly in the field of automation. In other fields, such as electric robots, CNC machine tools, electric multi-rotors, electric vehicles, mechanical prosthetics, robotic palms, electric mobile vehicles, controllers including motion control and motor control are also used.

Traditionally, most industrial automation systems (such as robots, large machine tools) use distributed control methods. Specifically, the distributed control method is that a motion controller cooperates with multiple motor controllers. Communication between the motion controller and the motor controller and between the motor controller and the motor controller uses a bus, such as a fieldbus.

This distributed control approach has a number of known disadvantages. For example, a large number of hardware devices will result in high hardware cost and large space occupation. For another example, the bus communication method is easily disturbed, and there is a bottleneck in the data transmission volume and transmission speed.

To this end, the industry has put forward the idea of "integration of drive and control", expecting to realize an industrial controller that integrates functions such as motion controller and motor controller. To realize motion control and motor control at the same time, an operating system is required to provide basic services such as task scheduling, file management and network communication. Moreover, the motor control task is executed in a fixed period, in order to ensure the performance of the motor control, the delay allowed for this task is small.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present application is to provide a controller and a control system suitable for performing motor control, which can meet the low delay requirement of motor control.

In order to solve the above technical problems, the present application provides a controller suitable for performing motor control, comprising: a first processor configured to run a first operating system and a motor control, wherein the motor control runs on the first In an interrupt service routine of a processor; coupled to a cache of the first processor; a cache controller for loading primitives of the first operating system into the cache, and locking the cache; Wherein the first processor, the cache and the cache controller are integrated in the same chip.

In an embodiment of the present application, the first processor includes a single processing core, and the first processor is further configured to run motion planning.

In an embodiment of the present application, the first processor includes a plurality of processing cores that run the first operating system in a symmetric multiprocessing mode and are further configured to run motion planning.

In an embodiment of the present application, the controller further includes: a second processor configured to run a second operating system and motion control, the second operating system is different from the first operating system; wherein the first operating system A processor and the second processor are integrated in the same chip.

In an embodiment of the present application, the first processor includes a first processing core combination, the second processor includes a second processing core combination, the first processing core combination and the second processing core combination Each includes one or more processing cores.

In an embodiment of the present application, the controller further includes a programmable logic device, coupled to the first processor, and performing motor control in cooperation with the first processor.

In an embodiment of the present application, the programmable logic device, the first processor and the second processor are integrated in the same chip.

In an embodiment of the present application, the motor control includes current loop calculation, or includes a combination of current loop calculation and speed loop calculation and/or position loop calculation.

In an embodiment of the present application, the programmable controller performs current loop calculations, and the first processor performs velocity loop calculations and/or position loop calculations.

In an embodiment of the present application, the controller further includes at least a part of the first operating system, which includes: a code segment and a data segment, where the code segment and the data segment respectively correspond to a designated memory area; a first identifier, The first identifier is used to designate the linker to put the primitives of the first operating system into the code segment; the second identifier is used to designate the linker to put the access data of the primitives of the first operating system into the code segment. in the data segment; wherein the first operating system is configured to load the code segment and the data segment into the designated memory area after startup.

In an embodiment of the present application, the step of loading the primitives of the first operating system into the cache by the cache controller includes: prohibiting the work of the cache; allowing a designated cache area to load data; accessing a designated memory area to load primitives and access data of the first operating system in the memory area into the cache area; and allowing the cache to function properly.

Another aspect of the present application provides a method of running motor control on a controller, the controller including a first processor, a cache controller, and a cache coupled to the first processor, and the first processor A processor, the cache and the cache controller are integrated in the same chip, and the method includes the steps of: starting the first processor; running the first operating system on the first processor ; loading primitives of the first operating system into the cache by the cache controller, and locking the cache; and running motor control in an interrupt service routine of the first processor.

In an embodiment of the present application, the first processor includes a single processing core, and the method further includes running motion planning on the first processor.

In an embodiment of the present application, the first processor includes a plurality of processing cores, wherein the first operating system is run in a symmetric multiprocessing mode on the first processor, and motion planning is executed.

In an embodiment of the present application, the controller further includes a second processor integrated with the first processor in the same chip, and the method further includes: starting the second processor; A second operating system and motion control run on the second processor, the second operating system being different from the first operating system.

In an embodiment of the present application, the controller further includes a programmable logic device coupled to the first processor and integrated with the first processor and the second processor in the same chip , the method further comprises: performing motor control on the programmable logic device in cooperation with the first processor.

In an embodiment of the present application, the first operating system includes: a code segment and a data segment, the code segment and data segment respectively correspond to a specified memory area; a first identifier, the first identifier is used to specify that the linker will Putting the primitives of the first operating system into the code segment; a second identifier, used to specify that the linker puts the access data of the primitives of the first operating system into the data segment; the method It also includes loading the code segment and the data segment into the designated memory area through the first operating system.

In an embodiment of the present application, the method further includes: defining a code segment and a data segment in a link file, the code segment and data segment respectively corresponding to a specified memory area; in the source code of the first operating system , a first identifier is added when defining the primitive of the first operating system, and the first identifier is used to designate the linker to put the primitive of the first operating system into the code segment; in the first In the source code of the operating system, a second identifier is added when defining the access data of the primitives of the first operating system, and the first identifier is used to designate the linker to put the access data into the data segment; The source code of the first operating system is described and linked as an executable program.

Another aspect of the present application proposes a control system including the controller as described above.

Compared with the prior art, the present invention executes the strong real-time tasks required for motor control through the interrupt service routine of the processor. And the operating system primitives are loaded into the cache and locked, which reduces the execution time of this part of the operating system primitives, so that the operation of masking the interrupt service during execution will not cause the interrupt required for motor control to be delayed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the application, are incorporated in and constitute a part of this application, illustrate embodiments of the application, and together with the description serve to explain the principles of the application. In the attached picture:

FIG. 1 is a logical structure of a controller according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram of a controller according to the first embodiment of the present invention.

FIG. 3 is an example operation process of the controller according to the first embodiment of the present invention.

4 is a circuit block diagram of a controller according to a second embodiment of the present invention.

FIG. 5 is an example operation process of the controller according to the second embodiment of the present invention.

6 is a circuit block diagram of a controller according to a third embodiment of the present invention.

7 is a circuit block diagram of a controller according to a fourth embodiment of the present invention.

FIG. 8 is an example operation process of the controller according to the fourth embodiment of the present invention.

9 is a flowchart of a method of operating motor control according to an embodiment of the present invention.

10 is a flowchart of a method for loading operating system primitives into a cache according to an embodiment of the present invention.

Preferred Embodiments of the Invention

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following briefly introduces the accompanying drawings that are used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without any creative effort, the present application can also be applied to the present application according to these drawings. other similar situations. Unless obvious from the locale or otherwise specified, the same reference numbers in the figures represent the same structure or operation.

As shown in this application and in the claims, unless the context clearly dictates otherwise, the words "a", "an", "an" and/or "the" are not intended to be specific in the singular and may include the plural. Generally speaking, the terms "comprising" and "comprising" only imply that the clearly identified steps and elements are included, and these steps and elements do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

The relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that, for the convenience of description, the dimensions of various parts shown in the accompanying drawings are not drawn in an actual proportional relationship. Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the authorized description. In all examples shown and discussed herein, any specific value should be construed as illustrative only and not as limiting. Accordingly, other examples of exemplary embodiments may have different values. It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further discussion in subsequent figures.

In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing corresponding components. Unless otherwise stated, the above words have no special meaning and therefore cannot be understood to limit the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and common terms, some terms mentioned in the specification of this application may be chosen by the applicant at his or her judgment, and the detailed meanings of which are set forth herein. described in the relevant section of the description. Furthermore, it is required that the application be understood not only by the actual terms used, but also by the meaning implied by each term.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to," or "contacting" another element, it can be directly on the other element On, connected to or coupled to, or in contact with the other component, or intervening components may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly in contact with" another element, there are no intervening elements present. Likewise, when a first component is referred to as being "in electrical contact" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow, even without direct contact between conductive components.

Embodiments of the present invention describe a controller that includes motion control and motor control functions. FIG. 1 is a logical structure of a controller according to an embodiment of the present invention. As understood by those skilled in the art, the motion control function refers to calculating the action targets of all motor axes of the device over time according to specific application tasks. Depending on the specific application, the calculation steps, calculation objects and calculated parameter variables may also be different, but the ultimate purpose is to obtain the relationship between the motor set value and time, and to generate the corresponding "each axis motor set value— —Time” data stream (data information). The given value of the motor may be, for example, any one or several of the angular position, rotational speed, and torque of the motor.

The motor given value will be delivered to the motor control function for execution on time at the corresponding time point. The motor control function is to control the drive circuit according to the given value calculated by the motion control, so as to drive the motor to meet the requirements of the given value quickly and stably. The calculation of "current loop", "speed loop" and "position loop" will be involved in motor control. The control loop that needs to be calculated varies according to the given value. In general, when the given value is the angle value, all three loops are calculated; when the given value is the speed value, the current loop and speed loop are calculated; when the given value is the torque, the current loop is calculated. So the most basic system will have at least a current loop. The motor control function can receive and process the data information of the given value of the motor of each axis in real time and control the rotation of the motor. ), the resulting synthetic motion reflected in the terminal execution will be what the application task requires. For a device or system that requires coordination of actions of all axes, it is ideal to calculate and control all axes synchronously at the same time, so that the coordinated and synthesized end effector moves accurately.

Referring to FIG. 1 , the controller 10 according to an embodiment of the present invention may include a motion controller 11 and a motor controller 12 . The motion controller 11 may perform the aforementioned motion control functions. The motor controller 12 may perform the aforementioned motor control functions. The teach pendant (Teach Pendant, TP) is the upper computer of the motion controller 11, and is used to send application task instructions to the motion controller 11, or edit the plan control. The motion controller 11 receives commands from the teach pendant, performs motion planning accordingly, and sends motion control data, such as the aforementioned given values of each axis motor, to the motor controller 12 . The motor controller 12 can accordingly generate a driving control signal (eg, a pulse width modulated PWM signal) to the motor driver 13, which drives the motor to run.

In various embodiments of the present invention, the controller 10 can be applied to electric robots, numerically controlled machine tools, electric multi-rotor aircraft, electric vehicles, mechanical prostheses, robotic palms, electric mobile vehicles, etc., for various types of multi-axis, Computational control and motor control of motion tasks for motor-driven equipment with coordinated movements between axes.

In each embodiment of the present invention, the number of shafts of the motor is not limited, and it may be 6 shafts or 8 shafts, or less shafts, or more shafts.

In the context of this application, a processing core is a central processing unit (CPU). The central processing unit (CPU) may contain a cache, such as the first level cache (L1 Cache). In the context of this application, a cache (cache), as commonly understood by those skilled in the art, is a memory that exists between main memory and the processor, which is much faster than main memory, close to on the speed of the processor. The second level cache (L2 Cache) in the processor acts as an additional cache. Communication between CPUs can be implemented using L2 caches coupled to multiple CPUs.

FIG. 2 is a circuit block diagram of a controller according to the first embodiment of the present invention. Referring to FIG. 2 , an integrated motion control and motor control controller 20 in this embodiment may include a processing core 21 , a cache controller 23 and a cache 24 . The single processing core 21, as the first processor in this embodiment, is configured to run the first operating system, motion control and motor control. The cache 24 is a second level cache between the processing core 21 and the memory. It will be appreciated that cache 24 may also be other levels of cache. Cache 24 is coupled to processing core 21 . The processing core 21, the cache controller 23 and the cache 24 are integrated in the same chip.

In this embodiment, the processing core 21 runs an operating system and performs motion control and motor control tasks. The operating system can manage the operation of the entire controller and complete basic functions such as network communication, file management, equipment management, task scheduling and system debugging. Specific application tasks, such as motion control tasks, can run on the operating system. The motion control task calculates the motion targets over time of all motor axes of the device where the controller is located. Motion control tasks can be implemented in a variety of ways. For example, according to different application requirements, different specific planning algorithm modules can be selectively embedded, task analysis software can be developed, and various path planning and joint space transformations can be performed. The specific algorithms for path planning and joint space transformation can also vary greatly depending on the application. For example, industrial robots can use kinematics and their inverse solution algorithms, and drones can achieve suspension, forward path planning variables, and joint transformation algorithms by adjusting the motor speed of each axis. Those skilled in the art can completely design the motion control function according to specific application requirements.

In this embodiment, the operating system is a small strong real-time system, such as RTThread.

By running the motion control task, the processing core 21 can plan the position value, speed value, torque value or combination thereof at different times of each axis of the equipment controlled by the controller 20 as the motor given value. That is to say, the given value of the motor can be any one or several of the above three values.

The processing core 21 can perform motor control tasks, control the motor driver according to the motor given value calculated above, and drive the motor to meet the requirements of the motor given value quickly and stably. In the present embodiment, the motor control 26 is executed in the interrupt service routine 25 of the processing core 21 . Specifically, a certain clock interrupt is designated as a high (eg highest) priority interrupt, which can preempt other interrupt service routines, and the strong real-time task of motor control runs in the interrupt service routine 25 . In this way, the strong real-time requirements of motor control can be met.

Current loop calculations, velocity loop calculations and/or position loop calculations are involved in motor control. The control loop that needs to be calculated varies according to the given value of the motor. In general, when the motor set value is the position value, all three loops are calculated; when the motor set value is the speed value, the current loop and the speed loop are calculated; when the motor set value is the torque, the current loop is calculated. Thus, the motor control tasks of the processing core 21 may selectively perform current loop calculations, or a combination of current loop calculations and velocity loop calculations and/or position loop calculations. The processing core 21 calculates the current required to drive the motor to achieve the required position, speed or torque of the required motor given value, and outputs a drive control signal (such as a PWM signal) according to the calculation result to IGBT or IPM or other types of power devices to drive the motor.

In the core part of the small strong real-time system run by the processing core 21, there is a key code segment that needs to shield interrupts - operating system primitives. Primitives are instructions that call kernel-level subroutines in the operating system. The difference from general generalized instructions is that primitives are uninterruptible and always appear as a basic unit. It differs from general procedures in that they are "primitive or atomic action". The so-called atomic operation means that all actions in an operation are either done or not done at all. In other words, a primitive is an indivisible basic unit and, therefore, cannot be interrupted during execution. Atomic operations are executed in tube state and reside in memory. In this embodiment, operating system primitives and the data they access (read and/or write) are loaded into cache 24 to ensure that their execution time is sufficiently short. Referring to FIG. 2 , cache controller 23 loads operating system primitive 24 a from memory 30 into cache 24 and locks cache 24 .

In one embodiment, the operating system includes a code segment and a data segment, which respectively correspond to designated memory regions. For example: define the code segment name as "RTcode" and the data segment name as "RTdata". The operating system also includes a first identifier and a second identifier. The first flag is used to designate the linker to put the operating system primitive 24a into the aforementioned code segment, and its format is, for example, __attribute__((section(".RTcode"))). The second flag is used to designate the linker to put the access data of the operating system primitives into the data segment, and its format is, for example, __attribute__((section(".RTdata"))). In one embodiment, the operating system source code is modified to include the aforementioned portions. Then, the operating system source code is compiled and linked into an executable program. The operating system is configured to load code segments and data segments into designated memory regions in memory 30 upon startup.

In the initialization phase after program startup, cache controller 23 loads operating system primitives into cache 24 . The specific process includes: prohibiting the work of the cache 24; allowing the designated cache area to load data; accessing the designated memory area in the memory 30 to load the primitives and access data of the operating system in the memory area into the cache 24 designated Cache area; allows Cache 24 to function properly. After these steps are completed, it is ensured that the code of the operating system primitive and the memory area where the accessed data is located are mapped to the cache 24 , and the code of the operating system primitive and the accessed data are also loaded into the cache 24 . After that, the cache controller 23 can lock the designated cache area so that the mapped memory address will not change, thereby preventing the controller from mapping the cache area to other addresses.

In some embodiments, the execution time of an operation primitive is less than 1 microsecond (μm).

In one embodiment, a lock-free queue is used to reduce latency when data flows from non-real-time tasks to strong real-time motor control tasks. In turn, the non-real-time tasks read the feedback data from the strong real-time motor control tasks and "write" the data.

FIG. 3 is an example operation process of the controller according to the first embodiment of the present invention. Referring to FIG. 3 , the processing core 21 generates motion control data during the motion control process, performs motor control according to the motion control data, generates a drive control signal to the motor driver 31 , and the motor driver 31 outputs current to control the motor 32 to run. Feedback data collected from the motor 32 can be fed back to the processing core 21 . Feedback data may include some or all of position data, velocity data, torque data, and current data.

4 is a circuit block diagram of a controller according to a second embodiment of the present invention. Referring to FIG. 4 , an integrated motion control and motor control controller 40 of this embodiment may further include a processing core 21 , a cache controller 23 , a cache 24 and a programmable logic device (PLD) 42 . The processing core 21 is configured to execute the operating system, motion control and motor control. The PLD 42 is coupled to the processing core 21 and cooperates with the processing core 21 to perform motor control. In this embodiment, the processing core 21, the cache controller 23, the cache 24 and the PLD 42 are integrated in the same processing chip.

Different from the previous embodiment, this embodiment introduces a PLD 42, and the PLD 42 has the characteristics of fast parallel calculation, so when the number of motor shafts is large, this is an obvious advantage. PLD 42 is coupled to processing core 21 for coordination. Here, the manner of coupling is realized, for example, through the interface 41 between the processor and the PLD. Some SoC chips, such as Altera's Cyclone V chip, provide such an interface. In various embodiments, the type of PLD 42 may be a Field Programmable Gate Array (FPGA).

In one embodiment, the processing core 21 and the PLD 42 form a motor controller, which cooperates to perform motor control tasks, controls the motor driver 31 according to the motor given value calculated by the processing core 21, and drives the motor 32 to reach the motor quickly and stably. requirements for a given value.

In various embodiments, motor control tasks may be distributed between processing core 21 and PLD 42 combined as a motor controller. When the combination of the processing core 21 and the PLD 42 is responsible for the calculation of the position loop, the calculation of the speed loop and the calculation of the current loop, the way of assigning the motor control tasks is for example: the processing core 21 is responsible for the calculation of the current loop, and the PLD 42 is responsible for the calculation of the speed loop and the position loop. calculation; or the processing core 21 is responsible for the position loop calculation and the velocity loop calculation, and the PLD 42 is responsible for the current loop calculation. When the combination of the processing core 21 and the PLD 42 is only responsible for a part of the position loop calculation, the velocity loop calculation and the current loop calculation, such as the velocity loop calculation and the current loop calculation, the assignment of tasks between the processing core 21 and the PLD 42 can be corresponding ground adjustment. For example, the processing core 21 is responsible for the speed loop calculation, and the PLD 42 is responsible for the current loop calculation. For other details of this embodiment, reference may be made to the first embodiment, which will not be described here.

FIG. 5 is an example operation process of the controller according to the second embodiment of the present invention. Referring to FIG. 5 , the processing core 21 may generate motion control data during the motion control process. The processing core 21 and the PLD 42 can further perform motor control according to the motion control data, generate a drive control signal to the motor driver 31, and the motor driver 31 outputs current to control the operation of the motor 32. Here, it is assumed that the processing core 21 handles the position loop and velocity loop calculations, while the PLD 42 handles the current loop calculations. Feedback data collected from the motor 32 can be fed back to the processing core 21 . Feedback data may include some or all of position data, velocity data, torque data, and current data. According to the application requirements, there can be no feedback data at all to form partial open-loop or full open-loop control, which will not affect the realization and performance of the basic functions of the entire control system. For other details of this embodiment, reference may be made to the first embodiment and the second embodiment, which will not be described here.

6 is a circuit block diagram of a controller according to a third embodiment of the present invention. Referring to FIG. 6 , the controller 60 of this embodiment may include a first processor 61 composed of a plurality of processing cores, a PLD 62 and a cache 63 . Different from the second embodiment, in this embodiment, a plurality of processing cores including processing cores 1 to N (N is a positive integer) are used as the first processor 61 to run the operating system in symmetric multiprocessing (SMP) mode.

For the first processor 61, the execution of the operating system and motion control tasks may be distributed among multiple processing cores. The PLD 62 is coupled to the first processor 61 and cooperates with the first processor 61 to perform motor control. Referring to the first embodiment, the PLD 62 can be omitted, and only the first processor 61 performs motor control at this time.

7 is a circuit block diagram of a controller according to a fourth embodiment of the present invention. Referring to FIG. 7 , the controller 70 of this embodiment may include a first processing core 21 , a second processing core 22 , a cache controller 23 , a cache (cache) 24 and a programmable logic device (PLD) 72 . The first processing core 21 is configured to execute the first operating system and motor control. The second processing core 22 is configured to execute a second operating system and motion control. The second operating system is different from the first operating system. The cache 24 is coupled to the first processing core 21 and the second processing core 22 . The first processing core 21 and the second processing core 22 are configured to exchange data through the cache 24 during motion control and motor control. The programmable logic device (PLD) 72 is coupled to the first processing core 21 , and forms a motor controller with the first processing core 21 to perform motor control in cooperation. The first processing core 21, the second processing core 22, the cache controller 23, the cache 24 and the PLD 72 are integrated in the same chip.

Different from the second embodiment, this embodiment introduces a second processing core 22 . The second processing core 22 runs a general-purpose operating system, such as a Linux system with real-time patches. This kind of operating system is ecologically sound, and its real-time performance is weak. The first processing core 21 still runs a small strong real-time system. According to the configuration of the first processing core 21 and the second processing core 22, both normally form an asymmetric multiplexing structure (AMP). The first processing core 41 completes functions such as motion task analysis and host computer communication. Specifically, after the user program is edited on the human-computer interaction interface of the upper computer, the upper computer transmits the user program to the controller 70 through the network cable, and the analysis of the program is completed by the second processing core 22. Commands are parsed into commands that the motion controller can recognize.

The file management functions such as system backup and recovery, classification, recording and management of data files and log files are implemented in the second processing core 22 .

The state management module runs on the second processing core 22 . The monitored states include the state of external devices, the state of the motion controller, and the state of the motor controller, etc. The controller 70 with integrated drive and control will perform corresponding processing according to the status collected by the status management module, and will also transmit some status information to the upper computer through the network.

By running the motion control task, the second processing core 22 can plan the position value, speed value, torque value or combination thereof at different times of each axis of the device controlled by the controller 70 as the motor given value. That is to say, the given value of the motor can be any one or several of the above three values. The second processing core 22 may output the corresponding motor given value to the first processing core 21 for execution at a predetermined time point (or a definite and definite amount of time in advance). In another embodiment, the first processing core 21 and the second processing core 22 coordinate to complete the motion planning task.

The first processing core 21 controls the motor driver according to the calculated motor given value, and drives the motor to meet the requirements of the motor given value quickly and stably. Current loop calculations, velocity loop calculations and/or position loop calculations are involved in motor control. The control loop that needs to be calculated varies according to the given value of the motor. In general, when the motor set value is the position value, all three loops are calculated; when the motor set value is the speed value, the current loop and the speed loop are calculated; when the motor set value is the torque, the current loop is calculated. Thereby, the motor control task of the motor controller can selectively perform current loop calculation, or current loop calculation and speed loop calculation, or current loop calculation and position loop calculation, or current loop calculation, speed loop calculation and position loop calculation. calculate. The tasks between the first processing core 21 and the PLD 42 can be allocated in various possible ways, such as the position loop calculation is performed in the first processing core 21, other loops are performed in the PLD 42, or both the position loop and the velocity loop are calculated in the first. Processing core 21 is performed while current loop calculations are performed at PLD 42. This mainly depends on the requirements of the control loop calculation rate and the performance constraints of the hardware platform.

In this embodiment, although the first processing core 21 and the second processing core 22 use the AMP mode, they can share the cache 24 . That is, the first processing core 21 and the second processing core 2242 are configured to perform data interaction through the cache 24 during motion control and motor control. Specifically, during motion control, the first processing core 21 can write motion control data (eg, motor given values) into the cache 24 , and the second processing core 22 can read the motion control data from the cache 24 . As previously mentioned, in each instance, the motion control data includes position data, velocity data, torque data, and/or current data, depending on the assignment of tasks between the first processing core 21 and the second processing core 22 . Accordingly, the first processing core 21 can write the feedback data into the cache 24 , and the second processing core 22 reads the feedback data from the cache 43 . Corresponding to the type of motion control data, the feedback data may include position data, velocity data, torque data and/or current data. For example, when the motion control data is position data, the feedback data generally includes position data, and may also include speed data and current data. When the motion control data is speed data, the feedback data generally includes speed data, and may also include position data and current data. It will of course be appreciated that the feedback data may be independent of the motion control data. For example, the feedback data normally includes any one or more of position data, speed data, torque data and current data; it is even feasible to directly feed back the position or attitude data of the end effector to the motion control processor according to the application situation ( For example, the attitude and speed of a drone, or the attitude and speed of an electric car).

In the embodiment not shown in the figure, the number of the first processing cores 21 and/or the second processing cores 22 may be multiple, so as to be expanded into multi-core first processors and/or second processors respectively.

FIG. 8 is an example operation process of the controller according to the fourth embodiment of the present invention. Referring to FIG. 8 , the second processing core 22 may generate motion control data to the first processing core 21 during the motion control process. The first processing core 21 and the PLD 72 can control the motor according to the motion control data, generate a drive control signal to the motor driver 31 , and the motor driver 31 outputs current to control the motor 32 to run. Here, it is assumed that the first processing core 21 handles the position loop and velocity loop calculations, while the PLD 72 handles the current loop calculations. The first feedback data collected from the motor 32 can be fed back to the first processing core 21 . The first processing core 21 may feed back the second feedback data to the second processing core 22 . The first feedback data may include some or all of position data, velocity data, torque data, and current data. The second feedback data may be derived entirely from the first feedback data. The second feedback data may also not come entirely from the first feedback data. For example, the second feedback data may include data generated by the first processing core 21 . According to application requirements, there may be no first feedback data or second feedback data at all, forming partial open-loop or full open-loop control, which will not affect the realization and performance of the basic functions of the entire control system.

9 is a flowchart of a method of operating motor control according to an embodiment of the present invention. Referring to Figure 9, the method includes the following steps:

In step 901, start the first processor;

At step 902, a first operating system is run on the first processor;

In step 903, the primitive of the first operating system is loaded into the cache by the cache controller, and the cache is locked;

At step 904, motor control is run in the interrupt service routine of the first processor.

According to the architecture of the aforementioned first embodiment, the first processor includes a single processing core 21 . At this point the method in step 902 further includes running the motion planning on the first processor.

According to the architecture of the aforementioned second embodiment, the controller further includes a PLD 42, and at this time it also includes performing motor control on the PLD 42 in cooperation with the first processor.

According to the architecture of the aforementioned third embodiment, the first processor includes a plurality of processing cores. At this point in step 902, the first operating system is run in the symmetric multiprocessing mode on the first processor, and the motion planning is executed.

According to the architecture of the aforementioned fourth embodiment, the controller further includes a second processor composed of the second processing core 22 . At this time, the method further includes: starting the second processor in step 901, and running a second operating system and motion control on the second processor in step 902, where the second operating system is different from the first operating system.

As mentioned above, the first operating system includes a code segment, a data segment, a first identifier and a second identifier, and is used to load operating system primitives and access data into a designated memory area. The implementation method of this step is shown in Figure 10, and includes the following steps. In step 1001, a code segment and a data segment are defined in the link file, and the code segment and the data segment respectively correspond to the designated memory areas. In step 1002, in the source code of the first operating system, a first identifier is added when defining the primitives of the first operating system, and the first identifier is used to designate the linker to put the primitives of the first operating system into the code segment; Step 1003 , in the source code of the first operating system, add a second identifier when defining the access data of the primitive of the first operating system, and the first identifier is used to designate the linker to put the access data in the data segment. In step 1004, the source code of the first operating system is compiled and linked into an executable program. In step 1005, after the first operating system is started, the data segment and the code segment are loaded into the designated memory area. At step 1006, the cache controller loads the data segment and the code segment from the designated memory area into the designated cache area. The flow of this step has been described above.

Flow diagrams are used in this application to illustrate operations performed by a system according to an embodiment of the application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Rather, the various steps may be processed in reverse order or concurrently. At the same time, other actions are either added to these processes, or a step or steps are removed from these processes.

The basic concept has been described above. Obviously, for those skilled in the art, the above disclosure of the invention is only an example, and does not constitute a limitation to the present application. Although not explicitly described herein, various modifications, improvements, and corrections to this application may occur to those skilled in the art. Such modifications, improvements, and corrections are suggested in this application, so such modifications, improvements, and corrections still fall within the spirit and scope of the exemplary embodiments of this application.

Meanwhile, the present application uses specific words to describe the embodiments of the present application. Such as "one embodiment," "an embodiment," and/or "some embodiments" means a certain feature, structure, or characteristic associated with at least one embodiment of the present application. Therefore, it should be emphasized and noted that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in different places in this specification are not necessarily referring to the same embodiment . Furthermore, certain features, structures or characteristics of the one or more embodiments of the present application may be combined as appropriate.

Some aspects of the present application may be performed entirely in hardware, entirely in software (including firmware, resident software, microcode, etc.), or in a combination of hardware and software. The above hardware or software may be referred to as a "data block", "module", "engine", "unit", "component" or "system". The processor may be one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DAPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors , controller, microcontroller, microprocessor, or a combination thereof. Furthermore, aspects of the present application may be embodied as a computer product comprising computer readable program code embodied in one or more computer readable media. For example, computer readable media may include, but are not limited to, magnetic storage devices (eg, hard disks, floppy disks, magnetic tapes, ...), optical disks (eg, compact disc CD, digital versatile disk DVD, ...), smart cards, and flash memory devices ( For example, cards, sticks, key drives...).

A computer-readable medium may contain a propagated data signal with the computer program code embodied therein, for example, on baseband or as part of a carrier wave. The propagating signal may take a variety of manifestations, including electromagnetic, optical, etc., or a suitable combination. A computer-readable medium can be any computer-readable medium other than a computer-readable storage medium that can communicate, propagate, or transmit a program for use by being coupled to an instruction execution system, apparatus, or device. Program code on a computer readable medium may be propagated by any suitable medium, including radio, cable, fiber optic cable, radio frequency signal, or the like, or a combination of any of the foregoing.

Similarly, it should be noted that, in order to simplify the expressions disclosed in the present application and thus help the understanding of one or more embodiments of the invention, in the foregoing description of the embodiments of the present application, various features are sometimes combined into one embodiment, in the drawings or descriptions thereof. However, this method of disclosure does not imply that the subject matter of the application requires more features than those mentioned in the claims. Indeed, there are fewer features of an embodiment than all of the features of a single embodiment disclosed above.

Some examples use numbers to describe quantities of ingredients and attributes, it should be understood that such numbers used to describe the examples, in some examples, use the modifiers "about", "approximately" or "substantially" to retouch. Unless stated otherwise, "about", "approximately" or "substantially" means that a variation of ±20% is allowed for the stated number. Accordingly, in some embodiments, the numerical parameters set forth in the specification and claims are approximations that can vary depending upon the desired characteristics of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and use a general digit reservation method. Notwithstanding that the numerical fields and parameters used in some embodiments of the present application to confirm the breadth of their ranges are approximations, in particular embodiments such numerical values are set as precisely as practicable.

Although the present application has been described with reference to the current specific embodiments, those skilled in the art should recognize that the above embodiments are only used to illustrate the present application, and can be made without departing from the spirit of the present application. Various equivalent changes or substitutions, therefore, as long as the changes and modifications to the above-mentioned embodiments within the spirit and scope of the present application, all fall within the scope of the claims of the present application.

Claims

A controller adapted to perform motor control, comprising:

a first processor configured to run a first operating system and a motor control, wherein the motor control runs in an interrupt service routine of the first processor;

a cache coupled to the first processor; and

a cache controller for loading primitives of the first operating system into the cache and locking the cache;

Wherein the first processor, the cache and the cache controller are integrated in the same chip.
The controller of claim 1, wherein the first processor comprises a single processing core, and wherein the first processor is further configured to execute motion planning.
The controller of claim 1, wherein the first processor includes a plurality of processing cores that run the first operating system in a symmetric multiprocessing mode and are further configured to run exercise planning.
The controller of claim 1, further comprising:

a second processor configured to run a second operating system and motion control, the second operating system being different from the first operating system;

Wherein the first processor and the second processor are integrated in the same chip.
5. The controller of claim 4, wherein the first processor includes a first combination of processing cores, the second processor includes a second combination of processing cores, the first combination of processing cores and the The second processing core groups each include one or more processing cores.
The controller according to any one of claims 1-5, further comprising a programmable logic device, coupled to the first processor, and performing motor control in cooperation with the first processor.
The controller of claim 6, wherein the programmable logic device is integrated with the first processor and the second processor in the same chip.
The controller of claim 1, wherein the motor control includes a current loop calculation, or a combination of a current loop calculation and a speed loop calculation and/or a position loop calculation.
6. The controller of claim 6, wherein the programmable controller performs current loop calculations, and the first processor performs velocity loop calculations and/or position loop calculations.
The controller of claim 1, further comprising at least a portion of the first operating system, comprising:

A code segment and a data segment, the code segment and the data segment respectively correspond to the specified memory area;

a first identifier, where the first identifier is used to specify that the linker puts the primitive of the first operating system into the code segment;

The second identifier is used to specify that the linker puts the access data of the primitive of the first operating system into the data segment;

The first operating system is configured to load the code segment and the data segment into the designated memory area after being started.
The controller of claim 1, wherein the step of the cache controller loading the primitives of the first operating system into the cache comprises:

disable the operation of the cache;

Allows the specified cache area to load data;

accessing a designated memory area to load primitives and access data of the first operating system in the memory area into the cache area; and

The cache is allowed to function properly.
A method of running motor control on a controller, the controller including a first processor, a cache controller, and a cache coupled to the first processor, and the first processor, the cache The cache and the cache controller are integrated in the same chip, and the method includes the following steps:

starting the first processor;

running the first operating system on the first processor;

Loading, by the cache controller, primitives of the first operating system into the cache and locking the cache; and

Motor control is run in an interrupt service routine of the first processor.
13. The method of claim 12, wherein the first processor comprises a single processing core, and wherein the method further comprises running motion planning on the first processor.
13. The method of claim 12, wherein the first processor includes a plurality of processing cores, wherein the first operating system is run in a symmetric multiprocessing mode on the first processor and a motion is executed planning.
The method according to claim 12, wherein the controller further comprises a second processor integrated with the first processor in the same chip, the method further comprising:

starting the second processor; and

A second operating system and motion control run on the second processor, the second operating system being different from the first operating system.
The method according to any one of claims 12-15, wherein the controller further comprises a programmable logic device coupled to the first processor and communicating with the first processor and the second processor The processor is integrated in the same chip, and the method further includes: performing motor control in cooperation with the first processor on the programmable logic device.
The method of claim 12, wherein the first operating system comprises:

A code segment and a data segment, the code segment and the data segment respectively correspond to the specified memory area;

a first identifier, where the first identifier is used to specify that the linker puts the primitive of the first operating system into the code segment;

The second identifier is used to specify that the linker puts the access data of the primitive of the first operating system into the data segment;

The method also includes loading, by the first operating system, the code segment and the data segment into the designated memory area.
The method of claim 12, wherein the method further comprises:

A code segment and a data segment are defined in the link file, and the code segment and the data segment respectively correspond to the specified memory areas;

In the source code of the first operating system, a first identifier is added when defining the primitives of the first operating system, and the first identifier is used to designate the linker to place the primitives of the first operating system in all in the above code segment;

In the source code of the first operating system, a second identifier is added when defining the access data of the primitives of the first operating system, and the first identifier is used to designate the linker to place the access data in the data segment;

The source code of the first operating system is compiled and linked into an executable program.
A control system comprising the controller of any one of claims 1-11.