CN113067527A

CN113067527A - Controller and control system adapted to perform motor control

Info

Publication number: CN113067527A
Application number: CN202110348872.7A
Authority: CN
Inventors: 贺岩; 龚劭秋; 钱进; 冯赟
Original assignee: Real Time Chivalrous Intelligent Control Technology Co ltd
Current assignee: Real Time Chivalrous Intelligent Control Technology Co ltd
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2021-07-02
Also published as: WO2022206214A1

Abstract

The invention provides a controller and a control system suitable for executing motor control. The controller includes: a first processor configured to run a first operating system and a motor control, wherein the motor control runs in an interrupt service routine of the first processor; a cache coupled to the first processor; a cache controller for loading primitives of the first operating system into the cache and locking the cache; wherein the first processor, the cache, and the cache controller are integrated in the same chip.

Description

Controller and control system adapted to perform motor control

Technical Field

The present invention relates generally to controllers, and more particularly to a controller and control system adapted to perform motor control.

Background

Motion control and motor control are core technologies in the field of industrial automation. A motion controller for realizing motion control and a motor controller for realizing motor control are two key control components on a device for automatically executing complex work, which are common in the field of automation at present. Controllers including motion control and motor control are also used in other fields, such as electric robots, numerically controlled machines, electric multi-rotor aircraft, electric vehicles, mechanical prosthetics, mechanical palms, electric mobile vehicles.

Traditionally, most industrial automation systems (e.g., robots, large machine tools) employ a distributed control approach. The distributed control mode is that one motion controller is matched with a plurality of motor controllers. Communication between the motion controller and the motor controller, and between the motor controller and the motor controller, is performed using a bus (e.g., a field bus).

This distributed control has a number of known disadvantages. For example, the hardware cost and the occupied space are large due to the large number of hardware devices. As another example, the bus communication method is susceptible to interference, and there is a bottleneck in terms of data transmission amount and transmission speed.

Therefore, the industry has proposed an idea of "driving and controlling integrated", and it is desirable to realize an industrial controller integrating functions such as a motion controller and a motor controller. Meanwhile, motion control and motor control are realized, and an operating system is required to provide basic services such as task scheduling, file management, network communication and the like. And the motor control task is executed in a fixed period, and the allowable delay of the task is small in order to ensure the performance of the motor control.

Disclosure of Invention

The technical problem to be solved by the application is to provide a controller and a control system suitable for executing motor control, which can meet the low delay requirement of the motor control.

In order to solve the above technical problem, the present application provides a controller adapted to perform motor control, including: a first processor configured to run a first operating system and a motor control, wherein the motor control runs in an interrupt service routine of the first processor; a cache coupled to the first processor; a cache controller for loading primitives of the first operating system into the cache and locking the cache; wherein the first processor, the cache, and the cache controller are integrated in the same chip.

In an embodiment of the application, the first processor comprises a single processing core and the first processor is further configured to run a motion plan.

In an embodiment of the application, the first processor includes a plurality of processing cores that run the first operating system in a symmetric multiprocessing mode and that are further configured to run an exercise plan.

In an embodiment of the present application, the controller further includes: a second processor configured to run a second operating system and motion control, the second operating system being different from the first operating system; wherein the first processor and the second processor are integrated in the same chip.

In an embodiment of the application, the first processor comprises a first processing core combination, the second processor comprises a second processing core combination, and the first processing core combination and the second processing core combination respectively comprise one or more processing cores.

In an embodiment of the present application, the controller further includes a programmable logic device, coupled to the first processor, and configured to cooperate with the first processor to perform motor control.

In an embodiment of the application, the programmable logic device is integrated in the same chip as the first processor and the second processor.

In an embodiment of the application, the motor control comprises a current loop calculation, or a combination of a current loop calculation and a speed loop calculation and/or a position loop calculation.

In an embodiment of the application, the programmable controller performs a current loop calculation and the first processor performs a velocity loop calculation and/or a position loop calculation.

In an embodiment of the application, the controller further comprises at least a portion of said first operating system, which comprises: the system comprises a code segment and a data segment, wherein the code segment and the data segment respectively correspond to a designated memory area; a first identifier for specifying a linker to place a primitive of the first operating system into the code segment; a second identifier for specifying a linker to place access data of a primitive of the first operating system into the data segment; wherein the first operating system is configured to load the code segments and data segments into the designated memory area after booting.

In an embodiment of the present application, the step of loading, by the cache controller, the primitive of the first operating system into the cache includes: disabling operation of the cache; allowing the specified cache region to load data; accessing a designated memory region to load primitives and access data of the first operating system in the memory region into the cache region; and allowing the cache to function properly.

Another aspect of the present application provides a method of operating motor control on a controller, the controller including a first processor, a cache controller, and a cache coupled to the first processor, and the first processor, the cache, and the cache controller being integrated in a same chip, the method including: starting the first processor; running the first operating system on the first processor; loading, by the cache controller, primitives of the first operating system into the cache and locking the cache; and running motor control in an interrupt service routine of the first processor.

In an embodiment of the application, the first processor comprises a single processing core, and the method further comprises running a motion plan at the first processor.

In an embodiment of the present application, the first processor includes a plurality of processing cores, wherein the first operating system is run in a symmetric multiprocessing mode on the first processor and a motion plan is run.

In an embodiment of the present application, the controller further includes a second processor integrated in the same chip as the first processor, and the method further includes: starting the second processor; and running a second operating system and motion control on the second processor, the second operating system being different from the first operating system.

In an embodiment of the application, the controller further includes a programmable logic device coupled to the first processor and integrated in the same chip as the first processor and the second processor, and the method further includes: performing motor control on the programmable logic device in cooperation with the first processor.

In an embodiment of the present application, the first operating system includes: the system comprises a code segment and a data segment, wherein the code segment and the data segment respectively correspond to a designated memory area; a first identifier for specifying a linker to place a primitive of the first operating system into the code segment; a second identifier for specifying a linker to place access data of a primitive of the first operating system into the data segment; the method also includes loading the code segments and data segments into the designated memory area by the first operating system.

In an embodiment of the present application, the method further includes: defining a code segment and a data segment in a link file, wherein the code segment and the data segment respectively correspond to a designated memory area; in the source code of the first operating system, adding a first identifier when defining the primitive of the first operating system, wherein the first identifier is used for specifying a linker to put the primitive of the first operating system into the code segment; adding a second identifier when defining access data of the primitive of the first operating system in the source code of the first operating system, wherein the first identifier is used for specifying a linker to place the access data into the data segment; and compiling the source code of the first operating system and linking the source code into an executable program.

Another aspect of the application proposes a control system comprising a controller as described above.

Compared with the prior art, the invention runs the strong real-time tasks required by the motor control through the interrupt service program of the processor. And the operating system primitives are loaded into the cache and locked, reducing the execution time of this portion of the operating system primitives so that their operation of masking interrupt service when executed does not cause the interrupts required for motor control to be delayed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the principle of the application. In the drawings:

fig. 1 is a logical structure of a controller according to an embodiment of the present invention.

Fig. 2 is a circuit block diagram of a controller according to a first embodiment of the present invention.

Fig. 3 is an example operation of the controller according to the first embodiment of the present invention.

Fig. 4 is a circuit block diagram of a controller according to a second embodiment of the present invention.

Fig. 5 is an example operation of a controller according to a second embodiment of the present invention.

Fig. 6 is a circuit block diagram of a controller according to a third embodiment of the present invention.

Fig. 7 is a circuit block diagram of a controller according to a fourth embodiment of the present invention.

Fig. 8 is an exemplary operation of a controller according to a fourth embodiment of the present invention.

FIG. 9 is a flow chart of a method of operating a motor control according to an embodiment of the present invention.

FIG. 10 is a flow diagram of a method for loading operating system primitives into a cache in accordance with one embodiment of the present invention.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only examples or embodiments of the application, from which the application can also be applied to other similar scenarios without inventive effort for a person skilled in the art. Unless otherwise apparent from the context, or otherwise indicated, like reference numbers in the figures refer to the same structure or operation.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

The relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood not only by the actual terms used but also by the meaning of each term lying within.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is referred to as being "in electrical contact" or "electrically coupled" to a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.

Embodiments of the present invention describe a controller that includes motion control and motor control functions. Fig. 1 is a logical structure of a controller according to an embodiment of the present invention. As understood by those skilled in the art, motion control functionality refers to calculating the motion targets of all motor shafts of a device over time, depending on the particular application task. The calculation steps, calculation objects and calculated parameter variables may also be different according to different specific applications, but the final purpose is to obtain the relationship between the motor set value and time and generate a corresponding data stream (data information) of the motor set value-time of each shaft. The motor set value can be any one or more of the rotation angle position, the rotation speed and the torque of the motor.

The motor set value is issued to the motor control function to be executed on time at the corresponding time point. The motor control function is to control the drive circuit according to the set value calculated by the motion control, so that the drive motor can quickly and stably reach the requirement of the set value. The motor control involves "current loop", "speed loop" and "position loop" calculations. The control loop required to be calculated is different according to different given values. In general, when the given value is an angle value, all three rings are calculated; when the given value is a speed value, calculating a current loop and a speed loop; and when the given value is the moment, calculating a current loop. The most basic system will therefore have at least a current loop. The motor control function can receive and process the data information of the motor set value of each shaft in real time and control the rotation of the motor, and when all the shafts reach the set value (possibly an angle value, and possibly a speed or a moment) at the set time point, the resultant motion finally reflected on the terminal execution is the required state of the application task. For a device or system that requires coordination of the axes, it is desirable to simultaneously calculate and control all axes simultaneously so that the end effector motion resulting from the coordination of the axes is accurate.

Referring to fig. 1, a controller 10 according to an embodiment of the present invention may include a motion controller 11 and a motor controller 12. The motion controller 11 may perform the aforementioned motion control functions. The motor controller 12 may perform the motor control functions previously described. A Teach Pendant (TP) is an upper computer of the motion controller 11, and is used to send an application task instruction to the motion controller 11 or to edit a plan control. The motion controller 11 receives commands from the teach pendant, performs motion planning based thereon, and sends motion control data, such as the aforementioned shaft motor set values, to the motor controller 12. The motor controller 12 may accordingly generate a drive control signal (e.g., a Pulse Width Modulation (PWM) signal) to the motor driver 13, which drives the motor to operate.

In the embodiments of the present invention, the controller 10 may be applied to an electric robot, a numerical control machine tool, an electric multi-rotor aircraft, an electric vehicle, a mechanical prosthesis, a mechanical palm, an electric mobile vehicle, and the like, and is used for the motion task calculation control and the motor control of various multi-axis, inter-axis motion coordination, motor-driven devices.

In each embodiment of the present invention, the number of shafts of the motor is not limited, and may be 6 shafts or 8 shafts, or fewer shafts, or more shafts.

In the context of the present application, the processing core is a Central Processing Unit (CPU). A Central Processing Unit (CPU) may include a Cache, such as a level one Cache (L1 Cache). In the context of this application, a cache (cache memory), as is generally understood by those skilled in the art, is a memory that exists between a main memory (memory) and a processor, at a much higher speed than the main memory, close to the speed of the processor. A level two Cache (L2 Cache) in the processor may be used as an additional Cache. Communication between the CPUs may be achieved using a second level cache coupled to the plurality of CPUs.

Fig. 2 is a circuit block diagram of a controller according to a first embodiment of the present invention. Referring to fig. 2, an integrated motion control and motor control controller 20 of the present embodiment may include a processing core 21, a cache controller 23, and a cache (cache) 24. The single processing core 21, as a first processor in the present embodiment, is configured to run a first operating system, motion control, and motor control. Cache 24 is a second level cache between processing core 21 and memory. It will be appreciated that the cache 24 may be other levels of cache. The cache 24 is coupled to the processing core 21. The processing core 21, the cache controller 23, and the cache (cache)24 are integrated in the same chip.

In this embodiment, the processing core 21 runs an operating system and performs motion control and motor control tasks. The operating system can manage the operation of the whole controller and complete the basic functions of network communication, file management, equipment management, task scheduling, system debugging and the like. Specific application tasks, such as motion control tasks, may be run on the operating system. The motion control task can calculate the motion targets of all motor shafts of the equipment where the controller is located over time. The implementation of the motion control task can be varied. For example, different specific planning algorithm modules can be selectively embedded according to different application requirements, task analysis software is developed, and various path planning and joint space transformation are performed. The specific algorithms for path planning and joint space transformation may also vary greatly depending on the application. For example, an industrial robot can use kinematics and inverse solution algorithm thereof, and the unmanned aerial vehicle can realize suspension and forward path planning variables and joint transformation algorithm by adjusting the rotating speed of each shaft motor. The skilled person is fully enabled to design the motion control functionality according to the specific application requirements.

In this embodiment, the operating system is a small, strong real-time system, such as RTThread.

The processing core 21 may, by running the motion control task, formulate a position value, a velocity value, a torque value, or a combination thereof, at different times for each axis of the device controlled by the controller 20 as a motor setpoint. That is, the motor setpoint may be any one or more of the 3 values previously described.

The processing core 21 can execute a motor control task, and control a motor driver according to the calculated motor set value, so that the driving motor can quickly and stably meet the requirement of the motor set value. In the present embodiment, the motor control 26 is executed in the interrupt service routine 25 of the processing core 21. In particular, a certain clock interrupt is designated as a high (e.g., highest) priority interrupt that can preempt other interrupt service routines, with the strong real-time tasks of motor control running in the interrupt service routine 25. In this way, the strong real-time requirements for motor control can be met.

The motor control may involve current loop calculations, speed loop calculations and/or position loop calculations. The control loop required to be calculated is different according to different set values of the motor. In general, when the given value of the motor is a position value, all three rings are calculated; when the given value of the motor is a speed value, calculating a current loop and a speed loop; and when the given value of the motor is the torque, calculating a current loop. Thus, the motor control task of the processing core 21 may selectively perform current loop calculations, or a combination of current loop calculations and velocity loop calculations and/or position loop calculations. The processing core 21 calculates the current required by the driving motor to reach the position, speed or torque required by the given value of the required motor, and outputs a driving control signal (such as a PWM signal) to an IGBT or IPM or other types of power devices according to the calculation result to drive the motor.

In the core part of the small and strong real-time system run by the processing core 21, there is a critical code segment, an operating system primitive, that needs to be masked from interrupts. Primitives are instructions that call core layer subroutines in the operating system. The difference with a generic generalized instruction is that the primitive is not interruptible and always appears as a basic unit. It differs from the general process in that: they are "atomic or atomic operations". An atomic operation is an operation in which all actions are either done or not done. In other words, a primitive is an indivisible basic unit and is therefore not allowed to be interrupted during execution. Atomic operations are performed in a managed state, residing in memory. In this embodiment, the operating system primitives and the data they access (read and/or write) are loaded into cache 24 to ensure that their execution time is sufficiently short. Referring to FIG. 2, the cache controller 23 loads the operating system primitives 24a from the memory 30 into the cache 24 and locks the cache 24.

In one embodiment, the operating system includes a code segment and a data segment, each corresponding to a designated memory region. For example: a code segment name is defined as 'RTcode' and a data segment name is defined as 'RTdata'. The operating system also includes a first identifier and a second identifier. The first identifier is used to specify that the linker places the operating system primitive 24a into the aforementioned code fragment, which is, for example, in the format of __ attribute __ (section (". RTcode")). The second identifier is used to specify that the linker places the access data of the operating system primitive in a data segment, for example, in the format of __ attribute __ (". RTdata")). In one embodiment, the operating system source code is modified to include the above-described portions. The operating system source code is then compiled and linked into an executable program. The operating system is configured to load code and data segments into designated memory areas in memory 30 after boot-up.

During initialization after program startup, cache controller 23 loads operating system primitives into cache 24. The specific process comprises the following steps: disabling the operation of cache 24; allowing the specified cache region to load data; accessing a specified memory region in memory 30 to load primitives and access data for the operating system in the memory region to a specified cache region in cache 24; allowing cache 24 to function properly. After these steps are completed, it is ensured that the memory region where the code and the access data of the operating system primitive are located is mapped to the cache 24, and the code and the access data of the operating system primitive are also loaded to the cache 24. The cache controller 23 may then lock the designated cache region so that its mapped memory address does not change, thereby preventing the controller from mapping the cache region to other addresses.

In some embodiments, the execution time of the operation primitive is less than 1 microsecond (μm).

In one embodiment, lock-free queues are used when streaming data from non-real-time tasks to strong real-time motor control tasks, thereby reducing latency. And in turn, the non-real-time task reads the feedback data of the strong real-time motor control task and performs writing control on the data.

Fig. 3 is an example operation of the controller according to the first embodiment of the present invention. Referring to fig. 3, the processing core 21 generates motion control data during the motion control process, performs motor control according to the motion control data, generates a driving control signal to the motor driver 31, and controls the operation of the motor 32 by outputting a current from the motor driver 31. Feedback data collected from motor 32 may be fed back to processing core 21. The feedback data may include some or all of position data, velocity data, torque data, and current data.

Fig. 4 is a circuit block diagram of a controller according to a second embodiment of the present invention. Referring to fig. 4, an integrated motion control and motor control controller 40 of the present embodiment may further include a processing core 21, a cache controller 23, a cache 24, and a Programmable Logic Device (PLD) 42. A processing core 21 configured to execute an operating system, motion control, and motor control. PLD42 is coupled to processing core 21 and cooperates with processing core 21 to provide motor control. In this embodiment, processing core 21, cache controller 23, cache 24, and PLD42 are integrated in the same processing chip.

Unlike the previous embodiment, this embodiment introduces PLD42, and PLD42 has the feature of fast parallel computation, so that it is a significant advantage when the number of motor shafts is large. PLD42 couples to processing core 21 to achieve coordination. The coupling is realized, for example, by an interface 41 between the processor and the PLD. Some SoC chips, such as the Altera corporation Cyclone V chip, provide such an interface. In various embodiments, PLD42 may be of the type Field Programmable Gate Array (FPGA).

In one embodiment, the processing core 21 and the PLD42 form a motor controller to cooperatively perform a motor control task, and the motor driver 31 is controlled according to the motor set value calculated by the processing core 21, so that the driving motor 32 can quickly and stably reach the motor set value.

In various embodiments, motor control tasks may be distributed between processing core 21 and PLD42 combined as a motor controller. When the combination of processing core 21 and PLD42 is cooperatively responsible for position loop calculation, velocity loop calculation, and current loop calculation, the manner of assigning motor control tasks is, for example: the processing core 21 is responsible for current loop calculation, and the PLD42 is responsible for speed loop calculation and position loop calculation; or processing core 21 is responsible for position loop calculations and velocity loop calculations and PLD42 is responsible for current loop calculations. When the combination of processing core 21 and PLD42 is cooperatively responsible for only a portion of the position loop calculation, velocity loop calculation, and current loop calculation, such as velocity loop calculation and current loop calculation, the distribution of tasks between processing core 21 and PLD42 may be adjusted accordingly. For example, processing core 21 is responsible for speed loop calculations and PLD42 is responsible for current loop calculations. Further details of this embodiment can be found in the first embodiment and will not be expanded upon.

Fig. 5 is an example operation of a controller according to a second embodiment of the present invention. Referring to fig. 5, the processing core 21 may generate motion control data during motion control. Processing core 21 and PLD42 may further perform motor control based on the motion control data, generate drive control signals to motor driver 31, and control operation of motor 32 by outputting current from motor driver 31. Here, assume that processing core 21 processes position loop and velocity loop calculations, while PLD42 processes current loop calculations. Feedback data collected from motor 32 may be fed back to processing core 21. The feedback data may include some or all of position data, velocity data, torque data, and current data. According to application requirements, feedback data can be completely absent, and local open-loop or full open-loop control is formed, so that the implementation of basic functions of the whole control system and the performance of the basic functions can not be influenced. Further details of this embodiment may be found in reference to the first and second embodiments and will not be expanded upon herein.

Fig. 6 is a circuit block diagram of a controller according to a third embodiment of the present invention. Referring to fig. 6, the controller 60 of the present embodiment may include a first processor 61 composed of a plurality of processing cores, a PLD62, and a cache 63. Unlike the second embodiment, in the present embodiment, a plurality of processing cores including processing cores 1 to N (N is a positive integer) are used as the first processor 61, and the operating system is operated in a Symmetric Multiprocessing (SMP) mode.

For the first processor 61, the operation of the operating system and motion control tasks may be distributed among multiple processing cores. The PLD62 is coupled to the first processor 61 and performs motor control in cooperation with the first processor 61. Referring to the first embodiment, PLD62 may be omitted, in which case motor control is performed only by first processor 61.

Fig. 7 is a circuit block diagram of a controller according to a fourth embodiment of the present invention. Referring to fig. 7, the controller 70 of the present embodiment may include a first processing core 21, a second processing core 22, a cache controller 23, a cache (cache)24, and a Programmable Logic Device (PLD) 72. A first processing core 21 configured to execute a first operating system and motor control. A second processing core 22 configured to execute a second operating system and motion control. The second operating system is different from the first operating system. The cache 24 is coupled to the first processing core 21 and the second processing core 22. The first processing core 21 and the second processing core 22 are configured to perform data interaction through the cache 24 during motion control and motor control. The Programmable Logic Device (PLD)72 is coupled to the first processing core 21, and forms a motor controller with the first processing core 21 to cooperatively control the motor. The first processing core 21, the second processing core 22, the cache controller 23, the cache 24, and the PLD72 are integrated in the same chip.

Unlike the second embodiment, the present embodiment introduces the second processing core 22. The second processing core 22 runs a general purpose operating system, such as the Linux system with real-time patches. The operating system is complete in ecology and weak in instantaneity. The first processing core 21 still runs a small, strong real-time system. The first processing core 21 and the second processing core 22 normally form an asymmetric multi-path processing Architecture (AMP) according to their configuration. The first processing core 41 performs functions such as motion task analysis and upper computer communication. Specifically, after the user program is edited on the human-computer interaction interface of the upper computer, the upper computer transmits the user program to the controller 70 through the network cable, the program is analyzed by the second processing core 22, and the second processing core 22 analyzes the user instruction into an instruction which can be recognized by the motion controller.

File management functions such as backup and restore of the system, and classification recording and management of data files and log files are implemented in the second processing core 22.

The state management module operates in the second processing core 22. The monitored states include the state of the external device, the state of the motion controller, the state of the motor controller, and the like. The controller 70 performs corresponding processing according to the state collected by the state management module, and transmits some state information to the upper computer through the network.

The second processing core 22 may schedule, by running the motion control task, position values, speed values, torque values, or combinations thereof, at different times for various axes of the device controlled by the controller 70 as motor setpoints. That is, the motor setpoint may be any one or more of the 3 values previously described. The second processing core 22 may output the corresponding motor setpoint to the first processing core 21 for execution at a predetermined point in time (or a determined, unambiguous amount of time ahead). In another embodiment, the first processing core 21 and the second processing core 22 coordinate the completion of the motion planning task.

The first processing core 21 controls the motor driver according to the calculated motor set value, and drives the motor to quickly and stably meet the requirement of the motor set value. The motor control may involve current loop calculations, speed loop calculations and/or position loop calculations. The control loop required to be calculated is different according to different set values of the motor. In general, when the given value of the motor is a position value, all three rings are calculated; when the given value of the motor is a speed value, calculating a current loop and a speed loop; and when the given value of the motor is the torque, calculating a current loop. Therefore, the motor control task of the motor controller can selectively perform current loop calculation, or perform current loop calculation and speed loop calculation, or perform current loop calculation and position loop calculation, or perform current loop calculation, speed loop calculation and position loop calculation. The tasks between first processing core 21 and PLD42 may be distributed as various possibilities, such as the position loop calculation being performed at first processing core 21 and the other loops at PLD42, or both the position loop and velocity loop calculation being performed at first processing core 21 and the current loop calculation being performed at PLD 42. This depends mainly on the control loop computation rate requirements and the performance limitations of the hardware platform.

In the present embodiment, the first processing core 21 and the second processing core 22 may share the cache 24 although they use the AMP mode. I.e., the first processing core 21 and the second processing core 2242, are configured to perform data interaction through the cache 24 during motion control and motor control. Specifically, during motion control, the first processing core 21 may write motion control data (e.g., motor set points) to the cache 24, and the second processing core 22 may read the motion control data from the cache 24. As previously described, in various examples, the motion control data includes position data, velocity data, torque data, and/or current data, depending on the task allocation between the first processing core 21 and the second processing core 22. Accordingly, the first processing core 21 may write the feedback data into the cache 24 and the second processing core 22 reads the feedback data from the cache 43. The feedback data may include position data, velocity data, torque data, and/or current data, corresponding to the type of motion control data. For example, when the motion control data is position data, the feedback data typically includes position data, and may also include velocity data, current data. When the motion control data is velocity data, the feedback data typically includes velocity data, and may also include position data, current data. It will of course be appreciated that the feedback data may be independent of the motion control data. For example, the feedback data normally includes any one or more of position data, speed data, torque data and current data; it is even possible to directly feed back the position or attitude data of the end effector to the motion control processor (e.g., the attitude, velocity of the drone, or the attitude, velocity of the electric vehicle) depending on the application needs.

In an embodiment not shown in the figure, the number of the first processing core 21 and/or the second processing core 22 may be plural, and thus extend to a first processor and/or a second processor with multiple cores, respectively.

Fig. 8 is an exemplary operation of a controller according to a fourth embodiment of the present invention. Referring to fig. 8, the second processing core 22 may generate motion control data to the first processing core 21 during the motion control process. The first processing core 21 and the PLD72 may perform motor control according to the motion control data, generate a drive control signal to the motor driver 31, and output a current from the motor driver 31 to control the operation of the motor 32. Here, it is assumed that the first processing core 21 processes position loop and velocity loop calculations, while PLD72 processes current loop calculations. The first feedback data collected from the motor 32 may be fed back to the first processing core 21. The first processing core 21 may feed back the second feedback data to the second processing core 22. The first feedback data may include some or all of position data, velocity data, torque data, and current data. The second feedback data may be entirely from the first feedback data. The second feedback data may not be entirely from the first feedback data. For example the second feedback data may comprise data generated by the first processing core 21. According to application requirements, the first feedback data or the second feedback data can be completely absent, and local open-loop or full open-loop control is formed, so that the implementation of basic functions of the whole control system and the performance of the basic functions are not influenced.

FIG. 9 is a flow chart of a method of operating a motor control according to an embodiment of the present invention. Referring to fig. 9, the method includes the steps of:

at step 901, a first processor is started;

at step 902, running a first operating system on a first processor;

in step 903, loading the primitive of the first operating system to the cache through the cache controller, and locking the cache;

at step 904, motor control is run in the interrupt service routine of the first processor.

According to the architecture of the foregoing first embodiment, the first processor comprises a single processing core 21. At this point the method also includes running the motion plan at the first processor in step 902.

According to the architecture of the second embodiment described above, the controller further includes PLD42, which in this case also includes motor control on PLD42 in cooperation with the first processor.

According to the architecture of the foregoing third embodiment, the first processor includes a plurality of processing cores. At this point, in step 902, a first operating system is run in a symmetric multiprocessing mode on a first processor and a motion plan is run.

According to the architecture of the foregoing fourth embodiment, the controller further comprises a second processor comprised of a second processing core 22. At this time, the method further comprises: a second processor is started in step 901 and a second operating system and motion control is run on the second processor in step 902, the second operating system being different from the first operating system.

As described above, the first operating system includes a code segment, a data segment, a first identifier, and a second identifier for loading operating system primitives and access data into a specified memory region. The implementation of this step is shown in fig. 10 and includes the following steps. In step 1001, a code segment and a data segment are defined in a link file, and the code segment and the data segment correspond to the designated memory area respectively. In step 1002, in source code of the first operating system, adding a first identifier when defining a primitive of the first operating system, wherein the first identifier is used for specifying a linker to put the primitive of the first operating system into a code segment; in step 1003, in the source code of the first operating system, a second identifier is added when defining the access data of the primitive of the first operating system, and the first identifier is used for specifying a linker to put the access data into a data segment. At step 1004, source code for the first operating system is compiled and linked into an executable program. In step 1005, the first operating system loads the data segment and the code segment into the designated memory area after booting. At step 1006, the cache controller loads the data segments and code segments from the specified memory region into the specified cache region. The flow of this step has been described above.

Flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.

Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.

Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.

Aspects of the present application may be embodied entirely in hardware, entirely in software (including firmware, resident software, micro-code, etc.) or in a combination of hardware and software. The above hardware or software may be referred to as "data block," module, "" engine, "" unit, "" component, "or" system. The processor may be one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), digital signal processing devices (DAPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, or a combination thereof. Furthermore, aspects of the present application may be represented as a computer product, including computer readable program code, embodied in one or more computer readable media. For example, computer-readable media may include, but are not limited to, magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips … …), optical disks (e.g., Compact Disk (CD), Digital Versatile Disk (DVD) … …), smart cards, and flash memory devices (e.g., card, stick, key drive … …).

The computer readable medium may comprise a propagated data signal with the computer program code embodied therein, for example, on a baseband or as part of a carrier wave. The propagated signal may take any of a variety of forms, including electromagnetic, optical, and the like, or any suitable combination. The computer readable medium can be any computer readable medium that can communicate, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or device. Program code on a computer readable medium may be propagated over any suitable medium, including radio, electrical cable, fiber optic cable, radio frequency signals, or the like, or any combination of the preceding.

Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.

Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.

Although the present application has been described with reference to the present specific embodiments, it will be recognized by those skilled in the art that the foregoing embodiments are merely illustrative of the present application and that various changes and substitutions of equivalents may be made without departing from the spirit of the application, and therefore, it is intended that all changes and modifications to the above-described embodiments that come within the spirit of the application fall within the scope of the claims of the application.

Claims

1. A controller adapted to perform motor control, comprising:

a first processor configured to run a first operating system and a motor control, wherein the motor control runs in an interrupt service routine of the first processor;

a cache coupled to the first processor; and

a cache controller for loading primitives of the first operating system into the cache and locking the cache;

wherein the first processor, the cache, and the cache controller are integrated in the same chip.

2. The controller of claim 1, wherein the first processor comprises a single processing core, and wherein the first processor is further configured to run a motion plan.

3. The controller of claim 1, wherein the first processor comprises a plurality of processing cores that run the first operating system in a symmetric multiprocessing mode and that are further configured to run an exercise plan.

4. The controller of claim 1, further comprising:

a second processor configured to run a second operating system and motion control, the second operating system being different from the first operating system;

wherein the first processor and the second processor are integrated in the same chip.

5. The controller of claim 4, wherein the first processor comprises a first combination of processing cores and the second processor comprises a second combination of processing cores, and wherein the first combination of processing cores and the second combination of processing cores each comprise one or more processing cores.

6. The controller of any one of claims 1-5, further comprising a programmable logic device coupled to the first processor and configured to cooperate with the first processor to control the motor.

7. The controller of claim 6, wherein the programmable logic device is integrated in the same chip as the first processor and the second processor.

8. A controller according to claim 1, characterised in that the motor control comprises a current loop calculation or a combination of a current loop calculation and a speed loop calculation and/or a position loop calculation.

9. The controller of claim 6, wherein the programmable controller performs a current loop calculation and the first processor performs a velocity loop calculation and/or a position loop calculation.

10. The controller of claim 1, further comprising at least a portion of the first operating system, comprising:

the system comprises a code segment and a data segment, wherein the code segment and the data segment respectively correspond to a designated memory area;

a first identifier for specifying a linker to place a primitive of the first operating system into the code segment;

a second identifier for specifying a linker to place access data of a primitive of the first operating system into the data segment;

wherein the first operating system is configured to load the code segments and data segments into the designated memory area after booting.

11. The controller of claim 1, wherein the step of the cache controller loading the primitives of the first operating system into the cache comprises:

disabling operation of the cache;

allowing the specified cache region to load data;

accessing a designated memory region to load primitives and access data of the first operating system in the memory region into the cache region; and

allowing the cache to function properly.

12. A method of operating motor control on a controller, the controller including a first processor, a cache controller, and a cache coupled to the first processor, and the first processor, the cache, and the cache controller integrated in a same chip, the method comprising:

starting the first processor;

running the first operating system on the first processor;

loading, by the cache controller, primitives of the first operating system into the cache and locking the cache; and

running motor control in an interrupt service routine of the first processor.

13. The method of claim 12, wherein the first processor comprises a single processing core, and further comprising running a motion plan at the first processor.

14. The method of claim 12, wherein the first processor comprises a plurality of processing cores, wherein the first operating system is run in a symmetric multiprocessing mode on the first processor, and wherein the motion plan is run.

15. The method of claim 12, wherein the controller further comprises a second processor integrated in the same chip as the first processor, the method further comprising:

starting the second processor; and

running a second operating system and motion control on the second processor, the second operating system being different from the first operating system.

16. The method of any of claims 12-15, wherein the controller further comprises a programmable logic device coupled to the first processor and integrated in the same chip as the first processor and the second processor, the method further comprising: performing motor control on the programmable logic device in cooperation with the first processor.

17. The method of claim 12, wherein the first operating system comprises:

the method also includes loading the code segments and data segments into the designated memory area by the first operating system.

18. The method of claim 12, wherein the method further comprises:

defining a code segment and a data segment in a link file, wherein the code segment and the data segment respectively correspond to a designated memory area;

in the source code of the first operating system, adding a first identifier when defining the primitive of the first operating system, wherein the first identifier is used for specifying a linker to put the primitive of the first operating system into the code segment;

adding a second identifier when defining access data of the primitive of the first operating system in the source code of the first operating system, wherein the first identifier is used for specifying a linker to place the access data into the data segment;

and compiling the source code of the first operating system and linking the source code into an executable program.

19. A control system comprising a controller as claimed in any one of claims 1 to 11.