WO2022200872A1 - Electrostatic protection device - Google Patents
Electrostatic protection device Download PDFInfo
- Publication number
- WO2022200872A1 WO2022200872A1 PCT/IB2022/051103 IB2022051103W WO2022200872A1 WO 2022200872 A1 WO2022200872 A1 WO 2022200872A1 IB 2022051103 W IB2022051103 W IB 2022051103W WO 2022200872 A1 WO2022200872 A1 WO 2022200872A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- coil
- circuit
- protection device
- electrostatic protection
- stacked
- Prior art date
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- 230000008878 coupling Effects 0.000 claims description 12
- 238000010168 coupling process Methods 0.000 claims description 12
- 238000005859 coupling reaction Methods 0.000 claims description 12
- 230000001939 inductive effect Effects 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000001465 metallisation Methods 0.000 claims description 5
- 230000009286 beneficial effect Effects 0.000 description 11
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Definitions
- the present invention relates to integrated circuits, in particular to the electrostatic protection of input ports for integrated circuits.
- Integrated circuits may incorporate dedicated circuitry to protect them against Electrostatic Discharge (ESD) events at their input/output (I/O) pads.
- ESD Electrostatic Discharge
- I/O input/output
- ESD protection devices in integrated circuits often comprise devices such as inductors and coils. As the dimensions of integrated circuits shrink and clock rates increase, it is difficult or sometimes not even possible to scale the designs of ESD protection devices. Existing ESD protection device designs often do not provide the necessary bandwidth.
- the invention relates to an electrostatic protection device for protecting an input port of an electronic circuit.
- the electronic protection device comprises a first stacked coil and a second stacked coil.
- the first stacked coil and the second stacked coil may be stacked upon each other.
- Formed in an integrated circuit, the first stacked coil and the second stacked coil may be formed physically one above the other.
- the electrostatic protection device comprises an input terminal.
- the first stacked coil comprises a first coil input connected to the input terminal.
- the first stacked coil comprises a first coil output port connected to a lower frequency ESD protection circuit.
- the first stacked coil comprises a first coil termination port connected to a termination load.
- the second stacked coil is inductively coupled to the first stacked coil.
- the second stacked coil comprises an output port connected to a higher frequency ESD protection circuit.
- the higher frequency ESD protection circuit comprises a higher frequency output.
- the lower frequency ESD protection circuit comprises a lower frequency output.
- the electrostatic protection device comprises a summation circuit configured for outputting a summation of the higher frequency output and the lower frequency output to the input port of the electronic circuit.
- the invention further provides for an integrated circuit incorporating the electrostatic protection device for protecting an input port of an electronic circuit.
- FIG. 1 illustrates an example of an electrostatic protection device
- FIG. 2 illustrates an example of a first stacked coil and a second stacked coil
- Fig. 3 shows a plot of the frequency transmission from a circuit simulation of the electrostatic device shown in Fig. 1;
- Fig. 4 illustrates the bandwidth provided by the electrostatic protection device of Fig. 1 as observed in an eye diagram
- Fig. 5 illustrates an example of an integrated circuit
- FIG. 6 illustrates a further example of an electrostatic protection device
- FIG. 7 illustrates a further example of an electrostatic protection device
- FIG. 8 illustrates a further example of an electrostatic protection device
- FIG. 9 illustrates a further example of an electrostatic protection device.
- Embodiments of the present invention are beneficial because they provide for an effective means of increasing the bandwidth of an electrostatic protection device.
- the signal is broken into lower and higher frequency components which are then treated separately and then recombined.
- the terms lower frequency ESD protection circuit and higher frequency ESD protection circuit are names which are used to differentiate two separate ESD protection circuits.
- the term higher frequency output and lower frequency output are used to differentiate or name two different frequency outputs that are used in the circuit.
- both the human body model (HBM) Electro Static Discharge (ESD) protection circuit and the charge device model (CDM) ESD protection circuit may refer to ESD protection circuits that incorporate clamping circuits, such as diodes, connected to both of the power supply rails (supply and ground).
- the HBM and CDM ESD devices may also, in practice, incorporate a capacitance to ground that is caused by the diode junction capacitance and the parasitic wiring capacitance of the diodes, for the CDM diode, the diode junction, parasitic and the RX input capacitance.
- the charge device ESD protection may further incorporate a resistor and/or impedance in series with an input that limits current and separated HBM and CDM protection circuits.
- the first stacked coil and the second stacked coil form a crossover network configured to divide a signal input into the input terminal into a higher frequency component and a lower frequency component.
- the use of the inductive circuit provides a means for naturally dividing the input signal into these two components.
- the higher frequency component is output by the higher frequency output and the lower frequency output is output by the lower frequency output.
- One potential advantage of this embodiment is that the higher and lower frequency components of an ESD event can have different amounts of current.
- the lower frequency component of the ESD event typically has a higher current than the higher frequency component of the ESD event.
- This effect may be used in designing an effective electrostatic protection device.
- the first stacked coil and the second stacked coil may effectively form a crossover network that decouples the higher frequency ESD protection circuit from the lower frequency component of the ESD event. This may enable the higher frequency ESD protection circuit and the lower frequency ESD protection circuit to have their components tailored for each particular type of ESD event.
- the higher frequency ESD protection circuit may be designed with a lower current rating than the lower frequency ESD protection circuit.
- the first stacked coil is a t-coil with a single coil tap.
- a t-coil structure is used for the lower frequency component. This may be beneficial because it is relatively simple to build the t-coil with a single tap and lower frequency ESD protection circuit so that it is able to deal with higher currents. However, this may affect the ability of it to respond to higher frequencies. It is therefore beneficial to couple the t-coil with the higher frequency ESD protection circuit to increase the bandwidth.
- the single coil tap divides the first stacked coil into a first coil portion and a second coil portion.
- the single coil tap is the first coil output.
- the second coil portion is connected between the single coil tap and the coil termination port.
- the first coil portion is connected between the single coil tap and the first coil input.
- the inductive coupling between the first coil portion and the second stacked coil is greater than the inductive coupling between the second coil portion and the second stacked coil.
- This embodiment may be beneficial during the construction of the electrostatic protection device because the signal picked up on the first coil portion may be more accurate. For example, if a signal goes through the first coil portion and then the second coil portion, the inductance of the first coil portion may cause a degradation in the high frequency component of the signal. Another advantage is that the current in the first coil portion may be higher. It may therefore increase the ability of the inductive coupling to take place.
- the second stacked coil comprises a reference port connected to a ground plane of the electrostatic protection device. This embodiment may be beneficial because it may provide for an effective means of referencing both the high and low frequency components.
- the lower frequency ESD protection circuit comprises a human body model ESD protection circuit. This may be beneficial because the human body model ESD protection circuit can be built specifically to handle the higher current and lower frequency component of an ESD event.
- the lower frequency ESD protection circuit comprises an additional charge device model ESD protection circuit.
- the various frequency components may be divided into upper, higher and lower portions but there may still be some portion of the higher frequency component of the ESD pulse that goes through the first stacked coil. Incorporating the additional charge device model ESD protection circuit may therefore be beneficial and increase the effectiveness of the ESD protection.
- the first stacked coil comprises a first coil tap and a second coil tap.
- the lower frequency ESD protection circuit is connected to the first coil tap and the second coil tap.
- This embodiment is similar to a t-coil arrangement, but instead of the first stacked coil being divided into two parts, it is divided into three parts. This may allow for a more sophisticated lower frequency ESD protection circuit.
- the first stacked coil comprises a first coil portion, an intermediate coil portion, and a second coil portion.
- the first coil portion is connected between the first coil input and the first coil tap.
- the intermediate coil portion is connected between the first coil tap and the second coil tap.
- the second coil portion is connected between the second coil tap and the first coil termination port.
- the lower frequency ESD protection circuit comprises a human body model ESD protection circuit.
- the lower frequency ESD protection comprises an additional charge device model ESD protection circuit.
- the additional charge device model ESD protection circuit is connected to the first coil tap and the human body model ESD protection circuit is connected to the second coil tap.
- the second stacked coil comprises a reference port connected to a ground plane of the electrostatic protection device.
- the second stacked coil comprises a reference port connected to the second coil tap.
- the first stacked coil is at least partially formed from the top two metallization layers of the electrostatic protection device. This may be beneficial because the currents going through the first stacked coil may be larger than through the second stacked coil.
- the top two metallization layers of the electrostatic protection device may be thicker and provide for a first stacked coil that is less likely to be destroyed by an ESD event and have a lower resistance.
- the higher frequency ESD protection circuit comprises a primary charge device model ESD protection circuit.
- the use of the terms primary charge device model ESD protection circuit and additional charge device model ESD protection circuit are intended to indicate that there are two separate charge device model ESD protection circuits.
- the primary charge device model ESD protection circuit has a primarily reactive impedance. Because the signal from the ESD event has been divided effectively into two with the higher frequency component having a lower current, the primary charge device model ESD protection circuit can be specialized and designed in a way so that there is less power loss. In a conventional electrostatic protection device, the primary charge device model ESD protection circuit uses diodes that for smaller signals are effectively lossy capacitors. However, for larger voltages, the diodes begin to conduct and effectively provide a resistance which dissipates the ESD energy to ground. A reactive impedance may be used for the ESD protection circuit instead, as the data signal for higher frequency and low frequency ESD protection circuit are lower current.
- the summation circuit may be a continuous time linear equalizer circuit. For example, this may be a particularly effective way of combining the low and high frequency signal components.
- the input port of the electronic circuit is a differential input port.
- the differential input port is formed by two electrostatic protection devices connected together via the continuous time linear equalization circuit.
- the continuous time linear equalization circuit is used to combine the signals from two separate electrostatic protection devices. This may be beneficial because it may provide for better rejection of noise.
- the termination load is resistive. This, for example, may provide for an effective means of constructing the circuit.
- the invention provides for an integrated circuit that comprises an electronic circuit.
- the integrated circuit comprises an electrostatic protection device for protecting the input port of the electronic circuit.
- the electrostatic protection device comprises a first stacked coil and a second stacked coil.
- the electrostatic protection device comprises an input terminal.
- the first stacked coil comprises a first coil input connected to the input terminal.
- the first stacked coil comprises a first coil output port connected to a lower frequency ESD protection circuit.
- the first stacked coil comprises a first coil termination port connected to a termination load.
- the second stacked coil is inductively coupled to the first stacked coil.
- the second stacked coil comprises an output port connected to a higher frequency ESD protection circuit.
- the higher frequency ESD protection circuit has a higher frequency output.
- the lower frequency ESD protection circuit has a lower frequency output.
- the electrostatic protection device comprises a summation circuit configured for outputting a summation of the higher frequency output and the lower frequency output to the input port of the electronic circuit.
- the integrated circuit may be any of the following: a microprocessor, a microcontroller, a graphical processing unit, a central processing unit, a wideband amplifier, an analogue-to-digital converter, a digital-to-analogue converter, a wireline transceiver circuit, and a telecommunications chip.
- the integrated circuit comprises a substrate.
- the electronic circuit is formed on the substrate.
- the electrostatic protection device is also formed on the substrate.
- the second stacked coil is formed closer to the substrate than the first stacked coil.
- Fig. 1 illustrates an example of an electrostatic protection device 100.
- the electrostatic protection device 100 has an input port 102.
- the input port 102 may be the input port for an electronic circuit that it is protecting.
- the electrostatic protection device 100 comprises a first stacked coil 104 and a second stacked coil 106.
- the first stacked coil 104 is divided into a first coil portion 110 and a second coil portion 112.
- the first stacked coil 104 and the second stacked coil 106 are physically stacked upon each other such that the first stacked coil 104 and the second stacked coil 106 have an inductive coupling.
- the second stacked coil 106 is coupling predominantly to the first coil portion 110. This is however just one option. It could also couple primarily to the second coil portion 112.
- the first stacked coil and the second stacked coil 104, 106 form a five-port device.
- the first port 120 is a first coil input.
- the second port 122 is a first coil output port and is the same as the single coil tap 114.
- the third port 124 is connected to the output of the second coil portion 112 and is connected to a termination load 116.
- the fourth port is a reference port 126 that is connected to one end of the second stacked coil 106 and the fifth port is a second coil output port 128 that is the other port of the second stacked coil 106.
- the inductive coupling between the second stacked coil 106 and the first stacked coil 104 is configured such that it preferentially couples the high frequency component of a signal to a higher frequency ESD protection circuit 140.
- the uncoupled portion of the signal remains in the lower frequency ESD protection circuit 130.
- This therefore forms a higher frequency circuit path 142 and a lower frequency circuit path 132.
- the lower frequency circuit path 132 has a human body model ESD protection circuit 134 and an additional charge device model ESD protection circuit 136.
- the higher frequency circuit path 142 has a primary charge device model ESD protection circuit 144.
- Both the higher frequency ESD protection circuit 140 and the lower frequency ESD protection circuit 130 are coupled to a summation circuit 150 through an amplifier.
- the summation circuit 150 sums a lower frequency output 154 and a higher frequency output 156 to an electrostatic protection device output 152 which has a summation 158 of both the lower frequency output 154 and the higher frequency output 156. This is illustrated by the graphs of the lower frequency signal and the higher frequency signal as shown in the plot.
- Fig. 2 shows an example of the first stacked coil 104 and the second stacked coil 106.
- This figure shows a perspective view 200 and a top view 202.
- the figures show the first coil portion 110 and second coil portion 112 of the first stacked coil 104 on top of the second stacked coil 106.
- the second coil portion 112 is adjacent to the second stacked coil 106.
- the inductive coupling is likely stronger between the second stacked coil 106 and the second coil portion 112 than between the second stacked coil 106 and the first coil portion 110.
- Fig. 1 where the drawing shows that the inductive coupling is primarily between the first coil portion 110 and the second stacked coil 106.
- the design in Fig. 2 could be readily modified to match what is illustrated in Fig. 1 by mechanically switching the position of the two coil portions 112 and 110.
- the coils illustrated in Fig. 2 could for example readily be manufactured using standard semiconductor manufacturing techniques.
- Fig. 3 shows the frequency transmission from a simulation of the circuit illustrated in Fig. 1.
- the lower frequency output 154 and the higher frequency output 156 are plotted.
- the low band -3dB point 300 is shown.
- the summation of both signals is illustrated by summation 158.
- the -3dB point for the summation 158 is illustrated by the line 302. In comparison with the low band -3dB point 300 the -3dB point for the summation of the signals is greatly increased.
- Fig. 4 illustrates the bandwidth provided by the electrostatic device of Fig. 1.
- the figures in column 400 represent the actual signals.
- the figures in column 402 are eye diagrams.
- Row 1 404 contains the higher frequency band.
- Row 2 is the lower frequency band 406.
- the lowest row 408 contains the summation of the higher frequency band 404 and the lower frequency band 406.
- the column 402 for the summation shows a relatively large bandwidth.
- Fig. 5 illustrates an example of an integrated circuit 500.
- the integrated circuit 500 comprises a substrate 502.
- the first stacked coil 104 and second stacked coil 106 as is illustrated in Fig.
- the integrated circuit 500 comprises the electrostatic protection device 100 and forms the input for an electronic circuit 508.
- the first coil portion 110 and the second coil portion 112 are formed from the top two metallization layers 510. This enables these two portions 110, 112 to have a higher current rating and better withstand an ESD event.
- Fig. 6 illustrates a further example of an electrostatic protection circuit 600.
- the electrostatic protection circuit 600 in Fig. 6 is similar to that as was illustrated in Fig. 1.
- the summation circuit is a continuous time linear equalizer circuit 150’.
- the continuous time linear equalizer circuit 150’ comprises an amplifier 602, a FET transistor 601, and several resistors 604.
- the resistances of resistors 604 can be adjusted so that the attenuation of the HF path 142 matches the amplitude of LF path 132.
- a virtual ground is formed 606. This forms a transimpedance amplifier (current to voltage amplifier).
- the LF 154 and the HF 156 signals are added at the bottom of the FET transistor 601 and the output 152 connects to a next stage, such as an analog to digital converter (ADC).
- ADC analog to digital converter
- Fig. 7 illustrates a further example of a differential electrostatic protection device 700.
- the first differential input 702 is connected to a first electrostatic protection device 706 which is similar to the electrostatic protection device 100 illustrated in Fig. 1.
- the second differential input 704 is connected as the input for a second electrostatic protection device 708.
- the second electrostatic protection device 708 is similar to the electrostatic protection device 100 illustrated in Fig. 1.
- the first electrostatic protection device 706 and the second electrostatic protection device 708 have some modifications with respect to the electrostatic protection device 100 of Fig. 1. Firstly, the second stacked coil 106 is shown as primarily coupling to the second coil portion 112 in both cases. The first electrostatic protection device 706 and the second electrostatic protection device 708 are shown as being connected and providing a differential summation using a continuous time linear actuator circuit 150”.
- the continuous time linear actuator circuit 150’ ’ is a differential amplifier in this example, with two FETs 710 with a resistor 712 at their drains.
- VDD DC voltage
- the high frequency output 156 reaches the output (to next stage) via the drain resistors 712 where it is combined with the low frequency output 154 slightly amplified by the FETs 710.
- a current source is typical for differential amplifiers.
- the adjustable resistors 714 are configured to tune the circuit in order for the signal amplitude of the high and low frequency channel to match. Capacitor 716 between the two VDDs is just to block the power supply.
- Fig. 8 illustrates a further example of an electrostatic protection device 800.
- the first stacked coil 104 has been modified with respect to the example illustrated in Fig. 1.
- the first stacked coil 104 has been divided into three parts, a first coil portion 110, an intermediate coil portion 802 and a second coil portion 112.
- the second coil tap 804 is between the intermediate coil portion 802 and the second coil portion 112.
- the first stacked coil 104 and the second stacked coil 106 therefore form a sixth port device in this example.
- the example in Fig. 8 is further modified from that which is shown in Fig.
- the additional charge device model ESD protection circuit 136 is shown as being connected to the second port or the first coil output port 122.
- the human body model ESD protection circuit 134 is shown as being connected to what is the sixth port or the second coil output port 806.
- the second stacked coil 106 is shown as coupling predominantly to the intermediate coil portion 802. However, this could be modified and the second stacked coil 106 could also predominantly couple to the first coil portion 110 or the second coil portion 112.
- Fig. 9 shows a further example of an electrostatic protection device 900.
- the example illustrated in Fig. 9 is very similar to the example illustrated in Fig. 8 with a modification.
- Fig. 9 shows a further example of an electrostatic protection device 900.
- the fourth port or the reference port 126 of the second stacked coil 106 was connected to a ground.
- the fourth port or reference port 126 is instead connected to the second coil tap 804. This is equivalent to the second coil output port 806 being connected to the reference port 126 of the second stacked coil 106.
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
Description
Claims
Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
MX2023011064A MX2023011064A (en) | 2021-03-22 | 2022-02-08 | Electrostatic protection device. |
CN202280014315.4A CN116918259A (en) | 2021-03-22 | 2022-02-08 | Electrostatic protection device |
GB2315277.0A GB2620314B (en) | 2021-03-22 | 2022-02-08 | Electrostatic protection device |
DE112022001649.3T DE112022001649T5 (en) | 2021-03-22 | 2022-02-08 | UNIT FOR PROTECTION AGAINST ELECTROSTATIC CHARGE |
BR112023017408A BR112023017408A2 (en) | 2021-03-22 | 2022-02-08 | ELECTROSTATIC PROTECTION DEVICE |
KR1020237028049A KR20230135112A (en) | 2021-03-22 | 2022-02-08 | electrostatic protection device |
CA3205079A CA3205079A1 (en) | 2021-03-22 | 2022-02-08 | Electrostatic protection device |
JP2023553653A JP2024511305A (en) | 2021-03-22 | 2022-02-08 | electrostatic protection device |
IL304371A IL304371A (en) | 2021-03-22 | 2023-07-10 | Electrostatic protection device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/208,090 US11418026B1 (en) | 2021-03-22 | 2021-03-22 | Electrostatic protection device |
US17/208,090 | 2021-03-22 |
Publications (1)
Publication Number | Publication Date |
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WO2022200872A1 true WO2022200872A1 (en) | 2022-09-29 |
Family
ID=82802967
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2022/051103 WO2022200872A1 (en) | 2021-03-22 | 2022-02-08 | Electrostatic protection device |
Country Status (11)
Country | Link |
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US (2) | US11418026B1 (en) |
JP (1) | JP2024511305A (en) |
KR (1) | KR20230135112A (en) |
CN (1) | CN116918259A (en) |
BR (1) | BR112023017408A2 (en) |
CA (1) | CA3205079A1 (en) |
DE (1) | DE112022001649T5 (en) |
GB (1) | GB2620314B (en) |
IL (1) | IL304371A (en) |
MX (1) | MX2023011064A (en) |
WO (1) | WO2022200872A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11664658B2 (en) | 2021-03-22 | 2023-05-30 | International Business Machines Corporation | Electrostatic protection device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020121924A1 (en) * | 2000-01-21 | 2002-09-05 | Atheros Communications, Inc. | System for providing electrostatic discharge protection for high-speed integrated circuits |
US20130064326A1 (en) * | 2011-09-09 | 2013-03-14 | International Business Machines Corporation | Serial link receiver for handling high speed transmissions |
US20180069396A1 (en) * | 2016-09-08 | 2018-03-08 | Nexperia B.V. | Inductive coupling for electrostatic discharge |
CN108809297A (en) * | 2018-04-27 | 2018-11-13 | 上海兆芯集成电路有限公司 | output driving system |
US10681802B1 (en) * | 2019-09-04 | 2020-06-09 | International Business Machines Corporation | Differential line time skew compensation for high data rate receivers |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4349848A (en) * | 1978-09-18 | 1982-09-14 | Tokyo Shibaura Denki Kabushiki Kaisha | Recording circuit |
US6147564A (en) * | 1996-12-04 | 2000-11-14 | Seiko Epson Corporation | Oscillation circuit having electrostatic protective circuit |
JP3536561B2 (en) * | 1996-12-04 | 2004-06-14 | セイコーエプソン株式会社 | Oscillation circuit, electronic circuit, semiconductor device, clock, and electronic device including the same |
EP1333588B1 (en) * | 2000-11-01 | 2012-02-01 | Hitachi Metals, Ltd. | High-frequency switch module |
DE102004040973A1 (en) * | 2004-08-24 | 2006-03-02 | Infineon Technologies Ag | Integrated circuit arrangement and circuit array |
JP2007074698A (en) * | 2005-08-08 | 2007-03-22 | Fujitsu Media Device Kk | Duplexer and ladder type filter |
EP1960796B1 (en) * | 2005-11-28 | 2014-05-07 | Ladislav Grno | Precision flexible current sensor |
JP4194110B2 (en) * | 2007-03-12 | 2008-12-10 | オムロン株式会社 | Magnetic coupler device and magnetically coupled isolator |
US7728695B2 (en) * | 2007-04-19 | 2010-06-01 | Tdk Corporation | Multilayer filter having an inductor portion and a varistor portion stacked with an intermediate portion |
US20100277839A1 (en) * | 2009-04-29 | 2010-11-04 | Agilent Technologies, Inc. | Overpower protection circuit |
US8181140B2 (en) | 2009-11-09 | 2012-05-15 | Xilinx, Inc. | T-coil network design for improved bandwidth and electrostatic discharge immunity |
EP2469648A4 (en) * | 2010-01-19 | 2013-05-01 | Murata Manufacturing Co | Frequency stabilization circuit, frequency stabilization device, antenna device, communication terminal apparatus, and impedance transformation element |
US8143987B2 (en) * | 2010-04-07 | 2012-03-27 | Xilinx, Inc. | Stacked dual inductor structure |
JP5234084B2 (en) * | 2010-11-05 | 2013-07-10 | 株式会社村田製作所 | Antenna device and communication terminal device |
US20120275074A1 (en) | 2011-04-29 | 2012-11-01 | International Business Machines Corporation | Esd protection device |
US9917079B2 (en) * | 2011-12-20 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection circuit and method for radio frequency circuit |
TWI485983B (en) * | 2012-07-20 | 2015-05-21 | Univ Nat Taiwan | Signal transmission circuit and signal transmission cell thereof |
KR101445741B1 (en) * | 2013-05-24 | 2014-10-07 | 주식회사 이노칩테크놀로지 | Circuit protection device |
US9502168B1 (en) * | 2013-11-15 | 2016-11-22 | Altera Corporation | Interleaved T-coil structure and a method of manufacturing the T-coil structure |
JP5994950B2 (en) * | 2013-12-09 | 2016-09-21 | 株式会社村田製作所 | Common mode filter and common mode filter with ESD protection circuit |
US9673134B2 (en) * | 2013-12-11 | 2017-06-06 | Semiconductor Components Industries, Llc | Semiconductor component and method of manufacture |
US9659924B2 (en) * | 2014-05-25 | 2017-05-23 | Mediatek Inc. | Signal receiving circuit and signal transceiving circuit |
US10879041B2 (en) * | 2015-09-04 | 2020-12-29 | Applied Materials, Inc. | Method and apparatus of achieving high input impedance without using ferrite materials for RF filter applications in plasma chambers |
US9397087B1 (en) | 2015-12-13 | 2016-07-19 | International Business Machines Corporation | Distributed electrostatic discharge protection circuit with magnetically coupled differential inputs and outputs |
US10637234B2 (en) * | 2016-06-22 | 2020-04-28 | International Business Machines Corporation | ESD protection circuit |
JP6493631B2 (en) * | 2016-10-07 | 2019-04-03 | 株式会社村田製作所 | filter |
WO2019006428A1 (en) * | 2017-06-30 | 2019-01-03 | Airity Technologies, Inc. | High gain resonant amplifier for resistive output impedance |
US10529480B2 (en) * | 2017-09-01 | 2020-01-07 | Qualcomm Incorporated | Asymmetrical T-coil design for high-speed transmitter IO ESD circuit applications |
US10498139B2 (en) | 2017-09-01 | 2019-12-03 | Qualcomm Incorporated | T-coil design with optimized magnetic coupling coefficient for improving bandwidth extension |
US10742026B2 (en) * | 2018-02-07 | 2020-08-11 | International Business Machines Corporation | Electrostatic protection device |
US10971458B2 (en) * | 2019-01-07 | 2021-04-06 | Credo Technology Group Limited | Compensation network for high speed integrated circuits |
US20220121924A1 (en) * | 2020-10-21 | 2022-04-21 | International Business Machines Corporation | Configuring a neural network using smoothing splines |
US11418026B1 (en) | 2021-03-22 | 2022-08-16 | International Business Machines Corporation | Electrostatic protection device |
-
2021
- 2021-03-22 US US17/208,090 patent/US11418026B1/en active Active
-
2022
- 2022-02-08 CA CA3205079A patent/CA3205079A1/en active Pending
- 2022-02-08 MX MX2023011064A patent/MX2023011064A/en unknown
- 2022-02-08 BR BR112023017408A patent/BR112023017408A2/en unknown
- 2022-02-08 WO PCT/IB2022/051103 patent/WO2022200872A1/en active Application Filing
- 2022-02-08 GB GB2315277.0A patent/GB2620314B/en active Active
- 2022-02-08 JP JP2023553653A patent/JP2024511305A/en active Pending
- 2022-02-08 DE DE112022001649.3T patent/DE112022001649T5/en active Pending
- 2022-02-08 KR KR1020237028049A patent/KR20230135112A/en active Search and Examination
- 2022-02-08 CN CN202280014315.4A patent/CN116918259A/en active Pending
- 2022-05-17 US US17/745,958 patent/US11664658B2/en active Active
-
2023
- 2023-07-10 IL IL304371A patent/IL304371A/en unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020121924A1 (en) * | 2000-01-21 | 2002-09-05 | Atheros Communications, Inc. | System for providing electrostatic discharge protection for high-speed integrated circuits |
US20130064326A1 (en) * | 2011-09-09 | 2013-03-14 | International Business Machines Corporation | Serial link receiver for handling high speed transmissions |
US20180069396A1 (en) * | 2016-09-08 | 2018-03-08 | Nexperia B.V. | Inductive coupling for electrostatic discharge |
CN108809297A (en) * | 2018-04-27 | 2018-11-13 | 上海兆芯集成电路有限公司 | output driving system |
US10681802B1 (en) * | 2019-09-04 | 2020-06-09 | International Business Machines Corporation | Differential line time skew compensation for high data rate receivers |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11664658B2 (en) | 2021-03-22 | 2023-05-30 | International Business Machines Corporation | Electrostatic protection device |
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GB2620314B (en) | 2024-06-05 |
IL304371A (en) | 2023-09-01 |
KR20230135112A (en) | 2023-09-22 |
US11664658B2 (en) | 2023-05-30 |
DE112022001649T5 (en) | 2024-01-04 |
JP2024511305A (en) | 2024-03-13 |
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GB2620314A (en) | 2024-01-03 |
US11418026B1 (en) | 2022-08-16 |
CA3205079A1 (en) | 2022-09-29 |
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