WO2022198675A1

WO2022198675A1 - Multi-chip module and electronic device having multi-chip module

Info

Publication number: WO2022198675A1
Application number: PCT/CN2021/083423
Authority: WO
Inventors: 王士伟
Original assignee: 华为技术有限公司
Priority date: 2021-03-26
Filing date: 2021-03-26
Publication date: 2022-09-29
Also published as: CN116670824A

Abstract

Provided in the present application is a multi-chip module, comprising a package substrate and at least two chips, which are arranged on the package substrate, wherein each chip has a bottom face, which faces the package substrate, and a side face, which is connected to the bottom face; the at least two chips comprise a first die and a second die, which are adjacent to each other, are spaced apart from each other, and have opposite side faces; a first wire is arranged on a bottom face of the first die; the first wire is connected to a circuit in the first die and extends to the side face of the first die that faces the second die; a second wire is arranged on a bottom face of the second die; the second wire is connected to a circuit in the second die and extends to the side face of the second die that faces the first die; and an electrical connection structure is arranged between the opposite side faces of the first die and the second die, so that the first wire and the second wire are electrically connected to each other. Multi-chip interconnection is performed by using the space of side faces of chips, such that the interconnection density between the chips is increased on the basis that the area of bottom faces of the chips is not occupied. Further provided in the present application is an electronic device having the multi-chip module.

Description

Multi-chip module and electronic equipment having the same

technical field

The present application relates to a multi-chip module and an electronic device having the multi-chip module.

Background technique

With the development of the information society, the generation of data presents an exponential explosion, which requires more stringent data processing capabilities. In the era of big data, the demand for high performance of chips is increasing day by day. Increasing the bandwidth density of chips is one of the research directions in the industry. Multi-chip Module (MCM) is a packaging technology that integrates multiple dies on the same substrate. bandwidth density.

At present, the package-level multi-chip interconnection architecture mainly includes the following: (1) the chips are directly interconnected through the substrate wiring; (2) the 2.5D package interconnection realized by setting up an interposer between the chip and the substrate This solution requires a silicon interposer and through-silicon via (TSV) technology; (3) by placing an organic fan-out packaging layer between the chip and the substrate, multiple dies are placed on the organic fan-out On the packaging layer, the signals are interconnected between dies through the redistribution layer in the organic fan-out packaging layer. All of the above-mentioned methods use the space of the chip facing the bottom surface of the substrate to perform chip interconnection.

SUMMARY OF THE INVENTION

In view of this, it is necessary to provide a multi-chip module with novel structure, which can perform multi-chip interconnection by utilizing the space on the side of the chip.

In the first aspect, the application provides a kind of multi-chip module, comprising:

package substrate;

at least two chips disposed on the packaging substrate, each chip having a bottom surface facing the packaging substrate and a side surface connected to the bottom surface;

The at least two chips include a first die and a second die that are adjacently spaced and have opposite sides, a first wire is provided on the bottom surface of the first die, and the first wire is connected to the first die The circuit in the chip extends from the bottom surface and side surface of the first die to the side opposite to the second die, and the bottom surface of the second die is provided with a second wire, the second wire is connected to the circuit in the second die and extends on the bottom surface and the side of the second die to the side of the second die opposite to the first die;

An electrical connection structure is provided between the opposite sides of the first die and the second die to electrically connect the first wire and the second wire; or the first die and the A wireless signal transceiving structure is disposed between the opposite sides of the second die, so that the first wire and the second wire are wirelessly communicatively connected.

It can be seen that, in the multi-chip module provided by the first aspect, the electrical connection structures are arranged on the sides of adjacent chips to be connected to the wires extending from the surface of the chips respectively, so that the electrical connection structures are respectively electrically connected to the adjacent chips. The first aspect also provides another multi-chip module, which is connected to the wires extending from the surface of the chip by arranging the wireless signal transceiver structure on the side of the adjacent chip, respectively. Therefore, the wireless signal transceiver structure is electrically connected to the circuits in the adjacent chips respectively, thereby realizing the non-contact data communication between the adjacent chips. On this basis, the data communication function of two adjacent chips is achieved, and the interconnection density between chips is increased by developing the side space of the chips.

With reference to the first aspect, in some embodiments, the electrical connection structure includes solder joints and pads that are connected to each other in contact with each other, and the solder joints are protruded on opposite sides of the first die and the second die and connected to the first wire, the pad is disposed on the opposite side of the second die and the first die and is connected to the second wire.

It can be seen that the multi-chip module is connected to the circuit in the adjacent chip by arranging contact-connected solder joints and pads on the sides of the adjacent chips, so as to realize the physical connection and electrical connection of the adjacent chips. Furthermore, by utilizing the space on the side of the chip to realize data communication between two adjacent chips, the interconnection density between chips is increased.

With reference to the first aspect, in some embodiments, the electrical connection structure includes a conductive pin and a conductive socket, the conductive pin is protruded on the opposite side of the first die and the second die and connects the a first wire, the conductive socket is protruded on the side of the second die opposite to the first die and connected to the second wire, the conductive socket is provided with a hole, and the conductive pin is inserted In the hole to make electrical connection between the conductive pin and the conductive socket.

It can be seen that the multi-chip module is connected to the circuits in the adjacent chips by arranging contact-connected conductive pins and conductive sockets on the sides of the adjacent chips, so as to realize the physical connection and electrical connection of the adjacent chips. Furthermore, by utilizing the space on the side of the chip to realize data communication between two adjacent chips, the interconnection density between chips is increased.

With reference to the first aspect, in some embodiments, the wireless signal transceiving structure includes a pair of passive transceiving inductive coils, wherein one passive transceiving inductive coil is disposed opposite the first die and the second die The side is connected to the first wire, and the first wire is connected to the circuit in the first bare chip as a transceiver circuit; another passive transmission and reception inductance coil is arranged on the second bare chip and the first bare chip. The opposite side of the chip is connected to the second wire, and the second wire is connected to the circuit in the second die as a transceiver circuit.

It can be seen that the multi-chip module is connected to the transceiver circuits in the adjacent chips by setting the inductance coils on the sides of the adjacent chips, so as to realize the non-contact short-range electromagnetic communication between the adjacent chips. The space on the side achieves the function of wireless communication between two adjacent chips, increasing the interconnection density between chips.

In conjunction with the first aspect, in some embodiments, the two passive transceiver inductors of the pair of passive transceiver inductors are aligned and spaced from each other.

With reference to the first aspect, in some embodiments, the wireless signal transceiving structure is a pair of optical transceiving elements, wherein one optical transceiving element is disposed on the opposite side of the first die and the second die and is connected to the two optical transceiving elements. The first wire, the first wire is connected to the circuit in the first die to be the first optical module processing circuit; another optical transceiver element is arranged on the second die opposite to the first die The side surface is connected to the second wire, and the second wire is connected to the circuit in the second die as a second optical module processing circuit.

It can be seen that the multi-chip module is connected to the optical module processing circuit in the adjacent chip by arranging the optical transceiver elements on the side of the adjacent chip, so as to realize the non-contact short-range optical communication between the adjacent chips. By utilizing the space on the side of the chip to achieve the function of wireless communication between two adjacent chips, the interconnection density between the chips is increased.

In conjunction with the first aspect, in some embodiments, the two optical transceiver elements of the pair of optical transceiver elements are aligned and spaced from each other.

With reference to the first aspect, in some embodiments, one of the pair of optical transceiver elements is a light-emitting element, and the other is a photosensitive element.

In conjunction with the first aspect, in some embodiments, each optical transceiver element of the pair of optical transceiver elements integrates the functions of transmitting optical signals and receiving optical signals.

With reference to the first aspect, in some embodiments, a solder joint is provided between the bottom surface of the first die and the package substrate, and the solder joint is connected to the first wire; the bottom surface of the second die is Additional solder joints are provided between the package substrate and the other solder joints, and the additional solder joints are connected to the second wires.

With reference to the first aspect, in some embodiments, the package substrate is provided with a conductive circuit, and the conductive circuit is connected to the solder joints on the bottom surface of the first die and the solder joints on the bottom surface of the second die. The surface of the package substrate facing away from the chip is further provided with solder balls, and the solder balls are connected to the conductive lines in the package substrate.

With reference to the first aspect, in some embodiments, an insulating material layer is respectively covered on the bottom surface and the side surface of the first die, and the insulating material layer insulates and separates the first die and the first wire; The bottom surface and the side surface of the second die are covered with insulating material layers respectively, and the insulating material layers are insulated from the second die and the second wires.

In a second aspect, the present application further provides an electronic device, including a circuit board and a multi-chip module as in the first aspect and possible embodiments thereof located on the circuit board.

Description of drawings

FIG. 1 is a schematic diagram of a multi-chip module of the present application.

FIG. 2 is a schematic diagram of a multi-chip module according to Embodiment 1 of the present application.

FIG. 3A is a schematic view of a side surface of a first die of the multi-chip module shown in FIG. 2 .

FIG. 3B is a schematic view of a side surface of the second die of the multi-chip module shown in FIG. 2 .

FIG. 4 is a schematic diagram of a multi-chip module according to Embodiment 2 of the present application.

FIG. 5 is a schematic diagram of another state of two chips of the multi-chip module shown in FIG. 4 .

FIG. 6A is a side view of a first die of the multi-chip module shown in FIG. 4 .

FIG. 6B is a schematic view of a side surface of the second die of the multi-chip module shown in FIG. 4 .

FIG. 7 is a schematic diagram of another multi-chip module of the present application.

8A is a schematic diagram of a side surface of a first die of a multi-chip module according to Embodiment 3 of the present application.

8B is a schematic diagram of a side surface of the second die of the multi-chip module according to the third embodiment of the present application.

FIG. 9 is a schematic diagram of a multi-chip module according to Embodiment 4 of the present application.

FIG. 10A is a schematic view of the side of the first die of the multi-chip module shown in FIG. 9 .

FIG. 10B is a schematic view of a side surface of the second die of the multi-chip module shown in FIG. 9 .

FIG. 11 is a schematic diagram of an electronic device using a multi-chip module.

Description of main component symbols

多芯片模组 Multi-chip module	100、200、100A、100B、200A、200B100, 200, 100A, 100B, 200A, 200B

封装基板Package substrate	1010
芯片 chip	3030
第一裸片 first die	30A30A
第二裸片second die	30B 30B

底面underside	3131
侧面 side	3333
第一导线 first wire	35A35A
第二导线 second wire	35B35B
电连接结构Electrical connection structure	5050
焊点solder joint	51、5551, 55
焊盘 pad	5353
绝缘材料层insulating material layer	2020
焊球 solder balls	6060
导电针头 Conductive needle	5252
导电插座 conductive socket	5454
孔 hole	541541
无源收发电感线圈Passive Transceiver Inductor Coil	7171
无线信号收发结构Wireless signal transceiver structure	7070
光收发元件 Optical transceiver	8080
电子设备 Electronic equipment	500500
壳体 case	510510
电路板 circuit board	530530

The following specific embodiments will further illustrate the present application in conjunction with the above drawings.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

It should be noted that when an element is referred to as being "electrically connected" to another element, it can be directly on the other element or intervening elements may also be present. When an element is considered to be "electrically connected" to another element, it can be a contact connection, for example, in the form of a wire connection, or a contactless connection, such as a contactless coupling.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are for the purpose of describing specific embodiments only, and are not intended to limit the application.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and features in the embodiments may be combined with each other without conflict.

The existing package-level multi-chip interconnect architectures are designed between the surface of the chip facing the package substrate and the package substrate, such as arranging conductive lines, transition boards or organic fan-out packaging layers between the chip and the package substrate. etc., to realize the interconnection between chips.

The embodiments of the present application provide a novel multi-chip module. By utilizing the space on the side of the chip for interconnection of multiple chips, on the basis of not consuming/occupying the area of the bottom surface of the chip, the side area of the chip is developed and the interaction between the chips is increased. Even density.

Referring to FIG. 1 , a multi-chip module 100 according to an embodiment of the present application includes a package substrate 10 and at least two chips 30 disposed on a surface of the package substrate 10 . The chip 30 may be a bare die. Each chip 30 has a bottom surface 31 facing the package substrate 10 and a side surface 33 connected to the bottom surface 31 . In this embodiment, the side surface 33 is substantially perpendicular to the bottom surface 31 .

For clarity of presentation, FIG. 1 only illustrates the interconnection of two chips 30 . The two chips 30 are a first die 30A and a second die 30B, respectively. As shown in FIG. 1 , the first die 30A and the second die 30B are spaced apart from each other and the side surfaces 33 are opposite to each other. The bottom surface 31 of the first die 30A is provided with a first wire 35A, and the first wire 35A is connected to the circuit in the first die 30A at the position of the bottom surface 31 of the first die 30A (Fig. (not shown), and the first wires 35A extend from the bottom surface 31 and the side surface 33 of the first die 30A to the side surface 33 of the first die 30A and the second die 30B opposite to each other. A second wire 35B is disposed on the bottom surface 31 of the second die 30B, and the second wire 35B is connected to the circuit in the second die 30B at the position of the bottom surface 31 of the second die 30B (Fig. (not shown), and the second wire 35B extends from the bottom surface 31 and the side surface 33 of the second die 30B to the side surface 33 of the second die 30B opposite to the first die 30A. An electrical connection structure 50 is provided between the opposite side surfaces 33 of the first die 30A and the second die 30B to electrically connect the first wires 35A and the second wires 35B, thereby realizing the first Interconnection of die 30A to second die 30B.

Referring to the multi-chip module 100A according to the first embodiment of the present application shown in FIG. 2 , FIG. 3A and FIG. 3B , in this embodiment, the electrical connection structure 50 includes a pad 51 and a pad 53 that are connected to each other in contact with each other. The solder joints 51 are protruded on the opposite side surfaces 33 of the first die 30A and the second die 30B and are connected to the first wires 35A. That is, one end of the first wire 35A is connected to the circuit (not shown) in the first die 30A, and the other end is connected to the solder joint 51 . The pads 53 are disposed on the side surface 33 of the second die 30B opposite to the first die 30A and are connected to the second wires 35B. That is, one end of the second wire 35B is connected to the circuit (not shown) in the second die 30B, and the other end is connected to the pad 53 . The solder joints 51 and the pads 53 are aligned and connected to each other, so as to realize the electrical connection between the first wire 35A and the second wire 35B, and then the first die 30A and the second wire are electrically connected. Die 30B is interconnected.

It can be understood that, as shown in FIG. 3A and FIG. 3B , the first die 30A is provided with a plurality of first wires 35A, and corresponding to the second die 30B is also provided with a plurality of second wires 35B. A plurality of electrical connection structures 50 are arranged between the first die 30A and the second die 30B, the plurality of first wires 35A and the plurality of second wires 35B are arranged in a one-to-one correspondence, and each pair of first The wires 35A and the second wires 35B are correspondingly provided with an electrical connection structure 50 , that is, a pair of pads 51 and pads 53 that are aligned with each other and are in contact with each other.

It can be understood that pads 53 may also be provided on the side 33 of the first die 30A, and the side 33 of the corresponding second die 30B is protruding and aligned with the pads 53 on the first die 30A. Contact the connected pads 51 .

As shown in FIG. 1 and FIG. 2 , the bottom surface 31 and the side surface 33 of the first die 30A are covered with insulating material layers 20 respectively, and the insulating material layers 20 are located between the first die 30A and the first die 30A. between a wire 35A to prevent the first wire 35A and the first die 30A from being short-circuited. Similarly, the bottom surface 31 and the side surface 33 of the second die 30B are respectively covered with an insulating material layer 20, and the insulating material layer 20 is located between the second die 30B and the second wire 35B, In order to prevent the short-circuit connection between the second wire 35B and the second die 30B. Therefore, although shown in the figure, the connection between the first wire 35A and the circuit in the first die 30A needs to pass through the insulating material layer 20; the second wire 35B and the circuit in the second die 30B The connection needs to penetrate through the insulating material layer 20 .

As shown in FIG. 1 and FIG. 2 , a plurality of solder joints 55 are disposed between the bottom surface 31 of the first die 30A and the package substrate 10 , and each solder joint 55 can be connected to one of the first wires 35A. A plurality of additional solder joints 55 are disposed between the bottom surface 31 of the second die 30B and the package substrate 10 , and each of the additional solder joints 55 can be connected to one of the second wires 35B.

As shown in FIG. 1 and FIG. 2 , the package substrate 10 is provided with conductive lines 11 , the conductive lines 11 and the solder joints 55 on the bottom surface 31 of the first die 30A and the second die 30B The solder joints 55 on the bottom surface 31 of the bottom surface 31 are electrically connected. The surface of the package substrate 10 facing away from the chip 30 is further provided with a plurality of solder balls 60 , the solder balls 60 are connected to the conductive lines 11 in the package substrate 10 , and the solder balls 60 can be connected with other electronic components. , The conductive lines are electrically connected to realize the extraction of the signal of the chip 30 .

In this embodiment, due to the small size of the chip 30 , the size of the solder joints 51 located between the opposite sides 33 of the chip is generally smaller than the size of the solder joints 55 on the bottom surface 31 of the chip 30 , which is soldered on the bottom surface 31 of the chip 30 . The size of the dots 55 is smaller than the size of the solder balls 60 .

The material of the packaging substrate 10 may be an organic resin material or a ceramic material, but not limited thereto.

The material of the first wire 35A and the second wire 35B can be metal or metal alloy, such as copper, aluminum, titanium, tungsten, nickel, palladium, gold or a metal alloy including one or more of the following metals: Copper, aluminum, titanium, tungsten, nickel, palladium and gold; other conductive materials are also possible.

The materials of the solder joints 51 , the solder joints 55 and the solder balls 60 can be conductive metal materials, such as tin, gold, silver, copper and the like.

It can be understood that the multi-chip module 100 may further include a plastic sealing layer (not shown) encapsulated on the chip 30 to protect the chip 30 .

In the multi-chip module 100A according to the first embodiment of the present application, two adjacent chips 30 are bound together by the bonding technology in which the solder joints 51 on the side surfaces 33 of the adjacent chips 30 are connected to the solder pads 53 to achieve physical bonding. The connection can realize data communication between the two chips 30 at the same time, and can be extended to the interconnection of multiple chips 30 according to the application of the chip side 33 .

Please refer to FIG. 4 , FIG. 5 , FIG. 6A and FIG. 6B . The multi-chip module 100B of the second embodiment of the present application is basically the same as the multi-chip module 100A of the first embodiment, and also includes the packaging substrate 10 and At least two chips 30 disposed on a surface of the packaging substrate 10; the same features of the two are not repeated here, and the difference between the two is that in this embodiment, the electrical connection structure 50 does not include solder joints and Pads, but include conductive pins 52 and conductive sockets 54, the conductive pins 52 are protruded on the side 33 of the first die 30A and the second die 30B opposite to each other and are connected to the first wires 35A, The conductive socket 54 is protruded on the side surface 33 of the second die 30B opposite to the first die 30A and is connected to the second wire 35B. The conductive socket 54 is provided with a hole 541 for the conductive socket 54 . The needle 52 is inserted into the hole 541 to connect the conductive needle 52 and the conductive socket 54 in contact. The conductive pins 52 and the conductive sockets 54 may be formed on the side surface 33 of the chip by electroplating or surface mounting, but not limited thereto.

As shown in FIG. 6A and FIG. 6B , in this embodiment, the conductive needle 52 is cylindrical, the hole 541 is a circular hole, and the size of the hole 541 is matched with the size of the conductive needle 52 , so that When the conductive pin 52 is inserted into the hole 541 , the conductive pin 52 abuts against the hole wall of the hole 541 , so that the conductive pin 52 and the conductive socket 54 are in contact with each other. It can be understood that the size and shape of the hole 541 and the size and shape of the conductive needle 52 can be designed as required, and are not limited to the shape shown in the figure, as long as it is ensured that when the conductive needle 52 is inserted into the hole 541 The conductive pin 52 and the conductive socket 54 can be connected in contact with each other.

In the multi-chip module 100B of the second embodiment of the present application, the conductive pins 52 and the conductive sockets 54 are arranged on the side 33 of the chip 30 to cooperate with each other, and the two chips 30 can be electrically connected by inserting the conductive pins 52 into the conductive sockets 54. According to the application of the chip side surface 33 , it can be extended to the interconnection of multiple chips 30 .

It can be understood that the electrical connection structure 50 is not limited to the above-mentioned forms of the solder joints 51 and pads 53 , the conductive pins 52 and the conductive sockets 54 , and can also be other various forms that can realize the electrical connection between the first wire 35A and the second wire 35B. Electrical connection structure for sexual connection.

Referring to FIG. 7 , another multi-chip module 200 provided by the embodiment of the present application is basically the same as the multi-chip module 100 shown in FIG. At least two chips 30 on the surface; the same features of the two will not be repeated here, and the difference between the two is: in this embodiment, the first die 30A and the second die 30B are opposite to each other. The side surfaces 33 are not provided with an electrical connection structure, but are provided with a wireless signal transceiver structure 70 to enable the first wire 35A and the second wire 35B to achieve a non-contact communication connection, thereby enabling the first wire The chip 30A and the second die 30B realize contactless communication interconnection.

Please refer to FIG. 7 , FIG. 8A and FIG. 8B , the wireless signal transceiving structure 70 in the multi-chip module 200A according to the third embodiment of the present application includes a pair of passive transceiving inductor coils 71 . One of the passive transceiver inductance coils 71 is disposed on the side 33 of the first die 30A and the second die 30B opposite to the second die 30B and is connected to the first wire 35A, and the first wire 35A is in the first die The bottom surface 31 of the chip 30A is connected to the transceiver circuit (not shown) in the first bare chip 30A. That is, one end of the first wire 35A is connected to the passive transceiver coil 71, and the other end is connected to the transceiver circuit (not shown) in the first bare chip 30A. Another passive transceiver coil 71 is disposed on the side 33 of the second die 30B opposite to the first die 30A and is connected to the second wire 35B, and the second wire 35B is connected to the second Transceiver circuitry in die 30B. That is, one end of the second wire 35B is connected to another passive transceiver coil 71, and the other end is connected to the transceiver circuit in the second bare chip 30B.

The two passive transceiving inductive coils 71 of the pair of passive transceiving inductive coils 71 are aligned and spaced apart from each other, so as to be able to transmit and receive signals to and from each other. Therefore, the first die 30A and the second die 30B need to maintain a proper distance, so that the first die 30A and the second die 30B can perform the function of wireless communication.

It can be understood that, as shown in FIG. 8A and FIG. 8B , a plurality of first wires 35A may be provided on the first die 30A, and a plurality of second wires 35B corresponding to the second die 30B. A plurality of pairs of passive transceiver coils 71 are arranged between the first die 30A and the second die 30B, the plurality of first wires 35A and the plurality of second wires 35B are arranged in a one-to-one correspondence, and each pair of The first wire 35A and the second wire 35B are provided with a pair of passive transceiver coils 71 correspondingly, and the two passive transceiver coils 71 of each pair of passive transceiver coils 71 are aligned and spaced apart from each other, so that each pair The passive transceiving inductive coils 71 can better transmit and receive signals.

In the multi-chip module 200A of the third embodiment of the present application, a pair of passive transceiver inductor coils 71 are arranged on the side surfaces 33 of adjacent chips 30 to perform short-range electromagnetic communication, so as to achieve the function of wireless communication between two adjacent chips 30 . The application of the side surface 33 of the chip 30 can be extended to the interconnection of multiple chips 30 . The scheme is a non-contact multi-chip communication scheme, which achieves the purpose of multi-chip interconnection through high-speed transceivers.

Please refer to FIG. 9 , FIG. 10A and FIG. 10B . The multi-chip module 200B of the fourth embodiment of the present application is basically the same as the multi-chip module 200A of the third embodiment, and also includes the packaging substrate 10 and the multi-chip module 200B disposed on the There are at least two chips 30 on a surface of the package substrate 10, and the first die 30A and the second die 30B are also non-contact communication interconnections. The same features of the two are not repeated here. The difference is that the wireless signal transceiving structure 70 is a pair of optical transceiving elements 80 , wherein one optical transceiving element 80 is disposed on the side 33 opposite to the first die 30A and the second die 30B and is connected to the first die 30A. A lead 35A, the first lead 35A is connected to the optical module processing circuit (not shown) in the first die 30A; another optical transceiver element 80 is disposed on the second die 30B and the first The opposite side 33 of a die 30A is connected to the second wire 35B, and the second wire 35B is connected to an optical module processing circuit (not shown) in the second die 30B.

In this embodiment, the two optical transceiver elements 80 of the pair of optical transceiver elements 80 are aligned and spaced apart from each other, so that the pair of optical transceiver elements 80 can better transmit and receive signals to each other. In this embodiment, one of the pair of optical transceiver elements 80 is a light-emitting element, such as a light-emitting diode, and the other is a photosensitive element. One end of the first wire 35A is connected to the optical module processing circuit in the first bare chip 30A, and the other end is connected to the light emitting element. One end of the second wire 35B is connected to the optical module processing circuit in the second bare chip 30B, and the other end is connected to the photosensitive element.

It can be understood that a photosensitive element may also be provided on the side surface 33 of the first bare chip 30A, and a light-emitting element corresponding to the side surface 33 of the second bare chip 30B is aligned with the photosensitive element on the first bare chip 30A.

In other embodiments, each optical transceiver element 80 integrates the functions of transmitting optical signals and receiving optical signals.

It can be understood that, as shown in FIG. 10A and FIG. 10B , a plurality of first wires 35A may be provided on the first die 30A, and a plurality of second wires 35B corresponding to the second die 30B. A plurality of pairs of optical transceiver elements 80 are arranged between the first die 30A and the second die 30B, the plurality of first wires 35A and the plurality of second wires 35B are arranged in a one-to-one correspondence, and each pair of first A pair of optical transceiver elements 80 are correspondingly provided on the conducting wire 35A and the second conducting wire 35B. It can be understood that light-emitting elements and photosensitive elements respectively connected to different first wires 35A can also be provided on the side 33 of the first die 30A at the same time, and corresponding to the side 33 of the second die 30B are provided with different The second wire 35B connects the light-emitting element and the photosensitive element, and the light-emitting element on the first bare chip 30A and the photosensitive element on the second bare chip 30B are paired with each other, and each pair of light-emitting element and photosensitive element Aligned with each other, the photosensitive elements on the first die 30A and the light emitting elements on the second die 30B are paired with each other, and the light emitting elements and the photosensitive elements of each pair are aligned with each other.

In the multi-chip module 200B of the fourth embodiment, a pair of optical transceiver elements 80 are arranged on the side surfaces 33 of adjacent chips 30 to perform short-range optical communication, so as to achieve the function of wireless communication between the two adjacent chips 30, and the non-contact multi-chip The interconnection communication scheme can effectively improve the chip interconnection bandwidth due to the small interference between optical signals and the large bandwidth.

It can be understood that the wireless signal transceiving structure is not limited to the above-mentioned passive transceiving inductive coil 71 and optical transceiving element 80 , but can also be other various types that can realize non-contact communication between the first wire 35A and the second wire 35B. Connected wireless signal transceiver structure.

As shown in FIG. 11 , the present application further provides an electronic device 500 , the electronic device 500 includes a housing 510 and a circuit board 530 located in the housing 510 , and at least one of the above-mentioned

multi-chip modules

100 and 200 is disposed in the circuit on the plate 530 and within the housing 510 . The electronic device 500 shown in FIG. 11 is a mobile phone, but is not limited to a mobile phone, and the electronic device can be various electronic devices that need to be provided with chips.

The above embodiments are only used to illustrate the technical solutions of the present application and not to limit them. Although the present application has been described in detail with reference to the above preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present application can be modified or equivalently replaced. Neither should depart from the spirit and scope of the technical solutions of the present application. Those skilled in the art can also make other changes within the spirit of the present application, etc. to be used in the design of the present application, as long as they do not deviate from the technical effects of the present application. These changes made in accordance with the spirit of the present application should all be included within the scope of protection claimed in the present application.

Claims

A multi-chip module, comprising:

package substrate;

at least two chips disposed on the packaging substrate, each chip having a bottom surface facing the packaging substrate and a side surface connected to the bottom surface;

The at least two chips include a first die and a second die that are adjacently spaced and have opposite sides, a first wire is provided on the bottom surface of the first die, and the first wire is connected to the first die The circuit in the chip extends from the bottom surface and side surface of the first die to the side opposite to the second die, and the bottom surface of the second die is provided with a second wire, the second wire is connected to the circuit in the second die and extends on the bottom surface and the side of the second die to the side of the second die opposite to the first die;

An electrical connection structure is provided between the opposite sides of the first die and the second die to electrically connect the first wire and the second wire; or the first die and the A wireless signal transceiving structure is disposed between the opposite sides of the second die, so that the first wire and the second wire are wirelessly communicatively connected.
1. The multi-chip module of claim 1, wherein the electrical connection structure comprises solder joints and pads that are in contact with each other, and the solder joints are protruded on the first die and the second die. The opposite side of the die is connected to the first wire, and the pad is disposed on the opposite side of the second die and the first die and is connected to the second wire.
The multi-chip module according to claim 1, wherein the electrical connection structure comprises a conductive pin and a conductive socket, and the conductive pin is protruded on the opposite side of the first die and the second die. The side surface is connected to the first wire, the conductive socket is protruded on the opposite side of the second die and the first die and is connected to the second wire, the conductive socket is provided with a hole, so The conductive pin head is inserted into the hole to make the conductive pin head and the conductive socket contact and electrically connect.
The multi-chip module of claim 1, wherein the wireless signal transceiving structure comprises a pair of passive transceiving inductive coils, wherein one passive transceiving inductive coil is disposed between the first die and the second The opposite sides of the two bare chips are connected to the first wire, and the first wire is connected to the circuit in the first bare chip as a transceiver circuit; another passive transmission and reception inductance coil is arranged between the second bare chip and the second bare chip. The opposite side of the first die is connected to the second wire, and the second wire is connected to a circuit in the second die as a transceiver circuit.
5. The multi-chip module of claim 4, wherein the two passive transceiver coils of the pair of passive transceiver coils are aligned and spaced apart from each other.
The multi-chip module of claim 1, wherein the wireless signal transceiving structure is a pair of optical transceiving elements, wherein one optical transceiving element is disposed opposite the first die and the second die The side of the optical fiber is connected to the first wire, and the first wire is connected to the circuit in the first die as a first optical module processing circuit; another optical transceiver element is arranged on the second die and the The opposite side of the first die is connected to the second wire, and the second wire is connected to the circuit in the second die to be a second optical module processing circuit.
The multi-chip module of claim 6, wherein the two optical transceiver elements of the pair of optical transceiver elements are aligned and spaced apart from each other.
The multi-chip module according to claim 6 or 7, wherein one of the pair of optical transceiver elements is a light-emitting element, and the other is a photosensitive element.
The multi-chip module according to claim 6 or 7, wherein each optical transceiver element of the pair of optical transceiver elements integrates the functions of transmitting optical signals and receiving optical signals.
The multi-chip module according to any one of claims 1 to 9, wherein a solder joint is provided between the bottom surface of the first die and the package substrate, and the solder joint is connected to the first die. A lead; another solder joint is disposed between the bottom surface of the second die and the package substrate, and the other solder joint is connected to the second lead.
11. The multi-chip module according to claim 10, wherein a conductive circuit is provided in the package substrate, and the conductive circuit is connected to a solder joint on the bottom surface of the first die and the second die. The solder joints on the bottom surface of the package substrate are electrically connected; the surface of the package substrate facing away from the chip is also provided with solder balls, and the solder balls are connected to the conductive lines in the package substrate.
The multi-chip module according to any one of claims 1 to 11, wherein the bottom surface and the side surface of the first die are covered with insulating material layers respectively, and the insulating material layers are insulatingly spaced from the The first bare chip and the first wire; the bottom surface and the side surface of the second bare chip are respectively covered with an insulating material layer, and the insulating material layer is insulated from the second bare chip and the second wire.
An electronic device, comprising a circuit board and a multi-chip module on the circuit board, wherein the multi-chip module is the multi-chip module according to any one of claims 1 to 12.