WO2022198652A1

WO2022198652A1 - Random number generation apparatus and method, random number generation system, and chip

Info

Publication number: WO2022198652A1
Application number: PCT/CN2021/083344
Authority: WO
Inventors: 朱幸尔; 郑乔石; 张精制; 杨方昱; 李克; 丰帆
Original assignee: 华为技术有限公司
Priority date: 2021-03-26
Filing date: 2021-03-26
Publication date: 2022-09-29
Also published as: CN116710890A

Abstract

Embodiments of the present application relate to the technical field of neural networks, and provide a random number generation apparatus and method, a random number generation system, and a chip, used for solving the problem of low efficiency of random number generation due to the use of a software program. The random number generation apparatus comprises at least one generator. The at least one generator contains a generator for synchronously generating a plurality of random numbers according to random number seeds. When the at least one generator is a plurality of generators, the random number generation apparatus further comprises a first selector for selecting, according to a first parameter, a random number generated by one of the plurality of generators.

Description

Random number generating device and generating method, random number generating system, chip

technical field

The present application relates to the technical field of neural networks, and in particular, to a random number generation device and generation method, a random number generation system, and a chip.

Background technique

Artificial intelligence (AI) technology has been widely used in social life and production, and it is also the development trend of future technologies and products. Various AI technologies are currently widely used in machine vision, image recognition, face recognition, object detection, intelligent driving, speech recognition, natural language processing, machine translation, speech generation, and text-to-speech.

The core of AI technology is the neural network system, and one of the keys to the normal operation of the neural network system is randomness. Whether it is neural network inference or neural network training, efficient random number generation is required. important part.

In related technologies, a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU) are usually used to control a software program (instruction fetch or operation). To generate random numbers, in the process of generating random numbers in this way, after the previous random number is generated, the next random number can be generated in a cycle, which is inefficient. Due to the increasing scale of the current neural network system, the amount of random number data required is also huge, and the random number generated by the control of CPU, GPU or NPU can no longer meet the needs of the current neural network system, becoming one of the bottlenecks of the training performance of the neural network system. one.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a random number generating device and method, a random number generating system, and a chip, which are used to solve the problem of low efficiency in generating random numbers by using a CPU, GPU, or NPU to control a software program.

To achieve the above object, the application adopts the following technical solutions:

A first aspect of the embodiments of the present application provides an apparatus for generating random numbers, including: at least one generator, and at least one generator includes a generator for synchronously generating multiple random numbers according to random number seeds; In the case of multiple generators, the random number generating apparatus further includes a first selector; the first selector is configured to select and output the random number generated by one of the multiple generators according to the first parameter.

The random number generating device provided by the embodiment of the present application includes a generator that can synchronously generate multiple random numbers at the same time according to the random number seed. That is, there is no need to wait for the previous random number to be generated before starting to generate the next random number. Compared with the method in the related art in which a CPU, GPU or NPU is used to control a software program to generate random numbers (one random number is generated at a time, and the next random number can only be generated after the previous random number is generated), the random number provided by the embodiment of the present application The generation device has good parallelism (multiple random numbers can be formed synchronously), which can significantly improve the generation efficiency of random numbers and improve the throughput of the random number generation device. In addition, random numbers are generated by hardware structures such as generators. After CPU, GPU or NPU provides parameters such as random number seeds, there is no need for CPU, GPU or NPU to intervene (instruction fetch or operation), which can reduce CPU, GPU or The operating pressure of the NPU. Furthermore, the generator can synchronously generate multiple random numbers, and the specific number of synchronously generated multiple random numbers can be adjusted. For example, the number of synchronously generated random numbers can be adjusted to a larger number, and the generator has good scalability.

Optionally, at least one generator includes a first generator, and the first generator includes multiple parallel first pipelines; the multiple parallel first pipelines are used for synchronously generating multiple random numbers according to random number seeds. The first generator includes multiple parallel first pipelines, the multiple parallel first pipelines can synchronously form multiple first random numbers, and the number of parallel first pipelines can be expanded as required. In addition, during the generation of the first random number, the generation of the next first random number starts, and there is no need to wait for the end of the generation of the previous first random number. Therefore, the parallelism of the first generator in the random number generating apparatus provided by the embodiment of the present application is good, and the generation efficiency of the random number can be significantly improved. In addition, the generation of the first random number is completed by the hardware structure of the first pipeline, and the performance of the random number generation device can meet the requirements of the hardware pipeline structure in the large-scale neural network training scenario.

Optionally, the first pipeline includes a plurality of cascaded operation subcircuits; the operation subcircuit includes a plurality of parallel data deformation modules; the data deformation module is used to receive the first data, the second data, the third data, the first design For the fixed value and the second set value, the lower bit of the product of the first data and the first set value is used as the first output data; the result of XORing the second data and the third data, and, the first data and the first data The high bit of the product of a set value is XORed as the second output data; the data deformation module is also used to use the sum of the third data and the second set value as the third output data; or, except the data in the last stage In addition to the deformation module, the data deformation module in each stage is also used to use the sum of the third data and the second set value as the third output data; the first output data, the second output data and the first output data of the data deformation module in the previous stage The three output data are respectively used as the second data, first data and third data of the data deformation module in the latter stage; wherein, at least one bit of the random number seed is used as the third data of the first stage operation subcircuit; the last stage The first output data and the second output data of the operation sub-circuit are used as random numbers generated by the first pipeline. The structure is simple and easy to implement.

Optionally, at least one of the first data, the second data, the third data, the first set value, and the second set value received by the multiple data deformation modules in the first-stage operation subcircuit are different. In this way, at least one of the first output data, the second output data and the third output data obtained by the multiple data deformation modules included in the same operation subcircuit is different, so that the randomness of the first random number generated by the first pipeline can be improved. sex.

Optionally, at least one of the first set value and the second set value received by the two data deformation modules connected in the adjacent-stage operation subcircuit is different. The randomness of the first random number generated by the first pipeline can be improved.

Optionally, the first setting value and the second setting value received by the same data deformation module are the same.

Optionally, the data deformation module includes a first multiplier, a first XOR, a second XOR, and a first adder; the first multiplier is used to receive the first data and the first set value, and convert the first data Multiply with the first set value, and output the lower bit of the obtained product as the first output data; the first XOR is used to receive the second data and the third data, and perform XOR operation on the second data and the third data The second XOR is used to receive the output of the first XOR and the high position of the product of the first multiplier, after the output of the first XOR and the high position of the product of the first multiplier are carried out XOR operation, as the first XOR Two output data outputs; the first adder is used to receive the third data and the second set value, add the third data and the second set value, and output as the third output data.

Optionally, at least one generator further includes a second generator; the second generator includes a seed initialization generation subcircuit, a state rotation subcircuit, and an output subcircuit; the seed initialization generation subcircuit is used to initialize according to the random number seed, and generate A rotation chain including a plurality of initial values; the state rotation subcircuit includes a plurality of parallel second pipelines, and the plurality of parallel second pipelines are used to rotate the rotation chain; the output subcircuit includes at least one output line, at least An output line is used to deform the output of the state rotation subcircuit to generate multiple random numbers. The second generator includes multiple parallel second pipelines, and multiple update values output by the multiple parallel second pipelines at the same time, can rotate multiple data in the rotation chain synchronously, and improve the rotation update of the rotation chain efficiency, thereby improving the generation efficiency of the second random number. In the case where the second generator further includes multiple parallel output lines, the multiple update values output by the multiple parallel second pipelines at the same time can synchronize the rotation of multiple data in the rotation chain, improving the accuracy of the rotation. The rotation update efficiency of the chain, multiple parallel output lines deform and output multiple update values at the same time, which can further improve the generation efficiency of the second random number.

Optionally, the seed initialization generating sub-circuit is used to receive the fourth data, the third setting value, the fourth setting value and the fifth setting value, and after shifting the fourth data to the right by a bit, it is XORed with the fourth data. As a result, and, the third set value, the product obtained by multiplying; and again, after the fourth set value is added, and the fifth set value to perform the AND operation; the result of the AND operation is output as the initialization value; wherein , and the fourth data is a random number seed or an initialization value.

Optionally, the seed initialization generation subcircuit includes a first right shifter, a third XOR, a second multiplier, a second adder, and a first AND gate; the first right shifter is used to receive the fourth data, The fourth data is shifted right by a bit; the third XOR is used to receive the output of the first right shifter, and the output of the first right shifter is XORed with the fourth data; the second multiplier is used to receive the third XOR the output of the third multiplier and the third set value, multiply the output of the third XOR by the third set value; the second adder is used to receive the output of the second multiplier and the fourth set value, and multiply the third The output of the adder is added with the fourth set value; the first AND gate is used to receive the output of the second adder and the fifth set value, and perform AND operation on the output of the second adder and the fifth set value, as Initial value output.

Optionally, the second pipeline includes a parity selection module, an odd number generation module, an even number generation module and a second selector; the parity selection module is used to receive the fifth data, the sixth data, the sixth setting value and the seventh setting value, the result of the AND operation of the fifth data and the sixth set value, and the result of the AND operation of the sixth data and the seventh set value after the modulo, or the result of the operation and the modulo, and the result of the modulo output to the second selector and the even number generation module; the odd number generation module is used to receive the fifth data and the eighth set value, and output the fifth data and the eighth set value to the second selector after XORing; the even number The generation module is used for receiving the output of the seventh data and the parity selection module, and after shifting the output of the parity selection module to the right by b bits, and, the modulo result of the seventh data is XORed and then output to the second selector; The second selector is used to select and output the output of the odd number generation module or the even number generation module according to the output of the parity selection module, so as to rotate the rotation chain; wherein, the fifth data, the sixth data and the seventh data are different data in the rotation chain .

Optionally, the parity selection module includes a second AND gate, a first modulo, a third AND, a first OR, and a second modulo; the second AND gate is used to receive the fifth data and the first Six set values, perform AND operation on the fifth data and the sixth set value; the first modulo is used to receive the sixth data, and the sixth data is modulo; the third AND gate is used to receive the first modulo output and the seventh set value, perform AND operation on the output of the first modulo taker and the seventh set value; the first OR gate is used to receive the output of the second AND gate and the output of the third AND gate, and the The output of the second AND gate is ORed with the output of the third AND gate; the second modulo is used to receive the output of the first OR gate, modulo the output of the first OR gate, and take the result of the modulo Output to the second selector and even generation block.

Optionally, the odd-number generation module includes a fourth XOR; the fourth XOR is used to receive the fifth data and the eighth set value, and perform an XOR operation on the fifth data and the eighth set value, and the XOR The result is output to the second selector.

Optionally, the even number generation module includes a third modulo extractor, a second right shifter and a fifth XOR; the third modulo extractor is used to receive the seventh data, and the seventh data is modulo taken; the second right shifter is used for Receive the output of the parity selection module, and shift the output of the parity selection module to the right by b bits; the fifth XOR is used to receive the output of the third modulo extractor and the output of the second right shifter, and the output of the third modulo extractor and the output of the second right shifter are received. The output of the second right shifter is XORed, and the XORed result is output to the second selector.

Optionally, the output line is used to receive the output of the state rotation subcircuit, the ninth set value and the tenth set value, and to perform an exclusive OR with the output of the state rotation subcircuit after shifting the output of the state rotation subcircuit to the right by c bits. ; Then the XOR result, and, the XOR result is left shifted by d bits and the result of the ninth set value and operation, and then XOR is performed; then the XOR result, and the XOR result are left shifted by e bits and the tenth The result of the set value and operation is XORed; then the result of the XOR, and, the result of the XOR is shifted to the right by f bits, and the XOR is output as a random number.

Optionally, the output line includes the third right shifter, the sixth XOR, the first left shifter, the fourth AND gate, the seventh XOR, the second left shifter, the fifth AND gate, the first Eight XORs, a fourth right shifter, and a ninth XOR; the third right shifter is used to receive the output of the state rotation subcircuit, and shift the output of the state rotation subcircuit to the right by c bits. The sixth XOR is used to receive the output of the state rotation sub-circuit and the output of the third right shifter, and perform XOR operation between the output of the state rotation subcircuit and the output of the third right shifter; the first left shifter is used to receive the first left shifter. The output of the six XORs shifts the output of the sixth XOR to the left by d bits; the fourth AND gate device is used to receive the ninth set value and the output of the first left shifter, and the ninth set value and the first The output of the left shifter is ANDed; the seventh XOR is used to receive the output of the sixth XOR and the output of the fourth AND gate, and XOR the output of the sixth XOR with the output of the fourth AND gate. OR operation; the second left shifter is used to receive the output of the seventh XOR, and the output of the seventh XOR is left shifted by e; the fifth AND gate device is used to receive the tenth set value and the second left shifter. Output, perform AND operation between the tenth set value and the output of the second left shifter; the eighth XOR is used to receive the output of the fifth AND gate and the output of the seventh XOR, and the fifth AND gate The output is XORed with the output of the seventh XOR; the fourth right shifter is used to receive the output of the eighth XOR and shift the output of the eighth XOR right by f bits; the ninth XOR is used to receive the output of the eighth XOR. The output of the eight XOR and the output of the fourth right shifter perform XOR operation on the output of the eighth XOR and the output of the fourth right shifter, and the XOR result is output as a random number.

Optionally, the second generator further includes a third selector, an interworking register, and a first memory; the third selector is configured to receive the rotation chain before the rotation output by the seed initialization generation subcircuit and the rotation output by the state rotation subcircuit. The rear rotation chain, under the control of the selection control terminal, transmits the rotation chain before rotation or the rotation chain after rotation to the intercommunication register; the intercommunication register is used to receive the rotation chain output by the third selector, and transmit the rotation chain to the third selector. a memory for retrieving the data in the rotation chain in batches from the first memory, and transmitting them to the second pipeline as the fifth data, the sixth data and the seventh data; it is also used for transmitting the output of the state rotation sub-circuit to the output a subcircuit; a first memory for receiving and storing the rotating chain output by the interworking register. The signal transmission between the seed initialization generation sub-circuit and the state rotation sub-circuit, and the signal transmission between the state rotation sub-circuit and the output sub-circuit are realized by the intercommunication register. By sharing the same intercommunication register, the number of intercommunication registers can be reduced.

Optionally, the random number generating apparatus further includes: a data type conversion module, configured to perform data type conversion on the random numbers generated by at least one generator. Since the random number generated by the generator is a random number of a fixed data type, it is only applicable to a network training device for training random numbers of a specific data type, and the applicable scope of the random number generating device is relatively limited. By arranging a data type conversion module in the random number generating device, the data type of the random number generated by the generator can be converted so as to be applicable to different network training devices, and the applicable scope of the random number generating device can be improved.

Optionally, the data type conversion module includes at least one data type converter; the data type converter is used to convert the random number generated by at least one generator into a random number of a preset data type; the data type conversion module includes a plurality of data types. In the case of a converter, the data type conversion module further includes a fourth selector, and the fourth selector is used to select and output the result of one of the multiple data type converters according to the second parameter; wherein, the multiple data type conversion The preset data types of the random numbers obtained by the converter are different.

Optionally, the random number generating apparatus further includes a distribution conversion module, configured to perform distribution type conversion on the output of the data type conversion module. Since the random number generated by the generator is a random number of a fixed distribution type, it is only applicable to a network training device for training random numbers of a certain distribution type, and the applicable scope of the random number generating device is relatively limited. By arranging a distribution conversion module in the random number generating device, the distribution type of the random number generated by the generator can be converted so as to be applicable to different network training devices, and the applicable scope of the random number generating device can be improved.

Optionally, the distribution conversion module includes at least one distribution generator; the distribution generator is used to convert the random numbers output by the data type conversion module into random numbers that obey a preset distribution; when the distribution conversion module includes multiple distribution generators , the random number generating device further includes a fifth selector, and the fifth selector is used for selecting and outputting the result of one of the multiple distribution generators according to the third parameter; wherein, the random numbers converted by the multiple distribution generators obey the The preset distribution types are different.

Optionally, the at least one distribution generator includes a normal distributor, and the normal distributor uses a box-muller algorithm to convert the random numbers output by the data type conversion module into random numbers that obey a normal distribution. The normal distribution generator adopts a hardened box-muller structure. The box-muller algorithm is the normal distribution transformation algorithm used in the current mainstream digital deep learning framework. The normal distribution characteristics of the normally distributed random numbers formed by the box-muller algorithm are relatively The normal distribution characteristics of the simulated normal distribution random numbers formed by the irwin-hall algorithm are better. In addition, taking the fp32 data type as an example, the box-muller algorithm is used, the input is two uint32 random numbers that satisfy the uniform distribution, and the output is two fp32 random numbers that satisfy the standard normal distribution. Using the irwin-hall algorithm, the input of multiple uniformly distributed random numbers is added to generate a normally distributed random number. The irwin-hall algorithm has a larger requirement on the number of uniformly distributed random numbers. Compared with the irwin-hall algorithm, the box-muller algorithm has lower performance requirements on the generator under the condition of satisfying the same amount of data output.

In a second aspect of the embodiments of the present application, a method for generating random numbers is provided, including: a generator synchronously generates multiple random numbers according to random number seeds; The method further includes that the first selector selects and outputs a plurality of random numbers generated by one of the plurality of generators according to the first parameter. The random number generation method provided in the embodiment of the present application has the same beneficial effects as the random number generation device provided in the first aspect, and details are not described herein again.

Optionally, the generator synchronously generates multiple random numbers according to the random number seed, including: multiple parallel first pipelines (pipelines) in the first generator synchronously generate multiple random numbers according to the random number seed.

Optionally, the generator generates multiple random numbers synchronously according to the random number seed, including: the seed initialization generation subcircuit performs initialization according to the random number seed, and generates a rotation chain including multiple initial values; The second pipeline (pipeline) rotates the rotation chain; a plurality of parallel output lines in the output sub-circuit perform deformation processing on the output of the state rotation sub-circuit, and generate a plurality of random numbers synchronously.

Optionally, the random number generation method further includes: the data type conversion module performs data type conversion on the multiple random numbers generated by the generator.

Optionally, the random number generation method further includes: the distribution conversion module performs distribution type conversion on the output of the data type conversion module.

In a third aspect of the embodiments of the present application, a neural network system is provided, including a second memory and any random number generating device of the first aspect, where the second memory is used to store random numbers generated by the random number generating device.

The neural network system provided by the embodiments of the present application includes the random number generating apparatus provided in the first aspect, and the beneficial effects thereof are the same as those of the random number generating apparatus, which will not be repeated here.

Optionally, the second memory is further configured to store the index of the last random number generated by the random number generating device. In this way, the random number seed remains unchanged, and when the random number generating device performs the next task, the random number generating device can read back from the second memory the random number chain generated by the previous task and the cut-off index of the Mersenne rotation chain, ensuring that Continuous distribution of tasks and continuous generation of random numbers.

In a fourth aspect of the embodiments of the present application, a chip is provided, including a substrate and any random number generating device of the first aspect, wherein the random number generating device is disposed on the substrate.

The chip provided by the embodiment of the present application includes the random number generating apparatus provided in the first aspect, and the beneficial effects thereof are the same as those of the random number generating apparatus, which will not be repeated here.

A fourth aspect of the embodiments of the present application provides a random number generation device, including: a second generator; the second generator, including a seed initialization generation subcircuit, a state rotation subcircuit, and an output subcircuit; and a seed initialization generation subcircuit For initializing according to the random number seed, generating a rotation chain including a plurality of initial values; the state rotation subcircuit includes a plurality of parallel second pipelines (pipelines), and the plurality of parallel second pipelines are used to rotate the rotation chain; The output subcircuit includes an output line, and the output line is used for deforming the output of the state rotation subcircuit to generate a random number.

Description of drawings

1 is a frame diagram of a neural network system provided by an embodiment of the present application;

FIG. 2a is a frame diagram of a random number generating apparatus provided by an embodiment of the present application;

FIG. 2b is a frame diagram of another random number generating apparatus provided by an embodiment of the present application;

2c is a frame diagram of another random number generating device provided by an embodiment of the present application;

2d is a frame diagram of another random number generating apparatus provided by an embodiment of the present application;

FIG. 2e is a frame diagram of another random number generating apparatus provided by an embodiment of the present application;

3a is a frame diagram of another random number generating device provided by an embodiment of the present application;

Fig. 3b is a usage scenario diagram of a random number generating apparatus provided by an embodiment of the present application;

4a is a schematic diagram of a framework of a first pipeline provided by an embodiment of the present application;

FIG. 4b is a schematic diagram of a framework of another first pipeline provided by an embodiment of the present application;

FIG. 4c is a schematic structural diagram of a first pipeline provided by an embodiment of the present application;

4d is a schematic structural diagram of another first pipeline provided by an embodiment of the present application;

Fig. 5a is a usage scenario diagram of a first pipeline provided by an embodiment of the present application;

5b is a schematic diagram of a random number chain provided by an embodiment of the present application;

6a is a frame diagram of another random number generating apparatus provided by an embodiment of the present application;

FIG. 6b is a usage scenario diagram of another random number generating apparatus provided by an embodiment of the present application;

6c is a schematic diagram of a box-muller algorithm provided by an embodiment of the present application;

FIG. 7 is a usage scenario diagram of another random number generating apparatus provided by an embodiment of the present application;

8a is a frame diagram of another random number generating apparatus provided by an embodiment of the present application;

8b is a frame diagram of another random number generating apparatus provided by an embodiment of the present application;

FIG. 8c is a usage scenario diagram of another random number generating apparatus provided by an embodiment of the present application;

9a is a schematic structural diagram of a sub-initialization generating sub-circuit provided by an embodiment of the present application;

FIG. 9b is a schematic structural diagram of a second pipeline provided by an embodiment of the present application;

FIG. 9c is a schematic structural diagram of an output line provided by an embodiment of the present application;

10a is a schematic diagram of a framework of a second generator provided by an embodiment of the present application;

FIG. 10b is a schematic structural diagram of a second generator provided by an embodiment of the application;

FIG. 11 is a schematic structural diagram of another second generator provided by an embodiment of the present application;

Figure 12a is a schematic diagram of a rotating chain provided by an embodiment of the application;

FIG. 12b is a schematic diagram of the internal division of a first memory according to an embodiment of the present application;

13 is a frame diagram of another random number generating apparatus provided by an embodiment of the present application;

FIG. 14a is a usage scenario diagram of another random number generation apparatus provided by an embodiment of the present application;

FIG. 14b is a diagram of a usage scenario of another random number generating apparatus provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

Hereinafter, the terms "first", "second", etc. are only used for convenience of description, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first", "second", etc., may expressly or implicitly include one or more of that feature. In the description of this application, unless stated otherwise, "plurality" means two or more.

In addition, in the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to be defined relative to the schematic placement of components in the drawings, and it should be understood that these directional terms may be relative concept, they are used for relative description and clarification, which may change accordingly according to the change in the orientation in which the components are placed in the drawings.

In this application, unless expressly stated and defined otherwise, the term "connected" should be interpreted in a broad sense, for example,

The "connection" may be a fixed connection, a detachable connection, or an integral body; it may be a direct connection or an indirect connection through an intermediate medium. In addition, the term "electrical connection" may be a direct electrical connection or an indirect electrical connection through an intermediate medium.

The core of AI technology is a neural network system. As shown in FIG. 1 , the neural network system usually includes a random number generating device, a first memory, and a network training device. The random number generating device is used to generate random numbers. The network training device is used for performing network training according to the random numbers generated by the random number generating device, and generating training results. The first memory is used for storing random numbers generated by the random number generating device and training results generated by the network training device.

In order to facilitate the network training device to retrieve the random numbers stored in the memory, the memory can be a high bandwidth memory (HBM), such as a double data rate synchronous dynamic random access memory (double data rate synchronous dynamic random access memory, DDR SDRAM, referred to as DDR).

An embodiment of the present application provides an apparatus for generating random numbers, including at least one generator, and the at least one generator includes a generator for synchronously generating multiple random numbers according to a random number seed.

Among them, multiple random numbers are generated synchronously, which can be understood as multiple random numbers are generated at the same time, rather than multiple random numbers being generated one by one for multiple times in succession.

In addition, in the case where the random number generating apparatus provided in the embodiment of the present application includes a generator, the generator is configured to generate multiple random numbers synchronously according to the random number seed.

When the random number generating apparatus provided in the embodiment of the present application includes multiple generators, at least one generator among the multiple generators is configured to generate multiple random numbers synchronously according to the random number seed. Other generators in the multiple generators can generate multiple random numbers synchronously according to the random number seed, or can generate multiple random numbers sequentially from the random number seed.

Based on this, in some embodiments of the present application, as shown in FIG. 2a, the random number generating apparatus 100 includes a first generator 10, and the first generator 10 is configured to generate multiple random numbers synchronously according to the random number seed.

In other embodiments of the present application, as shown in FIG. 2 b , the random number generating apparatus 100 includes a first generator 10 , a second generator 20 and a first selector 30 .

The first generator 10 is configured to generate multiple random numbers synchronously according to the random number seed, and the second generator 20 is configured to sequentially generate multiple random numbers according to the random number seed. The first selector 30 is configured to select and output the random number generated by the first generator 10 or the second generator 20 according to the first parameter.

That is, when the random number generating apparatus 100 includes multiple generators, only the random number generated by one of the generators is selected and output at the same time. That is, when generating random numbers, when there are multiple generators to generate random numbers, the first selector selects and outputs a random number generated by one of the multiple generators according to the first parameter.

Based on this, when generating a random number, if necessary, the output is the random number generated by the first generator 10 . Exemplarily, the first generator 10 synchronously generates multiple random numbers according to the random number seed, the second generator 20 sequentially generates multiple random numbers according to the random number seed, and the first selector 30 selects and outputs the first generated number according to the first parameter. The random number generated by the generator 10.

Or, when generating the random number, if necessary, the output is the random number generated by the second generator 20 . Exemplarily, the first generator 10 synchronously generates multiple random numbers according to the random number seed, the second generator 20 sequentially generates multiple random numbers according to the random number seed, and the first selector 30 selects and outputs the second generated number according to the first parameter. The random number generated by the generator 20.

In other embodiments of the present application, as shown in FIG. 2 c , the random number generating apparatus 100 includes a first generator 10 , a second generator 20 and a first selector 30 .

The first generator 10 is used for synchronously generating multiple random numbers according to the random number seed, and the second generator 20 is used for synchronously generating multiple random numbers according to the random number seed. The first selector 30 is configured to select and output the random number generated by the first generator 10 or the second generator 20 according to the first parameter.

The principle used by the first generator 10 to generate multiple random numbers synchronously according to the random number seed and the principle used by the second generator 20 to generate multiple random numbers synchronously according to the random number seed may be the same. Exemplarily, the first generator 10 and the second generator 20 are the same generator.

In this way, if one of the first generator 10 and the second generator 20 fails to work normally, the other can be used as a backup to reduce the number of replacements of the neural network system or chip integrated with the random number generator 100 .

Of course, the principle used by the first generator 10 to synchronously generate multiple random numbers according to the random number seed and the principle used by the second generator 20 to synchronously generate multiple random numbers according to the random number seed may also be different. Exemplarily, the first generator 10 and the second generator 20 are different generators.

In this way, although the same random number seed is received, due to the different principles of the first generator 10 and the second generator 20 for generating random numbers, the random numbers finally generated by the two are also different, which can meet the requirements of different training scenarios. The requirements for random numbers increase the applicable range of the random number generating apparatus 100 .

It can be understood that the random number generating apparatus 100 may include multiple generators that can generate multiple random numbers synchronously, and the principles of generating random numbers by multiple generators may be the same, or may be completely different, and may not be exactly the same ( That is, some are the same, and some are different), and the above is only illustrated by taking the random number generating apparatus 100 including the first generator 10 and the second generator 20 as an example.

The random number generating apparatus 100 provided in the embodiment of the present application includes a first generator 10, and the first generator 10 can generate multiple random numbers synchronously at the same time according to the random number seed. That is, there is no need to wait for the previous random number to be generated before starting to generate the next random number. Compared with the method in the related art in which a CPU, GPU or NPU is used to control a software program to generate random numbers (one random number is generated at a time, and the next random number can only be generated after the previous random number is generated), the random number provided by the embodiment of the present application The generation device 100 has a good degree of parallelism (multiple random numbers can be formed synchronously), which can significantly improve the generation efficiency of random numbers and improve the throughput of the random number generation device 100 .

In addition, the random number is generated by the hardware structure of the generator (for example, the first generator 10 and the second generator 20). After the CPU, GPU or NPU provides parameters such as random number seeds, there is no need for the CPU, GPU or NPU to Intervention (instruction fetch or operation) can reduce the operating pressure of CPU, GPU or NPU.

Furthermore, the generator can synchronously generate multiple random numbers, and the specific number of synchronously generated multiple random numbers can be adjusted. For example, the number of synchronously generated random numbers can be adjusted to a larger number, and the generator has good scalability.

In some embodiments of the present application, as shown in FIG. 2d , the random number generating apparatus 100 further includes a data type conversion module 40 . The data type conversion module 40 is configured to perform data type conversion on the random numbers generated by the generators in the random number generating apparatus 100 (for example, the first generator 10 and the second generator 20 described above).

That is to say, in the process of generating the random number by the random number generating apparatus 100, after the generator generates the random number, the data type conversion module 40 converts the data type of the random number generated by the generator before outputting.

In some application scenarios, the data type of the random number generated by the generator may not be suitable for some network training devices. By setting the data type conversion module 40, the data type of the random number generated by the generator can be changed to be suitable for different networks. The training device can improve the applicable range of the random number generating device 100 .

In some embodiments of the present application, as shown in FIG. 2e , the random number generating apparatus 100 further includes a distribution conversion module 50 . The distribution conversion module 50 is configured to perform distribution type conversion on the random numbers output by the data type conversion module 40 .

That is to say, in the process of generating random numbers by the random number generating apparatus 100 , after the data type conversion module 40 performs data type conversion on the random numbers generated by the generator, the distribution conversion module 50 performs data type conversion on the random numbers output by the data type conversion module 40 . The distribution type is converted and then output.

By disposing the distribution conversion module 50 in the random number generating device 100, the distribution type of the random number generated by the generator can be converted, and a rich random number generating function can be provided to be applicable to different network training devices.

Based on this, the random number generating apparatus 100 provided by the embodiment of the present application mainly includes two parts: an engine (engine) and a distribution (distribution). Among them, the engine (generator) is used to generate a pseudo-random number sequence. The distribution (data type conversion module 40 and distribution conversion module 50) then maps these values to some mathematical distribution (eg, normal distribution, uniform distribution, or bitmask distribution) that lies within a fixed range. The functions are complete, so as to be suitable for different random number application scenarios in the neural network training process, and the applicable scope of the random number generation device 100 can be improved.

Hereinafter, the random number generating apparatus 100 provided by the embodiments of the present application will be described with several detailed examples. In the process of describing the random number generating apparatus 100, for the convenience of distinction, the random number generated by the first generator 10 is referred to as the first random number, and the random number generated by the second generator 20 is referred to as the second random number .

Example 1

As shown in FIG. 3 a , the random number generating apparatus 100 includes a first generator 10 , a data type conversion module 40 and a distribution conversion module 50 .

The first generator 10 includes a plurality of parallel first pipelines 11; the plurality of parallel first pipelines 11 are used for synchronously generating a plurality of first random numbers according to random number seeds.

As shown in FIG. 3b, the random number seed, for example, can be transmitted to the first flash memory through a peripheral bus (advanced peripheral bus, APB) through a CPU, a GPU, an NPU or a system scheduler, and is provided by the first flash memory to the first generator 10.

The first flash memory may be, for example, a first register.

The multiple parallel first pipelines 11 are used to generate multiple first random numbers synchronously according to the random number seed, that is to say, during the working process of the first generator 10, each first pipeline 11 generates at least one first random number according to the random number seed. random number. Multiple first pipelines 11 are arranged in parallel, and multiple first random numbers are generated synchronously at the same time. Multiple first pipeline11 generates multiple first random numbers at a time, and multiple first pipeline11 can be cycled multiple times to generate a random number chain including a large number of first random numbers. Multiple first pipeline11 generates multiple first random numbers each time. Random numbers have their corresponding index in the random number chain.

For example, each first pipeline11 can generate y first random numbers at a time, there are z parallel first pipeline11s, and multiple parallel first pipeline11 loops can generate y*z first random numbers at one time. A plurality of parallel first pipeline11 cycles w times to generate a random number chain including y*z*w first random numbers. Each first random number has a corresponding index in the random number chain.

That is to say, multiple parallel first pipeline11 loops generate multiple (for example, y*z) first random numbers at a time, and according to the target number of first random numbers, multiple parallel first pipeline11 can loop multiple times ( For example, w times) to generate the first random number of the target number.

Regarding the structure of the first pipeline 11 , in some possible embodiments, as shown in FIG. 4 a , the first pipeline 11 includes a plurality of cascaded operation sub-circuits 111 .

Among them, the first-level operation sub-circuit 111 represents one iteration of the operation in the operation sub-circuit 111. In FIG. 4a, the first pipeline 11 includes 10 cascaded operation sub-circuits 111 as an example for illustration, that is to say, the operation of the operation sub-circuit 111 is illustrated. The number of iterations is 10. Of course, the 10 cascaded operation sub-circuits 111 in FIG. 4a are only an illustration, and the embodiment of the present application does not make any limitation on the number of operation sub-circuits 111 included in the first pipeline 11 . For example, the number of operation sub-circuits 111 included in the first pipeline 11 may also be 5, 7, 8, 11, 13, and so on.

Regarding the structure of the operation sub-circuit 111, as shown in Fig. 4a, the operation sub-circuit 111 includes a plurality of parallel data transformation modules 112 (Fig. 4a takes two parallel data transformation modules 112 as an example for illustration).

As shown in Fig. 4a and Fig. 4b, the cascade connection of a plurality of operation sub-circuits 111 is realized by the cascade connection of a plurality of data deformation modules 112 in the operation sub-circuit 111. The data transformation module 112 is connected to the plurality of data transformation modules 112 in the subsequent stage operation sub-circuit 111 in a one-to-one correspondence.

The embodiment of the present application does not limit the corresponding connection relationship between the multiple data deformation modules 112 in the adjacent two-stage operation sub-circuits 111, and FIG. 4a and FIG. 4b are only a schematic representation.

Regarding the data deformation module 112, in some embodiments of the present application, as shown in FIG. 4c, the data deformation module 112 is configured to receive the first data, the second data, the third data, the first setting value and the second setting value, and the lower order of the product of the first data and the first set value is used as the first output data. The result of the XOR of the second data and the third data, and the high-order bit of the product of the first data and the first set value, is XORed as the second output data. The sum of the third data and the second set value is used as the third output data. The function of the data warping module 112 in each stage is the same.

Regarding the structure of the data warping module 112 for implementing the above functions, in some embodiments of the present application, as shown in FIG. "x" represents the first multiplier), the first XOR (in the drawings of the embodiments of the present application, the first "xor" is used to represent the first XOR), the second XOR (in the embodiments of the present application) In the drawings of the present application, the second "xor" is used to represent the second XOR) and the first adder (the first "+" is used to represent the first adder in the drawings of the embodiments of the present application).

The first multiplier is used for receiving the first data and the first set value, multiplying the first data and the first set value, and outputting the lower bit of the obtained product as the first output data.

The first XOR is used for receiving the second data and the third data, and performing an XOR operation on the second data and the third data.

The second XOR is used to receive the high-order bits of the product of the output of the first XOR and the first multiplier. Output data output.

The first adder is used for receiving the third data and the second setting value, adding the third data and the second setting value, and outputting the third data as the third output data.

In other embodiments of the present application, as shown in FIG. 4d , the data deformation module 112 is configured to receive the first data, the second data, the third data, the first set value and the second set value, and convert the first The lower order of the product of the data and the first set value is used as the first output data. The result of the XOR of the second data and the third data, and the high-order bit of the product of the first data and the first set value, is XORed as the second output data.

Except for the data deformation module 112 in the operation sub-circuit 111 of the last stage, the data deformation module 112 in the operation sub-circuit 111 of other stages is also used for taking the sum of the third data and the second set value as the third output data.

That is to say, the structure of the data deformation module 112 in the operation sub-circuit 111 of the last stage is different from that of the data deformation module 112 in the operation sub-circuits 111 of other stages.

Regarding the structure of the data deformation module 112 for realizing the above functions, as shown in FIG. 4d , except for the data deformation module 112 in the operation sub-circuit 111 of the last stage, the data deformation modules 112 in the operation sub-circuits 111 of other stages are the same as those shown in the preceding figures. The data warping module 112 shown in 4c is the same. The data transformation module 112 in the last stage operation sub-circuit 111 includes a first multiplier, a first XOR and a second XOR, and no longer includes a first adder.

In the following, for the convenience of description, the data transformation module 112 in each stage of the operation sub-circuit 111 has the same structure as an example for illustration.

In some embodiments of the present application, the multiple data transformation modules 112 included in the same operation sub-circuit 111 receive at least one of the first data, the second data, the third data, the first set value, and the second set value. a different.

In this way, the first output data, the second output data and the third output data obtained by the multiple data transformation modules 112 included in the same operation sub-circuit 111 are different in at least one, so that the first random number generated by the first pipeline 11 can be improved. randomness.

In addition, the first setting value and the second setting value received by the same data transformation module 112 may be the same or different. Similarly, the first set value and the second set value received by the two data deformation modules 112 connected in adjacent stages may be the same or different.

As shown in FIG. 4c , after a plurality of data deformation modules 112 are cascaded, the first output data, second output data and third output data of the data deformation module 112 in the previous stage of operation sub-circuit 111 are respectively used as the latter stage of operation. The second data, the first data and the third data of the data deformation module 112 in the sub-circuit 111 .

In the multi-stage operation sub-circuit 11 , the first output data and the second output data of the last-stage operation sub-circuit 111 are used as the first random numbers generated by the first pipeline 11 .

The first pipeline 11 generates multiple first random numbers synchronously according to the random number seed. In some embodiments of the present application, at least one bit (bit) of the random number seed is used as the third data of the first-stage operation sub-circuit 111 .

That is to say, the random number seed is composed of a string including a plurality of bits. In the case where the third data received by the plurality of data deformation modules 112 included in the first-stage operation sub-circuit 111 are different, the random number can be composed of The string of seeds is divided into multiple segments, which are respectively used as the third data of the multiple parallel data transformation modules 112 .

Exemplarily, the random number seed is a 64-bit string, the operator circuit 111 includes two parallel data transformation modules 112, the high 32 bits of the random number seed are used as the third data of a data transformation module 112, and the low 32 bits of the random number seed are used as the third data of the data transformation module 112. The third data of another data warping module 112 .

Based on the structure of the first pipeline 11 provided in this example, in some embodiments of the present application, multiple parallel first pipeline 11 are used to generate multiple first random numbers synchronously based on the random number seed based on the philox algorithm .

In some embodiments of the present application, the implementation of the philox algorithm may be philox4_32_10. That is, the philox algorithm can generate 4 first random numbers of 32-bit unsigned integer (unit) type at a time, and 10 represents the number of iterations of the operator circuit 111 in the first pipeline 11 (or understood as the number of cascades).

Of course, the above is only an illustration, and the philox algorithm can also generate two first random numbers at a time. The philox algorithm can also generate a first random number of type 64-bit unsigned integer (unit). The number of iterations of the operation is not limited to 10, and may be 5, 7, 8, 11, or the like.

Exemplarily, as shown in FIG. 5a, each stage of the operation subcircuit 111 in the first pipeline 11 includes a first data transformation module 112' and a second data transformation module 112".

The first data deformation module 112' in the first stage operation sub-circuit 111 receives the first data counter[1]', the second data counter[2]' and the third data key', and outputs the first output data result[1 ]', the second output data result[2]', and the third output data result[3]'.

The second data deformation module 112 in the first stage operation sub-circuit 111 "receives the first data counter[1]", the second data counter[2]" and the third data key", and outputs the first output data result[1 ]", the second output data result[2]", and the third output data result[3]".

The first output data result[1]' and the second output data result[2]' of the first data deformation module 112' in the operation sub-circuit 111 of the previous stage are used as the first output data of the second data deformation module 112" of the next stage. The two data counter[2]" and the first data counter[1]". The first output data result[1]" and the second output data result[ 2]", as the second data counter[2]' and the first data counter[1]' of the next-level first data deformation module 112'.

The third output data result[3]' of the first data transformation module 112' in the upper-level operation sub-circuit 111 is used as the third data key' of the next-level first data transformation module 112'. The third output data result[3]" of the second data transformation module 112" in the upper-level operation sub-circuit 111 is used as the third data key" of the next-level second data transformation module 112".

For the sake of clarity, the first data counter[1]', the second data counter[2]' and the third data key' received by the first data deformation module 112' and received by the second data deformation module 112" will not be described again. The first data counter[1]", the second data counter[2]" and the third data key", the first data counter[1]', the second data counter[2]' and the third data key' are mentioned , that is, the data received by the first data transformation module 112 ′. Mentioning the first data counter[1]", the second data counter[2]" and the third data key" means the data received by the second data transformation module 112".

Similarly, the description of the first output data result[1]', the second output data result[2]', the third output data result[3]' and the second data deformation module of the first data deformation module 112' will not be repeated. 112" of the first output data result[1]", the second output data result[2]", and the third output data result[3]". Referring to the first output data result[1]', the second output data result[2]' and the third output data result[3]', it means the data output by the first data transformation module 112'. Referring to the first output data result[1]", the second output data result[2]" and the third output data result[3]", it means the data output by the second data transformation module 112".

As shown in Fig. 5a, the first output data result[1]", the second output data result[2]", the first output data result[1]" and The second output data result[2]" is used as the first random number generated by the first pipeline11.

The first data counter[1]' and the second data counter[2]' received by the first data deformation module 112' in the first-stage operation sub-circuit 111 and the first data received by the second data deformation module 112" counter[1]" and second data counter[2]" are respectively the index of the four first random numbers to be generated by the first pipeline 11 in the random number chain to be generated by the first generator 10 (a 32-bit data).

Exemplarily, as shown in FIG. 5a, the first data counter[1]', the second data counter[2]', the first data counter[1]" and the second data counter[2] of the first stage operation subcircuit 111 ]" can be provided by the second flash.

The first flash memory outputs the index of the four first random numbers to be generated by the first pipeline11 in the random number chain (128-bit counter_start data), and the second flash memory receives the 128-bit counter_start data output by the first flash memory and outputs it to the first flash memory. The first-level operation sub-circuit 111. The corresponding four indexes (32-bit data) in the 128-bit counter_start data are respectively used as the first data counter[1]', the second data counter[2]', and the first data counter[1] " and the second data counter[2]".

The third data counter[1]' received by the first data deformation module 112' in the first stage operation sub-circuit 111 and the third data counter[3]" received by the second data deformation module 112" are respectively the random number seed key. (64bit data) high 32bit and low 32bit.

Exemplarily, as shown in FIG. 5a, the third data key' and the third data key" of the first-stage operation sub-circuit 111 may be provided by the third flash memory.

The first flash memory outputs the random number seed key of the first generator 10 , and the third flash memory receives the random number seed key output by the first flash memory, and outputs it to the first stage operation sub-circuit 111 . The high 32 bits and the low 32 bits of the random number seed key are used as the third data key' and the third data key" respectively.

The second flash memory may be, for example, a second register, and the third flash memory may be, for example, a third register.

As shown in Figure 5b, a random number seed key corresponds to a random number chain. The generation of the first random number by the first pipeline 11 once is called a cycle, and the bits of the random number seeds received synchronously by multiple parallel first pipeline 11s in the same cycle are different. That is, the third data key' and the third data key" received synchronously by a plurality of parallel first pipelines 11 in the same cycle are different.

The bits of the random number seeds received by the same first pipeline11 in different cycles are the same, that is, the third data key' or the third data key' received by the same first pipeline11 in different cycles are the same. That is, receiving The first pipeline11 of the third data key', the third data key' received in each cycle is always the same. The first pipeline11 of the third data key "received in each cycle, the third data key" received in each cycle always the same.

One counter_start data corresponds to generating four first random numbers. In the process of generating the first random number, the input of the counter_start data is continuous, and the output of each first pipeline11 is also continuous. During the process of continuously generating the first random number by the first pipeline 11, the counter_start data received by the same first pipeline 11 in different cycles are different.

Exemplarily, as shown in FIG. 5a, when the operation of the first counter_start data (counter_start[0]) enters the second stage operation subcircuit 111, the first stage operation subcircuit 111 starts to process the second counter_start data (counter_start[0]). 16]) to perform the operation.

Illustratively, as shown in FIG. 3b, the first flash memory may be controlled by a pipeline control module (pipe_ctrl) to output corresponding counter_start data at different times.

Regarding the internal structure of the operation sub-circuit 111, as shown in FIG. 5a, the first data transformation module 112' includes a first multiplier, a first XOR, a second XOR and a first adder.

The first multiplier is used to receive the first data counter[1]' and the first set value, multiply the first data counter[1]' and the first set value, and use the lower 32 bits of the obtained product as the first Output data result[1]' output.

It can be seen from the above description that, for example, the first data counter[1]' received by the first-level first data deformation module 112' is the first random number among the four first random numbers to be generated by the first pipeline 11. The index of the number in the random number chain (32bit data). The first data counter[1]' received by the first data transformation module 112' of the other stage is the second output data result[2]" of the second data transformation module 112" of the previous stage.

The first XOR is used to receive the second data counter[2]' and the third data key', and perform an XOR operation on the second data counter[2]' and the third data key'.

It can be seen from the above description that, for example, the second data counter[2]' received by the first-level first data deformation module 112' is the second first random number among the four first random numbers to be generated by the first pipeline 11. The index of the number in the random number chain (32bit data). The second data counter[2]' received by the first data transformation module 112' of the other stage is the first output data result[1]" of the second data transformation module 112" of the previous stage.

The third data key' received by the first-level first data deformation module 112' is the high 32 bits of the random number seed key. The third data key' received by the first data transformation module 112' of the other stage is the third output data result[3]' of the first data transformation module 112' of the previous stage.

The second XOR is used to receive the high 32 bits of the product of the output of the first XOR and the first multiplier. The second output data result[2]' is output.

The first adder is configured to receive the third data key' and the second set value, add the third data key' and the second set value, and output the third data key' and the second set value as the third output data result[3]'.

The second data warping module 112" includes a first multiplier, a first XOR, a second XOR, and a first adder.

The first multiplier is used to receive the first data counter[1]" and the first set value, multiply the first data counter[1]" with the first set value, and use the lower 32 bits of the obtained product as the first Output data result[1]" output.

It can be seen from the above description that, for example, the first data counter[1]" received by the first-level second data deformation module 112 "is the third first random number among the four first random numbers to be generated by the first pipeline11" The index of the number in the random number chain (32bit data). The first data counter[1]' received by the second data transformation module 112'' of the other stage is the second output data result[2]' of the first data transformation module 112' of the previous stage.

The first XOR is used to receive the second data counter[2]" and the third data key", and perform an XOR operation on the second data counter[2]" and the third data key".

It can be seen from the above description that, for example, the second data counter[2]" received by the first-level second data deformation module 112 "is the fourth first random number among the four first random numbers to be generated by the first pipeline11" The index of the number in the random number chain (32bit data). The second data counter[2]' received by the second data transformation module 112'' of the other stage is the first output data result[1]' of the first data transformation module 112' of the previous stage.

The third data key "received by the first-level second data deformation module 112" is the lower 32 bits of the random number seed key. The third data key" received by the second data transformation module 112" of the other stage is the third output data result[3]" of the second data transformation module 112" of the previous stage.

The second XOR is used to receive the high 32 bits of the product of the output of the first XOR and the first multiplier. The second output data result[2]" is output.

The first adder is used for receiving the third data key" and the second setting value, adding the third data key" and the second setting value, and outputting the result as the third output data result[3]".

The first set value and the second set value received by the first data deformation module 112 ′ are the same, and the first set value and the second set value received by the second data deformation module 112 ″ are the same. The first data deformation module The first set value and the second set value received by the module 112 ′ are different from the first set value and the second set value received by the second data transformation module 112 ″.

The data type conversion module 40 in the random number generating apparatus 100 is configured to perform data type conversion on the first random number generated by the first generator 10 in the random number generating apparatus 100 .

In some embodiments of the present application, as shown in FIG. 6a, the data type conversion module 40 includes a data type converter 41, and the data type converter 41 is used to convert the first random number generated by the first generator 10 into a predetermined Let the random number of the data type.

The structure of the data type converter 41, in some embodiments of the present application, the data type converter 41 is a truncated floating point 16-bit (bfp16) converter. The bfp16 converter is used to convert the first random number generated by the first generator 10 into a bfp16 type random number.

For example, based on the philox algorithm, the data type of the first random number generated by the first generator 10 is uint32, and the bfp16 converter, according to the IEEE754 standard, reserves the lower 10 bits of the uint32 and fills the upper bits with 9 bits (001111111) to generate a range between 1 and 1. The floating point number of 2 is then subtracted by 1 to convert the data type of the first random number from uint32 to bfp16.

In other embodiments of the present application, the data type converter 41 is a floating point 16bit (fp16) converter. The fp16 converter is used to convert the first random number into a random number of fp16 type.

For example, the data type of the first random number is uint32, and the fp16 converter, according to the IEEE754 standard, generates a floating-point number in the range of 1 to 2 by reserving the lower 7 bits of uint32 and filling the upper bits with 6 bits (001111), and then subtracting 1 to realize the The data type of the first random number is converted from uint32 to fp16.

In other embodiments of the present application, the data type converter 41 is a floating point 32bit (fp32) converter. The fp32 converter is used to convert the first random number into a random number of fp32 type.

For example, the data type of the first random number is uint32, and the fp32 converter, according to the IEEE754 standard, generates a floating-point number in the range of 1 to 2 by reserving the lower 23 bits of uint32 and filling the upper bits with 9 bits (001111111), and then subtracting 1 to realize the The data type of the first random number is converted from uint32 to fp32.

In other embodiments of the present application, the data type converter 41 is a 32-bit unsigned integer (uint32) converter. The uint32 converter is used to convert the first random number to a random number of 32-bit unsigned integer type.

It can be understood that, when the data type of the first random number is uint32, the uint32 converter plays a role in transmitting the first random number.

In other embodiments of the present application, the data type converter 41 is a 64-bit unsigned integer (uint64) converter. The uint64 converter is used to convert the first random number to a random number of 64-bit unsigned integer type.

In other embodiments of the present application, the data type converter 41 is a 32-bit signed integer (int32) converter. The int32 converter is used to convert the first random number to a random number of 32-bit signed integer type.

In other embodiments of the present application, the data type converter 41 is a 64-bit signed integer (int64) converter. The int64 converter is used to convert the first random number to a random number of 64-bit signed integer type.

It can be seen from the above description that the data type of the random number converted by the data type converter 41 is related to the selection of the data type converter 41, which type of data type converter 41 the data type conversion module 40 includes, and the random number obtained by conversion. The data type of is the data type corresponding to the data type converter 41 . Therefore, the preset data type here can be understood as the data type corresponding to the data type converter 41 .

In other embodiments of the present application, as shown in FIG. 6 b , the data type conversion module 40 includes a plurality of data type converters 41 and a fourth selector 42 .

The data type converter 41 is used to convert the first random number generated by the first generator 10 into a random number of a preset data type.

The preset data types of the random numbers converted by the plurality of data type converters 41 are different. The data type converter 41 may be, for example, the above-mentioned bfp16 converter, fp16 converter, fp32 converter, uint32 converter, uint64 converter, int32 converter, or int64 converter.

The fourth selector 42 is used for selecting a random number generated for one of the plurality of data type converters 41 according to the second parameter.

For example, the second parameter can be transmitted to the first flash memory through the system scheduler, CPU, GPU or NPU, and the first flash memory is transmitted to the fourth selector 42 .

Since the first random number generated by the first generator 10 is a random number of a fixed data type, it is only applicable to a network training device that trains random numbers of a certain data type, and the scope of application of the random number generating device 100 is relatively limited. big. By setting the data type conversion module 40 in the random number generating apparatus 100, the data type of the first random number generated by the first generator 10 can be converted so as to be applicable to different network training apparatuses, and the performance of the random number generating apparatus 100 can be improved. Scope of application.

The distribution conversion module 50 in the random number generation device 100 is configured to perform distribution type conversion on the random numbers output by the data type conversion module 40 .

In some embodiments of the present application, as shown in FIG. 6a, the distribution conversion module 50 includes a distribution generator 51, and the distribution generator 51 is used to convert the random numbers output by the data type conversion module 40 into random numbers that obey a preset distribution. number.

In some embodiments of the present application, the distribution generator 51 is a bitmask gen. The bit mask distributor is used to convert the random numbers output by the data type conversion module 40 into random numbers that obey the mask distribution.

Taking the random number output by the data type conversion module 40 obeying a uniform distribution as an example, the bit mask distributor compares the number output by the data type conversion module 40 with a set parameter (such as a software-configured dropout ratio), If it is less than the inactivation ratio, output 0, otherwise output 1 to achieve the mask effect.

In other embodiments of the present application, the distribution generator 51 is a normal distributor (normal gen), and the normal distributor is used to convert the random numbers output by the data type conversion module 40 into random numbers that obey a normal distribution.

The normal distribution generator can be, for example, a normal distribution generator of any mean and variance or a truncated normal distribution generator.

Exemplarily, the normal distributor may use the box-muller algorithm to generate normally distributed random numbers subject to any mean and variance.

As shown in Figure 6c, the box-muller algorithm is used to convert two uint32 type data that satisfy the uniform distribution into two fp32 type data that satisfy the standard normal distribution as an example:

(1) First, convert the uint32 data x0 and x1 output by the first generator 10 into floating-point numbers u1 and v1 of 0-1.

(2) Compare u1 with 1.0e-7f, if u1<1.0e-7f, then u1=1.0e-7f; otherwise, u1 remains unchanged.

(3)

v2=2.0*π*v1.

(4) f0_tmp=sin(v2); f1_tmp=cos(v2).

(5) f0=u2*f0_tmp; f1=u2*f1_tmp.

The box-muller algorithm is the normal distribution transformation algorithm used in the current mainstream digital deep learning framework. The normal distribution uses the normal distribution characteristics of the normal distribution random numbers formed by the box-muller algorithm. The normal distribution characteristics of the simulated normal distribution random numbers formed by the Algorithm) are better.

In addition, taking the fp32 data type as an example, the box-muller algorithm is used, the input is two uint32 random numbers that satisfy the uniform distribution, and the output is two fp32 random numbers that satisfy the standard normal distribution. Using the irwin-hall algorithm, the input of multiple uniformly distributed random numbers is added to generate a normally distributed random number. The irwin-hall algorithm has a larger requirement on the number of uniformly distributed random numbers. Compared with the irwin-hall algorithm, the box-muller algorithm has lower performance requirements on the generator under the condition of satisfying the same amount of data output.

Exemplarily, the absolute value of the data output by the data type conversion module 40 can also be compared with 2, the ones less than 2 are retained, and those greater than or equal to 2 are discarded, so as to generate random numbers that obey the truncated normal distribution.

In other embodiments of the present application, the distribution generator 51 is a uniform gen, and the uniform gen is used to convert the random numbers output by the data type conversion module 40 into random numbers that obey a uniform distribution.

It can be understood that, if the output of the data type conversion module 40 is a random number of the uint32 type that is uniformly distributed, the uniform distributor is equivalent to transmitting the random number output by the data type conversion module 40 .

It can be seen from the above description that the type of distribution obeyed by the random numbers converted by the distribution generator 51 is related to the selection of the distribution generator 51 , which type of distribution generator 51 the distribution conversion module 50 includes, and the distribution obeyed by the converted random numbers The type is the distribution type corresponding to the distribution generator 51 . Therefore, the preset distribution here can be understood as the distribution type corresponding to the distribution generator 51 .

In other embodiments of the present application, as shown in FIG. 6 b , the distribution conversion module 50 includes a plurality of distribution generators 51 and a fifth selector 52 .

The distribution generator 51 is configured to convert the random numbers output by the data type conversion module 40 into random numbers obeying a preset distribution.

The random numbers converted by the multiple distribution generators 51 obey different preset distribution types. The distribution generator 51 may be, for example, the above-mentioned bitmask distributor, normal distributor, or uniform distributor.

The fifth selector 52 is configured to select and output the random number generated by one of the plurality of distribution generators 51 according to the third parameter.

For example, the third parameter may be transmitted to the first flash memory through the system scheduler, CPU, GPU or NPU, and the first flash memory may be transmitted to the fifth selector.

Since the first random number generated by the first generator 10 is a random number of a fixed distribution type, it is only suitable for a network training device that trains random numbers of a certain distribution type, and the scope of application of the random number generating device 100 is relatively limited. big. By disposing the distribution conversion module 50 in the random number generating apparatus 100, the distribution type of the first random number generated by the first generator 10 can be converted so as to be applicable to different network training apparatuses, and the applicability of the random number generating apparatus 100 can be improved. scope.

In some embodiments of the present application, as shown in FIG. 7 , the random number generating apparatus 100 further includes an output control module 60 . The output control module 60 is configured to buffer the first random number generated by the first generator 10 and output the first random number generated by the first generator 10 .

It can be understood that, when the random number generating apparatus 100 further includes the data type conversion module 40 and the distribution conversion module 50, the output control module 60 is configured to cache the random numbers generated by the distribution conversion module 50, and output the distribution conversion module. 50 Generated random numbers.

When the above-mentioned random number generating apparatus 100 is applied to the above-mentioned neural network system, the first random number generated by the random number generating apparatus 100 is stored in the second memory of the above-mentioned neural network system, and the output control module 60 and the second memory may be, for example, Interact through the AXI (advanced extensible interface) protocol for the network training device to call. The second memory may be, for example, DDR SDRAM.

In some embodiments, the second memory is further used for storing the index of the last first random number generated by the random number generating apparatus 100 .

That is, the second memory is used for storing the cutoff index of the random number chain generated by the random number generating apparatus 100 . The cutoff index can be understood as the index of the last first random number in the random number chain.

For example, after the random number seed is given, after this task is executed, the first generator 10 generates a random number chain with a length of 100,000 (including 100,000 first random numbers), and the bits of the 100,000th first random number are generated. Labeled 99999, 99999 is stored in the second memory. After the next task is issued, the index of the generated random number chain will start from 100000 instead of 0. That is to say, although the random number seed is the same, the first counter_start data received by this task is different from the first counter_start data received by the next task. Therefore, the first random numbers generated by each task are different.

In this way, by storing the index of the last first random number generated by the random number generating apparatus 100 in the second memory, when the random number generating apparatus 100 performs the next task, if the random number seed remains unchanged, the random number will be generated. The device 100 can read back the last index of the first random number generated by the last task from the second memory, instead of starting from 0 again. To ensure the continuous distribution of tasks, and the first random number generated by each task is different, it can be realized that there is an intermediate state in the process of random number generation.

In some embodiments of the present application, as shown in FIG. 7 , the random number generating apparatus 100 further includes an interrupt management module. The interrupt management module is used to output normal interrupt request and abnormal interrupt request.

That is, the interrupt request includes a random number generation complete normal interrupt and a random number generation incomplete abnormal interrupt. The interrupt management module transmits the interrupt request to the first flash memory, the first flash memory transmits the normal interrupt request to the processor (such as the system scheduler, CPU, GPU or NPU) of the neural network system through the first transmission line ioc, and the first flash memory transmits the normal interrupt request through the first transmission line ioc. The second transmission line ioe transmits the abnormal interrupt request to the processor of the neural network system. The processor outputs corresponding control instructions according to the received interrupt request type.

For example, when the processor receives a normal interrupt request, it indicates that the random number corresponding to the current seed has been generated, and the processor can output relevant parameters of the next task to the random number generating apparatus 100 . When the processor receives the abnormal interrupt request, it indicates that the generation of the random number corresponding to the current seed is not completed, and the processor can re-output the relevant parameters of the current task to the random number generating apparatus 100 .

It can be seen from the above description that the random number generation device 100 in the embodiment of the present application is provided with a flash memory configuration interface, the hardened transfer module, CPU, GPU or NPU configures the first flash memory, and transmits the second parameter and the third parameter respectively through the first flash memory to the fourth selector 42 and the fifth selector 52 . The software and hardware interfaces of the random number generating device 100 are flexible, and the working mode and parameters can be flexibly set. The random number generation process does not require the intervention of the system scheduler, CPU, GPU or NPU, reducing the need for the system scheduler, CPU, GPU or NPU. operating pressure.

In addition, after the system scheduler, the CPU, the GPU or the NPU issues the task, the random number generating apparatus 100 starts to work. As shown in FIG. 7 , the system scheduler, CPU, GPU or NPU can also send tasks to the first flash memory, and the first flash memory transmits the enable signal to the first generator 10 , and the system scheduler, CPU, etc. are not required in the subsequent process. , GPU or NPU intervention.

In some embodiments, the first flash memory includes a parameter register and a start register, where the parameter register is used for storing parameters, and the start register is used for storing task instructions.

The above random number generating apparatus 100 provided by the embodiment of the present application receives parameters such as random number seeds configured by software, generates a large number of first random numbers through a hardware structure, and stores them in the configured second memory.

In this example, the first generator 10 includes multiple parallel first pipelines 11 , the multiple parallel first pipelines 11 can simultaneously form multiple first random numbers, and the number of parallel first pipelines 11 can be expanded as required. In addition, during the generation of the first random number, the generation of the next first random number starts, and there is no need to wait for the end of the generation of the previous first random number. Therefore, the parallelism of the first generator 10 in the random number generating apparatus 100 provided by the embodiment of the present application is good, and the generation efficiency of the random number can be significantly improved. And the generation of the first random number is completed by the hardware structure of the first pipeline11, and the performance of the random number generation device 100 can meet the requirements of the hardware pipeline structure in the large-scale neural network training scenario.

In addition, the philox algorithm (eg philox4_32_10) is used to generate the first random number in the first pipeline11, which can pass the TestU01 test. And when the present invention uses 32 parallel first pipelines 11 to generate the first random number, the bitmask (bit mask) can generate up to 100Gb/s, which is close to the throughput performance of 100 CPUs using the ARS-2 (two advanced loop encryption) algorithm. , the first generator 10 can achieve higher throughput.

Example 2

The difference between Example 2 and Example 1 is that the random number generating apparatus 100 includes a second generator 20 .

As shown in FIGS. 8 a and 8 b , the random number generating apparatus 100 includes a second generator 20 , a data type conversion module 40 , a distribution conversion module 50 and an output control module 60 .

The second generator 20 includes a seed initialization generation subcircuit 21 , a state rotation subcircuit 22 and an output subcircuit 23 .

The seed initialization generation subcircuit 21 is used for initialization according to the random number seed, and generates a rotation chain including a plurality of initial values.

As shown in FIG. 8c , the random number seed may be transmitted to the first flash memory through the APB through the CPU, GPU, NPU or system scheduler, for example, and provided by the first flash memory to the second generator 20 .

The first flash memory may be, for example, a first register.

Regarding the manner in which the seed initialization subcircuit 21 generates multiple initial values, in some embodiments of the present application, the seed initialization generation subcircuit 21 is configured to receive fourth data, a third set value, a fourth set value, and a fifth set value. Set the value, and perform the XOR operation with the fourth data after shifting the fourth data to the right by a bit. The result obtained by the exclusive OR operation is multiplied by the third set value. The multiplied product is then added to the fourth set value. The sum obtained by the addition is ANDed with the fifth set value. The result of the AND operation is output as the initial value.

This process of generating initial values is repeated to obtain a rotation chain including a plurality of initial values.

Among them, the seed initialization subcircuit 21 is used for initialization according to the random number seed. Exemplarily, the fourth data received when the first initial value is generated is a random number seed. In the process of generating multiple initial values in subsequent loops, the generated initial values are used as the fourth data. That is, the last initial value is used as the fourth data of the next initial value to be generated.

Regarding the structure of the seed initialization sub-circuit 21 for realizing the above functions, in some embodiments of the present application, as shown in FIG. In the figure, the first ">>" is used to represent the first right shifter), the third XOR (the third "xor" is used to represent the third XOR in the drawings of the embodiments of this application), the second multiplier ( In the drawings of the embodiments of the present application, the second "x" is used to represent the second multiplier), the second adder (the second "+" is used to represent the second adder in the drawings of the embodiments of the present application), and the first An AND gate (in the drawings of the embodiments of the present application, the first "&" is used to represent the first AND gate).

The first right shifter is used for receiving the fourth data, and right-shifting the fourth data by a bits.

The third XOR is used for receiving the output of the first right shifter, and performing an XOR operation on the output of the first right shifter and the fourth data.

The second multiplier is used for receiving the output of the third XOR and the third set value, and multiplying the output of the third XOR with the third set value.

The second adder is used for receiving the output of the second multiplier and the fourth set value, and adding the output of the third multiplier and the fourth set value.

The first AND gate device is used for receiving the output of the second adder and the fifth set value, and performing AND operation on the output of the second adder and the fifth set value.

The output of the first AND gate is used as the output of the seed initialization sub-circuit 21, that is, the output of the first AND gate is output as the initial value.

It can be known from the above description that the fourth data is a random number seed or an initial value. Based on this, the first right shifter not only receives the random number seed transmitted by the first flash memory, but also receives the initial value output by the first AND gate.

Exemplarily, when the seed initialization generating sub-circuit 21 generates the first initial value, the first right shifter receives the random number seed. When the seed initialization generating sub-circuit 21 generates the second initial value, the first right shifter receives the first initial value output by the first AND gate. By analogy, when the seed initialization generating sub-circuit 21 generates the s-th initial value, the first right shifter receives the s-1-th initial value. By adjusting the cycle times of the seed initialization generating subcircuit 21, the number of initial values in the rotation chain can be adjusted.

As shown in Figures 8a and 8b, the state rotation sub-circuit 22 includes a plurality of parallel second pipelines 221 for rotating the rotation chain.

The state rotation subcircuit 22 includes a plurality of parallel second pipelines 221 , and at the same time, the plurality of parallel second pipelines 221 simultaneously rotate a plurality of values in the rotation chain. Among them, rotating the rotating chain can be understood as updating the data in the rotating chain.

In addition, it can be understood that since the state rotation sub-circuit 22 rotates the rotation chain (ie, updates the data in the rotation chain), the data in the rotation chain changes dynamically. In this way, the state rotation subcircuit 22 rotates the rotation chain, including the rotation of the initial value and the rotation of the updated value. Alternatively, it can be understood that the state rotation sub-circuit 22 rotates the rotation chain, including rotating the rotation chain containing multiple initial values, and also including rotating the rotation chain containing multiple rotated updated values.

In the embodiment of the present application, the seed initialization generating subcircuit 21 generates a rotation chain including a plurality of initial values, which is called a rotation chain before rotation. As the state rotation subcircuit 22 continuously updates the initial value in the rotation chain, the rotation chain generated by the state rotation subcircuit 22 including a plurality of updated values is called a rotated rotation chain. A plurality of parallel second pipelines 221 can be cycled multiple times, continuously cycle, and continuously update the rotation chain.

Regarding the manner in which the second pipeline 221 rotates the initial value, in some embodiments of the present application, as shown in FIG. 9b , the second pipeline 221 includes a parity selection module 2211 , an odd number generation module 2212 , an even number generation module 2213 and a second selector 2214.

The parity selection module 2211 is used to receive the fifth data, the sixth data, the sixth set value and the seventh set value, and the result of the AND operation of the fifth data and the sixth set value, and, the sixth data is obtained. The modulo and the result of AND operation with the seventh set value, the two are OR operation. Then, modulo the result of the OR operation, and output the modulo result to the second selector 2214 and the even number generating module 2213 .

Regarding the structure of the parity selection module 2211 for implementing the above functions, in some embodiments of the present application, as shown in FIG. The two "&" represent the second AND gate), the first modulo (in the drawings of the embodiments of this application, the first "mod" is used to represent the first modulo), the third AND gate (in this application In the drawings of the embodiments, the third "&" is used to represent the third AND gate), the first NOR gate (the first "or" is used to represent the first OR gate in the drawings of the embodiments of the present application) and the first NOR gate. Two modulo takers (in the drawings of the embodiments of the present application, the second modulo taker is represented by the second "mod").

The second AND gate is used to receive the fifth data and the sixth set value, and perform AND operation on the fifth data and the sixth set value.

The first modulo taker is used for receiving the sixth data and taking the modulo of the sixth data.

The third AND gate device is used to receive the seventh set value, and perform AND operation on the output of the first modulo extractor and the seventh set value.

The first OR gate is configured to receive the output of the second AND gate and the output of the third AND gate, and perform an OR operation on the output of the second AND gate and the output of the third AND gate.

The second modulo is used for receiving the output of the first OR gate, and taking the modulo of the output of the first OR gate.

The odd number generating module 2212 is configured to receive the fifth data and the eighth set value, perform an exclusive OR on the fifth data and the eighth set value, and output the result of the exclusive OR to the second selector 2214 .

Regarding the structure of the odd number generation module 2212 for implementing the above functions, in some embodiments of the present application, as shown in FIG. Four "xor" means the fourth XOR).

The fourth XOR is used for receiving the fifth data and the eighth setting value, performing an XOR operation on the fifth data and the eighth setting value, and outputting the XOR result to the second selector 2214 .

The even number generation module 2213 is used to receive the output of the seventh data and the parity selection module 2211, and after the output of the parity selection module 2211 is right-shifted by b bits, an XOR operation is performed with the modulo result of the seventh data, and the result of the XOR is output. to the second selector 2214.

Regarding the structure used by the even number generation module 2213 to realize the above functions, in some embodiments of the present application, as shown in FIG. The three "mod" represent the third modulo extractor), the second right shifter (in the drawings of the embodiments of the present application, the second ">>" represents the second right shifter) and the fifth XOR (in this In the drawings of the application embodiment, the fifth "xor" is used to represent the fifth XOR).

The third modulo is used for receiving the seventh data, and modulo the seventh data.

The second right shifter is used to receive the output of the parity selection module 2211 and right-shift the output of the parity selection module 2211 by b bits.

The fifth XOR is used to receive the output of the third modulo extractor and the output of the second right shifter, perform an XOR operation on the output of the third modulo extractor and the output of the second right shifter, and output the result of the XOR to the second selector 2214.

The second selector 2214 is configured to select and output the output of the odd number generation module 2212 or the even number generation module 2213 according to the output of the parity selection module 2211, so as to rotate the rotation chain.

Wherein, the output of the second modulo extractor in the parity selection module 2211 is an odd or even number, and the second selector 2214 is used to select and output the odd number generating module 2212 or the even number generating module according to the parity of the result output by the second modulo extractor The output of 2213, the output of the second selector 2214 is the updated value in the rotation chain.

The second pipeline 221 receives data in the rotating chain. In some embodiments of the present application, the fifth data, the sixth data, and the seventh data may be, for example, different data in the rotating chain.

Regarding the output sub-circuit 23, in some embodiments of the present application, as shown in FIG. After deforming and outputting, the output sub-circuit 23 finally deforms and outputs the output of the state rotation sub-circuit 22 to generate a plurality of second random numbers.

The second generator 20 provided in this example includes multiple parallel second pipelines 221 , and multiple update values output by the multiple parallel second pipelines 221 at the same time can rotate multiple data in the rotation chain synchronously, improving the accuracy of The rotation update efficiency of the rotation chain improves the generation efficiency of the second random number.

In other embodiments of the present application, as shown in FIG. 8 b , the output sub-circuit 23 includes a plurality of parallel output lines 231 , and the plurality of parallel output lines 231 are used for updating a plurality of values output by the state rotation sub-circuit 22 After synchronously deforming and outputting, the output sub-circuit 23 deforms and outputs the output of the state rotation sub-circuit 22, and generates a plurality of second random numbers synchronously.

The second generator 20 provided in this example includes multiple parallel second pipelines 221 and multiple parallel output lines 231. Multiple update values output by multiple parallel second pipelines 221 at the same time can be synchronized Rotate multiple data in the rotation chain to improve the rotation update efficiency of the rotation chain. Multiple parallel output lines 231 deform and output multiple update values at the same time, which can further improve the generation efficiency of the second random number .

In some embodiments, the number of output lines 231 included in the output sub-circuit 23 is the same as the number of the second pipelines 221 included in the state rotation sub-circuit 22 .

Regardless of how many output lines 231 the output sub-circuit 23 includes, the output lines 231 deform the update value in the same way.

In some embodiments of the present application, the output line 231 is used to receive the output of the state rotation sub-circuit 22, the ninth set value and the tenth set value, and to shift the output of the state rotation sub-circuit 22 to the right by c bits and the state The output of the rotary subcircuit 22 is XORed. Then, the XOR result, the sum, and the XOR result are left-shifted by d bits and the result of performing the AND operation with the ninth set value, and the XOR operation is performed on the two. Then, the XOR result, the sum, and the XOR result are left-shifted by e and the result of the AND operation with the tenth set value, and the XOR operation is performed on the two. Then, the XOR result, the sum, and the XOR result are shifted by f bits to the right, and the XOR operation is performed, and the XOR result is output as a second random number.

Regarding the structure of the output line 231 for realizing the above-mentioned functions, in some embodiments of the present application, as shown in FIG. ">>" represents the third right shifter), the sixth XOR (in the drawings of the embodiments of the present application, the sixth "xor" is used to indicate the sixth XOR), the first left shifter (in the present application In the drawings of the embodiments, the first "<<" is used to represent the first left shifter), the fourth AND gate (the fourth "&" is used to represent the fourth AND gate in the drawings of the embodiments of the present application), The seventh XOR (in the drawings of the embodiments of the present application, the seventh XOR is represented by the seventh "xor"), the second left shifter (in the drawings of the embodiments of the present application, the second "<< "represents the second left shifter), the fifth AND gate (in the drawings of the embodiments of this application, the fifth "&" is used to represent the fifth AND gate), the eighth XOR (in the In the drawings, the eighth "xor" is used to indicate the eighth XOR), the fourth right shifter (the fourth ">>" is used to indicate the fourth right shifter in the drawings of the embodiments of the present application) and the ninth XOR OR (a ninth XOR is represented by a ninth "xor" in the drawings of the embodiments of the present application).

The third right shifter is used for receiving the output of the state rotation sub-circuit, and right-shifting the output of the state rotation sub-circuit by c bits.

The sixth XOR is used to receive the output of the state rotation subcircuit and the output of the third right shifter, and to perform an XOR operation on the output of the state rotation subcircuit and the output of the third right shifter.

The first left shifter is used for receiving the output of the sixth XOR and shifting the output of the sixth XOR to the left by d bits.

The fourth AND gate is used to receive the ninth set value and the output of the first left shifter, and perform AND operation on the ninth set value and the output of the first left shifter.

The seventh XOR is used for receiving the output of the sixth XOR and the output of the fourth AND gate, and performing an XOR operation on the output of the sixth XOR and the output of the fourth AND gate.

The second left shifter is used for receiving the output of the seventh XOR and shifting the output of the seventh XOR to the left by e bits.

The fifth AND gate is used to receive the tenth set value and the output of the second left shifter, and perform AND operation on the tenth set value and the output of the second left shifter.

The eighth XOR is used for receiving the output of the fifth AND gate and the output of the seventh XOR, and performing XOR operation on the output of the fifth AND gate and the output of the seventh XOR.

The fourth right shifter is used for receiving the output of the eighth XOR, and right-shifting the output of the eighth XOR by f bits.

The ninth XOR is used to receive the output of the eighth XOR and the output of the fourth right shifter, and perform XOR operation on the output of the eighth XOR and the output of the fourth right shifter, and use the XOR result as the first XOR. Two random number outputs.

Regarding the way to realize the signal communication between the seed initialization generation sub-circuit 21 and the state rotation sub-circuit 22, and between the state rotation sub-circuit 22 and the output sub-circuit 23, as shown in FIG. 10a and FIG. 10b, the second generator 20 further includes The third selector 24 , the interworking register 25 and the first memory 26 .

The pre-rotation rotation chain output by the seed initialization generating sub-circuit 21 and the rotated rotation chain output by the state rotation sub-circuit 22 are respectively transmitted to the third selector 24 .

The third selector 24 is used to receive the rotation chain before rotation output by the seed initialization generating sub-circuit 21 and the rotation chain after rotation output by the state rotation sub-circuit 22. Under the control of the selection control terminal control, the rotation chain before rotation Or the rotated chain is transferred to the interworking register 25 .

The interworking register 25 is used to receive the rotation chain output by the third selector 24 . When the control signal output by the selection control terminal control is to control the third selector 24 to output the initial value output by the seed initialization generating sub-circuit 21, the intercommunication register 25 receives the rotation chain before rotation. When the control signal output by the selection control terminal control is to control the third selector 24 to output the updated value output by the state rotation sub-circuit 22, the intercommunication register 25 receives the rotated rotation chain.

In the process of generating the initial value by the seed initialization generating sub-circuit 21, one initial value is generated in a cycle, and finally a rotation chain including a plurality of initial values is generated. During the cycle, the intercommunication register receives the initial value every 25 minutes, and needs to store the received initial value.

Similarly, in the process of generating the update value by the state rotation sub-circuit 22, multiple update values are generated in one cycle. During the cycle, the intercommunication register receives the update value every 25 times, and needs to store the received update value.

Based on this, the intercommunication register 25 is used to transmit the received rotary chain to the first memory 26 , and the first memory 26 receives and stores the rotary chain output by the intercommunication register 25 .

Here, the first memory 26 may be, for example, a static random-access memory (static random-access memory, SRAM).

It can be seen from the above description that in the process of generating the second random number, the third selector 24, under the control of the control signal output by the selection control terminal control, firstly initializes the rotation including multiple initial values generated by the seed initialization generating sub-circuit 21 The chain is transferred to the interworking register 25 where it is stored in the first memory 26 . Then, the output of the state rotation subcircuit 22 is transmitted to the third selector 24 , and the third selector 24 transmits the updated value output by the state rotation subcircuit 22 to the interconnection register 25 under the control of the control signal output by the selection control terminal control. The intercommunication register 25 transmits the updated value output by the state rotation sub-circuit 22 to the first memory 26 to update the rotation chain in the first memory 26 . Continuous cycle, constantly updating the rotating chain.

In some embodiments of the present application, the rotation chain is stored in the first memory 26 , and when the state rotation subcircuit 22 rotates the rotation chain, the intercommunication register 25 transmits the rotation chain to each second pipeline 221 in the state rotation subcircuit 22 . , as the fifth data, sixth data and seventh data.

Based on this, the intercommunication register 25 is also used for retrieving the data in the rotation chain from the first memory 26 in batches and transferring it to the second pipeline 221 .

The intercommunication register 25 retrieves data in the rotation chain in batches from the first memory 26 , which means that the state rotation subcircuit 22 cycles once, and the intercommunication register 25 retrieves a batch of data in the rotation chain from the first memory 26 . During each cycle of the state rotation sub-circuit 22, the received data has a different index in the rotation chain, that is, the received data is different data in the rotation chain.

The state rotation subcircuit 22 rotates the rotation chain, and after outputting the update value, the output subcircuit 23 needs to receive the update value output by the state rotation subcircuit 22 to deform the output of the state rotation subcircuit 22 and output the second random number .

Based on this, the interworking register 24 also transmits the output (updated value) of the state rotation subcircuit 22 to the output subcircuit 23 .

In the process of generating the second random number, the state rotation subcircuit 22 rotates the data (initial value or update value) in the rotation chain, and the output subcircuit 23 performs deformation processing on the update value output by the state rotation subcircuit 22 , the synchronization can be completed.

For example, the state rotation subcircuit 22 performs rotation processing on the initial value of the first round, and outputs the updated value of the first round. The output subcircuit 23 performs deformation processing on the updated value of the first round, and outputs a second random number. At the same time, the state rotation subcircuit 22 performs rotation processing on the initial value of the second round, and outputs the updated value of the second round. The process of rotating the rotation chain and the process of processing the update value are performed synchronously, which can improve the generation efficiency of the second random number.

Based on this, the signal transmission between the seed initialization generation sub-circuit 21 and the state rotation sub-circuit 22, and the signal transmission between the state rotation sub-circuit 22 and the output sub-circuit 23 are realized through the intercommunication register 26, by sharing the same intercommunication register 25 , the number of intercommunication registers 25 can be reduced.

Based on the structure of the second generator 20 provided in this example, in some embodiments of the present application, the second generator 20 is configured to synchronously generate multiple second generators according to random number seeds based on a Mersenne twister (MT) algorithm. random number.

In some embodiments of the present application, the implementation of the Mersenne rotation algorithm may be the MT19937 algorithm.

Exemplarily, as shown in FIG. 11 , the second generator 20 includes a seed initialization generation subcircuit 21 , a state rotation subcircuit 22 , an output subcircuit 23 , a third selector 24 , an interworking register 25 and a first memory 26 .

The seed initialization generation subcircuit 21 receives the random number seed key, and the first right shifter right-shifts the random number seed key by 30 (ie, a=30). The third XOR performs XOR operation on the output of the first right shifter and the random number seed key. The second multiplier multiplies the output of the third XOR by 69069 (ie, the third set value=69069). The second adder adds the output of the second multiplier to s. The first AND gate performs an AND operation on the output of the second adder with 0xffffffff (ie, the fifth set value=0xffffffff), and outputs the result of the AND operation as the first initial value. The first initial value has a bit flag of 0.

Among them, s is the index of the initial value to be formed in the rotation chain. The position label of the initial value to be formed in the rotation chain is 0, then s=0.

Then, the seed initialization generating sub-circuit 21 receives the previously formed initial value, and the first right shifter will right-shift the initial value by 30. The third XOR XORs the output of the first right shifter with the initial value. The second multiplier multiplies the output of the third XOR by 69069. The second adder adds the output of the second multiplier to i. The first AND gate performs an AND operation on the output of the second adder with 0xffffffff, and outputs the result of the AND operation as the next initial value.

Loop the above process to get a rotating chain including 624 initial values.

The third selector 24 transmits the output of the seed initialization generating sub-circuit 21 to the intercommunication register 25 under the control of the selection control terminal control.

The intercommunication register 25 receives the output of the third selector 24, and transmits the received initial value to the first memory 26, and the first memory 26 receives and stores the initial value output by the intercommunication register 25 to form a rotating chain.

The intercommunication register 25 retrieves the data in the rotation chain in batches from the first memory 26 and transmits it to the state rotation sub-circuit 22 .

The state rotation sub-circuit 22 includes 16 parallel second pipelines 221, and each second pipeline 221 receives the data in the rotation chain retrieved by the interworking register 25 as the fifth data, the sixth data and the seventh data. Among them, the fifth data is the data with the bit label i in the rotation chain, the sixth data is the data with the bit label i+1 in the rotation chain, and the seventh data is the bit label in the rotation chain is (i+397) Data for the remainder of /624. The values of i in the fifth data, the sixth data and the seventh data received by the plurality of parallel second pipelines 221 are different.

For example, as shown in FIG. 12a , among the four parallel second pipelines 221 , the fifth data, sixth data and seventh data received by one second pipeline 221 are the data marked 0, 1, and 397 in the rotation chain in sequence. The fifth data, the sixth data and the seventh data received by the second pipeline 221 are the data marked 1, 2, and 398 in the rotation chain in sequence. The fifth data, the sixth data and the seventh data received by the second pipeline 221 are the data marked 2, 3, and 399 in the rotation chain in sequence. The fifth data, the sixth data and the seventh data received by the second pipeline 221 are the data marked 3, 4, and 400 in the rotation chain in sequence.

Each second pipeline 221 includes a parity selection module 2211 , an odd number generation module 2212 , an even number generation module 2213 and a second selector 2214 .

The parity selection module 2211 receives the data marked i in the rotation chain (the fifth data) and the data marked i+1 in the rotation chain (the sixth data), and the second AND gate marks the middle position of the rotation chain as The data of i is ANDed with 0x7fffffff (ie, the sixth setting value=0x7fffffff). The first modulo takes the modulo of the data marked i+1 in the rotation chain. The third AND gater performs an AND operation on the output of the first modulo taker with 0x80000000 (ie, the seventh set value=0x80000000). The first OR gate performs an OR operation on the output of the second AND gate and the output of the third AND gate. The second modulo takes the modulo of the output of the first OR gate, and outputs the modulo result to the second selector 2214 and the even number generating module 2213 .

The odd number generation module 2212 receives the data marked i in the rotation chain, and the fourth XOR XORs the data marked i in the rotation chain with the eighth set value, and outputs the result of the XOR to the first XOR. Two selectors 2214.

The even number generation module 2213 is used to receive the data (seventh data) marked as the remainder of (i+397)/624 in the rotation chain, and the second right shifter right-shifts the output of the parity selection module 2211 by 1 (ie, b = 1) bit. The third modulo takes the modulo of the data in the rotation chain marked with the remainder of (i+397)/624. The fifth XOR performs an XOR operation on the output of the third modulo and the output of the second right shifter, and outputs the XOR result to the second selector 2214 .

As shown in FIG. 12a , 16 parallel second pipelines 221 receive data (initial value or updated value) in the rotating chain synchronously, and the offsets of the fifth data of two adjacent second pipelines 221 in the rotating chain differ by 1.

The 16 parallel second pipelines 221 of the state rotation subcircuit 22 loop 39 times to complete the rotation of 624 pieces of data.

In this case, considering that only the data located in the same row can be read from the first memory 26 at a time, and the offsets of the fifth data and the seventh data are quite different, they are not located in the same row.

As shown in FIG. 12b , regarding the way of recalling the storage of 624 data in the rotation chain by the first memory 26, the first memory 26 includes a first buffer register (buffer) and a second buffer register, the first buffer register and the second buffer register The buffer registers store 624 pieces of data respectively. When the intercommunication register 25 retrieves data from the first memory 26, the first buffer register and the second buffer register alternately read and write, so as to provide data to 16 parallel second pipelines 221 .

As an example, the data obtained by accumulating the 39th row and the 1st row of the first buffer register is taken and marked as 17 data of 0, 1-16, and the 25th row and the 26th row of the second buffer register. The 16 data of 397-412 are taken and saved, and the 16 parallel second pipeline221 are calculated in parallel.

The fifth data, sixth data, and seventh data of the first and second pipeline221 correspond to the data marked 0, 1, and 397 in the rotation chain, respectively.

Among them, the remainder of (0+397)/624 is 397, and the seventh data corresponds to the data marked as 397 in the rotation chain.

The fifth data, sixth data and seventh data of the second second pipeline221 respectively correspond to the data marked 1, 2, and 398 in the rotation chain.

Among them, the remainder of (1+397)/624 is 398, and the seventh data corresponds to the data marked as 398 in the rotation chain.

The fifth data, sixth data and seventh data of the third second pipeline221 correspond to the data marked 3, 4, and 400 in the rotation chain in turn.

The fifth data, sixth data and seventh data of the fifth second pipeline221 correspond to the data marked 4, 5, and 401 in the rotation chain bit in turn.

The fifth data, sixth data and seventh data of the sixth second pipeline 221 correspond to the data marked 5, 6, and 402 in the rotation chain bit in turn.

The fifth data, sixth data and seventh data of the seventh second pipeline221 respectively correspond to the data marked 6, 7, and 403 in the rotation chain in turn.

The fifth, sixth, and seventh data of the eighth second pipeline 221 correspond to the data marked 7, 8, and 404 in the rotation chain in turn.

The fifth data, sixth data, and seventh data of the ninth second pipeline221 correspond to the data with the bit labels 8, 9, and 405 respectively.

Article 10 The fifth data, sixth data and seventh data of the second pipeline 221 respectively correspond to the data marked 9, 10, and 406 in the rotation chain.

The fifth data, the sixth data and the seventh data of the 11th second pipeline221 respectively correspond to the data marked 10, 11, and 407 in the rotation chain.

Article 12 The fifth data, sixth data and seventh data of the second pipeline221 respectively correspond to the data marked 11, 12, and 408 in the rotation chain.

Article 13 The fifth data, sixth data, and seventh data of the second pipeline221 correspond to the data marked 12, 13, and 409 in the rotation chain, respectively.

Article 14 The fifth data, sixth data and seventh data of the second pipeline 221 respectively correspond to the data marked 13, 14, and 410 in the rotation chain.

Article 15 The fifth data, sixth data and seventh data of the second pipeline221 correspond to the data marked 14, 15, and 411 in the rotation chain bit in turn.

Article 16 The fifth data, sixth data and seventh data of the second pipeline 221 respectively correspond to the data marked 15, 16, and 412 in the rotation chain.

The 16 data results obtained by the 16 second pipeline 221 are written into the output sub-circuit 23 through the interworking register 25 on the one hand, and the first buffer register and the second buffer register of the first memory 26 are written through the interworking register 25 on the one hand. . In a cycle, the 16 second pipelines 221 update the 16 data in the first buffer register and the second buffer register every beat.

The output subcircuit 23 includes 16 parallel output lines 231 , each output line 231 receiving the output of a second pipeline 221 in the state rotation subcircuit 22 .

A third right shifter in output line 231 right shifts the output of state rotation subcircuit 22 by 11 (ie, c=11) bits. The sixth XOR performs an XOR operation on the output of the third right shifter and the output of the state rotation subcircuit 22 . The first left shifter shifts the output of the sixth XOR left by 7 (ie, d=7) bits. The fourth AND gater ANDs the output of the first left shifter with 0x9d2c5680 (ie, the ninth set value=0x9d2c5680). The seventh XOR performs an XOR operation on the output of the sixth XOR and the output of the fourth AND gate. The second left shifter shifts the output of the seventh XOR left by 15 (ie, e=15) bits. The fifth AND gate performs an AND operation on the output of the second left shifter with 0xefc60000 (ie, the tenth set value=0xefc60000). The eighth XOR performs an XOR operation on the output of the fifth AND gate and the output of the seventh XOR. The fourth right shifter right shifts the output of the eighth XOR by 11 (ie, f=11) bits. The ninth XOR performs an XOR operation on the output of the fourth right shifter and the output of the eighth XOR, and outputs the XOR result as a second random number.

As shown in FIG. 13 , the structures of the data type conversion module 40 , the distribution conversion module 50 , the output control module 60 , and the interrupt management module in the random number generation device 100 may be the same as those in Example 1, and the relevant description in Example 1 can be referred to, It will not be repeated here.

Example three

The random number generating apparatus 100 in Example 3 includes the first generator 10 in Example 1 and the second generator 20 in Example 2.

As shown in FIGS. 14 a and 14 b , the random number generating apparatus 100 includes a first generator 10 , a second generator 20 , a first selector 30 , a data type conversion module 40 , a distribution conversion module 50 and an output control module 60 .

The structures of the first generator 10 , the data type conversion module 40 , the distribution conversion module 50 and the output control module 60 may be the same as those of the first generator 10 , the data type conversion module 40 , the distribution conversion module 50 and the output control module 60 in Example 1. The structure is the same and will not be repeated here.

Wherein, as shown in FIG. 14a , the second generator 20 may include a plurality of output lines 231 . As shown in FIG. 14b , the second generator 20 may include an output line 231 .

The structure of the second generator 20 may be the same as the structure of the second generator 20 in the second example, and reference may be made to the relevant description in the second example, which will not be repeated here.

As shown in FIG. 14 a , the first random number output by the first generator 10 and the second random number output by the second generator 20 are both transmitted to the first selector 30 . The first selector 30 is configured to select and output the first random number or the second random number according to the first parameter.

For example, the first parameter can be transmitted to the first flash memory through the system scheduler, CPU, GPU or NPU, and the first flash memory is transmitted to the first selector 30 .

The data type conversion module 40 is configured to perform data type conversion on the output of the first selector 30 .

That is, in the case of the first random number output by the first selector 30, the data type conversion module 40 is configured to perform data type conversion on the first random number. In the case of the second random number output by the first selector 30, the data type conversion module 40 is configured to perform data type conversion on the second random number.

The random number generating apparatus 100 provided in this example includes a first generator 10 and a second generator 20. The principle of the first generator 10 generating the first random number is different from the principle of the second generator 20 generating the second random number. Therefore, by arranging the first generator 10 and the second generator 20 in the random number generating apparatus 100, the random number can be generated by the first generator 10 or the random number can be generated by the second generator 20 according to the requirements, so as to adapt different application scenarios.

In some embodiments of the present application, any of the above random number generating apparatuses 100 may be integrated on the substrate of the chip.

Illustratively, the above random number generating apparatus 100 is arranged on the system on chip (SOC) side of the AI chip. The AI chip can be used in various AI inference and training networks that require large-scale random numbers. The random number seed, parameters, storage address, etc. received by the random number generating apparatus 100 are configured through software.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

A device for generating random numbers, comprising:

at least one generator, the at least one generator contains a generator for synchronously generating a plurality of random numbers according to the random number seed;

In the case where the at least one generator is multiple generators, the random number generating apparatus further includes a first selector; the first selector is configured to select and output one of the multiple generators according to the first parameter A generated random number.
The random number generation apparatus according to claim 1, wherein the at least one generator comprises a first generator, and the first generator comprises a plurality of parallel first pipelines; the plurality of The parallel first pipeline is used for synchronously generating the plurality of random numbers according to the random number seed.
The random number generation device according to claim 2, wherein the first pipeline comprises a plurality of cascaded operation subcircuits; the operation subcircuit comprises a plurality of parallel data deformation modules;

The data deformation module is configured to receive the first data, the second data, the third data, the first set value and the second set value, and convert the lower bit of the product of the first data and the first set value As the first output data; XOR the result of the second data and the third data, and, the high bit of the product of the first data and the first set value, XOR as the second Output Data;

The data deformation module is further configured to use the sum of the third data and the second set value as the third output data; or, except for the data deformation module in the last stage, the data in each stage The deformation module is further configured to use the sum of the third data and the second set value as the third output data;

The first output data, the second output data and the third output data of the data deformation module in the previous stage are respectively used as the second data and the third output data of the data deformation module in the latter stage. the first data and the third data;

Wherein, at least one bit of the random number seed is used as the third data of the first stage of the operation subcircuit; the first output data and the second output data of the last stage of the operation subcircuit are used as The random number generated by the first pipeline.
The random number generating apparatus according to any one of claims 1-3, wherein the at least one generator further comprises a second generator;

The second generator includes a seed initialization generation subcircuit, a state rotation subcircuit and an output subcircuit;

The seed initialization generating sub-circuit is used to initialize according to the random number seed to generate a rotation chain including a plurality of initial values;

The state rotation subcircuit includes a plurality of parallel second pipelines, and the plurality of parallel second pipelines are used to rotate the rotation chain;

The output subcircuit includes at least one output line, and the at least one output line is used for deforming the output of the state rotation subcircuit to generate the plurality of random numbers.
The random number generating device according to claim 4, wherein the seed initialization generating sub-circuit is configured to receive the fourth data, the third setting value, the fourth setting value and the fifth setting value, and convert the After the fourth data is shifted to the right by a bit and the result of the XOR of the fourth data, and, the third set value, the product obtained by multiplying; and again, after the fourth set value is added, And, the fifth set value is AND operation; the result of the AND operation is output as the initialization value;

Wherein, the fourth data is the random number seed or the initialization value.
The random number generation device according to claim 4, wherein the second pipeline comprises a parity selection module, an odd number generation module, an even number generation module and a second selector;

The parity selection module is configured to receive the fifth data, the sixth data, the sixth set value and the seventh set value, and the result of performing the AND operation on the fifth data and the sixth set value, and , after the sixth data modulo is taken and the result of the seventh set value and operation, carry out an OR operation and take the modulo, and output the result of the modulo to the second selector and the even number generation module;

The odd number generation module is configured to receive the fifth data and the eighth set value, and output the fifth data and the eighth set value to the second selector after XORing;

The even number generation module is used to receive the output of the seventh data and the parity selection module, and after the output of the parity selection module is right-shifted by b bits, and, the modulo result of the seventh data is XORed and then output to the second selector;

The second selector is configured to select and output the output of the odd number generation module or the even number generation module according to the output of the parity selection module, so as to rotate the rotation chain;

Wherein, the fifth data, the sixth data and the seventh data are different data in the rotating chain.
The random number generating device according to claim 4, wherein the output line is used to receive the output of the state rotator circuit, the ninth set value and the tenth set value, and the state rotator After the output of the circuit is shifted to the right by c bits, XOR is performed with the output of the state rotation sub-circuit; then the XOR result, the AND, the XOR result is left shifted by d bits and the result of the ninth set value AND operation, XOR is performed; then the XOR result and the XOR result are left shifted by e bits and the result of the tenth set value AND operation is XORed; then the XOR result, and, the XOR result is shifted to the right by f The bit result is XORed and output as a random number.
The random number generating device according to any one of claims 4-7, wherein the second generator further comprises a third selector, an interworking register and a first memory;

The third selector is configured to receive the rotation chain before the rotation output by the seed initialization generation subcircuit and the rotation chain after the rotation output by the state rotation subcircuit, under the control of the selection control terminal, transmitting the rotation chain before rotation or the rotation chain after rotation to the intercommunication register;

the intercommunication register for receiving the rotation chain output by the third selector, transmitting the rotation chain to the first memory, and retrieving the rotation chain from the first memory in batches The data in , are transmitted to the second pipeline as fifth data, sixth data and seventh data; also used to transmit the output of the state rotation sub-circuit to the output sub-circuit;

The first memory is used to receive and store the rotation chain output by the interworking register.
The random number generating device according to any one of claims 1-8, wherein the random number generating device further comprises: a data type conversion module, configured to perform data processing on the random number generated by the at least one generator Type conversion.
The random number generation device according to claim 9, wherein the data type conversion module comprises at least one data type converter; the data type converter is used to convert the random number generated by the at least one generator into Random numbers of preset data types;

In the case where the data type conversion module includes multiple data type converters, the data type conversion module further includes a fourth selector, and the fourth selector is configured to select, according to the second parameter, the data for the multiple data types. The result of one of the type converters is output;

The preset data types of the random numbers converted by the plurality of data type converters are different.
The random number generation device according to claim 9, wherein the random number generation device further comprises: a distribution conversion module, configured to perform distribution type conversion on the output of the data type conversion module.
The random number generation device according to claim 11, wherein the distribution conversion module includes at least one distribution generator; the distribution generator is configured to convert the random number output by the data type conversion module into a random number that obeys a preset distributed random numbers;

In the case where the distribution conversion module includes multiple distribution generators, the random number generation device further includes a fifth selector, and the fifth selector is configured to select the multiple distribution generators according to the third parameter. The result of one of the output is output;

Wherein, the random numbers converted by the multiple distribution generators obey different preset distribution types.
The random number generating apparatus according to claim 12, wherein the at least one distribution generator comprises a normal distributor, and the normal distributor adopts a box-muller algorithm to divide the The random numbers output by the data type conversion module are converted into random numbers that obey the normal distribution.
A method for generating random numbers, comprising:

The generator generates multiple random numbers synchronously according to the random number seed;

In the case where there are multiple generators to generate the multiple random numbers, the random number generation method further includes that the first selector selects and outputs the multiple generated by one of the multiple generators according to the first parameter. a random number.
The random number generation method according to claim 14, wherein the generator generates a plurality of random numbers synchronously according to the random number seed, comprising:

A plurality of parallel first pipelines (pipelines) in the first generator synchronously generate the plurality of random numbers according to the random number seed.
The random number generation method according to claim 14, wherein the generator generates a plurality of random numbers synchronously according to the random number seed, comprising:

The seed initialization generating subcircuit performs initialization according to the random number seed, and generates a rotation chain including a plurality of initial values;

a plurality of parallel second pipelines in the state rotation subcircuit to rotate the rotation chain;

A plurality of parallel output lines in the output subcircuit perform deformation processing on the output of the state rotation subcircuit to generate the plurality of random numbers synchronously.
The random number generation method according to any one of claims 14-16, wherein the random number generation method further comprises: a data type conversion module performs a data type conversion on the plurality of random numbers generated by the generator convert.
The random number generation method according to claim 17, wherein the random number generation method further comprises: the distribution conversion module performs distribution type conversion on the output of the data type conversion module.
A neural network system, characterized by comprising a second memory and the random number generating device according to any one of claims 1-13, wherein the second memory is used for storing random numbers generated by the random number generating device.
The neural network system according to claim 19, wherein the second memory is further configured to store the last index of the random number generated by the random number generating device.
A chip, characterized by comprising a substrate and the random number generating device according to any one of claims 1-13, wherein the random number generating device is arranged on the substrate.
A device for generating random numbers, comprising: a second generator;

The second generator includes a seed initialization generation subcircuit, a state rotation subcircuit and an output subcircuit;

The seed initialization generating subcircuit is used to initialize according to the random number seed, and generate a rotation chain including a plurality of initial values;

The state rotation subcircuit includes a plurality of parallel second pipelines, and the plurality of parallel second pipelines are used to rotate the rotation chain;

The output subcircuit includes an output line, and the output line is used for deforming the output of the state rotation subcircuit to generate a random number.