CN112328206A - Parallel random number generation method for vectorization component - Google Patents

Parallel random number generation method for vectorization component Download PDF

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CN112328206A
CN112328206A CN202011212670.1A CN202011212670A CN112328206A CN 112328206 A CN112328206 A CN 112328206A CN 202011212670 A CN202011212670 A CN 202011212670A CN 112328206 A CN112328206 A CN 112328206A
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random number
seed
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random numbers
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刘锋
侯晓东
朱肖雄
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Guangzhou Keze Yuntian Intelligent Technology Co ltd
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Abstract

The invention discloses a vectorization component-oriented parallel random number generation method, which comprises the following steps: step S10, generating a jump formula according to a linear congruence equation; step S20, determining LCG method parameters and initial values, vectorization width and the total number of pseudo-random numbers to be generated; step S30, distributing array space according to vectorization width; step S40, generating pseudo-random number subsequence seeds according to a jump formula iteration; step S50, generating random numbers according to LCG method; in step S60, it is determined whether all random numbers have been generated, and if not, the process returns to step S50, otherwise, the process ends. The invention can generate a plurality of pseudo random numbers simultaneously by executing the LCG method once, generates all random numbers by utilizing the vectorization part and the SIMD instruction iteration after inputting the initial value and the LCG method parameters, can generate a plurality of random numbers in parallel in each execution, and greatly improves the generation speed.

Description

Parallel random number generation method for vectorization component
Technical Field
The invention relates to the technical field of data processing, in particular to a parallel random number generation method for a vectorization component.
Background
With the increasing of the manufacturing process of microprocessors, it has become an important trend to integrate vectorization units supporting double-precision floating-point operations in commercial microprocessor chips to accelerate the floating-point operation capability. At present, vectorization components such as an Intel's MMX/SSE/AVX and a VPU in an MIC coprocessor are integrated on most commercial microprocessors, and the vectorization components operate vectors by using SIMD instructions, and one vector is composed of a plurality of floating point data, so that a single instruction operates a plurality of floating point data at the same time, and the calculation process of the microprocessor is accelerated.
At present, the pseudo-random number generator has important application in various scientific calculation programs, for example, in various Monte Carlo simulation programs, the rapid generation of high-quality pseudo-random numbers is the key for influencing the operation of the programs, and the program is vectorized by utilizing a vectorization component, so that the pseudo-random number generation process can be effectively accelerated. However, pseudo-random numbers are generally generated by using a mathematical method, and a digital sequence is sequentially generated from an initial value according to an iterative equation, and the digital sequence is called a pseudo-random number sequence, and in a patent with the patent number "CN 201110347722.0", which is named as a method and a device for generating pseudo-random number seeds and pseudo-random numbers, a pseudo-random number seed generation method and a pseudo-random number generation method are disclosed, which can generate pseudo-random numbers, but the method is generated serially, i.e., only one pseudo-random number can be generated at a time, the generation speed is slow, and the method may become a performance bottleneck of some programs sensitive to the pseudo-random number generation speed.
In summary, the current pseudo random number generation method is serial generation, only one pseudo random number can be generated in each execution, parallelism and execution speed of a main program are affected, and a vectorization component in a microprocessor provides vectorization support for an algorithm to generate a plurality of pseudo random numbers at one time from hardware; therefore, it is necessary to provide a parallel random number generation method for vectorization units, so as to generate multiple pseudo random numbers at a time.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a parallel random number generation method for a vectorization component.
The technical scheme of the invention is as follows:
a vectorized component-oriented parallel random number generation method, comprising the steps of:
step S10, generating a jump formula according to a linear congruence equation;
step S20, determining LCG method parameters and initial values, vectorization width and the total number of pseudo-random numbers to be generated;
step S30, distributing array space according to vectorization width;
step S40, generating pseudo-random number subsequence seeds according to a jump formula iteration;
step S50, generating random numbers according to LCG method;
and step S60, judging whether all random numbers are generated, wherein if not, jumping back to the step S50, otherwise, ending.
Further, the linear congruence equation in the step S10 is xi+1＝(axi) modM in which xiIs an initial value, a is a multiplier, and M is a modulus, then the step S10 is realized by letting x be a multiplieri+2＝(axi+1) mod M, let xi+3＝(axi+2) mod M, and let xi+3＝a(a(aximodM) and derives x from the formula x (ymodm) modM ═ xyymodmi+3＝a3ximod M, so that by fitting the formula xi+3＝a3xim iterations of modM derive the hopping formula as xi+m＝amximodM。
Further, the LCG method parameters in step S20 are a multiplier a and a modulus M, and an initial value x of the LCG method is setiIs x0The vectorization width is W, the total number of generated pseudo random numbers is N, the precision of the pseudo random numbers is J bits, and the number of the pseudo random numbers actually generated by each vector unit is W
Figure BDA0002759334040000031
Further, the array space in step S30 includes a high precision array seed h and a low precision array seed l allocated with the vectorization width as the length.
Further, the step S40 is according to the jump formula xi+m＝amxiThe modM jumps m steps in sequence to generate W pseudo-random number subsequence seeds which are respectively stored in a high-precision array seed H and a low-precision array seed L, wherein m is the number of steps jumping forwards
Figure BDA0002759334040000032
a is a known multiplier, xiIs a known initial value x0M is a known modulus and all data are high
Figure BDA0002759334040000033
Bit and low
Figure BDA0002759334040000034
Bit sorted storage, assigning a high precision data set seed of length W for storing a high of pseudo-random number subsequence seeds
Figure BDA0002759334040000035
Bit data, allocating a high precision data set seed L of length W for storing the pseudo random number subsequence seed
Figure BDA0002759334040000036
Bit data, in parallel with operator
Figure BDA0002759334040000037
Is taken as high as one number
Figure BDA0002759334040000038
Bit, operator
Figure BDA0002759334040000039
Is taken as one number low
Figure BDA00027593340400000310
A bit.
Further, the step S40 is realized by making i-1, t-1,
Figure BDA00027593340400000311
low of stored multiplier a
Figure BDA00027593340400000312
The bit data is a bit data,
Figure BDA00027593340400000313
store multiplier a high
Figure BDA00027593340400000314
The bit data is a bit data,
Figure BDA00027593340400000315
storing a high of a pseudorandom number subsequence seed
Figure BDA00027593340400000316
The bit data is a bit data,
Figure BDA00027593340400000317
storing pseudorandom number subsequence seed
Figure BDA00027593340400000318
Bit data, and let t be t +1, the first pseudorandom number subsequence seed is x0The first pseudorandom number subsequence seed being stored in
Figure BDA00027593340400000319
Or
Figure BDA00027593340400000320
Reissue to order
Figure BDA00027593340400000321
Figure BDA00027593340400000322
Let i equal i +1, if i is less than m, jump back
Figure BDA00027593340400000323
To complete solution amIf i is greater than or equal to m, let tmp1 be al×seedL[t-1]Obtaining the previous seed [ t-1 ] of pseudo-random number subsequence](ii) a Reissue to order
Figure BDA0002759334040000041
Figure BDA0002759334040000042
Let t be t +1, if t is smaller than W, jump back to tmp1 be al×seedL[t-1]Otherwise, all pseudorandom number subsequence seeds have been generated and the next action is performed.
Further, the step S50 generates random numbers by using an LCG method including a linear congruence equation x according to the pseudo random number subsequence seed generated by the step S40i+1＝(axi) modM, where the operator ═ x ++, and,
Figure BDA0002759334040000043
All corresponding SIMD instructions are adopted, the operated data are required to be packed into a vector register, mmvecH, mmvecL, mmvecK, mmvecA, mmvecB and mmvecR are set as temporary variables of the vector register, the variables are different from common variables, a vector is stored inside, the assignment of the variables is actually equivalent to the process of packing the data into the vector register, and an array rand [ W ] with the length of W is distributed]The generated random number is stored.
Further, the step S50 is implemented by setting n to 1, and setting mmvecH to seed h to implement packing the entire seed h array into the vector register; let mmvecL be seedL to implement packing the entire seedL array into the vector register; packing a multiplier a in the LCG parameter into a vector register by letting mmvecK be a; order to
Figure BDA0002759334040000044
Vector multiplication for SIMD instructions; order to
Figure BDA0002759334040000045
Order to
Figure BDA0002759334040000046
Reissue to order
Figure BDA0002759334040000047
Figure BDA0002759334040000048
An update value for calculating a next random number; let rand mmvecR to effect writing the value in the vector register back to array rand [ w ═ w]Middle, then the array rand [ w ]]The data stored in (1) is the W random numbers calculated this time.
Further, the determination condition in step S60 is to make n equal to n +1 and then compare n with n
Figure BDA0002759334040000049
The size of (d); if it is not
Figure BDA00027593340400000410
If it is determined that all the random numbers are not generated, the process returns to step S50 to continue generating the remaining random numbers, otherwise, the process ends.
By adopting the scheme, the invention has the following beneficial effects:
the invention can generate a plurality of pseudo random numbers simultaneously by executing the LCG method once, generates all random numbers by utilizing the vectorization part and the SIMD instruction iteration after inputting the initial value and the LCG method parameters, replaces serial generation, can generate a plurality of random numbers in parallel in each execution and greatly improves the generation speed.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a parallel random number generation method for a vectorization component according to the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The invention is described in detail below with reference to the figures and the specific embodiments.
Referring to fig. 1, the present invention provides a vectorization component-oriented parallel random number generation method, including the following steps:
step S10, generating a jump formula according to a linear congruence equation;
step S20, determining LCG method parameters and initial values, vectorization width and the total number of pseudo-random numbers to be generated;
step S30, distributing array space according to vectorization width;
step S40, generating pseudo-random number subsequence seeds according to a jump formula iteration;
step S50, generating random numbers according to LCG method;
and step S60, judging whether all random numbers are generated, wherein if not, jumping back to the step S50, otherwise, ending.
In this embodiment, the linear congruence equation in the step S10 is xi+1＝(axi) modM in which xiIs an initial value, a is a multiplier, and M is a modulus, then the implementation manner of step S10 is to make xi+2＝(axi+1) mod M, let xi+3＝(axi+2) mod M, and let xi+3＝a(a(aximodM) and derives x from the formula x (ymodm) modM ═ xyymodmi+3＝a3ximod M, so that by fitting the formula xi+3＝a3xim iterations of modM derive the hopping formula as xi+m＝amximodM。
In this embodiment, the LCG method parameters in step S20 are a multiplier a and a modulus M, and an initial value x of the LCG method is setiIs x0Vectorization width W, the total number of pseudo-random numbers generated is N, pseudoThe precision of the random number is J bits, the number of pseudo random numbers actually generated by each vector unit is
Figure BDA0002759334040000061
I.e. the range of pseudo-random number subsequences generated by the first vector unit is
Figure BDA0002759334040000062
The second vector unit generates a range of pseudo-random number subsequences of
Figure BDA0002759334040000063
The third and subsequent vector units generate a range of pseudo-random number subsequences and so on.
In the present embodiment, the array space in step S30 includes a high precision array seed h and a low precision array seed l allocated with the vectorization width as the length.
In the present embodiment, the step S40 is performed according to the jump formula xi+m＝amxiThe modM jumps m steps in sequence to generate W pseudo-random number subsequence seeds which are respectively stored in a high-precision array seed H and a low-precision array seed L, wherein m is the number of steps jumping forwards
Figure BDA0002759334040000064
a is a known multiplier, xiIs a known initial value x0M is a known modulus; in order to improve the calculation precision, all data are high in the calculation process
Figure BDA0002759334040000065
Bit and low
Figure BDA0002759334040000066
Bit sorted storage, assigning a high precision tuple seed H of length W (i.e., vectorization width) for storing a high of pseudo-random number subsequence seeds
Figure BDA0002759334040000071
Bit data, a high-precision data set seed L with the length of W is allocated for storing the fakeLow of random number subsequence seed
Figure BDA0002759334040000072
Bit data, in parallel with operator
Figure BDA0002759334040000073
Is taken as high as one number
Figure BDA0002759334040000074
Bit, operator
Figure BDA0002759334040000075
Is taken as one number low
Figure BDA0002759334040000076
A bit;
specifically, the step S40 is realized by setting i equal to 1, t equal to 1,
Figure BDA0002759334040000077
low of stored multiplier a
Figure BDA0002759334040000078
The bit data is a bit data,
Figure BDA0002759334040000079
store multiplier a high
Figure BDA00027593340400000710
The bit data is a bit data,
Figure BDA00027593340400000711
storing a high of a pseudorandom number subsequence seed
Figure BDA00027593340400000712
The bit data is a bit data,
Figure BDA00027593340400000713
storing pseudorandom number subsequence seed
Figure BDA00027593340400000714
Bit data, and let t be t +1, the first pseudorandom number subsequence seed is x0The first pseudorandom number subsequence seed being stored in
Figure BDA00027593340400000715
Or
Figure BDA00027593340400000716
Reissue to order
Figure BDA00027593340400000717
Figure BDA00027593340400000718
Let i equal i +1, if i is less than m, jump back
Figure BDA00027593340400000719
To complete solution amIf i is greater than or equal to m, let tmp1 be al×seedL[t-1]Obtaining the previous seed [ t-1 ] of pseudo-random number subsequence](ii) a Reissue to order
Figure BDA00027593340400000720
Figure BDA00027593340400000721
Let t be t +1, if t is smaller than W, jump back to tmp1 be al×seedL[t-1]Otherwise, all pseudorandom number subsequence seeds have been generated and the next action is performed.
In this embodiment, the step S50 generates random numbers by using an LCG method including a linear congruence equation x according to the pseudo random number subsequence seed generated in the step S40i+1＝(axi) modM, where the operator ═ x ++, and,
Figure BDA00027593340400000722
Corresponding SIMD instructions are all adopted, the operated data are packed into a vector register, mmvecH, mmvecL, mmvecK, mmvecA, mmvecB and mmvecR are set as temporary variables of the vector register,the variable is different from the common variable, the internal storage is a vector, the assignment of the variable is actually equivalent to the process of packing data into a vector register, and an array rand [ W ] with the length of W is distributed]Storing the generated random number;
specifically, the step S50 is implemented by setting n to 1, and setting mmvecH to seed h to implement packing the entire seed h array into the vector register; let mmvecL be seedL to implement packing the entire seedL array into the vector register; packing a multiplier a in the LCG parameter into a vector register by letting mmvecK be a; order to
Figure BDA0002759334040000081
Vector multiplication for SIMD instructions; order to
Figure BDA0002759334040000082
Order to
Figure BDA0002759334040000083
Reissue to order
Figure BDA0002759334040000084
Figure BDA0002759334040000085
An update value for calculating a next random number; let rand mmvecR to effect writing the value in the vector register back to array rand [ w ═ w]Middle, then the array rand [ w ]]The data stored in (1) is the W random numbers calculated this time.
In this embodiment, the determination condition of step S60 is to make n equal to n +1 and then compare n with n
Figure BDA0002759334040000086
The size of (d); if it is not
Figure BDA0002759334040000087
If it is determined that all the random numbers are not generated, the process returns to step S50 to continue generating the remaining random numbers, otherwise, the process ends.
Compared with the prior art, the invention has the following beneficial effects:
the invention can generate a plurality of pseudo random numbers simultaneously by executing the LCG method once, generates all random numbers by utilizing the vectorization part and the SIMD instruction iteration after inputting the initial value and the LCG method parameters, replaces serial generation, can generate a plurality of random numbers in parallel in each execution and greatly improves the generation speed.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A vectorized component-oriented parallel random number generation method, comprising the steps of:
step S10, generating a jump formula according to a linear congruence equation;
step S20, determining LCG method parameters and initial values, vectorization width and the total number of pseudo-random numbers to be generated;
step S30, distributing array space according to vectorization width;
step S40, generating pseudo-random number subsequence seeds according to a jump formula iteration;
step S50, generating random numbers according to LCG method;
and step S60, judging whether all random numbers are generated, wherein if not, jumping back to the step S50, otherwise, ending.
2. The vectorized component oriented parallel random number generation method according to claim 1, wherein the linear congruence equation in step S10 is xi+1＝(axi) mod M, where xiIs an initial value, a is a multiplier, and M is a modulus, then the step S10 is realized by letting x be a multiplieri+2＝(axi+1) mod M, let xi+3＝(axi+2) mod M, and let xi+3＝a(a(aximod M) mod M, and derives x by the formula x (y mod M) mod M-xy mod Mi+3＝a3ximod M, so that by matching the formula xi+3＝a3xiM iterations of mod M to derive the hopping formula as xi+m＝amximod M。
3. The parallel random number generation method for vectorized components according to claim 2, wherein the LCG parameters in step S20 are a multiplier a and a modulus M, and an LCG initial value x is setiIs x0The vectorization width is W, the total number of generated pseudo random numbers is N, the precision of the pseudo random numbers is J bits, and the number of the pseudo random numbers actually generated by each vector unit is W
Figure FDA0002759334030000011
4. The parallel random number generation method for the vectorization unit according to claim 3, wherein the array space in step S30 includes a high precision array seed h and a low precision array seed l allocated with the vectorization width as a length.
5. The vectorized component oriented parallel random number generation method according to claim 4, wherein said step S40 is according to the jump formula xi+m＝amxiThe mod M jumps M steps in sequence to generate W pseudo-random number subsequence seeds which are respectively stored in a high-precision array seed H and a low-precision array seed L, wherein M is the number of steps jumping forwards
Figure FDA0002759334030000021
a is a known multiplier, xiIs a known initial value x0M is a known modulus and all data are high
Figure FDA0002759334030000022
Bit and low
Figure FDA0002759334030000023
Bit sorted storage, assigning a high precision data set seed of length W for storing a high of pseudo-random number subsequence seeds
Figure FDA0002759334030000024
Bit data, allocating a high precision data set seed L of length W for storing the pseudo random number subsequence seed
Figure FDA0002759334030000025
Bit data, in parallel with operator
Figure FDA0002759334030000026
Is taken as high as one number
Figure FDA0002759334030000027
Bit, operator
Figure FDA0002759334030000028
Is taken as one number low
Figure FDA0002759334030000029
A bit.
6. The vectorized component oriented parallel random number generation method according to claim 5, wherein said step S40 is implemented by letting i-1, t-1,
Figure FDA00027593340300000210
low of stored multiplier a
Figure FDA00027593340300000211
The bit data is a bit data,
Figure FDA00027593340300000212
store multiplier a high
Figure FDA00027593340300000213
The bit data is a bit data,
Figure FDA00027593340300000214
storing a high of a pseudorandom number subsequence seed
Figure FDA00027593340300000215
The bit data is a bit data,
Figure FDA00027593340300000216
storing pseudorandom number subsequence seed
Figure FDA00027593340300000217
Bit data, and let t be t +1, the first pseudorandom number subsequence seed is x0The first pseudorandom number subsequence seed being stored in
Figure FDA00027593340300000218
Or
Figure FDA00027593340300000219
Reissue to order
Figure FDA00027593340300000220
Figure FDA00027593340300000221
Let i equal i +1, if i is less than m, jump back
Figure FDA00027593340300000222
To complete solution amIf i is greater than or equal to m, let tmp1 be al×seedL[t-1]Obtaining the previous seed [ t-1 ] of pseudo-random number subsequence](ii) a Reissue to order
Figure FDA0002759334030000031
Figure FDA0002759334030000032
Let t be t +1, if t is smaller than W, jump back to tmp1 be al×seedL[t-1]Otherwise, all pseudorandom number subsequence seeds have been generated and the next action is performed.
7. The parallel random number generation method for the vectorized component of claim 6, wherein said step S50 generates the random number according to the sub-sequence seed of the pseudo random number generated in said step S40 by using the LCG method including the linear congruence equation xi+1＝(axi) mod M, where the operator ═ x ++, and,
Figure FDA0002759334030000033
Figure FDA0002759334030000034
All corresponding SIMD instructions are adopted, the operated data are required to be packed into a vector register, mmvecH, mmvecL, mmvecK, mmvecA, mmvecB and mmvecR are set as temporary variables of the vector register, the variables are different from common variables, a vector is stored inside, the assignment of the variables is actually equivalent to the process of packing the data into the vector register, and an array rand [ W ] with the length of W is distributed]The generated random number is stored.
8. The parallel random number generation method for the vectorization unit according to claim 7, wherein said step S50 is implemented by making n-1, and making mmvecH-seed to implement packing the whole array of seed into the vector register; let mmvecL be seedL to implement packing the entire seedL array into the vector register; packing a multiplier a in the LCG parameter into a vector register by letting mmvecK be a; order to
Figure FDA0002759334030000035
Vector multiplication for SIMD instructions; order to
Figure FDA0002759334030000036
Order to
Figure FDA0002759334030000037
Reissue to order
Figure FDA0002759334030000038
Figure FDA0002759334030000039
An update value for calculating a next random number; let rand mmvecR to effect writing the value in the vector register back to array rand [ w ═ w]Middle, then the array rand [ w ]]The data stored in (1) is the W random numbers calculated this time.
9. The vectorization-unit-oriented parallel random number generation method according to claim 8, wherein the determination condition of step S60 is to make n-n +1 compare n with n
Figure FDA0002759334030000041
The size of (d); if it is not
Figure FDA0002759334030000042
If it is determined that all the random numbers are not generated, the process returns to step S50 to continue generating the remaining random numbers, otherwise, the process ends.
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