WO2022188358A1 - 半导体结构及半导体结构的制作方法 - Google Patents

半导体结构及半导体结构的制作方法 Download PDF

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Publication number
WO2022188358A1
WO2022188358A1 PCT/CN2021/112594 CN2021112594W WO2022188358A1 WO 2022188358 A1 WO2022188358 A1 WO 2022188358A1 CN 2021112594 W CN2021112594 W CN 2021112594W WO 2022188358 A1 WO2022188358 A1 WO 2022188358A1
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connection layer
layer
semiconductor structure
connection
thermal expansion
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PCT/CN2021/112594
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English (en)
French (fr)
Inventor
张志伟
刘杰
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长鑫存储技术有限公司
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Priority to KR1020227021434A priority Critical patent/KR20220127812A/ko
Priority to JP2022538973A priority patent/JP7387003B2/ja
Priority to EP21865335.0A priority patent/EP4086945A4/en
Priority to US17/648,722 priority patent/US20220293493A1/en
Publication of WO2022188358A1 publication Critical patent/WO2022188358A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for fabricating the semiconductor structure.
  • the metal conductive material filled in the connecting portion will affect the surrounding lattice of the connecting portion during the thermal expansion process, thereby affecting the performance of the semiconductor structure.
  • the present disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure to improve the performance of the semiconductor structure.
  • a semiconductor structure comprising:
  • connection part is located in the substrate, the connection part includes a first connection layer, a second connection layer and a third connection layer, the second connection layer is located on the first connection layer, and the third connection layer is located on the second connection layer;
  • first connection layer, the second connection layer and the third connection layer comprise different conductive materials, and the thermal expansion coefficients of the second connection layer and the third connection layer are all smaller than the thermal expansion coefficient of the first connection layer.
  • a semiconductor structure comprising:
  • connection part is located in the substrate, the connection part includes a first connection layer, a second connection layer and a third connection layer, the second connection layer is located on the first connection layer, and the third connection layer is located on the second connection layer;
  • the second connection layer and the third connection layer both include graphene, and the thermal expansion coefficients of the second connection layer and the third connection layer are both smaller than the thermal expansion coefficient of the first connection layer.
  • a method for fabricating a semiconductor structure comprising:
  • a connecting portion is formed on the base, the connecting portion includes a first connecting layer, a second connecting layer and a third connecting layer, the second connecting layer is formed on the first connecting layer, and the third connecting layer is formed on the second connecting layer;
  • first connection layer, the second connection layer and the third connection layer comprise different conductive materials, and the thermal expansion coefficients of the second connection layer and the third connection layer are all smaller than the thermal expansion coefficient of the first connection layer.
  • the semiconductor structure of the present disclosure includes a substrate and a communication part, the communication part includes a first connection layer, a second connection layer, and a third connection layer formed of different conductive materials, by making the thermal expansion coefficients of the second connection layer and the third connection layer Both are smaller than the thermal expansion coefficient of the first connection layer, that is, the thermal expansion of the second connection layer and the third connection layer changes less, thereby reducing the influence on the peripheral lattice of the connection part, thereby improving the performance of the semiconductor structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to a first exemplary embodiment
  • FIG. 2 is a schematic structural diagram of a connecting portion of a semiconductor structure according to the first exemplary embodiment
  • FIG. 3 is a schematic structural diagram of a semiconductor structure according to a second exemplary embodiment
  • FIG. 4 is a schematic structural diagram of a connecting portion of a semiconductor structure according to a second exemplary embodiment
  • FIG. 5 is a schematic structural diagram of a semiconductor structure according to a third exemplary embodiment
  • FIG. 6 is a schematic flowchart of a method for fabricating a semiconductor structure according to an exemplary embodiment
  • FIG. 7 is a schematic structural diagram of forming an opening according to a method for fabricating a semiconductor structure according to the first exemplary embodiment
  • FIG. 8 is a schematic structural diagram of forming a second insulating layer hole according to a method for fabricating a semiconductor structure according to the first exemplary embodiment
  • FIG. 9 is a schematic structural diagram of forming a third insulating layer hole according to a method for fabricating a semiconductor structure according to the first exemplary embodiment
  • FIG. 10 is a schematic structural diagram of forming a first initial connection layer according to a method for fabricating a semiconductor structure shown in the first exemplary embodiment
  • FIG. 11 is a schematic structural diagram of forming a second initial connection layer according to a method for fabricating a semiconductor structure shown in the first exemplary embodiment
  • FIG. 12 is a schematic structural diagram of forming a second connection layer according to a method for fabricating a semiconductor structure shown in the first exemplary embodiment
  • FIG. 13 is a schematic structural diagram of forming a third initial connection layer according to a method for fabricating a semiconductor structure shown in the first exemplary embodiment
  • FIG. 14 is a schematic structural diagram of forming a third connection layer according to a method for fabricating a semiconductor structure shown in the first exemplary embodiment
  • FIG. 15 is a schematic structural diagram of forming a first initial connection layer according to a method for fabricating a semiconductor structure according to a second exemplary embodiment
  • 16 is a schematic structural diagram of forming a second initial connection layer according to a method for fabricating a semiconductor structure according to a second exemplary embodiment
  • FIG. 17 is a schematic structural diagram of forming a second connection layer according to a method for fabricating a semiconductor structure according to a second exemplary embodiment
  • FIG. 18 is a schematic structural diagram of forming a third initial connection layer according to a method for fabricating a semiconductor structure according to a second exemplary embodiment
  • FIG. 19 is a schematic structural diagram of forming a third connection layer according to a method for fabricating a semiconductor structure according to the second exemplary embodiment.
  • An embodiment of the present disclosure provides a semiconductor structure. Please refer to FIG. 1 to FIG. 5 .
  • the semiconductor structure includes: a substrate 10 ;
  • the second connection layer 212 and the third connection layer 213, the second connection layer 212 is located on the first connection layer 211, and the third connection layer 213 is located on the second connection layer 212; wherein, the first connection layer 211, the second connection layer 212 and the third connection layer 213 include different conductive materials, and the thermal expansion coefficients of the second connection layer 212 and the third connection layer 213 are both smaller than the thermal expansion coefficient of the first connection layer 211 .
  • the semiconductor structure of an embodiment of the present disclosure includes a substrate 10 and a connecting portion 21, and the connecting portion 21 includes a first connecting layer 211, a second connecting layer 212 and a third connecting layer 213 formed of different conductive materials.
  • the thermal expansion coefficients of 212 and the third connection layer 213 are both smaller than the thermal expansion coefficient of the first connection layer 211, that is, the second connection layer 212 and the third connection layer 213 have smaller thermal expansion changes, thereby reducing the impact on the peripheral lattice of the connecting portion 21. to improve the performance of semiconductor structures.
  • the thermal expansion coefficients of the second connection layer 212 and the third connection layer 213 are both smaller than the thermal expansion coefficient of the first connection layer 211 , a material with a low thermal expansion coefficient is used as part of the conductive material of the connecting portion 21 to reduce the number of active components
  • the area is affected by the thermal expansion of the metal, which can also reduce the electrical changes of the surrounding lattice MOS elements and reduce the size of the chip design.
  • the second connection layer 212 and the third connection layer 213 with smaller thermal expansion coefficients are less deformed by heat, so there is no problem of pressing the peripheral lattice of the communication part 21 with a large pressure, thereby avoiding damage to other components in the substrate 10 . Impact.
  • connection part 21 is a part of the conductive part 20
  • the conductive part 20 further includes a first conductive layer 22
  • the first conductive layer 22 is located above the connection part 21
  • the third connection layer 213 and the first conductive layer 22 Since the second connection layer 212 and the third connection layer 213 are close to the first conductive layer 22, and the thermal expansion coefficients of the second connection layer 212 and the third connection layer 213 are small, the first conductive layer will not be excessively squeezed. 22 case.
  • the communication portion 21 is a TSV.
  • the thermal expansion coefficient of the second connection layer 212 is smaller than the thermal expansion coefficient of the third connection layer 213 , that is, the conductive material with the smallest thermal expansion coefficient in the connecting portion 21 is located in the middle position, and the position corresponding to the substrate 10 is generally provided with There are a large number of components, so the conductive material with the smallest thermal expansion coefficient is least affected by thermal expansion and basically does not squeeze the components.
  • the second connection layer 212 or the third connection layer 213 includes graphene
  • the first connection layer 211 includes copper.
  • the thermal expansion coefficient of copper is relatively large, but since it is in the lowermost layer, it will not affect the components in the substrate 10, while the second connection layer 212 or the third connection layer 213 is closer to the components in the substrate 10, while the graphene
  • the coefficient of thermal expansion is negative, so graphene can counteract the thermal expansion of copper, which can avoid squeezing problems.
  • the first connection layer 211 is formed of copper
  • the second connection layer 212 is formed of graphene
  • the third connection layer 213 is formed of tungsten.
  • the second connection layer 212 includes graphene
  • the graphene since the graphene is sandwiched between the first connection layer 211 and the third connection layer 213, at this time, since the graphene has a certain heat storage function, it can The heat of the conductive material with a relatively large thermal expansion coefficient is absorbed, that is, the heat of the first connection layer 211 and the third connection layer 213 is absorbed, so as to reduce the expansion of other conductive materials when heated.
  • the heat generated by the first connection layer 211 and the second connection layer 212 can be transferred from the graphene to the first conductive layer 22 in time, and through the structure connected with the first conductive layer 22 Pass it out, so as to achieve the effect of rapid heat dissipation.
  • the second connection layer 212 is located within the first connection layer 211 , that is, the second connection layer 212 is surrounded by the first connection layer 211 in the circumferential direction and has high thermal expansion.
  • the coefficient of the first connection layer 211 can play the role of protecting the second connection layer 212, but since the thermal expansion coefficient of the second connection layer 212 is relatively small, the thermal expansion will not generate a large extrusion force.
  • the second connection layer 212 is located in the first connection layer 211 , and the bottom end of the third connection layer 213 is aligned with the top end of the second connection layer 212 and the first connection layer 211 .
  • the second connection layer 212 is located in the first connection layer 211
  • the third connection layer 213 is located in the first connection layer 211, that is, the circumferential directions of the second connection layer 212 and the third connection layer 213 are both Surrounded by the first connection layer 211 , as shown in FIG. 1 and FIG. 2 .
  • the projections of the second connection layer 212 and the third connection layer 213 in the direction perpendicular to the substrate 10 are coincident, that is, the cross-sectional area of the second connection layer 212 is the same as that of the third connection layer 213 .
  • the cross-sectional areas of the three connection layers 213 are equal.
  • the top of the third connection layer 213 is flush with the top of the first connection layer 211 .
  • the first connection layer 211 is formed with a groove, and the second connection layer 212 and the third connection layer 213 are located there. In the groove, the top of the first connection layer 211 and the top of the third connection layer 213 are connected to the first conductive layer 22 , as shown in FIG. 1 and FIG. 2 .
  • the first connection layer 211 , the second connection layer 212 and the third connection layer 213 include different conductive materials
  • the thermal expansion coefficient of the second connection layer 212 is smaller than that of the third connection layer 213
  • the third connection layer The thermal expansion coefficient of the layer 213 is smaller than that of the first connection layer 211, which is formed of copper
  • the second connection layer 212 is formed of graphene
  • the third connection layer 213 is formed of tungsten.
  • the projections of the first connection layer 211 , the second connection layer 212 and the third connection layer 213 in the direction perpendicular to the substrate 10 are coincident, that is, the first connection layer 211 , the second connection layer 212 and the third connection layer 213 are stacked in sequence along the height direction of the substrate 10 , and the cross-sectional areas of the first connection layer 211 , the second connection layer 212 and the third connection layer 213 are all equal.
  • the third connection layer 213 is directly connected to the first conductive layer 22 .
  • the first connection layer 211 , the second connection layer 212 and the third connection layer 213 include different conductive materials
  • the thermal expansion coefficient of the second connection layer 212 is smaller than that of the third connection layer 213
  • the third connection layer The thermal expansion coefficient of the layer 213 is smaller than that of the first connection layer 211, which is formed of copper
  • the second connection layer 212 is formed of graphene
  • the third connection layer 213 is formed of tungsten.
  • the second connection layer 212 is located in the first connection layer 211 , and the projections of the first connection layer 211 and the third connection layer 213 in the direction perpendicular to the substrate 10 coincide The bottom end of the three connection layers 213 is connected to the second connection layer 212 and the top end of the first connection layer 211 .
  • the base 10 includes: a silicon substrate 11 , the bottom end of the second connection layer 212 is lower than the upper surface of the silicon substrate 11 ; the insulating layer 12 , an insulating layer The layer 12 covers the upper surface of the silicon substrate 11 and the outer surface of the connecting portion 21 , and the first conductive layer 22 is located in the insulating layer 12 .
  • the base 10 includes a silicon substrate 11 and an insulating layer 12 , a part of the communication part 21 is located in the silicon substrate 11 , and the bottom end of the second connection layer 212 is lower than the upper surface of the silicon substrate 11 , and due to the second connection layer 212
  • the thermal expansion coefficient of the connection layer 212 is smaller than the thermal expansion coefficient of the first connection layer 211 , so the second connection layer 212 will not be over-expanded by heat, thus avoiding the influence on the part of the silicon substrate 11 close to the upper surface thereof.
  • the functional layer 111 is formed in the silicon substrate 11 , and the bottom end of the second connection layer 212 is lower than the lower surface of the functional layer 111 , that is, the overall height of the second connection layer 212 and the third connection layer 213 and not less than the height of the functional layer 111 in the silicon substrate 11 , so as to avoid thermal expansion and extrusion of the functional layer 111 .
  • the height of the second connection layer 212 may be greater than that of the functional layer 111 .
  • the functional layer 111 can have a variety of components, and the types of components are not limited here, and can be selected according to actual needs.
  • the functional layer 111 is extruded, so that the functional layer 111 can be protected.
  • the top of the second connection layer 212 is higher than the upper surface of the silicon substrate 11 , that is, the height of the second connection layer 212 may be higher than that of the functional layer 111 , so that the silicon substrate 11 is close to the insulating layer 12
  • the part of 111 plays a protective role to avoid squeezing the functional layer 111 .
  • first connection layer 211, the second connection layer 212, and the third connection layer 213 may be cylindrical structures.
  • the diameter of the second connection layer 212 may be 200 nm ⁇ 10 ⁇ m, and the depth may be 1 ⁇ m ⁇ 20 ⁇ m.
  • the depth of the second connection layer 212 entering the silicon substrate 11 is greater than or equal to 1 um.
  • the silicon substrate 11 may be formed of a silicon-containing material.
  • the silicon substrate 11 may be formed of any suitable material including, for example, at least one of silicon, single crystal silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, silicon carbide, and sapphire.
  • the insulating layer 12 may include silicon dioxide (SiO2), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon carbon nitride (SiCN) and other related integrated circuit insulating materials.
  • the semiconductor structure further includes: a second conductive layer 30 located in the substrate 10 , the second conductive layer 30 and the first conductive layer 22
  • the first conductive layer 22 is connected to the second conductive layer 30 through the connection pillars 31, and the connection pillars 31 are conductive structures.
  • An embodiment of the present disclosure further provides a semiconductor structure, including: a substrate 10 ; a communication portion 21 , the communication portion 21 is located in the substrate 10 , and the communication portion 21 includes a first connection layer 211 , a second connection layer 212 and a third connection layer 213, the second connection layer 212 is located on the first connection layer 211, and the third connection layer 213 is located on the second connection layer 212; wherein, the second connection layer 212 and the third connection layer 213 both include graphene, and the second connection layer 213
  • the thermal expansion coefficients of the connection layer 212 and the third connection layer 213 are both smaller than the thermal expansion coefficient of the first connection layer 211 .
  • the semiconductor structure in this embodiment includes the first connecting layer 211 and the graphene located above it.
  • the setting of the graphene can effectively avoid the influence on the surrounding lattice of the communication part 21, and the graphene can Dissipate heat in time. This improves the performance of the semiconductor structure.
  • An embodiment of the present disclosure also provides a method for fabricating a semiconductor structure. Please refer to FIG. 6 .
  • the method for fabricating a semiconductor structure includes:
  • the communication part 21 includes a first connection layer 211, a second connection layer 212 and a third connection layer 213, the second connection layer 212 is formed on the first connection layer 211, and the third connection layer layer 213 is formed on the second connection layer 212;
  • the first connection layer 211 , the second connection layer 212 and the third connection layer 213 include different conductive materials, and the thermal expansion coefficients of the second connection layer 212 and the third connection layer 213 are both smaller than that of the first connection layer 211 .
  • a connecting portion 21 is formed on the base 13, and the connecting portion 21 includes a first connection layer 211, a second connection layer 212 and a third connection layer 213 formed of different conductive materials.
  • the thermal expansion coefficients of the second connection layer 212 and the third connection layer 213 are both smaller than the thermal expansion coefficient of the first connection layer 211, and the third connection layer 213 is connected to the first conductive layer 22, that is, the second connection layer 212 and the third connection layer 213.
  • the thermal expansion of the connection layer 213 is less changed, thereby reducing the influence on the peripheral lattice of the connecting portion 21, thereby improving the performance of the semiconductor structure.
  • the second connection layer 212 or the third connection layer 213 includes graphene
  • the first connection layer 211 includes copper.
  • the thermal expansion coefficient of copper is relatively large, but since it is in the lowermost layer, it will not affect the components in the substrate 10, while the second connection layer 212 or the third connection layer 213 is closer to the components in the substrate 10, while the graphene
  • the coefficient of thermal expansion is negative, so graphene counteracts the thermal expansion of copper, which avoids squeezing problems.
  • the opening 14 is formed on the first connection layer 211 , and the second connection layer 212 and the third connection layer 213 are sequentially formed in the opening 14 , that is, the structure shown in FIGS. 1 and 2 is formed.
  • the base body 13 includes a silicon substrate 11 and a first insulating layer 15 , an opening 16 is formed on the silicon substrate 11 and the first insulating layer 15 , and the opening 16 penetrates through the first insulating layer 15 .
  • the silicon substrate 11 which is not limited here.
  • a second insulating layer 17 is covered on the first insulating layer 15 , and the second insulating layer 17 covers the wall surface of the opening 16 , as shown in FIG. 8 .
  • a third insulating layer 18 is covered on the second insulating layer 17 , and the third insulating layer 18 covers the upper surface and the side surface of the second insulating layer 17 , as shown in FIG. 9 .
  • the first initial connection layer 19 is covered on the third insulating layer 18 , the first initial connection layer 19 fills the part of the opening 16 , and an opening 14 is formed above the first initial connection layer 19 , such as shown in Figure 10.
  • a second initial connection layer 32 is covered on the first initial connection layer 19 , and the second initial connection layer 32 fills the opening 14 , as shown in FIG. 11 .
  • the second initial connection layer 32 covering the upper surface of the first initial connection layer 19 and located outside the opening 14 is removed, and part of the opening 14 is leaked to form the second connection layer 212 , as shown in FIG. 12 . Show.
  • a third initial connection layer 33 is covered on the first initial connection layer 19 , and the third initial connection layer 33 fills the opening 14 , as shown in FIG. 13 .
  • the third initial connection layer 33 covering the upper surface of the first initial connection layer 19 and located outside the opening 14 and a part of the first initial connection layer 19 on the third insulating layer 18 are removed, so as to The first connection layer 211 and the third connection layer 213 are formed, as shown in FIG. 14 , that is, the semiconductor structure shown in FIG. 1 can be finally formed.
  • the first connection layer 211 , the second connection layer 212 and the third connection layer 213 are sequentially formed in the base body 13 ; wherein the first connection layer 211 , the second connection layer 212 and the third connection layer 213 are in The projections in the direction perpendicular to the base body 13 are coincident, that is, the structures shown in FIG. 3 and FIG. 4 are formed.
  • part of the first initial connection layer 19 is removed, ie, the upper part of the opening 16 is exposed to form the first connection layer 211 , as shown in FIG. 15 .
  • a second initial connection layer 32 is covered on the third insulating layer 18 , and the second initial connection layer 32 fills the opening 16 , as shown in FIG. 16 .
  • the third initial connection layer 33 is covered on the third insulating layer 18 , and the third initial connection layer 33 fills the opening 16 , as shown in FIG. 18 .
  • part of the third initial connection layer 33 is removed, that is, the upper surface of the third initial connection layer 33 is flush with the upper surface of the third insulating layer 18 to form the third connection layer 213 , as shown in FIG. 19 .
  • the semiconductor structure shown in FIG. 3 can be finally formed.
  • first insulating layer 15, the second insulating layer 17 and the third insulating layer 18 may include silicon dioxide (SiO2), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon carbonitride ( SiCN) and other related integrated circuit insulating materials.
  • the formation process of the first insulating layer 15, the second insulating layer 17, the third insulating layer 18, the second initial connection layer 32 and the third initial connection layer 33 can be performed in physical vapor deposition (Physical Vapor Deposition, PVD). ) process, chemical vapor deposition (Chemical Vapor Deposition, CVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process, in-situ steam generation (In-Situ Steam Generation, ISSG) process and spin-on dielectric layer (spin on dielectric, SOD) process, etc., which is not limited here.
  • physical vapor deposition Physical Vapor Deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • ISSG In-Situ Steam Generation
  • ISSG In-Situ Steam Generation
  • SOD spin-on dielectric layer
  • the formation process of the opening 14 and the opening 16 includes photolithography and etching. After each coating is formed, it can be combined with a chemical mechanical polishing (CMP) process to ensure the flatness of the coating.
  • CMP chemical mechanical polishing
  • the formation of the first initial connection layer 19 may adopt a process such as electroplating or sputtering, which is not limited here.
  • the semiconductor structure may be formed by the above-described method of fabricating a semiconductor structure.
  • the fabrication method of the semiconductor structure may further include forming the second conductive layer 30 and the like, which is not limited here.
  • the silicon substrate 11 and each of the above-mentioned insulating layers are all part of the base 10 , that is, the base 13 belongs to a part of the base 10 .
  • the first insulating layer 15 , the second insulating layer 17 and the third insulating layer 18 are all part of the insulating layer 12 .

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Abstract

本公开涉及半导体技术领域，提出了一种半导体结构及半导体结构的制作方法。半导体结构包括衬底和连通部，连通部位于衬底内，连通部包括第一连接层、第二连接层以及第三连接层，第二连接层位于第一连接层上，第三连接层位于第二连接层上；其中，第一连接层、第二连接层以及第三连接层包括不同的导电材料，第二连接层和第三连接层的热膨胀系数均小于第一连接层的热膨胀系数，即第二连接层和第三连接层受热膨胀变化较小，从而减小对连通部的周边晶格的影响，以此改善半导体结构的性能。

Description

半导体结构及半导体结构的制作方法
交叉引用
本公开要求于2021年03月10日提交的申请号为202110265111.5、名称为“半导体结构及半导体结构的制作方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及半导体结构的制作方法。
背景技术
相关技术中，连通部内填充的金属导电材料，在受热膨胀过程中会影响连通部周边晶格，从而影响半导体结构的性能。
发明内容
本公开提供一种半导体结构及半导体结构的制作方法，以改善半导体结构的性能。
根据本公开的第一个方面，提供了一种半导体结构，包括：
衬底；
连通部，连通部位于衬底内，连通部包括第一连接层、第二连接层以及第三连接层，第二连接层位于第一连接层上，第三连接层位于第二连接层上；
其中，第一连接层、第二连接层以及第三连接层包括不同的导电材料，第二连接层和第三连接层的热膨胀系数均小于第一连接层的热膨胀系数。
根据本公开的第二个方面，提供了一种半导体结构，包括：
衬底；
连通部，连通部位于衬底内，连通部包括第一连接层、第二连接层以及第三连接层，第二连接层位于第一连接层上，第三连接层位于第二连接层上；
其中，第二连接层和第三连接层均包括石墨烯，且第二连接层和第三连接层的热膨胀系数均小于第一连接层的热膨胀系数。
根据本公开的第三个方面，提供了一种半导体结构的制作方法，包括：
提供基体；
在基体上形成连通部，连通部包括第一连接层、第二连接层以及第三连接层，第二连接层形成于第一连接层上，第三连接层形成于第二连接层上；
其中，第一连接层、第二连接层以及第三连接层包括不同的导电材料，第二连接层和第三连接层的热膨胀系数均小于第一连接层的热膨胀系数。
本公开的半导体结构包括衬底和连通部，连通部包括不同的导电材料形成的第一连接层、第二连接层以及第三连接层，通过使得第二连接层和第三连接层的热膨胀系数均小于第一连接层的热膨胀系数，即第二连接层和第三连接层受热膨胀变化较小，从而减小对连通部的周边晶格的影响，以此改善半导体结构的性能。
附图说明
通过结合附图考虑以下对本公开的优选实施方式的详细说明，本公开的各种目标，特征和优点将变得更加显而易见。附图仅为本公开的示范性图解，并非一定是按比例绘制。在附图中，同样的附图标记始终表示相同或类似的部件。其中：
图1是根据第一个示例性实施方式示出的一种半导体结构的结构示意图；
图2是根据第一个示例性实施方式示出的一种半导体结构的连通部的结构示意图；
图3是根据第二个示例性实施方式示出的一种半导体结构的结构示意图；
图4是根据第二个示例性实施方式示出的一种半导体结构的连通部的结构示意图；
图5是根据第三个示例性实施方式示出的一种半导体结构的结构示意图；
图6是根据一示例性实施方式示出的一种半导体结构的制作方法的流程示意图；
图7是根据第一个示例性实施方式示出的一种半导体结构的制作方法形成开孔的结构示意图；
图8是根据第一个示例性实施方式示出的一种半导体结构的制作方法形成第二绝缘层孔的结构示意图；
图9是根据第一个示例性实施方式示出的一种半导体结构的制作方法形成第三绝缘层孔的结构示意图；
图10是根据第一个示例性实施方式示出的一种半导体结构的制作方法形成第一初始连接层的结构示意图；
图11是根据第一个示例性实施方式示出的一种半导体结构的制作方法形成第二初始连接层的结构示意图；
图12是根据第一个示例性实施方式示出的一种半导体结构的制作方法形成第二连接 层的结构示意图；
图13是根据第一个示例性实施方式示出的一种半导体结构的制作方法形成第三初始连接层的结构示意图；
图14是根据第一个示例性实施方式示出的一种半导体结构的制作方法形成第三连接层的结构示意图；
图15是根据第二个示例性实施方式示出的一种半导体结构的制作方法形成第一初始连接层的结构示意图；
图16是根据第二个示例性实施方式示出的一种半导体结构的制作方法形成第二初始连接层的结构示意图；
图17是根据第二个示例性实施方式示出的一种半导体结构的制作方法形成第二连接层的结构示意图；
图18是根据第二个示例性实施方式示出的一种半导体结构的制作方法形成第三初始连接层的结构示意图；
图19是根据第二个示例性实施方式示出的一种半导体结构的制作方法形成第三连接层的结构示意图。
附图标记说明如下：
10、基底；11、硅衬底；111、功能层；12、绝缘层；20、导电部；21、连通部；211、第一连接层；212、第二连接层；213、第三连接层；22、第一导电层；30、第二导电层；31、连接柱；
13、基体；14、开口；15、第一绝缘层；16、开孔；17、第二绝缘层；18、第三绝缘层；19、第一初始连接层；32、第二初始连接层；33、第三初始连接层。
具体实施方式
体现本公开特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是本公开能够在不同的实施例上具有各种的变化，其皆不脱离本公开的范围，且其中的说明及附图在本质上是作说明之用，而非用以限制本公开。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构，系统和步骤。应理解的是，可以使用部件，结构，示例性装置，系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用 术语“之上”，“之间”，“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。
本公开的一个实施例提供了一种半导体结构，请参考图1至图5，半导体结构包括：基底10；连通部21，连通部21位于基底10内，连通部21包括第一连接层211、第二连接层212以及第三连接层213，第二连接层212位于第一连接层211上，第三连接层213位于第二连接层212上；其中，第一连接层211、第二连接层212以及第三连接层213包括不同的导电材料，第二连接层212和第三连接层213的热膨胀系数均小于第一连接层211的热膨胀系数。
本公开一个实施例的半导体结构包括基底10和连通部21，连通部21包括不同的导电材料形成的第一连接层211、第二连接层212以及第三连接层213，通过使得第二连接层212和第三连接层213的热膨胀系数均小于第一连接层211的热膨胀系数，即第二连接层212和第三连接层213受热膨胀变化较小，从而减小对连通部21的周边晶格的影响，以此改善半导体结构的性能。
需要说明的是，由于第二连接层212和第三连接层213的热膨胀系数均小于第一连接层211的热膨胀系数，利用低热膨胀系数的材料作为连通部21的部分导电材料，来减少主动元件区域受金属热膨胀的影响，也可减小周边晶格MOS元件的电性变化，缩小芯片设计的尺。热膨胀系数较小的第二连接层212和第三连接层213受热变形较小，因此不会出现大压力挤压连通部21的周边晶格的问题，从而可以避免对基底10内的其他元器件的影响。
在一些实施例中，连通部21属于导电部20的一部分，导电部20还包括第一导电层22，第一导电层22位于连通部21的上方，第三连接层213与第一导电层22相连接，由于第二连接层212和第三连接层213靠近第一导电层22，由于第二连接层212和第三连接层213的热膨胀系数较小，也不会过度挤压第一导电层22的情况。
在一些实施例中，连通部21为硅通孔。
在一个实施例中，第二连接层212的热膨胀系数小于第三连接层213的热膨胀系数，即连通部21中热膨胀系数最小的导电材料位于中间位置，而此位置基底10对应的位置一般设置有大量元器件，因此热膨胀系数最小的导电材料受热膨胀影响最小，基本不会对元器件造成挤压。
在一个实施例中，第二连接层212或第三连接层213包括石墨烯，第一连接层211包 括铜。铜的热膨胀系数较大，但由于其在最下层，因此不会影响基底10内的元器件，而第二连接层212或第三连接层213更靠近基底10内的元器件，而石墨烯的热膨胀系数为负数，因此石墨烯可以抵消铜的热膨胀，从而可以避免出现挤压问题。
在一些实施例中，第一连接层211由铜形成，第二连接层212由石墨烯形成，而第三连接层213由钨形成。
需要说明的是，当第二连接层212包括石墨烯时，由于石墨烯夹持于第一连接层211和第三连接层213之间，此时由于石墨烯具备一定的储热功能，因此可以吸收热膨胀系数相大的导电材料的热量，即吸收第一连接层211和第三连接层213的热量，以此降低其他导电材料受热发生的膨胀。
当第二连接层212包括石墨烯时，第一连接层211和第二连接层212产生的热量可以由石墨烯及时传递至第一导电层22，并通过与第一导电层22相连接的结构传递出去，从而达到快速散热的效果。
在一个实施例中，如图1和图2所示，第二连接层212位于第一连接层211内，即第二连接层212的周向方向被第一连接层211所包围，具有高热膨胀系数的第一连接层211可以起到保护第二连接层212的作用，但由于第二连接层212的热膨胀系数相对较小，因此也不会受热膨胀产生较大的挤压力。
在一些实施例中，第二连接层212位于第一连接层211内，第三连接层213的底端与第二连接层212以及第一连接层211的顶端相对齐。
在一些实施例中，第二连接层212位于第一连接层211内，第三连接层213位于第一连接层211内，即第二连接层212和第三连接层213的周向方向均被第一连接层211所包围，具体如图1和图2所示。
在一个实施例中，如图1和图2所示，第二连接层212与第三连接层213在垂直于基底10方向上的投影相重合，即第二连接层212的横截面积与第三连接层213的横截面积相等。
可选的，第三连接层213的顶端与第一连接层211的顶端相平齐，此时第一连接层211形成有一个凹槽，而第二连接层212和第三连接层213位于此凹槽内，且第一连接层211的顶端以及第三连接层213的顶端与第一导电层22相连接，具体如图1和图2所示。在本实施例中，第一连接层211、第二连接层212以及第三连接层213包括不同的导电材料，第二连接层212的热膨胀系数小于第三连接层213的热膨胀系数，第三连接层213的热膨胀系数小于第一连接层211的热膨胀系数，第一连接层211由铜形成，第二连接层212由 石墨烯形成，而第三连接层213由钨形成。
在一个实施例中，如图3和图4所示，第一连接层211、第二连接层212以及第三连接层213在垂直于基底10方向上的投影相重合，即第一连接层211、第二连接层212以及第三连接层213沿着基底10的高度方向依次堆叠，且第一连接层211、第二连接层212以及第三连接层213的横截面积均相等，此时仅第三连接层213直接与第一导电层22相连接。在本实施例中，第一连接层211、第二连接层212以及第三连接层213包括不同的导电材料，第二连接层212的热膨胀系数小于第三连接层213的热膨胀系数，第三连接层213的热膨胀系数小于第一连接层211的热膨胀系数，第一连接层211由铜形成，第二连接层212由石墨烯形成，而第三连接层213由钨形成。
在一些实施例中，如图5所示，第二连接层212位于第一连接层211内，第一连接层211与第三连接层213在垂直于基底10方向上的投影相重合，即第三连接层213的底端与第二连接层212以及第一连接层211的顶端相连接。
在一个实施例中，如图1、图3以及图5所示，基底10包括：硅衬底11，第二连接层212的底端低于硅衬底11的上表面；绝缘层12，绝缘层12覆盖硅衬底11的上表面，且覆盖连通部21的外表面，第一导电层22位于绝缘层12内。
具体的，基底10包括硅衬底11和绝缘层12，连通部21的部分位于硅衬底11内，而第二连接层212的底端低于硅衬底11的上表面，且由于第二连接层212的热膨胀系数小于第一连接层211的热膨胀系数，因此第二连接层212不会受热过度膨胀，因此可以避免对硅衬底11靠近其上表面的部分造成影响。
在一个实施例中，硅衬底11内形成有功能层111，第二连接层212的底端低于功能层111的下表面，即第二连接层212和第三连接层213的整体高度之和不小于硅衬底11内的功能层111的高度，以此避免对功能层111造成的热膨胀挤压。其中，第二连接层212的高度可以大于功能层111的高度。
需要说明的是，功能层111内可以具有多种元器件，对于元器件的类型此处不作限定，可以根据实际需求进行选择，此处重在体现第二连接层212整体受热膨胀后不会对功能层111形成挤压，从而可以起到保护功能层111的作用。
在一个实施例中，第二连接层212的顶端高于硅衬底11的上表面，即第二连接层212的高度可以高于功能层111的高度，从而对硅衬底11靠近绝缘层12的部分起到保护作用，避免对功能层111造成挤压。
在一些实施例中，第一连接层211、第二连接层212以及第三连接层213可以为圆柱 结构。
在一些实施例中，第二连接层212的直径可为200nm～10um，深度可为1um～20um。第二连接层212进入硅衬底11的深度大于等于1um。
具体的，硅衬底11可以由含硅材料形成。硅衬底11可以由任何合适的材料形成，例如，包括硅、单晶硅、非晶硅、硅锗、单晶硅锗、碳化硅、蓝宝石中的至少一种。
绝缘层12可以包括二氧化硅(SiO2)、碳氧化硅(SiOC)、氮化硅(SiN)、碳氮化硅(SiCN)等相关集成电路绝缘材料。
在一个实施例中，如图1、图3和图5所示，半导体结构还包括：第二导电层30，第二导电层30位于基底10内，第二导电层30与第一导电层22相间隔，且位于第一导电层22的上方，第一导电层22通过连接柱31与第二导电层30相连接，连接柱31为导电结构。
本公开的一个实施例还提供了一种半导体结构，包括：基底10；连通部21，连通部21位于基底10内，连通部21包括第一连接层211、第二连接层212以及第三连接层213，第二连接层212位于第一连接层211上，第三连接层213位于第二连接层212上；其中，第二连接层212和第三连接层213均包括石墨烯，且第二连接层212和第三连接层213的热膨胀系数均小于第一连接层211的热膨胀系数。
相对于上述实施例，本实施例中的半导体结构包括第一连接层211和位于其上方的石墨烯，石墨烯的设置可以有效避免对连通部21的周边晶格的影响，并且通过石墨烯可以将热量及时传出。以此改善半导体结构的性能。
需要说明的是，对于其他相关结构可以参考上述实施例，此处不作赘述。
本公开的一个实施例还提供了一种半导体结构的制作方法，请参考图6，半导体结构的制作方法包括：
S101，提供基体13；
S103，在基体13上形成连通部21，连通部21包括第一连接层211、第二连接层212以及第三连接层213，第二连接层212形成于第一连接层211上，第三连接层213形成于第二连接层212上；
其中，第一连接层211、第二连接层212以及第三连接层213包括不同的导电材料，第二连接层212和第三连接层213的热膨胀系数均小于第一连接层211的热膨胀系数。
本公开一个实施例的半导体结构的制作方法在基体13上形成了连通部21，连通部21包括不同的导电材料形成的第一连接层211、第二连接层212以及第三连接层213，通过使得第二连接层212和第三连接层213的热膨胀系数均小于第一连接层211的热膨胀系 数，且第三连接层213与第一导电层22相连接，即第二连接层212和第三连接层213受热膨胀变化较小，从而减小对连通部21的周边晶格的影响，以此改善半导体结构的性能。
在一个实施例中，第二连接层212或第三连接层213包括石墨烯，第一连接层211包括铜。铜的热膨胀系数较大，但由于其在最下层，因此不会影响基底10内的元器件，而第二连接层212或第三连接层213更靠近基底10内的元器件，而石墨烯的热膨胀系数为负数，因此石墨烯可抵消铜的热膨胀，从而可以避免出现挤压问题。
在一个实施例中，第一连接层211上形成有开口14，第二连接层212和第三连接层213依次形成于开口14内，即形成图1和图2所示的结构。
具体的，如图7所示，基体13包括硅衬底11和第一绝缘层15，在硅衬底11和第一绝缘层15上形成开孔16，开孔16贯通第一绝缘层15，但不一定贯通硅衬底11，此处不作限定。
在图7的基础上，在第一绝缘层15上覆盖第二绝缘层17，第二绝缘层17覆盖开孔16的壁面，如图8所示。
在图8的基础上，在第二绝缘层17上覆盖第三绝缘层18，第三绝缘层18覆盖第二绝缘层17的上表面以及侧表面，如图9所示。
在图9的基础上，在第三绝缘层18上覆盖第一初始连接层19，第一初始连接层19填充开孔16的部分，且第一初始连接层19的上方形成有开口14，如图10所示。
在图10的基础上，在第一初始连接层19上覆盖第二初始连接层32，第二初始连接层32填充开口14，如图11所示。
在图11的基础上，去除覆盖在第一初始连接层19上表面，且位于开口14外侧的第二初始连接层32，并漏出部分开口14，以形成第二连接层212，如图12所示。
在图12的基础上，在第一初始连接层19上覆盖第三初始连接层33，第三初始连接层33填充开口14，如图13所示。
在图13的基础上，去除覆盖在第一初始连接层19上表面，且位于开口14外侧的第三初始连接层33，以及位于第三绝缘层18上的部分第一初始连接层19，以形成第一连接层211和第三连接层213，如图14所示，即最终可以形成图1所示的半导体结构。
在一个实施例中，第一连接层211、第二连接层212以及第三连接层213依次形成于基体13内；其中，第一连接层211、第二连接层212以及第三连接层213在垂直于基体13方向上的投影相重合，即形成图3和图4所示的结构。
具体的，在图10的基础上，去除部分的第一初始连接层19，即暴露出开孔16的上方， 形成第一连接层211，如图15所示。
在图15的基础上，在第三绝缘层18上覆盖第二初始连接层32，第二初始连接层32填充开孔16，如图16所示。
在图16的基础上，去除部分的第二初始连接层32，即暴露出开孔16的上方，形成第二连接层212，如图17所示。
在图17的基础上，在第三绝缘层18上覆盖第三初始连接层33，第三初始连接层33填充开孔16，如图18所示。
在图18的基础上，去除部分的第三初始连接层33，即使得第三初始连接层33的上表面与第三绝缘层18上表面平齐，形成第三连接层213，如图19所示，即最终可以形成图3所示的半导体结构。
需要说明的是，第一绝缘层15、第二绝缘层17以及第三绝缘层18可以包括二氧化硅(SiO2)、碳氧化硅(SiOC)、氮化硅(SiN)、碳氮化硅(SiCN)等相关集成电路绝缘材料。
需要说明的是，第一绝缘层15、第二绝缘层17、第三绝缘层18、第二初始连接层32以及第三初始连接层33的形成工艺可以在物理气相沉积(Physical Vapor Deposition，PVD)工艺、化学气相沉积(Chemical Vapor Deposition，CVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺、原位水汽生成(In-Situ Steam Generation，ISSG)工艺以及旋涂介电层(spin on dielectric，SOD)工艺等中进行选择，此处不作限定。
开口14以及开孔16的形成工艺包括光刻以及蚀刻等。在每个涂层形成后可以结合抛光(Chemical Mechanical Polishing，CMP)工艺进行处理，以此保证涂层的平整度。第一初始连接层19的形成可以采用电镀或者溅射等工艺，此处不作限定。
在一个实施例中，半导体结构可以由上述的半导体结构的制作方法形成。半导体结构的制作方法还可以包括形成第二导电层30等，此处不作限定。硅衬底11以及上述的各个绝缘层均是基底10的一部分，即基体13属于基底10的一部分。第一绝缘层15、第二绝缘层17以及第三绝缘层18均属于绝缘层12的一部分。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和示例实施方式仅被视为示例性的，本公开的真正范围和精神由前面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (20)

  1. 一种半导体结构，包括：
    基底；
    连通部，连通部位于所述基底内，所述连通部包括第一连接层、第二连接层以及第三连接层，所述第二连接层位于所述第一连接层上，所述第三连接层位于所述第二连接层上；
    其中，所述第一连接层、所述第二连接层以及所述第三连接层包括不同的导电材料，所述第二连接层和所述第三连接层的热膨胀系数均小于所述第一连接层的热膨胀系数。
  2. 根据权利要求1所述的半导体结构，其中，所述第二连接层的热膨胀系数小于所述第三连接层的热膨胀系数。
  3. 根据权利要求1或2所述的半导体结构，其中，所述第二连接层或所述第三连接层包括石墨烯，所述第一连接层包括铜。
  4. 根据权利要求1或2所述的半导体结构，其中，所述第二连接层位于所述第一连接层内。
  5. 根据权利要求4所述的半导体结构，其中，所述第三连接层位于所述第一连接层内。
  6. 根据权利要求5所述的半导体结构，其中，所述第二连接层与所述第三连接层在垂直于所述基底方向上的投影相重合；
    其中，所述第三连接层的顶端与所述第一连接层的顶端相平齐。
  7. 根据权利要求4所述的半导体结构，其中，所述第一连接层与所述第三连接层在垂直于所述基底方向上的投影相重合。
  8. 根据权利要求4所述的半导体结构，其中，所述第三连接层的底端与所述第二连接层以及所述第一连接层的顶端相对齐。
  9. 根据权利要求1或2所述的半导体结构，其中，所述第一连接层、所述第二连接层以及所述第三连接层在垂直于所述基底方向上的投影相重合。
  10. 根据权利要求1或2所述的半导体结构，其中，所述基底包括：
    硅衬底，所述第二连接层的底端低于所述硅衬底的上表面；
    绝缘层，所述绝缘层覆盖所述硅衬底的上表面，且覆盖所述连通部的外表面。
  11. 根据权利要求10所述的半导体结构，其中，所述硅衬底内形成有功能层，所述第二连接层的底端低于所述功能层的下表面。
  12. 根据权利要求10所述的半导体结构，其中，所述第二连接层的顶端高于所述硅衬 底的上表面。
  13. 根据权利要求10所述的半导体结构，其中，所述第二连接层进入所述硅衬底的深度大于等于1um。
  14. 根据权利要求1所述的半导体结构，其中，所述连通部为硅通孔。
  15. 根据权利要求1所述的半导体结构，其中，所述第二连接层的直径为200nm～10um，所述第二连接层的深度为1um～20um。
  16. 一种半导体结构，包括：
    基底；
    连通部，连通部位于基底内，所述连通部包括第一连接层、第二连接层以及第三连接层，所述第二连接层位于所述第一连接层上，所述第三连接层位于所述第二连接层上；
    其中，所述第二连接层和所述第三连接层均包括石墨烯，且所述第二连接层和所述第三连接层的热膨胀系数均小于所述第一连接层的热膨胀系数。
  17. 一种半导体结构的制作方法，包括：
    提供基体；
    在所述基体上形成连通部，所述连通部包括第一连接层、第二连接层以及第三连接层，所述第二连接层形成于所述第一连接层上，所述第三连接层形成于所述第二连接层上；
    其中，所述第一连接层、所述第二连接层以及所述第三连接层包括不同的导电材料，所述第二连接层和所述第三连接层的热膨胀系数均小于所述第一连接层的热膨胀系数。
  18. 根据权利要求17所述的半导体结构的制作方法，其中，所述第二连接层或所述第三连接层包括石墨烯，所述第一连接层包括铜。
  19. 根据权利要求17或18所述的半导体结构的制作方法，其中，所述第一连接层上形成有开口，所述第二连接层和所述第三连接层依次形成于所述开口内。
  20. 根据权利要求17或18所述的半导体结构的制作方法，其中，所述第一连接层、所述第二连接层以及所述第三连接层依次形成于所述基体内；
    其中，所述第一连接层、所述第二连接层以及所述第三连接层在垂直于所述基体方向上的投影相重合。
PCT/CN2021/112594 2021-03-10 2021-08-13 半导体结构及半导体结构的制作方法 WO2022188358A1 (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1667812A (zh) * 2004-02-27 2005-09-14 恩益禧电子股份有限公司 半导体器件及其制造方法
US20140015136A1 (en) * 2012-07-12 2014-01-16 Zhenghao Gan Ic device including package structure and method of forming the same
CN112151503A (zh) * 2020-08-17 2020-12-29 复旦大学 一种石墨烯/铜复合互连结构及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1667812A (zh) * 2004-02-27 2005-09-14 恩益禧电子股份有限公司 半导体器件及其制造方法
US20140015136A1 (en) * 2012-07-12 2014-01-16 Zhenghao Gan Ic device including package structure and method of forming the same
CN112151503A (zh) * 2020-08-17 2020-12-29 复旦大学 一种石墨烯/铜复合互连结构及其制造方法

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