WO2022188042A1 - 攻击检测方法和装置 - Google Patents

攻击检测方法和装置 Download PDF

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Publication number
WO2022188042A1
WO2022188042A1 PCT/CN2021/079829 CN2021079829W WO2022188042A1 WO 2022188042 A1 WO2022188042 A1 WO 2022188042A1 CN 2021079829 W CN2021079829 W CN 2021079829W WO 2022188042 A1 WO2022188042 A1 WO 2022188042A1
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Prior art keywords
data
chip
attack detection
storage module
module
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PCT/CN2021/079829
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English (en)
French (fr)
Inventor
刘彭劼
肖勇军
季彦平
贾波
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180005198.0A priority Critical patent/CN115398862A/zh
Priority to PCT/CN2021/079829 priority patent/WO2022188042A1/zh
Publication of WO2022188042A1 publication Critical patent/WO2022188042A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols

Definitions

  • the present application relates to the technical field of data security, and in particular, to an attack detection method and apparatus.
  • an alarm circuit or a data verification algorithm is usually used to detect whether a chip is attacked by an attacker.
  • the alarm circuit it is possible to detect whether the chip is attacked by an attacker by designing the wiring of the metal layer in the chip as a protective net, or by integrating a digital circuit inside the silicon chip for judging whether the operating state of the chip is stable.
  • a data verification algorithm can also be added to determine whether the data has been tampered with by the attacker by verifying whether the data is correct. .
  • the embodiments of the present application provide an attack detection method and apparatus, which are used to detect whether a chip is attacked by an attacker when the chip is powered off. To achieve the above purpose, the embodiments of the present application adopt the following technical solutions.
  • an attack detection method including: acquiring first data, where the first data is used to verify second data; reading the second data from a storage module, wherein the storage module is not easily powered off A volatile storage device, and the data in the storage module is changed when it encounters external heating; the second data is verified according to the first data to obtain a verification result, which indicates the system where the storage module is located Whether attacked by external heating.
  • the non-power-off volatility of the storage module and the characteristic that the data stored in the storage module is changed when encountering external heating are utilized.
  • the attack detection device for executing the attack detection method is located is powered off, the data stored in the storage module will not be lost. If no external heating attack occurs, the data stored in the storage module will remain unchanged; Heating attack, the data stored in the storage module will change.
  • the attack detection device determines whether the system where the attack detection device is located is attacked by external heating by verifying the second data read from the storage module.
  • the attack detection method can realize full-time system attack detection, that is, the attack detection method can not only detect whether the system is attacked by an attacker when powered on, but also detect whether the system is attacked by an attacker when the system is powered off. .
  • the attack detection method is aimed at external heating attacks, including the step of removing the chip package. Compared with the prior art, the attack detection method can detect the attack earlier and prevent the silicon of the chip from being directly exposed to the attacker. , thereby protecting the integrity of the chip.
  • the attack detection method can also be used in combination with the prior art to increase the time taken by the attacker to attack the chip, thereby increasing the complexity of the attack chip.
  • verifying the second data according to the first data to obtain a verification result includes: comparing the first data and the second data to obtain as the verification result the comparison result of the results; or, comparing the first data with the fourth data obtained by processing the second data to obtain a comparison result as the verification result; or, comparing the second data with the data obtained by processing the first data the third data to obtain the comparison result as the verification result; or, compare the fourth data obtained by processing the second data with the third data obtained by processing the first data to obtain the comparison result as the verification result .
  • the verification result can be obtained directly and simply; by first processing the first data and/or the second data and then comparing, the integrity of the second data can be indirectly verified, so that the Get the verification result.
  • the comparison result indicates that the system is not attacked by external heating; if the comparison result is different, the comparison result indicates that the system is subjected to external heating Heat attack.
  • acquiring the first data includes: acquiring the first data from an on-chip memory of a first chip of the system, where the first chip is a computing chip.
  • the storage module is located in the first chip, or the storage module is located in a second chip in the system, and the second chip is different from the first chip.
  • the method is executed after the system where the storage module is located is powered on or when the system needs to run a preset program.
  • the execution of the attack detection method may provide a reference in security for the operation of the system after the system is powered on, or may provide a reference for the system to run a preset program.
  • the storage module includes a phase change memory. Since the phase change memory has the characteristic of being stable in storage at normal temperature, but the data stored therein is changed when it encounters external heating, and the characteristic is stable, therefore, the memory module including the phase change memory can well perform the attack detection method .
  • an attack detection apparatus for implementing the above attack detection method.
  • the attack detection apparatus includes corresponding modules, units, or means (means) for implementing the above method, and the modules, units, or means can be implemented by hardware, software, or by executing corresponding software in hardware.
  • the hardware or software includes one or more modules or units corresponding to the above functions.
  • the attack detection device includes: an acquisition module, configured to acquire first data, where the first data is used to verify the second data; the acquisition module, further configured to The second data is read from a storage module, wherein the storage module is a non-power-down volatile storage device, and the data in the storage module is changed when external heating is encountered; a verification module is used for according to the first The data verifies the second data to obtain a verification result, which indicates whether the system in which the storage module is located is attacked by external heating.
  • the verification module is specifically configured to: compare the first data and the second data to obtain a comparison result as the verification result; or, compare the The first data and the fourth data obtained by processing the second data to obtain the comparison result as the verification result; or, comparing the second data and the third data obtained by processing the first data to obtain the verification result as the or comparing the fourth data obtained by processing the second data with the third data obtained by processing the first data to obtain a comparison result as the verification result.
  • the comparison result indicates that the system is not attacked by external heating; if the comparison result is different, the comparison result indicates that the system is attacked by external heating External heat attack.
  • the obtaining module configured to obtain the first data, includes: the obtaining module, configured to obtain the first data from the on-chip memory of the first chip of the system , the first chip is a computing chip.
  • the storage module is located in the first chip, or the storage module is located in a second chip in the system, and the second chip is different from the first chip.
  • the apparatus executes the attack detection method after the system where the storage module is located is powered on or when the system where the storage module is located needs to run a preset program.
  • the storage module includes a phase change memory.
  • the above acquisition module is an interface
  • the verification module includes a verification circuit, such as a logic circuit, or the verification module includes a processor that can run verification software.
  • a system comprising the attack detection apparatus described in the second aspect above.
  • the attack detection apparatus is included in a first chip of the system, wherein the first chip further includes an on-chip memory for storing the first data.
  • the system further includes a second chip different from the first chip, wherein the second chip includes the storage module.
  • the first chip further includes the storage module.
  • the attack detection apparatus is included in a second chip of the system, wherein the second chip includes the storage module.
  • the system further includes a first chip different from the second chip, wherein the first chip includes an on-chip memory that stores the first data.
  • 2a is a schematic diagram of pulses corresponding to "reading”, "writing” and “erasing” of a phase change memory in the prior art
  • Fig. 2b is a graph showing the corresponding relationship between the pulse shown in Fig. 2a and the transformation between the crystalline state and the amorphous state of the phase change material under different heating conditions;
  • FIG. 3 is a schematic diagram 1 of the architecture of a system provided by an embodiment of the present application.
  • FIG. 4 is a second schematic diagram of the architecture of a system provided by an embodiment of the present application.
  • FIG. 5 is a third schematic diagram of the architecture of the system provided by the embodiment of the present application.
  • FIG. 6 is a flowchart 1 of an attack detection method provided by an embodiment of the present application.
  • FIG. 7 is a second flowchart of an attack detection method provided by an embodiment of the present application.
  • FIG. 8 is a fourth schematic diagram of the architecture of the system provided by the embodiment of the present application.
  • FIG. 9 is a schematic diagram five of the architecture of the system provided by the embodiment of the present application.
  • FIG. 10 is a sixth schematic diagram of the architecture of the system provided by the embodiment of the present application.
  • FIG. 11 is a seventh schematic diagram of the architecture of the system provided by the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of an attack detection apparatus provided by an embodiment of the present application.
  • the steps of the attacker to attack the chip are as follows:
  • the first step is to remove the chip package.
  • an attacker could use a combination of grinding, heat, or chemical etching to remove the chip package.
  • the second step is to carry out the attack.
  • this step may include intrusive and semi-intrusive attacks. Both types of attacks above require direct exposure of the chip's silicon to the attacker, but they differ in that semi-invasive attacks do not require electrical contact with the silicon surface and therefore do not cause mechanical damage to the silicon. damage.
  • an attack that is a semi-invasive attack could use a laser or ultraviolet light for the attacker to irradiate the chip. In contrast, invasive attacks cause mechanical damage to the silicon.
  • an attack method that is an intrusive attack can cut the chip wiring for the attacker.
  • the attack detection method or device using an alarm circuit or a data verification algorithm in the prior art is mainly aimed at the detection of the second step "implementing an attack”. What this application detects is whether there is an external heating attack. Since an attacker uses grinding, heating, or chemical corrosion to remove the chip package, heat will be generated, which can be collectively referred to as a heating attack. Therefore, the technical solution of the present application is mainly aimed at the detection of the above-mentioned first step "removing the chip package".
  • the phase change memory is a memory made of phase change materials.
  • the phase change material has obvious phase change characteristics.
  • Phase change materials have two forms, crystalline and amorphous, and the two forms can be transformed into each other by heating.
  • the resistance value of the crystalline state and the amorphous state of the phase change material is very different.
  • the phase change material as the germanium antimony tellurium compound (Ge2Sb2Te5, GST) as an example
  • the resistance value of the crystalline state of GST can range from 1K to 10K ohms
  • the resistance of the amorphous resistance can exceed 1M ohms. Therefore, the crystalline state can also generally be referred to as a low-resistance state, and the amorphous state can also generally be referred to as a high-resistance state.
  • Fig. 2a shows the pulses corresponding to the action of the phase change memory, wherein the "erase” pulse has the largest amplitude and the shortest pulse duration; the "write” pulse has the longest pulse duration; the “read” pulse has the longest pulse duration; the smallest magnitude.
  • Fig. 2b shows the correspondence between the pulse shown in Fig.
  • T room represents the room temperature, abbreviated as room temperature
  • Tc Represents the crystallization temperature, that is, the temperature that the phase change material needs to reach from the amorphous state to the crystalline state
  • Tm represents the melting temperature, that is, the temperature that the phase change material needs to reach from the crystalline state to the amorphous state
  • the value of Tm is high depending on the value of Tc.
  • the "reading" of the phase change memory is realized by detecting the resistance value of the phase change memory. Since the current passing through the resistive conductor will cause heat generation when the resistance is detected at room temperature, the temperature of the phase change material is slightly higher than the room temperature at this time.
  • the "writing" of the phase change memory is achieved by the process of converting the phase change material from an amorphous state to a crystalline state. Specifically, when the temperature of the phase change material is maintained above Tc for a period of time, the transformation from an amorphous state to a crystalline state can be achieved.
  • the period of time during which the temperature of the phase change material is maintained above Tc can be referred to as the crystallization time.
  • the "erasing" of the phase change memory is achieved through the process of the phase change material being transformed from a crystalline state to an amorphous state. Specifically, the temperature of the phase change material reaches Tm in a short period of time, and then rapidly cools to achieve the transformation from a crystalline state to an amorphous state.
  • phase change materials Due to the different molecular structures, the crystallization temperature and crystallization time of different phase change materials are also different. Common phase change materials and their crystallization temperature and crystallization time are shown in Table 1.
  • At least one item(s) below” or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s).
  • at least one (a) of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c may be single or multiple .
  • words such as “first” and “second” are used to distinguish the same or similar items with basically the same function and effect. Those skilled in the art can understand that the words “first”, “second” and the like do not limit the quantity and execution order, and the words “first”, “second” and the like are not necessarily different.
  • FIG. 3 shows a system 30 provided by an embodiment of the present application.
  • the system 30 includes an attack detection device 30a and a storage module 30b.
  • the attack detection device 30a is used to obtain the first data
  • the first data is used to verify the second data.
  • the attack detection device 30a is further configured to read the second data from the storage module 30b, and verify the second data according to the first data to obtain a verification result, which indicates whether the system 30 where the storage module 30b is located is affected by external Heat attack.
  • the storage module 30b is a non-power-down volatile storage device, and has the characteristic that the data stored therein does not change at normal temperature, but changes when it encounters external heating.
  • the storage module 30b may be a phase change memory.
  • the system 30 in this embodiment may be an electronic system located in an electronic device, where the electronic device includes but is not limited to a terminal, a server or a consumer electronic product.
  • the terminal includes but is not limited to a mobile phone, a personal computer, a tablet computer, a wearable device, or a fixed phone.
  • the specific compound composition of the phase change material used to make the phase change memory can be selected according to the actual situation, such as welding material, packaging material or processing technology, etc., which is not made in the embodiment of the present application. any restrictions.
  • the storage module 30b may also be a NAND memory, or may be other memories having the above-mentioned variable characteristics of data in case of heat, which is not limited in this embodiment of the present application.
  • At least one of the first data, the data after the first data processing, or the data before the first data processing is pre-written into the storage module 30b as the second data.
  • the second data read from the storage module 30b needs to be checked according to the first data.
  • the crystallization temperature of the phase change material is usually in the range of 100°C to 250°C, which is much higher than the temperature of the system 30 during normal operation, "normal operation” means that the system 30 works after power-on and is not attacked by external heating , at this time, the temperature of the system 30 is slightly higher than the room temperature. Therefore, when the system 30 works normally or is powered off, only the data stored in the storage module 30b can be “read”, that is, the data stored in the storage module 30b is not will change.
  • the generated heat causes the temperature of the system 30 to approach or even exceed the crystallization temperature of the phase change material, and the data stored in the storage module 30b is "erased” and /or "write", that is, the data stored in the storage module 30b is changed.
  • the attack detection is performed on the system 30, if the data stored in the storage module 30b has not changed, it can be deduced that the system where the storage module 30b is located during the time period between the detection of the previous attack and the detection of this attack can be deduced.
  • the system 30 is not attacked by external heating; if the data stored in the storage module 30b changes, it can be deduced that the system 30 where the storage module 30b is located has been attacked by external heating during the time period between the detection of the previous attack and the detection of this attack .
  • the system 30 provided in this embodiment of the present application may be one or more integrated circuits of a system in package (SIP) type integrated inside a package, which is not specifically limited in this embodiment of the present application.
  • SIP system in package
  • both the attack detection device 30 a and the storage module 30 b are deployed in the system 30 . Therefore, the “system where the storage module is located” in the embodiment of the present application is the same as the following embodiments.
  • the "system where the attack detection device is located” has the same meaning and can be replaced with each other, and is described here in a unified manner, and will not be repeated below.
  • the system 30 provided in this embodiment of the present application may specifically include one or more chips.
  • the system 30 includes a first chip 401 and a second chip 402 .
  • the second chip 402 is different from the first chip 401, and the first chip 401 and the second chip 402 communicate through a communication bus.
  • the first chip 401 includes an attack detection device 30a
  • the second chip 402 includes a storage module 30b.
  • the first chip 401 may be a computing chip with a processor function.
  • the second chip 402 may be a sensor chip integrated in the protected system.
  • the first chip 401 may further include an on-chip memory 401a.
  • the on-chip memory 401a is used to store the first data.
  • the attack detection device 30a is configured to acquire the first data from the on-chip memory 401a of the first chip 401 .
  • the on-chip memory 401a has non-power-down volatility. That is, after the first chip 401 is powered off, the first data stored in the on-chip memory 401a of the first chip 401 will not be lost.
  • the on-chip memory 401a includes one-time programmable memory.
  • the schematic diagram of the architecture of the system 30 may be as shown in FIG. 5 .
  • the system 30 includes a processor chip 501 and a sensor chip 502 .
  • the processor chip 501 and the sensor chip 502 communicate through a communication bus.
  • the processor chip 501 includes a security processor 501b, and the on-chip memory 401a and the attack detection device 30a are deployed in the security processor 501b.
  • the processor chip 501 further includes a service processor 501a, and the service processor 501a and the security processor 501b communicate through an interface.
  • the service processor 501a may run an operating system or an application program.
  • the service processor 501a can control the processor chip 501 to be turned on or off.
  • the sensor chip 502 includes the memory module 30b.
  • the sensor chip 502 further includes a security protection module 502a.
  • the storage module 30b and the security protection module 502a communicate through an interface.
  • the on-chip memory 401a For the functional description of the on-chip memory 401a, the attack detection device 30a, and the storage module 30b, reference may be made to the above embodiments, and details are not repeated here.
  • the functions of the service processor 501a, the security processor 501b and the security protection module 502a are described below.
  • the service processor 501a is used to process the main service of the system 30 by running a preset program.
  • the service processor 501a may refer to the attack detection result reported by the security processor 501b when running the preset program.
  • the service processor 501a stops running a preset program, such as a preset application program.
  • the secure processor 501b may be a processor with safeguards. Different from the service processor 501a, the security processor 501b does not directly process the main services of the system 30 by running preset programs, but is used for the management of the security aspects of the system 30. Specifically, the security processor 501b can be used to detect whether the system 30 is attacked by external heating. In addition, the security processor 501b can also be used to report the attack detection result to the service processor 501a, or directly take security protection measures according to the detection result of the attack on the system 30, such as running a camouflage program to confuse the attacker, forcibly shutting down the system 30, 30 forced reset or system 30 forced self-destruction, etc.
  • the security protection module 502a is used to prevent data stored in the storage module 30b from being tampered with.
  • the content in the storage module can be protected from being tampered by a data verification algorithm in the prior art or a one-time programmable (one time programmable, OTP) memory.
  • FIG. 6 shows a flowchart of the attack detection method provided by the embodiment of the present application.
  • the attack detection method includes the following steps: S601.
  • the attack detection apparatus acquires first data, wherein the first data is used to verify the second data.
  • the attack detection apparatus may acquire the first data from the on-chip memory of the first chip of the system where the attack detection apparatus is located.
  • the first chip may be a computing chip.
  • the attack detection apparatus 30a may acquire the first data from the on-chip memory 401a of the security processor 501b.
  • the activation of the attack detection method in a possible implementation manner, at least one of the first data, the data after the first data processing, or the data before the first data processing may be pre-written into the storage module 30b as the second data , and the first data is written into the on-chip memory in advance as a benchmark for verification.
  • the above activation operation may be performed after all the manufacturing processes in the high temperature environment are completed before the chip leaves the factory, for example, after the SIP and/or the module is soldered to the whole product.
  • the first data may be a random number generated randomly, or a check value of the random number, or a software code.
  • the attack detection apparatus reads the second data from the storage module.
  • the storage module is a non-power-down volatile storage device, and the data in the storage module is changed when it encounters external heating. It should be noted that this embodiment of the present application does not limit the order of execution of the above steps S601 and S602. That is, step S601 may be performed first, and then step S602 may be performed, or, step S602 may be performed first, and then step S601 may be performed, or step S601 and step S602 may be performed simultaneously.
  • the attack detection apparatus verifies the second data according to the first data to obtain a verification result.
  • the verification result indicates whether the system where the storage module is located is attacked by external heating.
  • the attack detection apparatus verifies the second data according to the first data to obtain the verification result includes: comparing the first data and the second data to obtain the comparison result as the verification result; Or, compare the first data with the fourth data obtained by processing the second data to obtain a comparison result as a verification result; or compare the second data with the third data obtained by processing the first data to obtain a verification result or, comparing the fourth data obtained by processing the second data with the third data obtained by processing the first data to obtain a comparison result as a verification result.
  • At least one of the first data, the data after the first data processing, or the data before the first data processing can be pre-written into the storage module, and the first data can be pre-written on-chip
  • the memory serves as the benchmark for verification. The following describes how the attack detection apparatus verifies the second data according to the first data to obtain the verification result with reference to several specific examples.
  • the attack detection device obtains the first data from the on-chip memory, and after reading the second data from the storage module. , the attack detection device verifies the second data according to the first data to obtain the verification result comprising: the attack detection device compares the first data and the second data to obtain a comparison result as the verification result; or, the attack detection device compares the first The check value of the data and the check value of the second data are obtained to obtain a comparison result as the check result.
  • the check value of the first data may be regarded as the third data obtained by processing the first data
  • the check value of the second data may be regarded as the fourth data obtained by processing the second data.
  • the check value of the random number is a value obtained by processing the random number using a check algorithm
  • the check algorithm may be, for example, a hash algorithm, which is not specified in this embodiment. limited.
  • a unified description is provided, and details are not repeated below.
  • the attack detection device obtains the first data from the on-chip memory, and after reading the second data from the storage module, the attack detection device verifies the second data according to the first data to obtain the verification result, which includes: the attack detection device compares the first data The check value and the second data to obtain the comparison result as the check result.
  • the check value of the first data may be regarded as the third data obtained by processing the first data.
  • the first data is a check value of a randomly generated random number
  • the first data is pre-written into the on-chip memory
  • the data before the first data processing ie the randomly generated random number
  • the attack detection device obtains the first data from the on-chip memory
  • the attack detection device verifies the second data according to the first data to obtain the verification result.
  • the check value of the second data may be regarded as the fourth data obtained by processing the second data above.
  • the first data is a software code
  • the attack detection device obtains the first data from the on-chip memory, and reads the second data from the storage module, and then attacks
  • the detection device verifying the second data according to the first data to obtain the verification result includes: attacking the detection device by comparing the operation result obtained by running the first data and the operation result obtained by running the second data to obtain the comparison result as the verification result.
  • the operation result obtained by running the first data may be regarded as the third data obtained by processing the first data
  • the operation result obtained by running the second data may be regarded as the fourth data obtained by processing the second data.
  • the comparison results indicate that the system is not attacked by external heating; if the comparison results are different, the comparison results indicate that the system is attacked by external heating.
  • the attack detection method shown in FIG. 6 is executed after the system where the attack detection device is located is powered on or when the system where the attack detection device is located needs to run a preset program to detect the attack detection device.
  • the preset program may be a sensitive program, such as a payment-related program.
  • the attack detection method may include the following step S701 as a trigger condition: S701 , the system where the attack detection apparatus is located is powered on. or, when the system where the attack detection device is located needs to run a preset program.
  • the attack detection method may further include the following steps: S702 , the attack detection apparatus determines whether the system where the storage module is located is subjected to external heating according to the verification result. attack. If "Yes”, go to step S704, if "No", go to step S703. S703, the system runs normally.
  • the system takes safety protection measures.
  • the security protection measure may be executed by, for example, a security processor or a service processor.
  • a security processor or a service processor.
  • the non-power-off volatility of the storage module and the characteristic that the data stored therein is changed when encountering external heating are utilized.
  • the attack detection device for executing the attack detection method is located is powered off, the data stored in the storage module will not be lost. If no external heating attack occurs, the data stored in the storage module will remain unchanged; Heating attack, the storage module will save the changed data.
  • the attack detection device determines whether the system where the attack detection device is located is attacked by external heating by verifying the second data read from the storage module.
  • the attack detection method can realize full-time system attack detection, that is, the attack detection method can not only detect whether the system is attacked by an attacker when powered on, but also detect whether the system is attacked by an attacker when the system is powered off. .
  • the attack detection method is aimed at external heating attacks, including the step of removing the chip package. Compared with the prior art, the attack detection method can detect the attack earlier and prevent the silicon of the chip from being directly exposed to the attacker. , thereby protecting the integrity of the chip.
  • the attack detection method can also be used in combination with the prior art to increase the time taken by the attacker to attack the chip, thereby increasing the complexity of the attack chip.
  • the system 30 includes a second chip 802 .
  • the second chip 802 includes the attack detection device 30a and the storage module 30b.
  • the system 30 further includes a first chip 801 .
  • the second chip 802 is different from the first chip 801, and the first chip 801 and the second chip 802 communicate through a communication bus.
  • the first chip 801 includes an on-chip memory 801a.
  • the on-chip memory 801a is used to store the first data.
  • the attack detection apparatus 30a configured to acquire the first data, includes: acquiring the first data from the on-chip memory 801a of the first chip 801 .
  • the first chip 801 may be a computing chip with a processor function.
  • the second chip 802 may be a sensor chip integrated in the protected system.
  • the system 30 includes a processor chip 901 and a sensor chip 902 .
  • the processor chip 901 and the sensor chip 902 communicate through a communication bus.
  • the processor chip 901 includes a security processor 901b, and the on-chip memory 801a is deployed in the security processor 901b.
  • the processor chip 901 further includes a service processor 901a, and the service processor 901a and the security processor 901b communicate through an interface.
  • the sensor chip 902 includes the attack detection device 30a and the storage module 30b.
  • the sensor chip 902 further includes a security protection module 902a.
  • the storage module 30b, the security protection module 902a and the attack detection device 30a communicate through the interface.
  • each module in FIG. 9 For the related description of each module in FIG. 9 , reference may be made to the description of the corresponding module in the embodiment shown in FIG. 5 , and details are not repeated here. Specifically, for the attack detection method performed by the attack detection device in the system shown in FIG. 8 or FIG. 9 and its technical effect, reference may be made to the attack detection method performed by the attack detection device in the system shown in FIG. 3 to FIG. The attack detection method shown in FIG. 7 ) and its technical effects will not be repeated here.
  • the system 30 includes a first chip 1001 .
  • the first chip 1001 includes an attack detection device 30a and a storage module 30b.
  • the first chip 1001 may further include an on-chip memory 1001a.
  • the on-chip memory 1001a is used to store the first data.
  • the attack detection device 30a configured to acquire the first data, includes: acquiring the first data from the on-chip memory 1001a of the first chip 1001 .
  • the first chip 1001 may be a computing chip with a processor function.
  • the schematic diagram of the architecture of the system 30 may be as shown in FIG. 11 .
  • the system 30 includes a security chip 1101 .
  • the security protection chip 1101 includes a security processor 1101a, an attack detection device 30a and a storage module 30b.
  • the on-chip memory 1001a is deployed in the secure processor 1101a.
  • the system 30 further includes a service processor 1102 .
  • the service processor 1102 and the security protection chip 1101 communicate through the interface.
  • the security protection chip 1101 further includes a security protection module 1101b.
  • the storage module 30b, the security protection module 1101b and the attack detection device 30a communicate through the interface.
  • the storage module 30b, the security protection module 1101b and the attack detection device 30a communicate with the security processor 1101a through a communication bus.
  • each module in FIG. 11 For the relevant description of each module in FIG. 11 , reference may be made to the description of the corresponding module in the embodiment shown in FIG. 5 , and details are not repeated here. Specifically, for the attack detection method performed by the attack detection device in the system shown in FIG. 10 or FIG. 11 and its technical effect, reference may be made to the attack detection method performed by the attack detection device in the system shown in FIG. 3 to FIG. The attack detection method shown in FIG. 7 ) and its technical effects will not be repeated here.
  • the attack detection apparatus 1201 includes an acquisition module 1202 and a verification module 1203 .
  • the obtaining module 1202 is used to obtain the first data
  • the first data is used to verify the second data.
  • the obtaining module 1202 is configured to read the second data from the storage module, wherein the storage module is a non-power-down volatile storage device, and the data in the storage module is changed when encountering external heating.
  • the verification module 1203 is configured to verify the second data according to the first data to obtain a verification result, where the verification result indicates whether the system where the storage module is located is attacked by external heating.
  • the acquisition module 1202 is an interface
  • the verification module 1203 includes a verification circuit, such as a logic circuit
  • the verification module 1203 includes a processor, which can run verification software.
  • the verification module 1203 is specifically configured to: compare the first data and the second data to obtain a comparison result as the verification result; or, compare the first data with the first data obtained by processing the second data four data to obtain the comparison result as the verification result; or, compare the second data with the third data obtained by processing the first data to obtain the comparison result as the verification result; or, compare the third data obtained by processing the second data The fourth data and the third data obtained by processing the first data to obtain a comparison result as a verification result.
  • the obtaining module 1202 is configured to obtain the first data from the on-chip memory of the first chip of the system, and the first chip is a computing chip.
  • the storage module is located in a first chip, or the storage module is located in a second chip in the system, and the second chip is different from the first chip.
  • the attack detection device 1201 executes the attack detection method after the system where the attack detection device 1201 is located is powered on or when the system where the attack detection device 1201 is located needs to run a preset program.
  • the memory module includes a phase change memory.
  • the attack detection apparatus 1201 provided in this embodiment may be the attack detection apparatus 30a in any of the embodiments described in FIG. 3 to FIG. 5 and FIG. 8 to FIG. 11 , so as to execute the attack detection method shown in FIG. 6 or FIG. 7 . Since the attack detection apparatus 1201 provided in this embodiment can perform the above-mentioned attack detection method, the technical effect obtained by the attack detection apparatus 1201 can refer to the above-mentioned method embodiments, and details are not repeated here.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be Incorporation may either be integrated into another device, or some features may be omitted, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, and may also be implemented at least partially in the form of software functional units.
  • a unit can be stored in a readable storage medium if it is implemented in the form of a software functional unit and sold or used as an independent product.
  • the technical solutions of the embodiments of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, which are stored in a storage medium , including several instructions to make a device (may be a single chip microcomputer, a chip, etc.) or a processor (processor) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program codes.

Abstract

本申请实施例提供攻击检测方法和装置，用于检测掉电时芯片是否受到攻击者攻击。方法包括: 获取第一数据，第一数据用于校验第二数据; 从存储模块读取第二数据，其中，存储模块是非掉电易失性存储设备，且存储模块中的数据在遇到外部加热时被改变; 根据第一数据校验第二数据以得到校验结果，校验结果指示了存储模块所在的系统是否受到外部加热攻击。

Description

攻击检测方法和装置 技术领域
本申请涉及数据安全技术领域，尤其涉及攻击检测方法和装置。
背景技术
随着信息化技术的发展，芯片的应用领域越来越广。相应地，针对芯片的攻击手段也越来越多。为此，如何检测针对芯片的攻击，成为了重要的研究课题。
现有技术中，通常采用报警电路或数据校验算法检测芯片是否受到攻击者攻击。在报警电路中，可以通过将芯片内金属层的走线设计成防护网，或者通过在硅片内部集成用于判断芯片的运行状态是否稳定的数字电路，来检测芯片是否受到攻击者攻击。在不同芯片之间的数据发送和接收过程中或者在芯片内部各模块之间的数据发送和接收过程中，还可以增加数据校验算法，通过校验数据是否正确来判断数据是否被攻击者篡改。
然而，由于报警电路的正常运行需要芯片上电，数据的收发和校验过程也需要芯片上电，因此，以上两种攻击检测方法无法检测到芯片掉电时是否受到攻击者攻击。
发明内容
本申请实施例提供攻击检测方法和装置，用于检测芯片掉电时是否受到攻击者攻击。为达到上述目的，本申请的实施例采用如下技术方案。
第一方面，提供了一种攻击检测方法，包括：获取第一数据，该第一数据用于校验第二数据；从存储模块读取该第二数据，其中，该存储模块是非掉电易失性存储设备，且该存储模块中的数据在遇到外部加热时被改变；根据该第一数据校验该第二数据以得到校验结果，该校验结果指示了该存储模块所在的系统是否受到外部加热攻击。
本申请实施例提供的攻击检测方法中，利用了存储模块的非掉电易失性，以及存储模块中存储的数据在遇到外部加热时被改变的特征。第一，在执行攻击检测方法的攻击检测装置所在的系统掉电的情况下，存储模块中存储的数据不会丢失，如果未发生外部加热攻击，存储模块中存储的数据不变；如果发生外部加热攻击，存储模块保存的数据会改变。在执行攻击检测方法的攻击检测装置所在的系统上电后，攻击检测装置通过校验从存储模块读取的第二数据来判断攻击检测装置所在的系统是否受到外部加热攻击。因此，该攻击检测方法可以实现全时段的系统攻击检测，即，该攻击检测方法不仅能检测到系统在上电时是否受到攻击者攻击，还能检测到系统在掉电时是否受到攻击者攻击。第二，该攻击检测方法针对的是外部加热攻击，包括去除芯片封装的步骤，相比于现有技术，该攻击检测方法能够更早地检测到攻击，防止芯片的硅片直接暴露给攻击者，从而保护芯片的完整度。第三，该攻击检测方法也可以与现有技术结合使用，以增加攻击者攻击芯片的耗时，从而提高攻击芯片的复杂度。
结合上述第一方面，在一种可能的实现方式中，根据该第一数据校验该第二数据以得到校验结果包括：比较该第一数据和该第二数据，以得到作为该校验结果的比较 结果；或者，比较该第一数据和处理该第二数据得到的第四数据，以得到作为该校验结果的比较结果；或者，比较该第二数据和处理该第一数据得到的第三数据，以得到作为该校验结果的比较结果；或者，比较处理该第二数据得到的第四数据和处理该第一数据得到的第三数据，以得到作为该校验结果的比较结果。通过比较第一数据和第二数据，可以直接、简单地得到校验结果；通过先对第一数据和/或第二数据进行处理再进行比较，可以间接校验第二数据的完整性，以得到校验结果。
结合上述第一方面，在一种可能的实现方式中，如果比较结果相同，则该比较结果指示了该系统未受到外部加热攻击；如果该比较结果不同，则该比较结果指示了该系统受到外部加热攻击。
结合上述第一方面，在一种可能的实现方式中，获取第一数据包括：从该系统的第一芯片的片上存储器中获取该第一数据，该第一芯片是计算芯片。
结合上述第一方面，在一种可能的实现方式中，该存储模块位于该第一芯片中，或者该存储模块位于该系统中第二芯片中，该第二芯片不同于该第一芯片。
结合上述第一方面，在一种可能的实现方式中，该方法在该存储模块所在的系统上电后或者在该系统需要运行预设程序时执行。其中，攻击检测方法的执行，可以为系统上电后的运行，或者可以为该系统运行预设程序提供安全方面的参考。
结合上述第一方面，在一种可能的实现方式中，该存储模块包括相变存储器。由于相变存储器中具有常温下存储稳定，但在遇到外部加热时其中存储的数据会发生改变的特性，并且该特性稳定，因此，包括相变存储器的存储模块可以很好地执行攻击检测方法。
第二方面，提供了一种攻击检测装置用于实现上述攻击检测方法。该攻击检测装置包括实现上述方法相应的模块、单元、或手段(means)，该模块、单元、或means可以通过硬件实现，软件实现，或者通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块或单元。
结合上述第二方面，在一种可能的实现方式中，该攻击检测装置包括：获取模块，用于获取第一数据，该第一数据用于校验第二数据；该获取模块，还用于从存储模块读取该第二数据，其中，该存储模块是非掉电易失性存储设备，且该存储模块中的数据在遇到外部加热时被改变；校验模块，用于根据该第一数据校验该第二数据以得到校验结果，该校验结果指示了该存储模块所在的系统是否受到外部加热攻击。
结合上述第二方面，在一种可能的实现方式中，该校验模块，具体用于：比较该第一数据和该第二数据，以得到作为该校验结果的比较结果；或者，比较该第一数据和处理该第二数据得到的第四数据，以得到作为该校验结果的比较结果；或者，比较该第二数据和处理该第一数据得到的第三数据，以得到作为该校验结果的比较结果；或者，比较处理该第二数据得到的第四数据和处理该第一数据得到的第三数据，以得到作为该校验结果的比较结果。
结合上述第二方面，在一种可能的实现方式中，如果该比较结果相同，则该比较结果指示了该系统未受到外部加热攻击；如果该比较结果不同，则该比较结果指示了该系统受到外部加热攻击。
结合上述第二方面，在一种可能的实现方式中，该获取模块，用于获取第一数据， 包括：该获取模块，用于从该系统的第一芯片的片上存储器中获取该第一数据，该第一芯片是计算芯片。
结合上述第二方面，在一种可能的实现方式中，该存储模块位于该第一芯片中，或者该存储模块位于该系统中第二芯片中，该第二芯片不同于该第一芯片。
结合上述第二方面，在一种可能的实现方式中，该装置在该存储模块所在的系统上电后或者在该存储模块所在的系统需要运行预设程序时执行攻击检测方法。
结合上述第二方面，在一种可能的实现方式中，该存储模块包括相变存储器。
可选地，上述获取模块是一个接口，所述校验模块包括校验电路，如逻辑电路，或者所述校验模块包括处理器，可运行校验软件。
其中，第二方面中任一种可能的实现方式所带来的技术效果可参见上述第一方面中不同实现方式所带来的技术效果，此处不再赘述。
第三方面，提供了一种系统，该系统包括如上述第二方面所述的攻击检测装置。
结合上述第三方面，在一种可能的实现方式中，该攻击检测装置包含在该系统的第一芯片中，其中，该第一芯片还包括存储该第一数据的片上存储器。
结合上述第三方面，在一种可能的实现方式中，该系统还包括不同于该第一芯片的第二芯片，其中，该第二芯片包括该存储模块。
结合上述第三方面，在一种可能的实现方式中，该第一芯片还包括该存储模块。
结合上述第三方面，在一种可能的实现方式中，该攻击检测装置包含在该系统的第二芯片中，其中，该第二芯片包括该存储模块。
结合上述第三方面，在一种可能的实现方式中，该系统还包括不同于该第二芯片的第一芯片，其中，该第一芯片包括存储该第一数据的片上存储器。
其中，第三方面中任一种可能的实现方式所带来的技术效果可参见上述第一方面中不同实现方式所带来的技术效果，此处不再赘述。
附图说明
图1为现有技术中攻击者攻击芯片的流程图；
图2a为现有技术中相变存储器的“读”、“写”和“擦”所对应的脉冲的示意图；
图2b为表示图2a所示的脉冲与不同加热条件下相变材料的晶态与非晶态之间的转化的对应关系的曲线图；
图3为本申请实施例提供的系统的架构示意图一；
图4为本申请实施例提供的系统的架构示意图二；
图5为本申请实施例提供的系统的架构示意图三；
图6为本申请实施例提供的攻击检测方法的流程图一；
图7为本申请实施例提供的攻击检测方法的流程图二；
图8为本申请实施例提供的系统的架构示意图四；
图9为本申请实施例提供的系统的架构示意图五；
图10为本申请实施例提供的系统的架构示意图六；
图11为本申请实施例提供的系统的架构示意图七；
图12为本申请实施例提供的攻击检测装置的结构示意图。
具体实施方式
为了方便理解本申请实施例的技术方案，首先给出本申请相关技术或名词的简要介绍如下。
第一，攻击者攻击芯片的步骤，如图1所示，攻击者攻击芯片时，主要采取如下步骤：第一步，去除芯片封装。例如，攻击者可以采用研磨、加热、或化学腐蚀等手段的组合去除芯片封装。第二步，实施攻击。具体地，该步骤可以包括侵入式攻击和半侵入式攻击。以上两种类型的攻击方式都需要将芯片的硅片直接暴露给攻击者，但它们的区别之处在于：半侵入式攻击不需要与硅片表面进行电接触，因此不会对硅片造成机械损伤。例如，属于半侵入式攻击的攻击手段可以为攻击者采用激光或紫外线照射芯片。相反，侵入式攻击会对硅片造成机械损伤。例如，属于侵入式攻击的攻击手段可以为攻击者切割芯片连线。需要说明的是，现有技术中采用报警电路或数据校验算法的攻击检测方法或装置主要针对的是上述第二步“实施攻击”的检测。本申请检测的是是否存在外部加热攻击。由于攻击者采用研磨、加热、或化学腐蚀等手段去除芯片封装时会产生热量，可以统称为加热攻击，因此，本申请的技术方案主要针对的是上述第一步“去除芯片封装”的检测。
第二，相变存储器，为采用相变材料制成的存储器。其中，相变材料具有明显的相变特征。相变材料具有晶态和非晶态两种形态，并且两种形态可以通过加热方式互相转化。相变材料的晶态与非晶态的电阻阻值差别很大，以相变材料为锗锑碲化合物(Ge2Sb2Te5，GST)为例，GST的晶态的电阻阻值范围可以从1K到10K欧姆，非晶态的电阻阻值可以超过1M欧姆。因此，晶态通常也可以称为低阻态，非晶态通常也可以称为高阻态。
示例性地，图2a示出了相变存储器的动作所对应的脉冲，其中，“擦”脉冲的幅度最大，并且脉冲持续时间最短；“写”脉冲的脉冲持续时间最长；“读”脉冲的幅度最小。进一步地，图2b示出了图2a所示的脉冲与不同加热条件下相变材料的晶态与非晶态之间的转化的对应关系，其中，T室内表示室内温度，简称为室温；Tc表示结晶温度，即相变材料由非晶态转化为晶态所需要达到的温度；Tm表示融化温度，即相变材料由晶态转化为非晶态所需要达到的温度；Tm的取值高于Tc的取值。下面将分别介绍相变存储器的“读”、“写”和“擦”。
相变存储器的“读”，是通过检测相变存储器的电阻阻值实现的。由于常温下检测电阻时，电流通过阻性导体会引起发热，因此，此时相变材料的温度略高于室温。
相变存储器的“写”，是通过相变材料由非晶态转化为晶态的过程实现的。具体地，相变材料的温度维持在Tc以上一段时间，就可以实现由非晶态转化为晶态。其中，相变材料的温度维持在Tc以上的一段时间可以称为结晶时间。
相变存储器的“擦”，是通过相变材料由晶态转化为非晶态的过程实现的。具体地，相变材料的温度在短时间内达到Tm，然后迅速冷却，就可以实现由晶态转化为非晶态。
由于分子结构不同，不同相变材料的结晶温度和结晶时间也不同。常见的相变材料及其结晶温度和结晶时间如表1所示。
表1
相变材料 Sb 2Te 3 GST Ge 1Sb 2Te 4
结晶温度(℃) 120 174 153
结晶时间(ns) 30 50 40
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。其中，在本申请的描述中，除非另有说明，“/”表示前后关联的对象是一种“或”的关系，例如，A/B可以表示A或B；本申请中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A，B可以是单数或者复数。并且，在本申请的描述中，除非另有说明，“多个”是指两个或多于两个。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
图3示出了本申请实施例提供的一种系统30，该系统30包括攻击检测装置30a和存储模块30b。其中，攻击检测装置30a，用于获取第一数据，第一数据用于校验第二数据。攻击检测装置30a，还用于从存储模块30b读取第二数据，并根据第一数据校验第二数据以得到校验结果，该校验结果指示了存储模块30b所在的系统30是否受到外部加热攻击。本申请实施例中，存储模块30b是非掉电易失性存储设备，并且具有其中存储的数据在常温下不变，但在遇到外部加热时会发生改变的特性。示例性的，存储模块30b可以是相变存储器。本实施例的系统30可以是一个电子系统，位于电子设备中，该电子设备科包括但不限于终端、服务器或消费类电子产品。所述终端包括但不限于手机、个人电脑、平板电脑、可穿戴设备或固定电话等。
需要说明的是，本申请实施例中，可以根据实际情况，例如焊接材料、封装材料或者加工工艺等，来选择制成相变存储器的相变材料的具体化合物成分，本申请实施例对此不作任何限定。除了相变存储器之外，存储模块30b也可以是与非门(NAND)存储器，还可以是其他具有上述遇热数据可变特性的存储器，本申请实施例对此不作任何限定。
本申请实施例中，第一数据、第一数据处理后的数据或者第一数据处理前的数据中的至少一个作为第二数据被预先写入存储模块30b中。当对系统30进行攻击检测时，需要校验存储模块30b中存储的数据是否发生改变，即需要根据第一数据校验从存储模块30b读取的第二数据。通过校验存储模块30b中存储的第二数据是否发生改变，能够推导出系统30是否受到外部加热攻击。原因如下具体介绍。
由于通常相变材料的结晶温度大约在100℃至250℃的范围内，远高于系统30正常工作时的温度，其中，“正常工作”是指系统30上电后工作且未受到外部加热攻击，此时系统30的温度略高于室温，因此，在系统30正常工作或下电时，仅能实现“读” 存储模块30b中存储的数据，也就是说，存储模块30b中存储的数据不会发生改变。然而，当系统30在上电或下电的状态下受到外部加热攻击时，产生的热量使得系统30的温度接近甚至超过相变材料的结晶温度，存储模块30b中存储的数据被“擦”和/或“写”，也就是说，存储模块30b中存储的数据会发生改变。综上，当对系统30进行攻击检测时，如果存储模块30b中存储的数据未发生改变，则可以推导出上一次攻击检测到本次攻击检测之间的时间段内，存储模块30b所在的系统30未受到外部加热攻击；如果存储模块30b中存储的数据发生改变，则可以推导出上一次攻击检测到本次攻击检测之间的时间段内，存储模块30b所在的系统30受到了外部加热攻击。示例性地，本申请实施例提供的系统30可以为集成在一个封装内部的系统(system in package，SIP)类型的一个或多个集成电路，本申请实施例对此不做具体限定。
需要说明的是，结合图3可知，本申请实施例中，攻击检测装置30a和存储模块30b均部署在系统30内，因此本申请实施例中的“存储模块所在的系统”与下述实施例中的“攻击检测装置所在的系统”含义等同，可以相互替换，在此统一说明，以下不再赘述。
可选的，本申请实施例提供的系统30可能具体包括一个或多个芯片。结合图3，一种可能的实现方式中，如图4所示，系统30包括第一芯片401和第二芯片402。其中，第二芯片402不同于第一芯片401，并且第一芯片401和第二芯片402通过通信总线进行通信。具体地，如图4所示，第一芯片401包括攻击检测装置30a，第二芯片402包括存储模块30b。可选的，本申请实施例中，第一芯片401可以是具有处理器功能的计算芯片。可选的，本申请实施例中，第二芯片402可以是集成在被保护的系统中的传感器芯片。
可选的，如图4所示，第一芯片401还可以包括片上存储器401a。片上存储器401a用于存储第一数据。攻击检测装置30a，用于从第一芯片401的片上存储器401a中获取第一数据。其中，片上存储器401a具有非掉电易失性。也就是说，第一芯片401掉电后，第一芯片401的片上存储器401a中存储的第一数据不会丢失。可选地，片上存储器401a包括一次性可编程存储器。
示例性的，结合图4，以第一芯片401为处理器芯片501，第二芯片402为传感器芯片502为例，系统30的架构示意图可以如图5所示。参照图5，系统30包括处理器芯片501和传感器芯片502。处理器芯片501和传感器芯片502通过通信总线进行通信。其中，处理器芯片501包括安全处理器501b，片上存储器401a和攻击检测装置30a部署在安全处理器501b中。可选的，处理器芯片501还包括业务处理器501a，业务处理器501a和安全处理器501b通过接口进行通信。可选地，业务处理器501a可运行操作系统或应用程序。可选地，业务处理器501a可控制处理器芯片501的开启或关闭。传感器芯片502包括存储模块30b。可选的，传感器芯片502还包括安全防护模块502a。存储模块30b和安全防护模块502a通过接口进行通信。
片上存储器401a、攻击检测装置30a和存储模块30b的功能描述可参考上述实施例，在此不再赘述。下面对业务处理器501a、安全处理器501b和安全防护模块502a的功能进行阐述。
其中，业务处理器501a用于通过运行预设程序来处理系统30的主要业务。在本 申请实施例中，业务处理器501a运行预设程序时可以参考安全处理器501b上报的攻击检测结果。示例性地，当安全处理器501b上报的攻击检测结果为系统30受到攻击时，业务处理器501a停止运行预设程序，例如预设应用程序。
安全处理器501b可以是具有安全防护措施的处理器。区别于业务处理器501a，安全处理器501b不直接通过运行预设程序来处理系统30的主要业务，而是用于系统30的安全方面的管理。具体地，安全处理器501b可以用于检测系统30是否受到外部加热攻击。此外，安全处理器501b还可以用于将攻击检测结果上报至业务处理器501a，或者根据系统30受到攻击的检测结果直接采取安全防护措施，例如运行伪装程序迷惑攻击者、系统30强制关机、系统30强制复位或者系统30强制自毁等。
安全防护模块502a用于防止存储模块30b中存储的数据被篡改。示例性地，可以通过现有技术中的数据校验算法或者一次性可编程(one time programmable，OTP)存储器来保护存储模块中的内容不被篡改。
结合图3、图4或图5所示的系统中的攻击检测装置，图6示出了本申请实施例提供的攻击检测方法的流程图。该攻击检测方法包括如下步骤：S601、攻击检测装置获取第一数据，其中，第一数据用于校验第二数据。可选的，在本申请的实施例中，攻击检测装置可以从攻击检测装置所在系统的第一芯片的片上存储器中获取第一数据。其中，第一芯片可以是计算芯片。比如，结合图5，攻击检测装置30a可以从安全处理器501b的片上存储器401a中获取第一数据。
作为攻击检测方法的激活，一种可能的实现方式中，可以将第一数据、第一数据处理后的数据或者第一数据处理前的数据中的至少一个作为第二数据预先写入存储模块30b，并且将第一数据预先写入片上存储器作为校验的基准。示例性地，以上激活操作可以在芯片出厂前所有高温环境的制造环节结束后进行，例如在SIP和/或模块焊接到产品整机之后进行。示例性地，本申请实施例中，第一数据可以是随机生成的随机数，或者随机数的校验值，或者软件代码。
S602、攻击检测装置从存储模块读取第二数据。其中，存储模块是非掉电易失性存储设备，且存储模块中的数据在遇到外部加热时被改变。需要说明的是，本申请实施例不限定以上步骤S601和步骤S602执行的先后顺序。也就是说，可以先执行步骤S601，后执行步骤S602，或者，先执行步骤S602，后执行步骤S601，或者，同时执行步骤S601和步骤S602。
S603、攻击检测装置根据第一数据校验第二数据以得到校验结果。该校验结果指示了存储模块所在的系统是否受到外部加热攻击。可选的，在本申请的实施例中，攻击检测装置根据第一数据校验第二数据以得到校验结果包括：比较第一数据和第二数据，以得到作为校验结果的比较结果；或者，比较第一数据和处理第二数据得到的第四数据，以得到作为校验结果的比较结果；或者，比较第二数据和处理第一数据得到的第三数据，以得到作为校验结果的比较结果；或者，比较处理第二数据得到的第四数据和处理第一数据得到的第三数据，以得到作为校验结果的比较结果。
如上所述，本申请实施例中，可以将第一数据、第一数据处理后的数据或者第一数据处理前的数据中的至少一个预先写入存储模块，并且将第一数据预先写入片上存储器作为校验的基准。下面结合几个具体示例说明攻击检测装置如何根据第一数据校 验第二数据以得到校验结果。
示例性的，假设第一数据是随机生成的随机数，第一数据被预先写入存储模块和片上存储器，则攻击检测装置从片上存储器获取第一数据，以及从存储模块读取第二数据之后，攻击检测装置根据第一数据校验第二数据以得到校验结果包括：攻击检测装置比较第一数据和第二数据，以得到作为校验结果的比较结果；或者，攻击检测装置比较第一数据的校验值和第二数据的校验值，以得到作为校验结果的比较结果。其中，该示例中，第一数据的校验值可以视为上述处理第一数据得到的第三数据，第二数据的校验值可以视为上述处理第二数据得到的第四数据。需要说明的是，本申请实施例中，随机数的校验值是采用校验算法对随机数进行处理后得到的数值，校验算法例如可以为哈希算法，本实施例对此不做具体限定。在此统一说明，以下不再赘述。
或者，示例性的，假设第一数据是随机生成的随机数，第一数据被预先写入片上存储器，第一数据处理后的数据(即第一数据的校验值)被预先写入存储模块，则攻击检测装置从片上存储器获取第一数据，以及从存储模块读取第二数据之后，攻击检测装置根据第一数据校验第二数据以得到校验结果包括：攻击检测装置比较第一数据的校验值和第二数据，以得到作为校验结果的比较结果。其中，该示例中，第一数据的校验值可以视为上述处理第一数据得到的第三数据。
或者，示例性的，第一数据是随机生成的随机数的校验值，第一数据被预先写入片上存储器；第一数据处理前的数据(即该随机生成的随机数)被预先写入存储模块，则攻击检测装置从片上存储器获取第一数据，以及从存储模块读取第二数据之后，攻击检测装置根据第一数据校验第二数据以得到校验结果包括：攻击检测装置比较第一数据和第二数据的校验值，以得到作为校验结果的比较结果。其中，该示例中，第二数据的校验值可以视为上述处理第二数据得到的第四数据。
或者，示例性的，第一数据是软件代码，第一数据被预先写入存储模块和片上存储器，则攻击检测装置从片上存储器获取第一数据，以及从存储模块读取第二数据之后，攻击检测装置根据第一数据校验第二数据以得到校验结果包括：攻击检测装置比较运行第一数据得到的运行结果和运行第二数据得到的运行结果，以得到作为校验结果的比较结果。其中，该示例中，运行第一数据得到的运行结果可以视为上述处理第一数据得到的第三数据，运行第二数据得到的运行结果可以视为上述处理第二数据得到的第四数据。
可选的，在本申请实施例中，如果比较结果相同，则比较结果指示了系统未受到外部加热攻击；如果比较结果不同，则比较结果指示了系统受到外部加热攻击。
可选的，在本申请实施例中，图6所示的攻击检测方法在攻击检测装置所在的系统上电后或者在攻击检测装置所在的系统需要运行预设程序时执行，以检测攻击检测装置所在的系统上电前的掉电过程中该系统是否受到加热攻击，或者为攻击检测装置所在的系统运行预设程序提供安全方面的参考。示例性地，预设程序可以为敏感程序，例如与付款相关的程序。
可选的，在本申请实施例中，如图7所示，执行图6所示的攻击检测方法之前，攻击检测方法可以包括如下步骤S701作为触发条件：S701、攻击检测装置所在的系统上电后，或者，攻击检测装置所在的系统需要运行预设程序时。可选的，在本申请实 施例中，执行图6所示的攻击检测方法之后，攻击检测方法还可以包括如下步骤：S702、攻击检测装置根据校验结果确定存储模块所在的系统是否受到外部加热攻击。如果“是”，则执行步骤S704，如果“否”，则执行步骤S703。S703、系统正常运行。S704、系统采取安全防护措施。可选的，在本申请的实施例中，安全防护措施可以例如由安全处理器或者业务处理器执行。具体的安全防护措施可参考图5所述的安全处理器501b或者业务处理器501a的描述，在此不再赘述。
本申请实施例提供的攻击检测方法中，利用了存储模块的非掉电易失性，以及其中存储的数据在遇到外部加热时被改变的特征。第一，在执行攻击检测方法的攻击检测装置所在的系统掉电的情况下，存储模块中存储的数据不会丢失，如果未发生外部加热攻击，存储模块中存储的数据不变；如果发生外部加热攻击，存储模块会保存改变后的数据。在执行攻击检测方法的攻击检测装置所在的系统上电后，攻击检测装置通过校验从存储模块读取的第二数据来判断攻击检测装置所在的系统是否受到外部加热攻击。因此，该攻击检测方法可以实现全时段的系统攻击检测，即，该攻击检测方法不仅能检测到系统在上电时是否受到攻击者攻击，还能检测到系统在掉电时是否受到攻击者攻击。第二，该攻击检测方法针对的是外部加热攻击，包括去除芯片封装的步骤，相比于现有技术，该攻击检测方法能够更早地检测到攻击，防止芯片的硅片直接暴露给攻击者，从而保护芯片的完整度。第三，该攻击检测方法也可以与现有技术结合使用，以增加攻击者攻击芯片的耗时，从而提高攻击芯片的复杂度。
结合图3，另一种可能的实现方式中，如图8所示，系统30包括第二芯片802。其中，第二芯片802包括攻击检测装置30a和存储模块30b。可选的，如图8所示，系统30还包括第一芯片801。第二芯片802不同于第一芯片801，并且第一芯片801和第二芯片802通过通信总线进行通信。具体地，如图8所示，第一芯片801包括片上存储器801a。片上存储器801a用于存储第一数据。攻击检测装置30a，用于获取第一数据，包括：从第一芯片801的片上存储器801a中获取第一数据。其中，片上存储器801a的相关描述可参考图4所述的实施例中片上存储器401a的描述，在此不再赘述。可选的，本申请实施例中，第一芯片801可以是具有处理器功能的计算芯片。可选的，本申请实施例中，第二芯片802可以是集成在被保护的系统中的传感器芯片。
示例性的，结合图8，以第一芯片801为处理器芯片901，第二芯片802为传感器芯片902为例，系统30的架构示意图可以如图9所示。参照图9，系统30包括处理器芯片901和传感器芯片902。处理器芯片901和传感器芯片902通过通信总线进行通信。其中，处理器芯片901包括安全处理器901b，片上存储器801a部署在安全处理器901b中。可选的，处理器芯片901还包括业务处理器901a，业务处理器901a和安全处理器901b通过接口进行通信。传感器芯片902包括攻击检测装置30a和存储模块30b。可选的，传感器芯片902还包括安全防护模块902a。存储模块30b、安全防护模块902a和攻击检测装置30a通过接口进行通信。
图9中各模块的相关描述可参考图5所述的实施例中对应模块的描述，在此不再赘述。具体地，图8或图9所示的系统中攻击检测装置执行的攻击检测方法及其技术效果可参考图3-图5所示的系统中攻击检测装置执行的攻击检测方法(即图6或图7所述的攻击检测方法)及其技术效果，在此不再赘述。
结合图3，又一种可能的实现方式中，如图10所示，系统30包括第一芯片1001。其中，第一芯片1001包括攻击检测装置30a和存储模块30b。可选的，如图10所示，第一芯片1001还可以包括片上存储器1001a。片上存储器1001a用于存储第一数据。攻击检测装置30a，用于获取第一数据，包括：从第一芯片1001的片上存储器1001a中获取第一数据。其中，片上存储器1001a的相关描述可参考图4所述的实施例中片上存储器401a的描述，在此不再赘述。可选的，本申请实施例中，第一芯片1001可以是具有处理器功能的计算芯片。
示例性的，结合图10，以第一芯片1001为安全防护芯片1101为例，系统30的架构示意图可以如图11所示。参照图11，系统30包括安全防护芯片1101。其中，安全防护芯片1101包括安全处理器1101a、攻击检测装置30a和存储模块30b。其中，片上存储器1001a部署在安全处理器1101a中。可选的，系统30还包括业务处理器1102。业务处理器1102和安全防护芯片1101通过接口进行通信。可选的，安全防护芯片1101还包括安全防护模块1101b。存储模块30b、安全防护模块1101b和攻击检测装置30a通过接口进行通信。存储模块30b、安全防护模块1101b和攻击检测装置30a通过通信总线与安全处理器1101a进行通信。
图11中各模块的相关描述可参考图5所述的实施例中对应模块的描述，在此不再赘述。具体地，图10或图11所示的系统中攻击检测装置执行的攻击检测方法及其技术效果可参考图3-图5所示的系统中攻击检测装置执行的攻击检测方法(即图6或图7所述的攻击检测方法)及其技术效果，在此不再赘述。
本申请实施例还提供一种攻击检测装置以实现上述攻击检测方法。如图12所示，该攻击检测装置1201包括获取模块1202和检验模块1203。其中：获取模块1202，用于获取第一数据，第一数据用于校验第二数据。获取模块1202，用于从存储模块读取第二数据，其中，存储模块是非掉电易失性存储设备，且存储模块中的数据在遇到外部加热时被改变。检验模块1203，用于根据第一数据校验第二数据以得到校验结果，校验结果指示了存储模块所在的系统是否受到外部加热攻击。可选地，上述获取模块1202是一个接口，所述校验模块1203包括校验电路，如逻辑电路，或者所述校验模块1203包括处理器，可运行校验软件。
在一种可能的实现方式中，检验模块1203，具体用于：比较第一数据和第二数据，以得到作为校验结果的比较结果；或者，比较第一数据和处理第二数据得到的第四数据，以得到作为校验结果的比较结果；或者，比较第二数据和处理第一数据得到的第三数据，以得到作为校验结果的比较结果；或者，比较处理第二数据得到的第四数据和处理第一数据得到的第三数据，以得到作为校验结果的比较结果。
在一种可能的实现方式中，如果比较结果相同，则比较结果指示了系统未受到外部加热攻击；如果比较结果不同，则比较结果指示了系统受到外部加热攻击。在一种可能的实现方式中，获取模块1202，用于从系统的第一芯片的片上存储器中获取第一数据，第一芯片是计算芯片。在一种可能的实现方式中，存储模块位于第一芯片中，或者存储模块位于系统中第二芯片中，第二芯片不同于第一芯片。在一种可能的实现方式中，攻击检测装置1201在攻击检测装置1201所在的系统上电后或者在攻击检测装置1201所在的系统需要运行预设程序时执行攻击检测方法。在一种可能的实现方式 中，存储模块包括相变存储器。
本实施例提供的攻击检测装置1201可以为图3至图5、图8至图11任一个所述的实施例中的攻击检测装置30a，以执行图6或图7所示的攻击检测方法。由于本实施例提供的攻击检测装置1201可执行上述攻击检测方法，因此其所能获得的技术效果可参考上述方法实施例，在此不再赘述。
通过以上实施例的描述，所属领域的技术人员可以了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以至少部分采用软件功能单元的形式实现。一个单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该软件产品存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上内容，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种攻击检测方法，其特征在于，包括：
    获取第一数据，所述第一数据用于校验第二数据；
    从存储模块读取所述第二数据，其中，所述存储模块是非掉电易失性存储设备，且所述存储模块中的数据在遇到外部加热时被改变；
    根据所述第一数据校验所述第二数据以得到校验结果，所述校验结果指示了所述存储模块所在的系统是否受到外部加热攻击。
  2. 根据权利要求1所述的攻击检测方法，其特征在于，所述根据所述第一数据校验所述第二数据以得到校验结果包括：
    比较所述第一数据和所述第二数据，以得到作为所述校验结果的比较结果；或者，
    比较所述第一数据和处理所述第二数据得到的第四数据，以得到作为所述校验结果的比较结果；或者，
    比较所述第二数据和处理所述第一数据得到的第三数据，以得到作为所述校验结果的比较结果；或者，
    比较处理所述第二数据得到的第四数据和处理所述第一数据得到的第三数据，以得到作为所述校验结果的比较结果。
  3. 根据权利要求2所述的攻击检测方法，其特征在于，
    如果所述比较结果相同，则所述比较结果指示了所述系统未受到外部加热攻击；
    如果所述比较结果不同，则所述比较结果指示了所述系统受到外部加热攻击。
  4. 根据权利要求1-3中任一项所述的攻击检测方法，其特征在于，所述获取第一数据包括：从所述系统的第一芯片的片上存储器中获取所述第一数据，所述第一芯片是计算芯片。
  5. 根据权利要求4所述的攻击检测方法，其特征在于，所述存储模块位于所述第一芯片中，或者所述存储模块位于所述系统中第二芯片中，所述第二芯片不同于所述第一芯片。
  6. 根据权利要求1-5任一项所述的攻击检测方法，其特征在于，所述方法在所述存储模块所在的系统上电后或者在所述系统需要运行预设程序时执行。
  7. 根据权利要求1-6中任一项所述的攻击检测方法，其特征在于，所述存储模块包括相变存储器。
  8. 一种攻击检测装置，其特征在于，包括：
    获取模块，用于获取第一数据，所述第一数据用于校验第二数据；以及从存储模块读取所述第二数据，其中，所述存储模块是非掉电易失性存储设备，且所述存储模块中的数据在遇到外部加热时被改变；
    校验模块，用于根据所述第一数据校验所述第二数据以得到校验结果，所述校验结果指示了所述存储模块所在的系统是否受到外部加热攻击。
  9. 根据权利要求8所述的攻击检测装置，其特征在于，所述校验模块，具体用于：
    比较所述第一数据和所述第二数据，以得到作为所述校验结果的比较结果；或者，
    比较所述第一数据和处理所述第二数据得到的第四数据，以得到作为所述校验结果的比较结果；或者，
    比较所述第二数据和处理所述第一数据得到的第三数据，以得到作为所述校验结果的比较结果；或者，
    比较处理所述第二数据得到的第四数据和处理所述第一数据得到的第三数据，以得到作为所述校验结果的比较结果。
  10. 根据权利要求9所述的攻击检测装置，其特征在于，
    如果所述比较结果相同，则所述比较结果指示了所述系统未受到外部加热攻击；
    如果所述比较结果不同，则所述比较结果指示了所述系统受到外部加热攻击。
  11. 根据权利要求8-10中任一项所述的攻击检测装置，其特征在于，所述获取模块，具体用于从所述系统的第一芯片的片上存储器中获取所述第一数据，所述第一芯片是计算芯片。
  12. 根据权利要求11所述的攻击检测装置，其特征在于，所述存储模块位于所述第一芯片中，或者所述存储模块位于所述系统中第二芯片中，所述第二芯片不同于所述第一芯片。
  13. 根据权利要求11或12所述的攻击检测装置，其特征在于，所述装置在所述存储模块所在的系统上电后或者在所述存储模块所在的系统需要运行预设程序时执行攻击检测方法。
  14. 根据权利要求8-13中任一项所述的攻击检测装置，其特征在于，所述存储模块包括相变存储器。
  15. 一种系统，其特征在于，所述系统包括如权利要求8-14任一项所述的攻击检测装置。
  16. 根据权利要求15所述的系统，其特征在于，所述攻击检测装置包含在所述系统的第一芯片中，其中，所述第一芯片还包括存储所述第一数据的片上存储器。
  17. 根据权利要求16所述的系统，其特征在于，所述系统还包括不同于所述第一芯片的第二芯片，其中，所述第二芯片包括所述存储模块。
  18. 根据权利要求16所述的系统，其特征在于，所述第一芯片还包括所述存储模块。
  19. 根据权利要求15所述的系统，其特征在于，所述攻击检测装置包含在所述系统的第二芯片中，其中，所述第二芯片包括所述存储模块。
  20. 根据权利要求19所述的系统，其特征在于，所述系统还包括不同于所述第二芯片的第一芯片，其中，所述第一芯片包括存储所述第一数据的片上存储器。
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