WO2022179532A1

WO2022179532A1 - Auxiliary winding measurement method and circuit

Info

Publication number: WO2022179532A1
Application number: PCT/CN2022/077503
Authority: WO
Inventors: 於昌虎; 曾正球; 赵志伟
Original assignee: 深圳南云微电子有限公司
Priority date: 2021-02-26
Filing date: 2022-02-23
Publication date: 2022-09-01
Also published as: CN112769340A; CN112769340B

Abstract

The present invention provides an auxiliary winding measurement method and circuit. The measurement method and circuit are based on existing circuit elements, do not need extra cost, and enable auxiliary winding clamping topology to be more practical. The method specifically comprises: clamping a measurement pin to a power supply voltage in an excitation stage, so that the current flowing into the measurement pin is proportional to an input voltage, and the accurate measurement of the input voltage is achieved; making a voltage difference between the power supply voltage and the voltage of the measurement pin fall onto one internal resistor at a demagnetization stage, then transferring the current flowing through the resistor to another internal resistor, and using a sampling and holding circuit to sample and store the voltage of the other internal resistor, thereby achieving the accurate measurement of an output voltage; and comparing the voltage of the measurement pin with the voltage of a power supply pin, thereby achieving the measurement of a voltage resonance period of a drain electrode of a main switch tube. Input under-voltage protection, input feedforward, ZVS detection, and the like can be achieved according to the input voltage; output overvoltage protection and primary-side feedback can be achieved according to the output voltage; and quasi-resonance control and the like can be achieved according to the resonance period measurement.

Description

A kind of auxiliary winding detection method and circuit

technical field

The invention belongs to the field of soft-switching flyback converters, in particular to auxiliary winding voltage detection.

Background technique

Active clamp flyback converter is a power converter topology that can realize soft switching of power tubes. Reasonably design the inductance of the transformer excitation inductance, so that the conduction process of the clamp tube continues until there is enough negative excitation current, and then turns off. Zero-voltage turn-on (ZVS, Zero-Voltage-Switch) of the switch. In this way, the turn-on loss of the main switch tube can be eliminated, the overall efficiency of the converter can be improved, and the development of high frequency and high power density of the converter is facilitated.

As shown in Figure 1, it is the circuit diagram of a typical active clamp flyback converter. In the figure, 101 is the clamping capacitor, 102 (LK) is the leakage inductance, 103 is the power transformer, 104 (LM) is the excitation inductance, 105 (MA) is the clamping tube, 106 is the main control chip, and 107 is the half-bridge driver Chip, 108 (MP) is the main switch tube, 109 is the excitation inductor current sampling resistor, 110 is the power supply auxiliary winding of the main control chip, 111 is the rectifier diode that supplies power to the main control chip, 112 is the power supply capacitor of the main control chip, 113 is The rectifier diode for the power supply of the half-bridge driver chip, 114 is the power supply capacitor of the half-bridge driver chip, 115 (R1) is the upper voltage dividing resistor of the auxiliary winding detection circuit, 116 (R2) is the lower voltage dividing resistor of the detection circuit, and VDD is the main The power supply pin of the control chip, FA is the detection pin of the main control chip, 117 is the secondary side rectifier diode, and 118 is the output filter capacitor. As shown in Figure 2, it is a schematic diagram of the key signal waveform of a typical non-complementary mode active clamp flyback converter. Among them, GL is the gate driving voltage waveform of the main switch, GH is the gate driving voltage waveform of the clamping tube, VDS is the drain voltage waveform of the main switch, I _LM is the excitation inductor current waveform, and I _LK is the leakage inductance current. waveform.

With reference to Figure 1 and Figure 2, to understand the working principle of the non-complementary active clamp flyback converter, the clamp tube MA is briefly turned on at the end of the resonant phase of degaussing, and the drive signal GH becomes high (time T1 in Figure 2). ), based on the circuit topology of Figure 1, the excitation inductor LM realizes negative excitation, that is, the inductor current I _LM is a negative current, and the slope of the current is the difference between the voltage saved on the clamping capacitor 101 minus the input voltage divided by the excitation inductance The inductance of LM; the clamp tube MA is turned on for a period of time until it is turned off at T2 in Figure 2. Since the current of the excitation inductance LM cannot be abruptly changed, the negative current will discharge the charge on the drain of the main switch tube MP. , that is, the voltage VDS becomes close to 0V, the current of the excitation inductance LM gradually increases, and the slope is the input voltage divided by the inductance of the excitation inductance LM; time, turn on the main switch tube of the next cycle (time T3 in Figure 2), at this time, the main switch tube MP realizes zero-voltage turn-on, eliminating the turn-on loss; after a period of time, the excitation inductor LM is excited in the forward direction When the current reaches the current limiting point of the entire converter control loop (time T4 in Figure 2), the main switch tube MP is turned off to realize PWM control. According to the aforementioned functions, in addition to the main control chip, a high-voltage side half-bridge driver chip is also required to raise the driving level of the clamping tube MA to the voltage of VDS to realize the effective driving of the clamping tube MA, and the clamping tube MA can be effectively driven. The maximum working voltage of the drain-source of MA is the input voltage plus the reflected voltage of the secondary side of the converter. Therefore, the clamp tube MA needs to use a transistor with high withstand voltage, which is costly.

In view of the cost of active clamping, an auxiliary winding clamping technique is proposed, as shown in Fig. 3, which is the topology of the auxiliary winding clamping flyback converter. Replace the active clamp branch in Figure 1 with a traditional RCD clamp, that is, the clamp capacitor 301, the bleeder resistor 302, and the clamp diode 303 in Figure 3, and the clamp tube MA is connected in series to the main control In the auxiliary winding of the chip power supply. Specifically, the clamping tube MA is connected to the low-voltage side of the auxiliary winding in series, so that the source of the clamping tube MA is the reference ground, which greatly simplifies the design of the driving circuit; and the maximum working voltage of the clamping tube MA becomes The input voltage is divided by the turns ratio (NP/NA) of the primary and auxiliary windings of the transformer, so that low-cost, low-voltage transistors can be used. The working sequence of the clamp tube MA and the main switch tube MP can still refer to Fig. 2. After the degaussing of the excitation inductance, the clamp tube MA is turned on briefly, so that the power supply capacitor 308 of the auxiliary winding is briefly discharged. According to the terminal of the same name, the excitation inductance LM realizes the negative to excitation. Similar to the active clamp, as long as the negative current of the excitation inductor LM is sufficient, the zero-voltage turn-on of the main switch tube MP in the next cycle can be realized.

The auxiliary winding clamping method in Figure 3 will not affect the normal power supply of the main control chip, but it will bring difficulties to the detection of important parameters: in Figure 1, the rectifier diode 111 of the auxiliary winding power supply circuit is on the high voltage side of the auxiliary winding. The voltage dividing

resistors

115 and 116 of the detection circuit take the ground as the reference potential. When the input voltage VIN is detected in the excitation phase, the anode voltage of the rectifier diode is

Simply clamp the 115/116 divider point, the FA pin, to 0V to convert the input voltage to a current proportional to VIN

When the output voltage is detected in the degaussing stage, the FA pin voltage is

When detecting the resonance period in the VDS resonance stage, it is only necessary to detect the time when the voltage of the FA pin crosses zero; in Figure 3, the clamping tube MA is connected in series to the low-voltage side of the auxiliary winding to block the DC path to the ground, so, The detection of the above-mentioned three important parameters cannot take the ground as the reference potential. How to accurately detect the three important parameters has become an important problem in the use of the auxiliary winding clamp topology.

SUMMARY OF THE INVENTION

In view of the fact that there is no simple and practical detection circuit for input voltage, output voltage and resonance period in the auxiliary winding clamping topology, the purpose of the present invention is to provide an accurate and novel detection method of input voltage, output voltage and resonance period and The circuit, the detection method and the circuit are based on the existing circuit components, and can realize the detection of the above-mentioned parameters without additional cost, making the auxiliary winding clamping topology more practical. The detection based on the input voltage can realize the functions of input undervoltage protection, input feedforward, ZVS detection, etc.; based on the output voltage detection, it can realize the functions of output overvoltage protection and primary side feedback; based on the detection of the resonance period, it can realize the functions of quasi-resonant control and so on.

The detection method provided by the invention is realized by the following scheme:

An auxiliary winding detection method, which is used for the auxiliary winding to clamp a flyback converter, and the auxiliary winding in the auxiliary winding clamped flyback converter is controlled by a main control chip. The resistor 403 and the lower voltage dividing resistor 404 are connected in series to form a two-terminal network. It is connected to the pin VDD of the main control chip, and the other end of the lower voltage dividing resistor 404 is connected to the end of the same name of the auxiliary winding 311;

The method controls the main control chip to detect the pin FA and its pin VDD voltage, so that the value ratio of the measured parameter falls on the detection end of the corresponding detection circuit;

The method specifically includes an input voltage detection step, the detection circuit involved in this step is an input voltage detection circuit, the circuit is connected between the detection pin FA and the pin VDD of the main control chip, and in the transformer excitation stage, it clamps the main control chip. The control chip detects the voltage of the pin FA to the voltage value of its pin VDD, so that the input voltage is proportional to the detection end of the input voltage detection circuit.

As another specific embodiment of the detection method, the method further includes an output voltage detection step, the detection circuit involved in this step is an output voltage detection circuit, and the circuit is also connected to the detection pin FA and the pin of the main control chip. Between VDD, in the degaussing stage of the transformer, the voltage difference between the main control chip detection pin FA voltage and its pin VDD voltage falls on a resistor, the voltage difference is the proportional value of the output voltage, and then transmitted to the output voltage detection circuit detection terminal.

Preferably, the method further includes a resonant cycle detection step, the detection circuit involved in this step is a resonant cycle detection circuit, and the circuit is also connected between the detection pin FA and the pin VDD of the main control chip. The control chip detects the voltage of the main control chip's detection pin FA and its pin VDD, compares the magnitudes of the two, and obtains the resonant period of the drain voltage of the main switch tube of the auxiliary winding clamped flyback converter.

The invention also provides an auxiliary winding detection circuit, which is used for the auxiliary winding clamped flyback converter, and the auxiliary winding clamped flyback converter realizes operation through the main control chip, including an upper voltage dividing resistor, a lower voltage dividing resistor and an input voltage In the detection circuit, one end of the upper voltage divider resistor is connected to the other end of the auxiliary winding, the other end of the upper voltage divider resistor is connected to one end of the lower voltage divider resistor, the other end of the lower voltage divider resistor is connected to the same name terminal of the auxiliary winding, and one end of the upper voltage divider resistor is connected to the input voltage detection circuit One end is connected to the main control chip pin VDD, the other end of the upper voltage divider resistor and the other end of the input voltage detection circuit are connected to the main control chip detection pin FA, and the input voltage detection circuit is used to control the main control chip detection pin FA and its pin VDD voltage, so that the value ratio of the input voltage of the measured parameter falls on the detection end of the input voltage detection circuit, specifically, it is used to clamp the voltage of the detection pin FA of the main control chip to the voltage of the main control chip pin VDD during the transformer excitation stage , so that the ratio of the input voltage value falls on the lower voltage divider resistor.

As a specific implementation of the input voltage detection circuit, it includes a power input amplifier 407, a PMOS transistor 408, a PMOS transistor 410, an NMOS transistor 409, an NMOS transistor 411 and an NMOS transistor 412, and the negative input terminal of the power input amplifier 407 and the PMOS transistor. The source of 410 is connected to the detection pin FA of the main control chip, the positive input terminal of the power input amplifier 407 and the source of the PMOS transistor 408 are connected to the main control chip pin VDD, and the output terminal of the power input amplifier 407 is connected to the gate of the PMOS transistor 410 and the gate of the PMOS transistor 408, the drain of the PMOS transistor 408 is connected to its gate and the drain of the NMOS transistor 409, the gate of the NMOS transistor 409 is connected to the drain of the NMOS transistor 411 and the drain of the PMOS transistor 410, the NMOS transistor The gate of 411 is shorted to its drain and connected to the gate of NMOS transistor 412. The sources of NMOS transistor 409, NMOS transistor 411 and NMOS transistor 412 are all grounded, and the drain of NMOS transistor 412 is the detection terminal of the input voltage detection circuit.

According to the detection method, the auxiliary winding detection circuit further includes an output voltage detection circuit; the output voltage detection circuit is used to control the main control chip to detect the voltage of the pin FA and its pin VDD, so that the value ratio of the output voltage of the measured parameter falls within The detection terminal of the output voltage detection circuit is specifically used to control the voltage difference between the detection pin FA voltage of the main control chip and its pin VDD voltage to fall on a resistor in the transformer degaussing stage, and the voltage difference is the ratio of the output voltage The value is then transmitted to the detection terminal of the output voltage detection circuit.

As an embodiment of the output voltage detection circuit, it includes a power input amplifier 413, a resistor 414, a PMOS transistor 415, a resistor 416, a sampling switch 417 and a holding capacitor 418. The positive input terminal of the power input amplifier 413 is connected to the detection lead of the main control chip. Pin FA, its negative input terminal is connected to one end of the resistor 414 and the source of the PMOS tube 415, its output terminal is connected to the gate of the PMOS tube 415, the other end of the resistor 414 is connected to the main control chip pin VDD, and the drain of the PMOS tube 415 The pole is connected to one end of the resistor 416 and one end of the sampling switch 417, the other end of the sampling switch 417 is connected to the upper plate of the holding capacitor 418, the other end of the resistor 416 and the lower plate of the holding capacitor 418 are grounded, and the upper plate of the holding capacitor 418 It is the detection terminal of the output voltage detection circuit.

Preferably, the detection circuit further includes a resonance period detection circuit, one end of the resonance period detection circuit is connected to the detection pin FA of the main control chip, and the other end of the resonance period detection circuit is connected to the main control chip pin VDD for detecting the detection lead of the main control chip. Pin FA and its pin VDD voltage, compare the magnitude of the two, and output the resonant cycle signal of the drain voltage of the main switch tube of the main switch tube of the auxiliary winding clamped flyback converter.

As an embodiment of the resonance period detection circuit, it includes an NPN transistor 419 , an NPN transistor 420 , a current limiting resistor 421 , a current limiting resistor 422 , an NMOS transistor 423 , an NMOS transistor 424 , an NMOS transistor 425 , an NMOS transistor 426 and a current comparator 427 , the collector of the NPN transistor 419 is connected to its own base, the collector of the NPN transistor 420 and the main control chip pin VDD, the emitter of the NPN transistor 419 is connected to one end of the current limiting resistor 421, and the other end of the current limiting resistor 421 is connected to the NMOS The gate of the transistor 423, the drain of the NMOS transistor 423 and the gate of the NMOS transistor 424, the drain of the NMOS transistor 424 is connected to the positive input terminal of the current comparator 427, and the base of the NPN transistor 420 is connected to the detection pin of the main control chip FA, the emitter of the NPN transistor 420 is connected to one end of the current limiting resistor 422, and the other end of the current limiting resistor 422 is connected to the gate of the NMOS transistor 425, the drain of the NMOS transistor 425 and the gate of the NMOS transistor 426, and the drain of the NMOS transistor 426. The pole is connected to the negative input terminal of the current comparator 427, the sources of the NMOS transistor 423, NMOS transistor 424, NMOS transistor 425 and NMOS transistor 426 are all grounded, and the output terminal of the current comparator 427 outputs the resonant period signal ZCD.

The beneficial effects of the present invention are:

1. Provide an accurate and new detection method and circuit for input voltage, output voltage and resonance period based on the characteristics of auxiliary winding clamping topology;

2. The accurate detection based on important parameters makes the auxiliary winding clamping topology more simple and practical, realizes the zero-voltage turn-on of the main switch tube, and facilitates the high frequency and miniaturization of the converter;

3. Based on the accurate detection of important parameters, important functions such as input undervoltage protection, feedforward, output overvoltage protection, primary side feedback, and quasi-resonant control of the converter can be realized.

Description of drawings

Figure 1 is a circuit diagram of a typical active clamp flyback converter;

Figure 2 is a key signal waveform diagram of a typical non-complementary active clamp flyback converter;

Fig. 3 is the circuit diagram of the auxiliary winding clamp flyback converter;

FIG. 4 is a circuit diagram of an auxiliary winding voltage detection according to an embodiment of the present invention;

Fig. 5 is the key signal waveform diagram of the detection circuit of the present invention;

FIG. 6 is a key signal waveform diagram of the auxiliary winding clamped converter applying the detection circuit of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention is further described in detail below with reference to FIG. 4 to FIG. 6 . It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. 402 in FIG. 4 is 310 in FIG. 3 , 405 in FIG. 4 is 309 in FIG. 3 , and 406 in FIG. 4 is 308 in FIG. 3 .

As shown in FIG. 4, it is an embodiment of the auxiliary winding detection circuit of the present invention, including an upper voltage dividing resistor 403, a lower voltage dividing resistor 404, a power input amplifier 407, a PMOS transistor 408, a PMOS transistor 410, an NMOS transistor 409, NMOS transistor 411, NMOS transistor 412, power input amplifier 413, resistor 414, PMOS transistor 415, resistor 416, sampling switch 417, holding capacitor 418, transistor 419, transistor 420, resistor 421, resistor 422, NMOS transistor 423, NMOS transistor 424 , NMOS transistor 425 , NMOS transistor 426 and current comparator 427 .

Wherein, the upper voltage dividing resistor 403 and the lower voltage dividing resistor 404 are connected in series across the two ends of the auxiliary winding to detect the voltage difference between the two ends of the auxiliary winding. The common ends of the upper and lower voltage dividing resistors are connected to the detection pin FA of the main control chip, and the high voltage side of the auxiliary winding supplies power to the pin VDD of the main control chip through the decoupling capacitor 406 .

The power input amplifier 407 , the PMOS transistor 408 , the PMOS transistor 410 , the NMOS transistor 409 , the NMOS transistor 411 and the NMOS transistor 412 form an input voltage detection circuit. The negative input terminal of the power input amplifier 407 is connected to the detection pin FA of the main control chip and the source of the PMOS transistor 410 , the positive input terminal is connected to the main control chip pin VDD, and the output terminal of the power input amplifier 407 is connected to the gate of the PMOS transistor 410 and the gate of the PMOS tube 408; the drain of the PMOS tube 408 is connected to its own gate and the drain of the NMOS tube 409, the source of the PMOS tube 408 is connected to the main control chip pin VDD; the gate of the NMOS tube 409 is connected to the NMOS tube The drain of the transistor 411, the gate of the NMOS transistor 411 is shorted to its drain, and connected to the gate of the NMOS transistor 412; the drain of the NMOS transistor 411 is also connected to the drain of the PMOS transistor 410; the NMOS transistor 409, the NMOS transistor 411 and the The sources of the NMOS transistors 412 are all grounded; the drain current of the NMOS transistor 412 is the detected current IVIN which is proportional to the input voltage.

The specific working process is as follows: In the transformer excitation stage, that is, the TC stage in FIG. 5 , the voltage across the primary winding NP of the transformer 401 is VIN, and the voltage coupled to both ends of the auxiliary winding is

The terminal VA of the same name of the auxiliary winding, that is, the drain voltage of the clamping tube 402 is:

If no processing is performed on the detection pin FA of the main control chip, the voltage of the detection pin FA of the main control chip should be:

Since the power input amplifier 407 and the PMOS transistor 410 form a negative feedback, when the voltage of the detection pin FA of the main control chip is higher than that of the main control chip pin VDD, the gate of the PMOS transistor 410 is pulled down, thereby increasing the saturation of the PMOS transistor 410 The current causes the voltage of the detection pin FA of the main control chip to drop. Therefore, the voltage of the main control chip detection pin FA is clamped to the main control chip pin VDD voltage, no current flows through the resistor R1, and the current flowing into the main control chip detection pin FA is:

The input terminals of the power input amplifier 407 are all high impedance, which can be regarded as no current flowing, and the current flowing into the detection pin FA of the main control chip flows into the drain of the NMOS transistor 411 through the PMOS transistor 410 . The NMOS transistor 411 and the NMOS transistor 412 form a current mirror. Assuming that the current mirror ratio is 1:m, the detected current proportional to the input voltage VIN is:

In fact, according to the voltage waveform of the same-named terminal VA of the auxiliary winding in FIG. 5 , at the beginning of excitation, the voltage of the same-named terminal VA of the auxiliary winding suddenly becomes high, and the feedback loop formed by the power input amplifier 407 and the PMOS transistor 410 takes time to respond. It will cause the actual detected current IVIN to lag behind the change of the same-name terminal VA of the auxiliary winding. Here, another feedback loop is formed by using the PMOS transistor 408 and the NMOS transistor 409 to speed up the response speed of the PMOS transistor 410 . The current of the PMOS transistor 410 becomes larger, so that the current of the NMOS transistor 411 becomes larger, and the NMOS transistor 409 and the PMOS transistor 411 form a current mirror, so that the current of the NMOS transistor 409 becomes larger; The voltage difference increases, causing the gate voltage of the PMOS transistor 410 to be pulled down rapidly, which speeds up the response speed of the PMOS transistor 410 . As shown in Figure 5, in the TC stage of the transformer excitation, the voltage waveform (dotted line) of the detection pin FA of the main control chip is actually clamped to VDD.

The output voltage sampling circuit includes a power input amplifier 413 , a resistor 414 , a PMOS transistor 415 , a resistor 416 , a sampling switch 417 and a holding capacitor 418 . The positive input terminal of the power input amplifier 413 is connected to the detection pin FA of the main control chip, the negative input terminal of the power input amplifier 413 is connected to one end of the resistor 414 and the source of the PMOS transistor 415, The other end is connected to the main control chip pin VDD, the drain of the PMOS transistor 415 is connected to one end of the resistor 416 and one end of the sampling switch 417, the other end of the resistor 416 is grounded, and the other end of the sampling switch 417 is connected to the upper plate of the holding capacitor 418, The lower plate of the holding capacitor 418 is grounded, and the voltage of the upper plate of the holding capacitor 418 is the detected output voltage proportional value.

The specific working process is as follows: In the degaussing stage of the transformer, that is, the TD stage in Figure 5, the voltage across the secondary winding of the transformer 401 is VOUT, and the voltage coupled to the auxiliary winding is

The voltage of the main control chip detection pin FA is:

Since the power input amplifier 413 and the PMOS transistor 415 form a negative feedback, the voltage of the main control chip detection pin FA is lower than the main control chip pin VDD voltage, the gate voltage of the PMOS transistor 415 is pulled down, and the current of the PMOS transistor 415 increases. , the voltage drop on the resistor 414 increases, and finally the voltages of the positive and negative input terminals of the power input amplifier 413 are equalized. Thus the voltage difference across resistor 414 is:

The current flowing through resistor 414 also flows through resistor 416, so the voltage drop across resistor 416 is:

The resistance value R 414 of the resistor ₄₁₄ and the resistance value R ₄₁₆ of the resistor 416 can be set equal, and the voltage drop on the resistor 416 can be completely set by the upper voltage dividing resistor R1 and the lower voltage dividing resistor R2 on the periphery of the chip.

The sampling switch 417 is turned on during the transformer degaussing stage, and the voltage on the resistor 416 is sampled and stored in the holding capacitor 418 to obtain the DC output voltage proportional value VO_SAMP.

The resonance period detection circuit includes NPN transistor 419 , NPN transistor 420 , current limiting resistor 421 , current limiting resistor 422 , NMOS transistor 423 , NMOS transistor 424 , NMOS transistor 425 , NMOS transistor 426 and current comparator 427 . The collector of the NPN transistor 419 is connected to its own base, the collector of the NPN transistor 420 and the main control chip pin VDD, the emitter of the NPN transistor 419 is connected to one end of the current limiting resistor 421; the other end of the current limiting resistor 421 is connected to the NMOS transistor The gate of 423, the drain of NMOS tube 423 and the gate of NMOS tube 424, the sources of NMOS tube 423 and NMOS tube 424 are all grounded; the drain of NMOS tube 424 is connected to the positive input terminal of current comparator 427; NPN The base of the transistor 420 is connected to the detection pin FA of the main control chip, the emitter of the NPN transistor 420 is connected to one end of the current limiting resistor 422; the other end of the current limiting resistor 422 is connected to the gate of the NMOS transistor 425, the drain of the NMOS transistor 425 and the The gate of the NMOS transistor 426, the sources of the NMOS transistor 425 and the NMOS transistor 426 are all grounded; the drain of the NMOS transistor 426 is connected to the negative input terminal of the current comparator 427, and the current comparator 427 outputs the resonant period signal ZCD.

The specific working process is as follows: the base of the NPN transistor 420 is connected to the voltage of the detection pin FA of the main control chip. Figure 5 shows the TR resonance stage. The voltage waveform of the detection pin FA of the main control chip is a sine wave with VDD as the center value. Its resonance period is the same as that of VA, that is, the same as that of VDS. In this way, the resonance period can be detected only by comparing the voltage of the main control chip detection pin FA and the main control chip pin VDD. After the main control chip pin VDD voltage passes through the NPN transistor 419, the voltage drop across the resistor 421 is:

VDD- _VBE419 - _VGS423

Among them, V _BE419 is the emitter junction voltage drop of the NPN transistor 419 , and V _GS423 is the gate-source voltage drop of the NMOS transistor 423 . Assuming that the ratio of the current mirror formed by the NMOS transistor 423 and the NMOS transistor 424 is 1:1, the current flowing from the positive input terminal of the current comparator 427 is:

It is assumed that the size of the NPN transistor 420 is the same as that of the NPN transistor 419, the resistance value of the current limiting resistor 422 is the same as the resistance value (R421) of the current limiting resistor 421, the size of the NMOS transistor 425 is the same as that of the NMOS transistor 423, the NMOS transistor 425 and the NMOS transistor 426 The ratio of the formed current mirror is 1:1, then when the voltage of the detection pin FA of the main control chip is greater than the voltage of the pin VDD of the main control chip, the current flowing from the negative input terminal of the current comparator 427 is greater than the current flowing out from the positive input terminal of the current comparator 427. The current comparator 427 outputs a low level. Similarly, when the voltage of the detection pin FA of the main control chip is lower than the voltage of the pin VDD of the main control chip, the current comparator 427 outputs a high level.

Figure 6 shows a schematic diagram of the key signal waveforms of the entire auxiliary winding clamp converter. In the excitation phase of each switching cycle, that is, the main switch tube drive signal GL is at a high level, the voltage of the main control chip detection pin FA is clamped to the main control chip pin VDD voltage, and the internal detection of the chip is consistent with the input voltage VIN. The proportional current value IVIN; the difference between the main control chip pin VDD voltage and the main control chip detection pin FA voltage is restored to the voltage with the ground as the reference potential, as shown by the dotted line on the VO_SAMP coordinate axis, in the degaussing stage, By sampling and holding the restored voltage, a detection value proportional to the output voltage VOUT can be obtained; in the resonance stage, the main control chip detection pin FA is compared with the main control chip pin VDD voltage, and the resonance period signal ZCD is output.

The circuit in Fig. 4, except 401, 402, 405, and 406, can be set in the main control chip and form a part of the main control chip.

It should be clear that the embodiments of the present invention are not limited to this. According to the above content, according to the common technical knowledge and conventional means in the field, and without departing from the above-mentioned basic technical idea of the present invention, the auxiliary winding voltage detection circuit of the present invention has other Therefore, the present invention can also make other modifications, substitutions or changes in various forms, which all fall within the protection scope of the present invention.

Claims

An auxiliary winding detection method, which is used for the auxiliary winding to clamp a flyback converter, and the auxiliary winding in the auxiliary winding clamped flyback converter is controlled by a main control chip. The resistor 403 and the lower voltage dividing resistor 404 are connected in series to form a two-terminal network. It is connected to the pin VDD of the main control chip, and the other end of the lower voltage dividing resistor 404 is connected to the end of the same name of the auxiliary winding 311;

The method controls the main control chip to detect the pin FA and its pin VDD voltage, so that the value ratio of the measured parameter falls on the detection end of the corresponding detection circuit;

The method specifically includes an input voltage detection step, the detection circuit involved in this step is an input voltage detection circuit, the circuit is connected between the detection pin FA and the pin VDD of the main control chip, and in the transformer excitation stage, it clamps the main control chip. The control chip detects the voltage of the pin FA to the voltage value of its pin VDD, so that the input voltage is proportional to the detection end of the input voltage detection circuit.
The auxiliary winding detection method according to claim 1, wherein the method further comprises an output voltage detection step, the detection circuit involved in this step is an output voltage detection circuit, and the circuit is also connected to the detection lead of the main control chip. Between pin FA and pin VDD, in the degaussing stage of the transformer, the voltage difference between the main control chip detection pin FA voltage and its pin VDD voltage falls on a resistor, and the voltage difference is the proportional value of the output voltage. It is transmitted to the detection terminal of the output voltage detection circuit.
The detection method according to claim 1 or 2, characterized in that: the method further comprises a resonant cycle detection step, the detection circuit involved in this step is a resonant cycle detection circuit, and the circuit is also connected to the detection pin of the main control chip Between FA and pin VDD, in the resonance stage, the main control chip detects the voltage of pin FA and pin VDD of the main control chip through its detection, and compares the magnitudes of the two to obtain the main switch tube of the flyback converter clamped by the auxiliary winding. Drain voltage resonant period.
An auxiliary winding detection circuit is used for the auxiliary winding clamp flyback converter, and the auxiliary winding clamp flyback converter realizes work through a main control chip, and is characterized in that: it includes an upper voltage dividing resistor, a lower voltage dividing resistor and an input voltage In the detection circuit, one end of the upper voltage divider resistor is connected to the other end of the auxiliary winding, the other end of the upper voltage divider resistor is connected to one end of the lower voltage divider resistor, the other end of the lower voltage divider resistor is connected to the same name terminal of the auxiliary winding, and one end of the upper voltage divider resistor is connected to the input voltage detection circuit One end is connected to the main control chip pin VDD, the other end of the upper voltage divider resistor and the other end of the input voltage detection circuit are connected to the main control chip detection pin FA,

The input voltage detection circuit is used to control the main control chip to detect the voltage of the pin FA and its pin VDD, so that the value ratio of the input voltage of the measured parameter falls on the detection end of the input voltage detection circuit;

Specifically, in the transformer excitation stage, the voltage of the detection pin FA of the main control chip is clamped to the voltage of the pin VDD of the main control chip, so that the ratio of the input voltage value falls on the lower voltage dividing resistor.
The detection circuit according to claim 4, wherein the input voltage detection circuit comprises a power input amplifier 407, a PMOS transistor 408, a PMOS transistor 410, an NMOS transistor 409, an NMOS transistor 411 and an NMOS transistor 412, and a power supply input amplifier 407 The negative input terminal and the source of the PMOS tube 410 are connected to the detection pin FA of the main control chip, the positive input terminal of the power input amplifier 407 and the source of the PMOS tube 408 are connected to the main control chip pin VDD, and the power input amplifier 407 The output terminal is connected to the gate of the PMOS transistor 410 and the gate of the PMOS transistor 408, the drain of the PMOS transistor 408 is connected to its gate and the drain of the NMOS transistor 409, and the gate of the NMOS transistor 409 is connected to the drain of the NMOS transistor 411 and the PMOS transistor The drain of the transistor 410, the gate of the NMOS transistor 411 is shorted to its drain, and connected to the gate of the NMOS transistor 412, the sources of the NMOS transistor 409, the NMOS transistor 411 and the NMOS transistor 412 are all grounded, and the drain of the NMOS transistor 412 is Input voltage detection circuit detection terminal.
The detection circuit according to claim 5, characterized in that: it further comprises an output voltage detection circuit; the output voltage detection circuit is used to control the main control chip to detect the voltage of the pin FA and its pin VDD, so that the measured parameter The value ratio of the output voltage falls on the detection end of the output voltage detection circuit;

Specifically, it is used to control the voltage difference between the main control chip detection pin FA voltage and its pin VDD voltage to fall on a resistor in the transformer degaussing stage, and the voltage difference is the proportional value of the output voltage, and then transmitted to the output voltage detection circuit detection terminal.
The detection circuit according to claim 6, wherein the output voltage detection circuit comprises a power input amplifier 413, a resistor 414, a PMOS transistor 415, a resistor 416, a sampling switch 417 and a holding capacitor 418. The positive input terminal is connected to the detection pin FA of the main control chip, the negative input terminal is connected to one end of the resistor 414 and the source of the PMOS tube 415, the output terminal is connected to the gate of the PMOS tube 415, and the other end of the resistor 414 is connected to the main control Chip pin VDD, the drain of the PMOS transistor 415 is connected to one end of the resistor 416 and one end of the sampling switch 417, the other end of the sampling switch 417 is connected to the upper plate of the holding capacitor 418, the other end of the resistor 416 and the lower pole of the holding capacitor 418 The plate is grounded, and the upper plate of the holding capacitor 418 is the detection terminal of the output voltage detection circuit.
The detection circuit according to any one of claims 4 to 7, further comprising a resonance period detection circuit, one end of the resonance period detection circuit is connected to the detection pin FA of the main control chip, and the other end of the resonance period detection circuit is connected to the main control The chip pin VDD is used to detect the voltage of the main control chip detection pin FA and its pin VDD, compare the magnitudes of the two, and output the resonant period signal of the drain voltage of the main switch tube of the auxiliary winding clamped flyback converter.
The detection circuit according to claim 8, wherein the resonance period detection circuit comprises an NPN transistor 419, an NPN transistor 420, a current limiting resistor 421, a current limiting resistor 422, an NMOS transistor 423, an NMOS transistor 424, and an NMOS transistor 425 , NMOS transistor 426 and current comparator 427, the collector of NPN transistor 419 is connected to its own base, the collector of NPN transistor 420 and the main control chip pin VDD, the emitter of NPN transistor 419 is connected to one end of the current limiting resistor 421, The other end of the current limiting resistor 421 is connected to the gate of the NMOS transistor 423 , the drain of the NMOS transistor 423 and the gate of the NMOS transistor 424 , the drain of the NMOS transistor 424 is connected to the positive input terminal of the current comparator 427 , and the The base is connected to the detection pin FA of the main control chip, the emitter of the NPN transistor 420 is connected to one end of the current limiting resistor 422 , and the other end of the current limiting resistor 422 is connected to the gate of the NMOS transistor 425 , the drain of the NMOS transistor 425 and the NMOS transistor 426 The gate of the NMOS transistor 426 is connected to the negative input terminal of the current comparator 427, the sources of the NMOS transistor 423, NMOS transistor 424, NMOS transistor 425 and NMOS transistor 426 are all grounded, and the output terminal of the current comparator 427 outputs resonance Periodic signal ZCD.