WO2022170923A1 - 一种数据读写方法和混合型存储器 - Google Patents

一种数据读写方法和混合型存储器 Download PDF

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WO2022170923A1
WO2022170923A1 PCT/CN2022/072416 CN2022072416W WO2022170923A1 WO 2022170923 A1 WO2022170923 A1 WO 2022170923A1 CN 2022072416 W CN2022072416 W CN 2022072416W WO 2022170923 A1 WO2022170923 A1 WO 2022170923A1
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storage medium
volatile storage
data
volatile
memory
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PCT/CN2022/072416
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English (en)
French (fr)
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许仲杰
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荣耀终端有限公司
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Priority to US18/015,889 priority Critical patent/US20230280932A1/en
Priority to EP22752085.5A priority patent/EP4160380A4/en
Publication of WO2022170923A1 publication Critical patent/WO2022170923A1/zh

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Definitions

  • the present application relates to the field of terminals, and in particular, to a data reading and writing method and a hybrid memory.
  • Volatile memory may include random access memory (RAM).
  • RAM may be, for example, double data rate (DDR) memory.
  • DDR double data rate
  • Volatile memory loses its stored contents when the system experiences a sudden power loss.
  • the non-volatile memory may include, for example, a hard drive disk (HDD), a solid state disk (SSD), and the like. Non-volatile memory does not lose data when the computer is turned off or when the computer is shut down abruptly or unexpectedly.
  • Volatile memory and non-volatile memory have the following problems: volatile memory consumes high power consumption when reading and writing data, and non-volatile memory encounters long delays and waits when reading and writing data , the read and write performance is low.
  • Embodiments of the present application provide a data read and write method and a hybrid memory, which can improve read and write performance and reduce power consumption.
  • embodiments of the present application provide a hybrid memory, where the hybrid memory includes a storage controller, a volatile storage medium, and a nonvolatile storage medium; a physical address segment of the volatile storage medium and a nonvolatile storage medium The physical address segments of the storage media are different; the storage controller is used to receive read/write instructions from the processor, and the read/write instructions carry the first address; the first address corresponds to the storage space of the volatile storage medium or the non-volatile storage medium storage space; if the first address corresponds to the storage space of the volatile storage medium, the storage controller is used to write data into the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium; An address corresponds to the storage space of the non-volatile storage medium, and the storage controller is used for writing data into the storage space of the non-volatile storage medium or reading data from the storage space of the non-volatile storage medium.
  • the volatile storage medium group in the hybrid memory provided by the embodiment of the present application can support high-speed processing of data, and can achieve high read and write performance.
  • the group of non-volatile storage media in the hybrid memory has higher performance and lower power consumption at lower frequencies. Therefore, the use of hybrid memory can improve the read and write performance of electronic devices and reduce power consumption. It can meet the basic demands of low power consumption and high performance of electronic devices on the market.
  • the hardware implementation of the hybrid memory is simple, the internal design is simple, and the cost is low.
  • the hybrid memory further includes at least one of a bus, a substrate, a package shell and a bus interface; wherein the storage controller, the volatile storage medium and the non-volatile storage medium are integrated on the substrate Above, the volatile storage medium and the non-volatile storage medium are connected by a bus, the storage controller, the volatile storage medium and the non-volatile storage medium, the bus and the substrate are packaged inside the package shell, and the package shell 006 is external A bus interface is presented, which is used to interface with the processor.
  • the hardware implementation of the hybrid memory is simple, the internal design is simple, it is easier to implement, and the cost is lower.
  • the volatile storage medium includes double data rate DDR memory, DDR2, DDR3, DDR4, high bandwidth memory (HBM), dynamic random access memory (dynamic random access memory, At least one of DRAM) and 3D Super DRAM (Super-DRAM); non-volatile storage media include single-level storage flash memory/single level cell flash memory (single level cell, SLC)-NAND, magnetic random access memory ( Magnetic radom access memory, MRAM), resistance random access memory (resistance radom access memory, RRAM), phase change random access memory (phase change radom access memory, PCRAM), 3D-Xpoint storage medium or 3D-SLC NAND flash memory at least one of the memories.
  • the embodiments of the present application do not limit the types of volatile storage media or non-volatile storage media.
  • the hybrid memory is installed in the electronic device as memory.
  • Program data can be stored in hybrid memory during operation.
  • the volatile storage medium group in the hybrid memory can support high-speed data processing, and can achieve high read and write performance.
  • the group of non-volatile storage media in the hybrid memory has higher performance and lower power consumption at lower frequencies. Therefore, the use of hybrid memory can improve the read and write performance of electronic devices and reduce power consumption. It can meet the basic demands of low power consumption and high performance of electronic devices on the market.
  • the hybrid memory when the screen of the electronic device is off, the hybrid memory is powered off.
  • Traditional memory for example, using RAM as memory
  • RAM random access memory
  • the data of the non-volatile storage medium group of the hybrid memory provided by the embodiment of the present application will not be lost, and useful data can be stored in the non-volatile storage medium group, so that the electronic device can be completely powered off when the screen is off. , which can greatly reduce power consumption.
  • the traditional memory is powered off, the data in the memory will be lost.
  • the running program needs to be imported into the memory for processing before the system can be booted.
  • the hybrid memory When the hybrid memory is powered off, the data in the non-volatile storage medium group in the hybrid memory will not be lost, and the running program can be stored in the non-volatile storage medium group, so that the next time it is turned on, it can be quickly Resuming programs to be run can better reduce standby power consumption and improve startup performance.
  • the non-volatile storage medium is used to store data of a preset type, and the data of the preset type includes at least one of artificial intelligence AI data, models and training results for instant training.
  • the SoC can directly read data of a preset type from the hybrid memory used as memory, and the time it takes is far less than the time and resource consumption of recalculation, and it is also far less than the time spent reading from slow storage. time.
  • the first address is a physical address or a logical address; if the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address. If the first address is a physical address, the storage controller can directly address the volatile storage medium or the non-volatile storage medium according to the physical address to determine the storage space corresponding to the physical address. When the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address, and then address the volatile storage medium or the nonvolatile storage medium according to the physical address to determine the storage space corresponding to the physical address.
  • an embodiment of the present application provides a hybrid memory, where the hybrid memory includes a storage controller, a volatile storage medium, and a nonvolatile storage medium; a physical address segment of the volatile storage medium and a nonvolatile storage medium The physical address segments of the storage medium are the same; the storage controller receives the read/write command from the processor, and the read/write command carries the first address; if the main frequency of the processor is greater than the highest read/write frequency of the non-volatile storage medium, the storage The controller is used to write data into the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium; if the main frequency of the processor is less than or equal to the highest read and write frequency of the non-volatile storage medium, The storage controller is used for writing data into the storage space of the nonvolatile storage medium or reading data from the storage space of the nonvolatile storage medium.
  • the processor when the processor is at a high main frequency (that is, the clock frequency of the processor is higher than the highest reading and writing frequency of the non-volatile storage medium), since the highest reading and writing frequency of the non-volatile storage medium is lower than the main frequency (i.e. Non-volatile storage media can process data at a lower speed than a processor can process data), so data is written to volatile storage media to meet the requirements of fast action.
  • the main frequency of the processor is reduced, the highest read and write frequency of the non-volatile storage medium is greater than or equal to the main frequency, that is, the data processing speed of the non-volatile storage medium can reach the speed of the processor processing data, so the data can be Write to non-volatile storage media for lower power consumption.
  • the volatile storage medium can enter an extremely low power consumption state, which can achieve the effect of reducing power consumption.
  • the storage controller is further configured to write the data written into the storage space of the volatile storage medium into the non-volatile storage medium.
  • the storage space of the volatile storage medium if the main frequency of the processor is less than or equal to the highest read and write frequency of the non-volatile storage medium, the storage controller is also used to write the data into the storage space of the non-volatile storage medium Storage space for writing to volatile storage media.
  • the storage controller automatically transfers the data to the non-volatile storage medium with a lower rate; when the system is in a non-volatile storage medium When the low-speed range that the storage medium can match, the data is first written to the non-volatile storage medium, and then the storage controller automatically transfers the data to the volatile storage medium.
  • the above process can be completed by the storage controller of the hybrid memory without processor processing, which can reduce the load on the processor side and improve the processing performance of the processor.
  • the hybrid memory further includes at least one of a bus, a substrate, a package shell and a bus interface; wherein the storage controller, the volatile storage medium and the non-volatile storage medium are integrated on the substrate Above, the volatile storage medium and the non-volatile storage medium are connected by a bus, the storage controller, the volatile storage medium and the non-volatile storage medium, the bus and the substrate are packaged inside the package shell, and the package shell 006 is external A bus interface is presented, which is used to interface with the processor.
  • the volatile storage medium includes at least one of double data rate DDR memory, DDR2, DDR3, DDR4, high bandwidth memory HBM, dynamic random access memory DRAM or 3D super DRAM; Volatile storage media include single-layer storage flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage media or 3D-SLC NAND flash memory at least one of them.
  • the hybrid memory is installed in the electronic device as memory.
  • the hybrid memory when the screen of the electronic device is off, the hybrid memory is powered off.
  • the non-volatile storage medium is used to store data of a preset type, and the data of the preset type includes at least one of artificial intelligence AI data, models and training results for instant training.
  • the first address is a physical address or a logical address; if the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address.
  • embodiments of the present application provide a hybrid memory, where the hybrid memory includes a storage controller, a volatile storage medium, and a nonvolatile storage medium; a physical address segment of the volatile storage medium and a nonvolatile storage medium The physical address segment of the storage medium is partially the same; the storage controller receives the read/write instruction from the processor, and the read/write instruction carries the first address; the first address corresponds to the non-volatile storage medium and the volatile storage medium at the same time.
  • the storage controller is used to write data into the storage space of the volatile storage medium or from the storage space of the volatile storage medium.
  • the storage controller is used to write data into the storage space of the non-volatile storage medium or from the non-volatile storage medium
  • the storage space of the medium reads the data; if the first address corresponds to the storage space of the non-volatile storage medium or the volatile storage medium, if the first address corresponds to the storage space of the volatile storage medium, the storage controller is used for Write data into the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium; if the first address corresponds to the storage space of the non-volatile storage medium, the storage controller is used to write the data into the non-volatile storage medium.
  • the storage space of the volatile storage medium or data is read from the storage space of the non-volatile storage medium.
  • the hybrid memory after the hybrid memory receives the first address, in the case that the first address corresponds to the storage space of the non-volatile storage medium and the volatile storage medium at the same time, when the processor is at a high main frequency (ie, When the clock frequency of the processor is higher than the maximum read and write frequency of the non-volatile storage medium), because the maximum read and write frequency of the non-volatile storage medium is lower than the main frequency (that is, the speed of processing data of the non-volatile storage medium) slower than the processor can process the data), so the data is written to a volatile storage medium for fast action.
  • a high main frequency ie, When the clock frequency of the processor is higher than the maximum read and write frequency of the non-volatile storage medium
  • the main frequency that is, the speed of processing data of the non-volatile storage medium
  • the highest read and write frequency of the non-volatile storage medium is greater than or equal to the main frequency, that is, the data processing speed of the non-volatile storage medium can reach the speed of the processor processing data, so the data can be Write to non-volatile storage media for lower power consumption.
  • the volatile storage medium can enter an extremely low power consumption state, which can achieve the effect of reducing power consumption.
  • the volatile storage medium group can support high-speed data processing, and can achieve high read and write performance.
  • the group of non-volatile storage media in the hybrid memory has higher performance and lower power consumption at lower frequencies. Therefore, the use of hybrid memory can improve the read and write performance of electronic devices and reduce power consumption. It can meet the basic demands of low power consumption and high performance of electronic devices on the market.
  • the storage controller is further configured to write the data written into the storage space of the volatile storage medium into the non-volatile storage medium.
  • the storage space of the volatile storage medium if the main frequency of the processor is less than or equal to the highest read and write frequency of the non-volatile storage medium, the storage controller is also used to write the data into the storage space of the non-volatile storage medium Storage space for writing to volatile storage media.
  • the hybrid memory further includes at least one of a bus, a substrate, a package shell and a bus interface; wherein the storage controller, the volatile storage medium and the non-volatile storage medium are integrated on the substrate Above, the volatile storage medium and the non-volatile storage medium are connected by a bus, the storage controller, the volatile storage medium and the non-volatile storage medium, the bus and the substrate are packaged inside the package shell, and the package shell 006 is external A bus interface is presented, which is used to interface with the processor.
  • the volatile storage medium includes at least one of double data rate DDR memory, DDR2, DDR3, DDR4, high bandwidth memory HBM, dynamic random access memory DRAM or 3D super DRAM; Volatile storage media include single-layer storage flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage media or 3D-SLC NAND flash memory at least one of them.
  • the hybrid memory is installed in the electronic device as memory.
  • the hybrid memory when the screen of the electronic device is off, the hybrid memory is powered off.
  • the non-volatile storage medium is used to store data of a preset type, and the data of the preset type includes at least one of artificial intelligence AI data, models and training results for instant training.
  • the first address is a physical address or a logical address; if the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address.
  • an embodiment of the present application provides a method for reading and writing data, which is applied to a hybrid memory, where the hybrid memory includes a storage controller, a volatile storage medium, and a non-volatile storage medium;
  • the address segment is different from the physical address segment of the non-volatile storage medium;
  • the method includes: the storage controller receives a read/write instruction from the processor, and the read/write instruction carries the first address; if the first address corresponds to the volatile storage medium If the first address corresponds to the storage space of the non-volatile storage medium, the storage controller will write data into the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium;
  • the device writes data to the storage space of the non-volatile storage medium or reads data from the storage space of the non-volatile storage medium.
  • the hybrid memory further includes at least one of a bus, a substrate, a package shell and a bus interface; wherein the storage controller, the volatile storage medium and the non-volatile storage medium are integrated on the substrate Above, the volatile storage medium and the non-volatile storage medium are connected by a bus, the storage controller, the volatile storage medium and the non-volatile storage medium, the bus and the substrate are packaged inside the package shell, and the package shell 006 is external A bus interface is presented, which is used to interface with the processor.
  • the volatile storage medium includes at least one of double data rate DDR memory, DDR2, DDR3, DDR4, high bandwidth memory HBM, dynamic random access memory DRAM or 3D super DRAM; Volatile storage media include single-layer storage flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage media or 3D-SLC NAND flash memory at least one of them.
  • the hybrid memory is installed in the electronic device as memory.
  • the hybrid memory when the screen of the electronic device is off, the hybrid memory is powered off.
  • the non-volatile storage medium is used to store data of a preset type, and the data of the preset type includes at least one of artificial intelligence AI data, models and training results for instant training.
  • the first address is a physical address or a logical address; if the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address.
  • an embodiment of the present application provides a method for reading and writing data, which is applied to a hybrid memory, where the hybrid memory includes a storage controller, a volatile storage medium, and a non-volatile storage medium;
  • the address segment is the same as the physical address segment of the non-volatile storage medium;
  • the method includes: the storage controller receives a read/write instruction from the processor, and the read/write instruction carries the first address; if the main frequency of the processor is greater than the nonvolatile the highest read/write frequency of the volatile storage medium, the storage controller writes data to the storage space of the volatile storage medium or reads data from the storage space of the volatile storage medium; if the main frequency of the processor is less than or equal to the non-volatile storage medium The highest read/write frequency of the non-volatile storage medium, the storage controller writes data to the storage space of the non-volatile storage medium or reads data from the storage space of the non-volatile storage medium.
  • the storage controller is further configured to write the data written into the storage space of the volatile storage medium into the non-volatile storage medium.
  • the storage space of the volatile storage medium if the main frequency of the processor is less than or equal to the highest read and write frequency of the non-volatile storage medium, the storage controller is also used to write the data into the storage space of the non-volatile storage medium Storage space for writing to volatile storage media.
  • the hybrid memory further includes at least one of a bus, a substrate, a package shell and a bus interface; wherein the storage controller, the volatile storage medium and the non-volatile storage medium are integrated on the substrate Above, the volatile storage medium and the non-volatile storage medium are connected by a bus, the storage controller, the volatile storage medium and the non-volatile storage medium, the bus and the substrate are packaged inside the package shell, and the package shell 006 is external A bus interface is presented, which is used to interface with the processor.
  • the volatile storage medium includes at least one of double data rate DDR memory, DDR2, DDR3, DDR4, high bandwidth memory HBM, dynamic random access memory DRAM or 3D super DRAM; Volatile storage media include single-layer storage flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage media or 3D-SLC NAND flash memory at least one of them.
  • the hybrid memory is installed in the electronic device as memory.
  • the hybrid memory when the screen of the electronic device is off, the hybrid memory is powered off.
  • the non-volatile storage medium is used to store data of a preset type, and the data of the preset type includes at least one of artificial intelligence AI data, models and training results for instant training.
  • the first address is a physical address or a logical address; if the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address.
  • an embodiment of the present application provides a method for reading and writing data, which is applied to a hybrid memory, where the hybrid memory includes a storage controller, a volatile storage medium, and a non-volatile storage medium;
  • the address segment is the same as the physical address segment of the non-volatile storage medium;
  • the method includes: the storage controller receives a read/write instruction from the processor, and the read/write instruction carries the first address; the first address corresponds to the nonvolatile In the case of the storage space of the volatile storage medium and the volatile storage medium, if the main frequency of the processor is greater than the maximum read and write frequency of the non-volatile storage medium, the storage controller will write the data into the storage space of the volatile storage medium.
  • the storage controller writes the data into the storage space of the non-volatile storage medium space or read data from the storage space of the non-volatile storage medium; if the first address corresponds to the storage space of the non-volatile storage medium or the storage space of the volatile storage medium, if the first address corresponds to the volatile storage medium If the first address corresponds to the storage space of the non-volatile storage medium, the storage controller will write data into the storage space of the volatile storage medium or read data from the storage space of the volatile storage medium; The device writes data to the storage space of the non-volatile storage medium or reads data from the storage space of the non-volatile storage medium.
  • the storage controller is further configured to write the data written into the storage space of the volatile storage medium into the non-volatile storage medium.
  • the storage space of the volatile storage medium if the main frequency of the processor is less than or equal to the highest read and write frequency of the non-volatile storage medium, the storage controller is also used to write the data into the storage space of the non-volatile storage medium Storage space for writing to volatile storage media.
  • the hybrid memory further includes at least one of a bus, a substrate, a package shell and a bus interface; wherein the storage controller, the volatile storage medium and the non-volatile storage medium are integrated on the substrate Above, the volatile storage medium and the non-volatile storage medium are connected by a bus, the storage controller, the volatile storage medium and the non-volatile storage medium, the bus and the substrate are packaged inside the package shell, and the package shell 006 is external A bus interface is presented, which is used to interface with the processor.
  • the volatile storage medium includes at least one of double data rate DDR memory, DDR2, DDR3, DDR4, high bandwidth memory HBM, dynamic random access memory DRAM or 3D super DRAM; Volatile storage media include single-layer storage flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage media or 3D-SLC NAND flash memory at least one of them.
  • the hybrid memory is installed in the electronic device as memory.
  • the hybrid memory when the screen of the electronic device is off, the hybrid memory is powered off.
  • the non-volatile storage medium is used to store data of a preset type, and the data of the preset type includes at least one of artificial intelligence AI data, models and training results for instant training.
  • the first address is a physical address or a logical address; if the first address is a logical address, the storage controller is further configured to convert the logical address into a physical address.
  • an embodiment of the present application provides an electronic device, which is characterized in that it includes a processor, a hybrid memory, and a bus, wherein the processor and the hybrid memory are connected to each other through a bus, and the hybrid memory includes a storage controller , volatile storage medium and non-volatile storage medium; wherein, the hybrid memory is used to store computer program code, and the computer program code includes computer instructions; when the computer instructions are executed by the processor, the processor and the hybrid memory are executed. Any one of the methods provided by the third aspect to the fifth aspect.
  • an embodiment of the present application provides a computer-readable storage medium, including instructions, which, when executed on a computer, cause the computer to execute any one of the methods provided in the third to fifth aspects.
  • an embodiment of the present application provides a computer program product containing instructions, which, when run on a computer, enables the computer to execute any one of the methods provided in the third to fifth aspects above.
  • an embodiment of the present application provides a chip system, where the chip system includes a processor, and may further include a memory, for implementing any one of the methods provided in the third aspect to the fifth aspect.
  • the chip system can be composed of chips, and can also include chips and other discrete devices.
  • FIG. 1 is a schematic structural diagram of a hybrid memory provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of signal interaction provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of signal interaction provided by an embodiment of the present application.
  • FIG. 4 is a cross-sectional view and a three-dimensional structural view of a hybrid memory provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a physical address segment of a hybrid memory provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a physical address segment of another hybrid memory provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a physical address segment of another hybrid memory provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a physical address segment of another hybrid memory provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a physical address segment of a hybrid memory provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a physical address segment of a hybrid memory provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a physical address segment of a hybrid memory provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • DDR synchronous dynamic random access memory DDR-SDRAM
  • DDR-SDRAM double data rate synchronous dynamic random access memory
  • the storage (Storage) that can permanently access data is slow in processing data.
  • the system wants to write data to Storage it usually encounters long delays and waits. For example, the synchronous disk write command (SyncWrite) of critical data will cause the storage's input and output (IO) performance to drop instantaneously.
  • SyncWrite synchronous disk write command
  • the embodiments of the present application provide a hybrid memory (also referred to as a heterogeneous memory or a hybrid heterogeneous memory, which is not limited in this application), which can be flexibly used as a memory device and can improve the readability of an operating system (OS).
  • the write performance can also improve the performance of the database using the hybrid storage as the storage medium.
  • the fast-access data can be powered off without being lost, and the power can be powered off after the writing is completed, thereby saving power consumption.
  • the hybrid memory 100 may include a storage controller 001 , a volatile storage medium 002 , a nonvolatile storage medium 003 , a bus 004 , a substrate 005 , a package 006 and a bus interface 007 .
  • the volatile storage medium 002 and the non-volatile storage medium 003 can be connected to the storage controller 001 .
  • the storage controller 001 , the volatile storage medium 002 and the nonvolatile storage medium 003 may be integrated on the substrate 005 .
  • the volatile storage medium 002 and the nonvolatile storage medium 003 can be connected through a bus 004 .
  • the storage controller 001 , the volatile storage medium 002 and the non-volatile storage medium 003 , the bus 004 and the substrate 005 may be packaged inside the package shell 006 , and the package shell 006 may present a bus interface 007 to the outside.
  • the volatile storage medium may include DDR memory (DDR for short), DDR2, DDR3, DDR4, high bandwidth memory HBM, dynamic random access memory DRAM, 3D super DRAM (Super-DRAM), and the like.
  • DDR memory DDR for short
  • DDR2, DDR3, DDR4, high bandwidth memory HBM dynamic random access memory DRAM
  • 3D super DRAM Super-DRAM
  • the volatile storage medium may be HBM with a width of 512 bits and a capacity of 1 GB.
  • Non-volatile storage media can be, for example, single-layer storage flash memory/single-layer cell flash memory SLC-NAND, magnetic random access memory MRAM, resistive random access memory RRAM, phase change random access memory PCRAM, 3D-Xpoint storage media or 3D-SLC NAND flash memory, etc.
  • the packaging method of the hybrid memory 100 may be, for example, a flip package (flip package), a ball grid array (BGA) package, or a wafer level chip scale package (WLCSP) or the like.
  • flip package flip package
  • BGA ball grid array
  • WLCSP wafer level chip scale package
  • the bus interface 007 presented to the outside by the package shell 006 may be an interface.
  • it may be a DDR4 interface that conforms to the specification of the Joint Electron Device Engineering Council (JEDEC).
  • JEDEC Joint Electron Device Engineering Council
  • the bus interface 007 externally presented by the package shell 006 may include multiple (two or more) interfaces.
  • two DDR4 interfaces that conform to the JEDEC specification can be included.
  • the above-mentioned hybrid memory can be set in the electronic device, and the hybrid memory can be used as the memory of the electronic device, that is, the program data can be stored in the hybrid memory during the running process.
  • the electronic device also includes a processor (eg, a system on chip (SoC)).
  • SoC can act as a master device (HOST), and the hybrid memory can act as a slave device (DEVICE).
  • the SoC can write data to and read data from the hybrid memory.
  • the SoC and hybrid memory can be connected through one or more of the DDR5 interface, the HBM DDR interface, or the PCIeGen5x4 interface. That is, the bus connection between the SoC and the hybrid memory is rich in choice and composability.
  • the SoC can send a read command to the memory controller 001, and the read command includes the first address.
  • the storage controller 001 determines the storage space corresponding to the first address, and reads data from the storage space.
  • the first address may be the first physical address, or may be the first logical address. If the first address is the first physical address, after receiving the read command, the storage controller 001 directly addresses the volatile storage medium or the non-volatile storage medium according to the first physical address, and determines the storage space corresponding to the first physical address , read the first data from the storage space corresponding to the first physical address.
  • the storage controller 001 determines the first physical address according to the first logical address, and then addresses the volatile storage medium or non-volatile storage medium according to the first physical address.
  • the medium determines the storage space corresponding to the first physical address, and reads the first data from the storage space corresponding to the first physical address. Then, the memory controller 001 sends the first data to the SoC.
  • the SoC can send a write command to the memory controller 001, and the write command includes the second address and the data to be written.
  • the storage controller 001 determines the storage space corresponding to the second address, and writes the data to be written into the storage space.
  • the second address may be the second physical address, or may be the second logical address. If the second address is the second physical address, after receiving the write instruction, the storage controller 001 directly addresses the volatile storage medium or the non-volatile storage medium according to the second physical address, and determines the storage space corresponding to the second physical address , and write the data to be written into the storage space corresponding to the second physical address.
  • the storage controller 001 determines the second physical address according to the second logical address, and then addresses the volatile storage medium or non-volatile storage medium according to the second physical address.
  • the medium determines the storage space corresponding to the second physical address, and reads the second data from the storage space corresponding to the second physical address.
  • the storage controller 001 may send a response message to the SoC, where the response message is used to indicate that the write operation has been completed.
  • FIG. 4 shows a cross-sectional view of the hybrid memory.
  • FIG. 4 shows a three-dimensional structural diagram of the hybrid memory.
  • it includes a substrate 501, an internal wiring 502, a volatile storage medium group 503 (the volatile storage medium may include multiple, and may be referred to as a volatile storage medium group), a nonvolatile storage medium Type storage medium group 504 (the non-volatile storage medium may include multiple, may be referred to as a non-volatile storage medium group), a storage controller 505 , a housing 506 , a BGA pad 507 and a bus interface 508 .
  • a substrate 501 , a volatile storage medium group 503 , a nonvolatile storage medium group 504 , and a BGA pad 507 are included.
  • a volatile storage medium group 503 and a non-volatile storage medium group 504 may be mounted on the substrate 501 .
  • the volatile storage medium group 503 may be connected to the BGA pad 507 through the interconnection 502 .
  • the non-volatile storage medium group 504 may be connected to the BGA pad 507 through the interconnection 502 .
  • the memory controller 505 may be connected to the substrate 501 through pads 507 .
  • the thickness of the substrate 501 may be 0.15 mm.
  • Volatile storage medium set 503 may include four (4pcs) MicronDDR4 chips using 1Alphanm process node.
  • the storage space size of each MicronDDR4 chip can be 8Gb (ie 1GB).
  • the bond wires (ie, the interconnects 502 ) between the MicronDDR4 chips can be gold wires.
  • the non-volatile storage medium group 504 may include four (4pcs) GlobalFoundry MRAM chips of 28nm process node, and the storage space size of each GlobalFoundry MRAM chip may be 1Gb.
  • the bond wires between the non-volatile storage media ie, the interconnect wires 502) may be gold wires.
  • the storage controller 505 is responsible for communicating with the HOST device (eg, SoC), and is responsible for managing the volatile storage medium group 503 and the non-volatile storage medium group 504 .
  • the storage space size of the hybrid memory may include the sum of the storage space size of the volatile storage medium group 503 (32Gb, ie 4GB) and the storage space size of the nonvolatile storage medium group 504 (4Gb, ie 1GB).
  • the memory controller 505 may be a custom controller developed on the basis of an application specific integrated chip (ASIC) at a 22nm process node.
  • the casing 506 can be made of plastic material, and the device model number can be marked on it.
  • the pitch of the BGA pad 507 may be 0.45mm.
  • the hybrid memory may also include power modules, glue and fillers, etc., which are not shown in FIG. 4 . After the hybrid memory packaging is completed, a package level (Package Level) test can be performed on an automatic test equipment (ATE) machine to ensure the packaging quality
  • the volatile storage medium group in the hybrid memory can support high-speed data processing, and can achieve high read and write performance.
  • the group of non-volatile storage media in the hybrid memory has higher performance and lower power consumption at lower frequencies. Therefore, the use of hybrid memory can improve the read and write performance of electronic devices and reduce power consumption. It can meet the basic demands of low power consumption and high performance of electronic devices on the market.
  • the running program After the next power-on, the running program needs to be imported into the memory for processing before the system can be booted.
  • the hybrid memory When the hybrid memory is powered off, the data in the non-volatile storage medium group in the hybrid memory will not be lost, and the running program can be stored in the non-volatile storage medium group, so that the next time it is turned on, it can be quickly Resuming programs to be run can better reduce standby power consumption and improve startup performance.
  • the above-mentioned hybrid memory can adopt different address allocation modes.
  • the address allocation modes may include parallel mode, shadow mode, mixed mode, and the like.
  • the parallel mode, shadow mode, and hybrid mode are described below.
  • the physical address segments respectively corresponding to the volatile storage medium and the non-volatile storage medium do not overlap (are different).
  • the SoC accesses the hybrid memory, the volatile storage medium and the non-volatile storage medium can be addressed separately.
  • the storage space size of the volatile storage medium and the non-volatile storage medium can be equal or different.
  • the number of physical addresses corresponding to the volatile storage medium may be equal to the number of physical addresses corresponding to the non-volatile storage medium.
  • the volatile storage medium and the nonvolatile storage medium may correspond to physical address segment 1 and physical address segment 2, respectively.
  • Physical address segment 1 includes 0x1-0x4; physical address segment 2 includes 0x5-0x8.
  • the number of physical addresses corresponding to the volatile storage medium may be greater than the number of physical addresses corresponding to the non-volatile storage medium.
  • the volatile storage medium and the nonvolatile storage medium may correspond to physical address segment 1 and physical address segment 2, respectively.
  • Physical address segment 1 includes 0x1-0x5; physical address segment 2 includes 0x6-0x8. This application is not limited. Alternatively, the number of physical addresses corresponding to the volatile storage medium may be less than the number of physical addresses corresponding to the nonvolatile storage medium. As shown in FIG. 6 , the volatile storage medium and the nonvolatile storage medium may correspond to physical address segment 1 and physical address segment 2, respectively. Physical address segment 1 includes 0x1-0x3; physical address segment 2 includes 0x4-0x8.
  • the preset types of data may include, for example, artificial intelligence (artificial intelligence, AI) data for real-time training, models (patterns), training results, and the like.
  • AI artificial intelligence
  • a non-volatile storage medium (eg, FastNVM) of a hybrid memory can write data of a preset type. These data are stored in FastNVM and can be accessed at any time. Even if the system is powered off, the data will not be lost, and there is no need for repeated calculations.
  • the SoC can directly read data of a preset type from the hybrid memory used as memory, and the time it takes is far less than the time and resource consumption of recalculation, and it is also far less than the time spent reading from slow storage. time.
  • the hardware implementation of the hybrid memory in the parallel mode is simple, the internal design is simple, it is easier to implement, and the cost is lower.
  • the physical address segments of the volatile storage medium and the non-volatile storage medium are the same (coincident). That is, the same physical address can point to both a volatile storage medium and a non-volatile storage medium.
  • volatile and non-volatile storage media are equal in size. That is, the number of physical addresses corresponding to the volatile storage medium is equal to the number of physical addresses corresponding to the non-volatile storage medium.
  • the volatile storage medium and the non-volatile storage medium may correspond to physical address segment 1 and physical address segment 2, respectively. Physical address segment 1 includes 0x1-0x4; physical address segment 2 also includes 0x1-0x4.
  • the hybrid memory can implement a variety of data storage modes through the storage controller, including power/performance auto balance mode and data shadow mode. As shown in Table 1, the power/performance auto-balance mode and data shadow mode can be configured through the mode register (MR).
  • MR mode register
  • the hybrid memory can default to a certain mode.
  • a hybrid memory can be defined to default to data shadow mode after power-up.
  • the default is in power/performance auto-balance mode.
  • the default hybrid memory in Table 1 is in the power consumption/performance automatic balance mode after power-on.
  • the SoC when the SoC is at a high frequency (that is, the CPU Clock Speed is higher than the maximum read/write frequency of the non-volatile storage medium), due to the non-volatile storage
  • the maximum read and write frequency of the medium is lower than the main frequency (ie, the speed of processing data of non-volatile storage medium is lower than that of processor), so data is written to volatile storage medium to meet the requirements of fast action.
  • the main frequency of the SoC is reduced, the maximum read and write frequency of the non-volatile storage medium is greater than or equal to the main frequency, that is, the data processing speed of the non-volatile storage medium can reach the processing speed of the processor, so the data can be processed by the processor.
  • the volatile storage medium can enter an extremely low power consumption state to reduce power consumption.
  • the above process can be completed by the storage controller of the hybrid memory, without the need for the SoC to write data to two different types of storage subunits, which can reduce the load on the SoC side and improve the processing performance of the SoC.
  • the storage controller In the data shadow mode, when the SoC is at a high frequency, the data is first written to the volatile storage medium, and then the storage controller automatically transfers the data to the lower-speed non-volatile storage medium; when the system In the low-speed range that the non-volatile storage medium can match, after the data is first written to the non-volatile storage medium, the storage controller automatically transfers the data to the volatile storage medium.
  • the above process can be completed by the storage controller of the hybrid memory without SoC processing, which can reduce the load on the SoC side and improve the processing performance of the SoC.
  • some physical address segments of the hybrid memory can point to both volatile and non-volatile storage media; while other physical address segments only point to volatile or non-volatile storage.
  • one of the mediums As shown in Table 2, the physical address corresponding to the volatile storage medium and the physical address corresponding to the non-volatile storage medium may have various combinations. For example, the combinations may include Combination 1, Combination 2, and Combination 3, respectively.
  • independent addresses can be accessed through direct addressing.
  • Overlapping addresses need to be accessed through the mode register configuration. That is, overlapping addresses need to be determined by the memory controller how to access them. For example, it can be accessed in power/performance auto-balance mode and data shadow mode. This can not only ensure the data processing rate, but also prevent data loss.
  • the overlapping addresses can be flexibly set according to the quantity of important data (such as "user portrait" training data, key context information (context), AI instant training data, etc.) that the electronic device needs to process. If the electronic device needs to process a lot of important data, more overlapping addresses can be set to ensure the processing rate of the important data and avoid the loss of the important data. If the electronic device needs to process less important data, less overlapping addresses can be set to avoid wasting storage space.
  • important data such as "user portrait" training data, key context information (context), AI instant training data, etc.
  • both the volatile storage medium and the nonvolatile storage medium have a part of independent addresses, and at the same time, some addresses overlap.
  • the number of independent addresses included in the volatile storage medium and the number of individual addresses included in the non-volatile storage medium may be the same or different, which is not limited in this application.
  • the volatile storage medium and the non-volatile storage medium may correspond to physical address segment 1 and physical address segment 2, respectively.
  • Physical address segment 1 includes 0x1-0x4.
  • the physical address segment 1 includes independent addresses and overlapping addresses, and the independent addresses include 0x1-0x2; the overlapping addresses include 0x3-0x4.
  • Physical address segment 2 includes 0x3-0x6.
  • the physical address segment 2 includes independent addresses and overlapping addresses, and the independent addresses include 0x5-0x6; the overlapping addresses include 0x3-0x4.
  • the number of independent addresses included in the physical address segment 1 and the number of independent addresses included in the physical address segment 2 may be different, which is not limited in this application.
  • Combination 1 is suitable for complex multi-core electronic devices such as mobile phones and tablets.
  • the CPU of the electronic device can read and write in the storage space (for example, 4-8 GB) indicated by the independent address of the volatile storage medium when the main frequency is high, so as to meet the requirement of fast data processing.
  • Important data such as "user portrait" training data, key context information (context), AI real-time training data, etc.
  • the boot code of the Boot stage can be stored in a storage space (for example, 128MB) indicated by an independent address of the non-volatile storage medium, so as to realize fast startup.
  • the volatile storage medium and the non-volatile storage medium may correspond to physical address segment 1 and physical address segment 2 respectively.
  • Physical address segment 1 includes 0x1-0x6.
  • the physical address segment 1 includes independent addresses and overlapping addresses.
  • the independent addresses include 0x1-0x2 and 0x5-0x6; the overlapping addresses include 0x3-0x4.
  • Physical address segment 2 includes 0x3-0x4.
  • Physical address segment 2 includes only coincident addresses, ie 0x3-0x4.
  • Combination 2 is also suitable for complex multi-core electronic devices such as mobile phones and tablets. And when the hybrid memory adopts the combination 2, the manufacturing cost is lower than that of the combination 1. Since the non-volatile storage medium does not have an independent address, the boot code in the Boot phase needs to be stored in the storage space indicated by the overlapping address, so that when the electronic device is booted in the Boot phase, the volatile storage medium needs to be in a ready state, which increases the ease of use. The current consumption of the deformable storage medium. However, the additional power consumption added here is small compared to the operating state where the electronic device is in operation most of the time, and the cost reduction of the chip is better.
  • the non-volatile storage medium has a part of independent addresses, and a part of the addresses of the non-volatile storage medium and the volatile storage medium completely overlap.
  • the volatile storage medium and the non-volatile storage medium may correspond to physical address segment 1 and physical address segment 2 respectively.
  • Physical address segment 1 includes 0x1-0x2.
  • Physical address segment 1 includes only coincident addresses, ie 0x1-0x2.
  • the physical address segment 2 includes independent addresses and overlapping addresses.
  • the independent addresses include 0x3-0x4 and 0x5-0x6; the overlapping addresses include 0x1-0x2.
  • Combination 3 is suitable for wearable devices, IoT devices, etc.
  • the main frequency of the processors of wearable devices and IoT devices is usually lower than the maximum read and write frequency of non-volatile storage media, so most of the data can be stored in the storage space indicated by the independent address of the non-volatile storage media (for example, 256MB) Read and write processing.
  • Data that requires high-speed processing (such as instant training data such as speech recognition) can be processed in the storage space indicated by the coincident address (for example, 128MB), that is, it can be processed in the storage space of the volatile storage medium, so as to obtain power without loss, No need for repeated training, fast recovery effect.
  • the processed operation results can be stored in non-volatile memory to avoid loss.
  • the hybrid memory when the hybrid memory is powered off and then powered on, the data in the physical address segment of the non-volatile storage medium is still retained. If there is a separate volatile memory address segment, the previous data is lost after power-on.
  • the mixed mode allows volatile storage media and non-volatile storage media to multiplex physical addresses according to actual needs, which is more flexible and convenient.
  • the Soc can use the hybrid memory of the parallel mode as a shadow mode or a hybrid mode by means of software according to actual requirements, which is not limited in this application.
  • the embodiment of the present application also provides an electronic device, in which the above-mentioned hybrid memory can be set, and the electronic device can be, for example, a mobile phone, a tablet computer, a desktop computer, a laptop computer, an ultra-mobile personal computer (ultra-mobile personal computer) computer, UMPC), handheld computer, netbook, personal digital assistant (personal digital assistant, PDA) and other devices.
  • the electronic device can be, for example, a mobile phone, a tablet computer, a desktop computer, a laptop computer, an ultra-mobile personal computer (ultra-mobile personal computer) computer, UMPC), handheld computer, netbook, personal digital assistant (personal digital assistant, PDA) and other devices.
  • the electronic device 200 may include: a processor 210, an external memory interface 220, a hybrid memory 221, a universal serial bus (USB) interface 230, a charge management module 240, a power management module 241, a battery 242, an antenna 1, an antenna 2.
  • Mobile communication module 250 wireless communication module 260, audio module 270, speaker 270A, receiver 270B, microphone 270C, headphone jack 270D, sensor module 280, buttons 290, motor 291, indicator 292, camera 293, display screen 294, And a subscriber identification module (subscriber identification module, SIM) card interface 295 and so on.
  • SIM subscriber identification module
  • the above-mentioned sensor module 280 may include sensors such as a pressure sensor, a gyroscope sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor and a bone conduction sensor.
  • sensors such as a pressure sensor, a gyroscope sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor and a bone conduction sensor.
  • the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device 200 .
  • the electronic device 200 may include more or fewer components than shown, or combine some components, or separate some components, or different component arrangements.
  • the illustrated components may be implemented in hardware, software, or a combination of software and hardware.
  • the processor 210 may include one or more processing units, for example, the processor 210 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), controller, memory, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural-network processing unit (NPU) Wait. Wherein, different processing units may be independent devices, or may be integrated in one or more processors.
  • application processor application processor, AP
  • modem processor graphics processor
  • ISP image signal processor
  • controller memory
  • video codec digital signal processor
  • DSP digital signal processor
  • NPU neural-network processing unit
  • the controller may be the nerve center and command center of the electronic device 200 .
  • the controller can generate an operation control signal according to the instruction operation code and timing signal, and complete the control of fetching and executing instructions.
  • a memory may also be provided in the processor 210 for storing instructions and data.
  • the memory in processor 210 is cache memory.
  • the memory may hold instructions or data that have just been used or recycled by the processor 210 . If the processor 210 needs to use the instruction or data again, it can be called directly from the memory. Repeated accesses are avoided, and the waiting time of the processor 210 is reduced, thereby improving the efficiency of the system.
  • the processor 210 may include one or more interfaces.
  • the interface may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous transceiver (universal asynchronous transmitter) receiver/transmitter, UART) interface, mobile industry processor interface (MIPI), general-purpose input/output (GPIO) interface, subscriber identity module (SIM) interface, and / or universal serial bus (universal serial bus, USB) interface, etc.
  • I2C integrated circuit
  • I2S integrated circuit built-in audio
  • PCM pulse code modulation
  • PCM pulse code modulation
  • UART universal asynchronous transceiver
  • MIPI mobile industry processor interface
  • GPIO general-purpose input/output
  • SIM subscriber identity module
  • USB universal serial bus
  • the interface connection relationship between the modules illustrated in this embodiment is only a schematic illustration, and does not constitute a structural limitation of the electronic device 200 .
  • the electronic device 200 may also adopt different interface connection manners in the foregoing embodiments, or a combination of multiple interface connection manners.
  • the charging management module 240 is used to receive charging input from the charger.
  • the charger may be a wireless charger or a wired charger. While the charging management module 240 charges the battery 242 , the power management module 241 can also supply power to the electronic device.
  • the power management module 241 is used to connect the battery 242 , the charging management module 240 and the processor 210 .
  • the power management module 241 receives input from the battery 242 and/or the charge management module 240, and supplies power to the processor 210, the hybrid memory 221, the external memory, the display screen 294, the camera 293, and the wireless communication module 260.
  • the power management module 241 and the charging management module 240 may also be provided in the same device.
  • the wireless communication function of the electronic device 200 may be implemented by the antenna 1, the antenna 2, the mobile communication module 250, the wireless communication module 260, the modulation and demodulation processor, the baseband processor, and the like.
  • the antenna 1 of the electronic device 200 is coupled with the mobile communication module 250
  • the antenna 2 is coupled with the wireless communication module 260, so that the electronic device 200 can communicate with the network and other devices through wireless communication technology.
  • Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals.
  • Each antenna in electronic device 200 may be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization.
  • the antenna 1 can be multiplexed as a diversity antenna of the wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.
  • the mobile communication module 250 may provide a wireless communication solution including 2G/3G/4G/5G, etc. applied on the electronic device 200 .
  • the mobile communication module 250 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), and the like.
  • the mobile communication module 250 can receive electromagnetic waves from the antenna 1, filter and amplify the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation.
  • the mobile communication module 250 can also amplify the signal modulated by the modulation and demodulation processor, and then convert it into electromagnetic waves for radiation through the antenna 1 .
  • at least part of the functional modules of the mobile communication module 250 may be provided in the processor 210 .
  • at least part of the functional modules of the mobile communication module 250 may be provided in the same device as at least part of the modules of the processor 210 .
  • the wireless communication module 260 can provide applications on the electronic device 200 including WLAN (such as (wireless fidelity, Wi-Fi) network), Bluetooth (bluetooth, BT), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation ( frequency modulation, FM), near field communication technology (near field communication, NFC), infrared technology (infrared, IR) and other wireless communication solutions.
  • WLAN such as (wireless fidelity, Wi-Fi) network
  • Bluetooth bluetooth, BT
  • global navigation satellite system global navigation satellite system, GNSS
  • frequency modulation frequency modulation, FM
  • near field communication technology near field communication, NFC
  • infrared technology infrared, IR
  • the wireless communication module 260 may be one or more devices integrating at least one communication processing module.
  • the wireless communication module 260 receives electromagnetic waves via the antenna 2 , modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 210 .
  • the wireless communication module 260 can also receive the signal to be sent from the processor 210 , perform frequency modulation on the signal, amplify the signal, and then convert it into an electromagnetic wave for radiation through the antenna 2 .
  • the electronic device 200 implements a display function through a GPU, a display screen 294, an application processor, and the like.
  • the GPU is a microprocessor for image processing, and is connected to the display screen 294 and the application processor.
  • the GPU is used to perform mathematical and geometric calculations for graphics rendering.
  • Processor 210 may include one or more GPUs that execute program instructions to generate or alter display information.
  • Display screen 294 is used to display images, videos, and the like.
  • the display screen 294 includes a display panel.
  • the electronic device 200 can realize the shooting function through the ISP, the camera 293, the video codec, the GPU, the display screen 294 and the application processor.
  • the ISP is used to process the data fed back by the camera 293 .
  • Camera 293 is used to capture still images or video.
  • the electronic device 200 may include 1 or N cameras 293 , where N is a positive integer greater than 1.
  • the external memory interface 220 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 200.
  • the external memory card communicates with the processor 210 through the external memory interface 220 to realize the data storage function. For example to save files like music, video etc in external memory card.
  • Hybrid memory 221 may be used to store computer executable program code including instructions.
  • the processor 210 executes various functional applications and data processing of the electronic device 200 by executing the instructions stored in the hybrid memory 221 .
  • the processor 210 may execute instructions stored in the hybrid memory 221, and the hybrid memory 221 may include a program storage area and a data storage area.
  • the storage program area can store an operating system, an application program required for at least one function (such as a sound playback function, an image playback function, etc.), and the like.
  • the storage data area can store data (such as audio data, phone book, etc.) created during the use of the electronic device 200 and the like.
  • the hybrid memory 221 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, universal flash storage (UFS), and the like.
  • the electronic device 200 may implement audio functions through an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, an earphone interface 270D, and an application processor. Such as music playback, recording, etc.
  • the keys 290 include a power-on key, a volume key, and the like. Keys 290 may be mechanical keys. It can also be a touch key. Motor 291 can generate vibrating cues. The motor 291 can be used for vibrating alerts for incoming calls, and can also be used for touch vibration feedback. The indicator 292 can be an indicator light, which can be used to indicate the charging status, the change of power, and can also be used to indicate messages, missed calls, notifications, and the like.
  • the SIM card interface 295 is used to connect a SIM card. The SIM card can be contacted and separated from the electronic device 200 by inserting into the SIM card interface 295 or pulling out from the SIM card interface 295 .
  • the electronic device 200 may support 1 or N SIM card interfaces, where N is a positive integer greater than 1.
  • the SIM card interface 295 can support Nano SIM card, Micro SIM card, SIM card and so on.
  • the mobile phone 100 described above may have more or fewer components than those shown in FIG. 12 , may combine two or more components, or may have different component configurations.
  • the various components shown in Figure 12 may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing or application specific integrated circuits.
  • This embodiment also provides a computer storage medium, where computer instructions are stored in the computer storage medium, and when the computer instructions are executed on the electronic device, the electronic device executes the above-mentioned relevant method steps to implement the methods in the above-mentioned embodiments.
  • This embodiment also provides a computer program product, which when the computer program product runs on a computer, causes the computer to execute the above-mentioned relevant steps, so as to implement the method in the above-mentioned embodiment.
  • the embodiments of the present application also provide an apparatus, which may specifically be a chip, a component or a module, and the apparatus may include a connected processor and a memory; wherein, the memory is used for storing computer execution instructions, and when the apparatus is running, The processor can execute the computer-executed instructions stored in the memory, so that the chip executes the methods in the foregoing method embodiments.
  • the electronic device, computer storage medium, computer program product or chip provided in this embodiment are all used to execute the corresponding method provided above. Therefore, for the beneficial effects that can be achieved, reference can be made to the corresponding provided above. The beneficial effects in the method will not be repeated here.
  • the disclosed apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of modules or units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or May be integrated into another device, or some features may be omitted, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • Units described as separate components may or may not be physically separated, and components shown as units may be one physical unit or multiple physical units, that is, may be located in one place, or may be distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be realized in the form of hardware, and can also be realized in the form of software functional units.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a readable storage medium.
  • a readable storage medium including several instructions to make a device (which may be a single chip microcomputer, a chip, etc.) or a processor (processor) to execute all or part of the steps of the methods in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), RAM, magnetic disk or optical disk and other media that can store program codes.

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Abstract

一种数据读写方法和混合型存储器，涉及终端领域，能够提升读写性能和降低功耗。该混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质。易失性存储介质的物理地址段与非易失性存储介质的物理地址段不同。存储控制器可以从处理器接收读/写指令，该读/写指令中携带第一地址(第一地址可以是物理地址或逻辑地址)；若第一地址对应易失型存储介质的存储空间，存储控制器可以在易失型存储介质的存储空间进行数据读写处理；若第一地址对应非易失型存储介质的存储空间，存储控制器可以在非易失型存储介质的存储空间进行数据读写处理。

Description

一种数据读写方法和混合型存储器
本申请要求于2021年02月09日提交国家知识产权局、申请号为202110182302.5、发明名称为“一种混合易失型与非易失型存储介质的器件实现方法及其装置”的中国专利申请的优先权，以及于2021年06月11日提交国家知识产权局、申请号为202110654001.8、发明名称为“一种数据读写方法和混合型存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及终端领域，尤其涉及一种数据读写方法和混合型存储器。
背景技术
目前，各种电子设备(诸如智能手机、平板电脑等)中存在两种存储介质，分别为易失性存储器(volatile memory，VM)和非易失性存储器(none volatile memory，NVM)。易失性存储器可以包括随机访问存储器(radom access memory，RAM)。RAM例如可以是双倍数据速率(dual data rate，DDR)内存。易失性存储器当系统遭遇突然掉电时，其存储的内容会丢失。非易失性存储器例如可以包括硬盘驱动器(hard drive disk，HDD)和固态硬盘(solid state disk，SSD)等。非易失性存储器在关闭计算机或者突然性、意外性关闭计算机的时候数据不会丢失。
易失性存储器和非易失性存储器存在以下问题：易失性存储器在读写数据时会消耗较高的功耗，非易失性存储器在读写数据时会遇到较长的延迟和等待，读写性能低。
发明内容
本申请实施例提供一种数据读写方法和混合型存储器，能够提升读写性能和降低功耗。
第一方面，本申请实施例提供一种混合型存储器，混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；易失性存储介质的物理地址段与非易失性存储介质的物理地址段不同；存储控制器用于从处理器接收读/写指令，读/写指令中携带第一地址；第一地址对应易失型存储介质的存储空间或非易失型存储介质的存储空间；若第一地址对应易失型存储介质的存储空间，存储控制器用于将数据写入易失型存储介质的存储空间或者从易失型存储介质的存储空间读取数据；若第一地址对应非易失型存储介质的存储空间，存储控制器用于将数据写入非易失型存储介质的存储空间或者从非易失型存储介质的存储空间读取数据。
本申请实施例提供的混合型存储器中的易失型存储介质组可以支持高速处理数据，可以实现高读写性能。混合型存储器中的非易失型存储介质组在较低的频率下具有较高性能和较低功耗。因此，采用混合型存储器可以提升电子设备读写性能和降低功耗。可以满足市场上的电子设备的低功耗和高性能的基本诉求。并且，混合型存储器硬件实现简单，内部设计简单，成本低。
在一种可能的实现方式中，混合型存储器还包括总线、基板、封装外壳和总线接口中的至少一项；其中，存储控制器、易失型存储介质和非易失型存储介质集成在基板上，易 失型存储介质和非易失型存储介质之间通过总线连接，存储控制器、易失型存储介质和非易失型存储介质、总线以及基板封装在封装外壳内部，封装外壳006对外呈现总线接口，总线接口用于与处理器连接。混合型存储器硬件实现简单，内部设计简单，更易实现，成本更低。
在一种可能的实现方式中，易失型存储介质包括双倍数据速率DDR内存，DDR2，DDR3，DDR4，高带宽存储器(high bandwidth memory，HBM)、动态随机存取存储器(dynamic random access memory，DRAM)、3D超级DRAM(Super-DRAM)中的至少一种；非易失型存储介质包括单层式存储闪存/单层单元闪存(single level cell，SLC)-NAND，磁性随机存取存储器(magnetic radom access memory，MRAM)，阻变随机存取存储器(resistance radom access memory，RRAM)，相变随机存取存储器(phase change radom access memory，PCRAM)、3D-Xpoint存储介质或3D-SLC NAND闪存存储器中的至少一种。本申请实施例不限定易失型存储介质或非易失型存储介质的种类。
在一种可能的实现方式中，混合型存储器作为内存安装在电子设备中。程序数据在运行过程中可保存在混合型存储器中。这样，当电子设备采用混合型存储器作为内存时，混合型存储器中的易失型存储介质组可以支持高速处理数据，可以实现高读写性能。混合型存储器中的非易失型存储介质组在较低的频率下具有较高性能和较低功耗。因此，采用混合型存储器可以提升电子设备读写性能和降低功耗。可以满足市场上的电子设备的低功耗和高性能的基本诉求。
在一种可能的实现方式中，电子设备息屏时，混合存储器下电。传统内存(例如，以RAM为内存)在息屏状态下不能完全断电，否则会导致内存中的数据丢失。本申请实施例提供的混合型存储器的非易失型存储介质组的数据不会丢失，可以将有用数据存储在非易失型存储介质组中，这样电子设备在息屏状态下可以完全断电，能够大幅降低功耗。并且，传统内存下电时，内存中的数据会丢失。下次开机上电后，需要把运行的程序导入到内存中进行处理，才能引导系统开机。当混合型存储器下电时，混合型存储器中的非易失型存储介质组的数据并不丢失，可以将运行的程序存储在非易失型存储介质组中，这样，下次开机时可以快速恢复待运行的程序，可以更好地降低待机功耗和提升启动性能。
在一种可能的实现方式中，非易失性存储介质用于存储预设类型的数据，预设类型的数据包括即时训练的人工智能AI数据、模型与训练结果中的至少一项。相比现有技术，上电后需要重新计算预设类型的数据导致功耗消耗，或者从慢速的Storage读取预设类型的数据导致效率低下。本申请实施例中，SoC可以从作为内存的混合型存储器中直接读取预设类型的数据，其花费的时间远小于重新计算的时间资源消耗，也远小于从慢速的Storage读取所花费的时间。
在一种可能的实现方式中，第一地址为物理地址或逻辑地址；若第一地址为逻辑地址，存储控制器还用于将逻辑地址转换为物理地址。若第一地址为物理地址，存储控制器可以直接根据物理地址寻址易失型存储介质或非易失型存储介质，确定物理地址对应的存储空间。当第一地址为逻辑地址时，存储控制器还用于将逻辑地址转换为物理地址，再根据物理地址寻址易失型存储介质或非易失型存储介质，确定物理地址对应的存储空间。
第二方面，本申请实施例提供一种混合型存储器，混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；易失性存储介质的物理地址段与非易失性存储介质的 物理地址段相同；存储控制器从处理器接收读/写指令，读/写指令中携带第一地址；若处理器的主频大于非易失型存储介质的最高读写频率，存储控制器用于将数据写入易失型存储介质的存储空间或者从易失型存储介质的存储空间读取数据；若处理器的主频小于或等于非易失型存储介质的最高读写频率，存储控制器用于将数据写入非易失型存储介质的存储空间或者从非易失型存储介质的存储空间读取数据。
这样，当处理器处于高主频(即处理器工作的时钟频率高于非易失型存储介质的最高读写频率)时，由于非易失型存储介质的最高读写频率小于主频(即非易失型存储介质的处理数据的速度低于处理器处理数据的速度)，因此数据被写入易失型存储介质，以满足快速动作的要求。当处理器的主频降低时，非易失型存储介质的最高读写频率大于或等于主频，即非易失型存储介质的处理数据的速度可以达到处理器处理数据的速度，因此数据可以被写入非易失型存储介质，以获得更低的功耗表现。此时易失型存储介质可以进入极低功耗状态，可以达到降低功耗的效果。
在一种可能的实现方式中，若处理器的主频大于非易失型存储介质的最高读写频率，存储控制器还用于将写入易失型存储介质的存储空间的数据写入非易失型存储介质的存储空间；若处理器的主频小于或等于非易失型存储介质的最高读写频率，存储控制器还用于将写入非易失型存储介质的存储空间的数据写入易失型存储介质的存储空间。
即当处理器处于高主频时，数据先被写入易失型存储介质后，再由存储控制器自动将数据转写到速率较低的非易失型存储介质；当系统处于非易失型存储介质能够匹配的低速率范围时，数据先被写入非易失型存储介质后，再由存储控制器自动将数据转写入易失型存储介质。上述过程可以由混合存储器的存储控制器完成，无需处理器处理，可以降低处理器侧的负载，提高处理器的处理性能。
在一种可能的实现方式中，混合型存储器还包括总线、基板、封装外壳和总线接口中的至少一项；其中，存储控制器、易失型存储介质和非易失型存储介质集成在基板上，易失型存储介质和非易失型存储介质之间通过总线连接，存储控制器、易失型存储介质和非易失型存储介质、总线以及基板封装在封装外壳内部，封装外壳006对外呈现总线接口，总线接口用于与处理器连接。
在一种可能的实现方式中，易失型存储介质包括双倍数据速率DDR内存，DDR2，DDR3，DDR4，高带宽存储器HBM、动态随机存取存储器DRAM或3D超级DRAM中的至少一种；非易失型存储介质包括单层式存储闪存SLC-NAND，磁性随机存取存储器MRAM，阻变随机存取存储器RRAM，相变随机存取存储器PCRAM、3D-Xpoint存储介质或3D-SLC NAND闪存存储器中的至少一种。
在一种可能的实现方式中，混合型存储器作为内存安装在电子设备中。
在一种可能的实现方式中，电子设备息屏时，混合存储器下电。
在一种可能的实现方式中，非易失性存储介质用于存储预设类型的数据，预设类型的数据包括即时训练的人工智能AI数据、模型与训练结果中的至少一项。
在一种可能的实现方式中，第一地址为物理地址或逻辑地址；若第一地址为逻辑地址，存储控制器还用于将逻辑地址转换为物理地址。
第三方面，本申请实施例提供一种混合型存储器，混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；易失性存储介质的物理地址段与非易失性存储介质的 物理地址段部分相同；存储控制器从处理器接收读/写指令，读/写指令中携带第一地址；在第一地址同时对应非易失性存储介质和易失性存储介质的存储空间的情况下，若处理器的主频大于非易失型存储介质的最高读写频率，存储控制器用于将数据写入易失型存储介质的存储空间或者从易失型存储介质的存储空间读取数据；若处理器的主频小于或等于非易失型存储介质的最高读写频率，存储控制器用于将数据写入非易失型存储介质的存储空间或者从非易失型存储介质的存储空间读取数据；在第一地址对应非易失性存储介质或易失性存储介质的存储空间的情况下，若第一地址对应易失型存储介质的存储空间，存储控制器用于将数据写入易失型存储介质的存储空间或者从易失型存储介质的存储空间读取数据；若第一地址对应非易失型存储介质的存储空间，存储控制器用于将数据写入非易失型存储介质的存储空间或者从非易失型存储介质的存储空间读取数据。
本申请实施例中，混合型存储器接收到第一地址后，在第一地址同时对应非易失性存储介质和易失性存储介质的存储空间的情况下，当处理器处于高主频(即处理器工作的时钟频率高于非易失型存储介质的最高读写频率)时，由于非易失型存储介质的最高读写频率小于主频(即非易失型存储介质的处理数据的速度低于处理器处理数据的速度)，因此数据被写入易失型存储介质，以满足快速动作的要求。当处理器的主频降低时，非易失型存储介质的最高读写频率大于或等于主频，即非易失型存储介质的处理数据的速度可以达到处理器处理数据的速度，因此数据可以被写入非易失型存储介质，以获得更低的功耗表现。此时易失型存储介质可以进入极低功耗状态，可以达到降低功耗的效果。
在第一地址对应非易失性存储介质或易失性存储介质的存储空间的情况下，可以直接从第一地址指示的非易失性存储介质或易失性存储介质的存储空间读写数据。其中，易失型存储介质组可以支持高速处理数据，可以实现高读写性能。混合型存储器中的非易失型存储介质组在较低的频率下具有较高性能和较低功耗。因此，采用混合型存储器可以提升电子设备读写性能和降低功耗。可以满足市场上的电子设备的低功耗和高性能的基本诉求。
在一种可能的实现方式中，若处理器的主频大于非易失型存储介质的最高读写频率，存储控制器还用于将写入易失型存储介质的存储空间的数据写入非易失型存储介质的存储空间；若处理器的主频小于或等于非易失型存储介质的最高读写频率，存储控制器还用于将写入非易失型存储介质的存储空间的数据写入易失型存储介质的存储空间。
在一种可能的实现方式中，混合型存储器还包括总线、基板、封装外壳和总线接口中的至少一项；其中，存储控制器、易失型存储介质和非易失型存储介质集成在基板上，易失型存储介质和非易失型存储介质之间通过总线连接，存储控制器、易失型存储介质和非易失型存储介质、总线以及基板封装在封装外壳内部，封装外壳006对外呈现总线接口，总线接口用于与处理器连接。
在一种可能的实现方式中，易失型存储介质包括双倍数据速率DDR内存，DDR2，DDR3，DDR4，高带宽存储器HBM、动态随机存取存储器DRAM或3D超级DRAM中的至少一种；非易失型存储介质包括单层式存储闪存SLC-NAND，磁性随机存取存储器MRAM，阻变随机存取存储器RRAM，相变随机存取存储器PCRAM、3D-Xpoint存储介质或3D-SLC NAND闪存存储器中的至少一种。
在一种可能的实现方式中，混合型存储器作为内存安装在电子设备中。
在一种可能的实现方式中，电子设备息屏时，混合存储器下电。
在一种可能的实现方式中，非易失性存储介质用于存储预设类型的数据，预设类型的数据包括即时训练的人工智能AI数据、模型与训练结果中的至少一项。
在一种可能的实现方式中，第一地址为物理地址或逻辑地址；若第一地址为逻辑地址，存储控制器还用于将逻辑地址转换为物理地址。
第四方面，本申请实施例提供一种数据读写方法，应用于混合型存储器，混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；易失性存储介质的物理地址段与非易失性存储介质的物理地址段不同；方法包括：存储控制器从处理器接收读/写指令，读/写指令中携带第一地址；若第一地址对应易失型存储介质的存储空间，存储控制器将数据写入易失型存储介质的存储空间或者从易失型存储介质的存储空间读取数据；若第一地址对应非易失型存储介质的存储空间，存储控制器将数据写入非易失型存储介质的存储空间或者从非易失型存储介质的存储空间读取数据。
在一种可能的实现方式中，混合型存储器还包括总线、基板、封装外壳和总线接口中的至少一项；其中，存储控制器、易失型存储介质和非易失型存储介质集成在基板上，易失型存储介质和非易失型存储介质之间通过总线连接，存储控制器、易失型存储介质和非易失型存储介质、总线以及基板封装在封装外壳内部，封装外壳006对外呈现总线接口，总线接口用于与处理器连接。
在一种可能的实现方式中，易失型存储介质包括双倍数据速率DDR内存，DDR2，DDR3，DDR4，高带宽存储器HBM、动态随机存取存储器DRAM或3D超级DRAM中的至少一种；非易失型存储介质包括单层式存储闪存SLC-NAND，磁性随机存取存储器MRAM，阻变随机存取存储器RRAM，相变随机存取存储器PCRAM、3D-Xpoint存储介质或3D-SLC NAND闪存存储器中的至少一种。
在一种可能的实现方式中，混合型存储器作为内存安装在电子设备中。
在一种可能的实现方式中，电子设备息屏时，混合存储器下电。
在一种可能的实现方式中，非易失性存储介质用于存储预设类型的数据，预设类型的数据包括即时训练的人工智能AI数据、模型与训练结果中的至少一项。
在一种可能的实现方式中，第一地址为物理地址或逻辑地址；若第一地址为逻辑地址，存储控制器还用于将逻辑地址转换为物理地址。
第五方面，本申请实施例提供一种数据读写方法，应用于混合型存储器，混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；易失性存储介质的物理地址段与非易失性存储介质的物理地址段相同；方法包括：存储控制器从处理器接收读/写指令，读/写指令中携带第一地址；若处理器的主频大于非易失型存储介质的最高读写频率，存储控制器将数据写入易失型存储介质的存储空间或者从易失型存储介质的存储空间读取数据；若处理器的主频小于或等于非易失型存储介质的最高读写频率，存储控制器将数据写入非易失型存储介质的存储空间或者从非易失型存储介质的存储空间读取数据。
在一种可能的实现方式中，若处理器的主频大于非易失型存储介质的最高读写频率，存储控制器还用于将写入易失型存储介质的存储空间的数据写入非易失型存储介质的存储空间；若处理器的主频小于或等于非易失型存储介质的最高读写频率，存储控制器还用于将写入非易失型存储介质的存储空间的数据写入易失型存储介质的存储空间。
在一种可能的实现方式中，混合型存储器还包括总线、基板、封装外壳和总线接口中 的至少一项；其中，存储控制器、易失型存储介质和非易失型存储介质集成在基板上，易失型存储介质和非易失型存储介质之间通过总线连接，存储控制器、易失型存储介质和非易失型存储介质、总线以及基板封装在封装外壳内部，封装外壳006对外呈现总线接口，总线接口用于与处理器连接。
在一种可能的实现方式中，易失型存储介质包括双倍数据速率DDR内存，DDR2，DDR3，DDR4，高带宽存储器HBM、动态随机存取存储器DRAM或3D超级DRAM中的至少一种；非易失型存储介质包括单层式存储闪存SLC-NAND，磁性随机存取存储器MRAM，阻变随机存取存储器RRAM，相变随机存取存储器PCRAM、3D-Xpoint存储介质或3D-SLC NAND闪存存储器中的至少一种。
在一种可能的实现方式中，混合型存储器作为内存安装在电子设备中。
在一种可能的实现方式中，电子设备息屏时，混合存储器下电。
在一种可能的实现方式中，非易失性存储介质用于存储预设类型的数据，预设类型的数据包括即时训练的人工智能AI数据、模型与训练结果中的至少一项。
在一种可能的实现方式中，第一地址为物理地址或逻辑地址；若第一地址为逻辑地址，存储控制器还用于将逻辑地址转换为物理地址。
第六方面，本申请实施例提供一种数据读写方法，应用于混合型存储器，混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；易失性存储介质的物理地址段与非易失性存储介质的物理地址段部分相同；方法包括：存储控制器从处理器接收读/写指令，读/写指令中携带第一地址；在第一地址同时对应非易失性存储介质和易失性存储介质的存储空间的情况下，若处理器的主频大于非易失型存储介质的最高读写频率，存储控制器将数据写入易失型存储介质的存储空间或者从易失型存储介质的存储空间读取数据；若处理器的主频小于或等于非易失型存储介质的最高读写频率，存储控制器将数据写入非易失型存储介质的存储空间或者从非易失型存储介质的存储空间读取数据；在第一地址对应非易失性存储介质或易失性存储介质的存储空间的情况下，若第一地址对应易失型存储介质的存储空间，存储控制器将数据写入易失型存储介质的存储空间或者从易失型存储介质的存储空间读取数据；若第一地址对应非易失型存储介质的存储空间，存储控制器将数据写入非易失型存储介质的存储空间或者从非易失型存储介质的存储空间读取数据。
在一种可能的实现方式中，若处理器的主频大于非易失型存储介质的最高读写频率，存储控制器还用于将写入易失型存储介质的存储空间的数据写入非易失型存储介质的存储空间；若处理器的主频小于或等于非易失型存储介质的最高读写频率，存储控制器还用于将写入非易失型存储介质的存储空间的数据写入易失型存储介质的存储空间。
在一种可能的实现方式中，混合型存储器还包括总线、基板、封装外壳和总线接口中的至少一项；其中，存储控制器、易失型存储介质和非易失型存储介质集成在基板上，易失型存储介质和非易失型存储介质之间通过总线连接，存储控制器、易失型存储介质和非易失型存储介质、总线以及基板封装在封装外壳内部，封装外壳006对外呈现总线接口，总线接口用于与处理器连接。
在一种可能的实现方式中，易失型存储介质包括双倍数据速率DDR内存，DDR2，DDR3，DDR4，高带宽存储器HBM、动态随机存取存储器DRAM或3D超级DRAM中的至少一种；非易失型存储介质包括单层式存储闪存SLC-NAND，磁性随机存取存储器 MRAM，阻变随机存取存储器RRAM，相变随机存取存储器PCRAM、3D-Xpoint存储介质或3D-SLC NAND闪存存储器中的至少一种。
在一种可能的实现方式中，混合型存储器作为内存安装在电子设备中。
在一种可能的实现方式中，电子设备息屏时，混合存储器下电。
在一种可能的实现方式中，非易失性存储介质用于存储预设类型的数据，预设类型的数据包括即时训练的人工智能AI数据、模型与训练结果中的至少一项。
在一种可能的实现方式中，第一地址为物理地址或逻辑地址；若第一地址为逻辑地址，存储控制器还用于将逻辑地址转换为物理地址。
第七方面，本申请实施例提供一种电子设备，其特征在于，包括处理器、混合型存储器和总线，其中，处理器、混合型存储器之间通过总线互相连接，混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；其中，混合型存储器用于存储计算机程序代码，计算机程序代码包括计算机指令；当计算机指令被处理器执行时，使得处理器和混合型存储器执行上述第三方面至第五方面提供的任意一种方法。
第八方面，本申请实施例提供一种计算机可读存储介质，包括指令，当其在计算机上运行时，使得计算机执行上述第三方面至第五方面提供的任意一种方法。
第九方面，本申请实施例提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第三方面至第五方面提供的任意一种方法。
第十方面，本申请实施例提供了一种芯片系统，该芯片系统包括处理器，还可以包括存储器，用于实现上述第三方面至第五方面提供的任意一种方法。该芯片系统可以由芯片构成，也可以包含芯片和其他分立器件。
附图说明
图1为本申请实施例提供的一种混合型存储器的结构示意图；
图2为本申请实施例提供的一种信号交互示意图；
图3为本申请实施例提供的一种信号交互示意图；
图4为本申请实施例提供的一种混合型存储器的剖面图和三维结构图；
图5为本申请实施例提供的一种混合型存储器的物理地址段示意图；
图6为本申请实施例提供的又一种混合型存储器的物理地址段示意图；
图7为本申请实施例提供的又一种混合型存储器的物理地址段示意图；
图8为本申请实施例提供的又一种混合型存储器的物理地址段示意图；
图9为本申请实施例提供的一种混合型存储器的物理地址段示意图；
图10为本申请实施例提供的一种混合型存储器的物理地址段示意图；
图11为本申请实施例提供的一种混合型存储器的物理地址段示意图；
图12为本申请实施例提供的一种电子设备的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。其中，在本申请的描述中，除非另有说明，“至少一个”是指一个或多个，“多个”是指两个或多于两个。另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二” 等字样也并不限定一定不同。
目前，常用于数据快速存取的RAM是双倍数据速率同步动态随机存取内存(DDR synchronous dynamic random access memory，DDR-SDRAM)。由于半导体漏电的原因，DDR-SDRAM需要不断地刷新所保存的数据(即定期将数据重写一遍)，功耗消耗较高。当系统突然掉电(断电)时，其存储的内容会丢失。而能够持久存取数据的存储器(Storage)处理数据的速度慢。当系统要将数据写入Storage时，通常会遇到较长的延迟和等待。例如，关键数据的同步写盘命令(SyncWrite)会导致Storage的输入输出(Input output，IO)性能瞬间下降。
本申请实施例提供一种混合型存储器(也可以称为异构存储器或者混合异构存储器，本申请不做限定)，可以作为内存器件灵活使用，能够提升操作系统(operating system,OS)的读写性能，也能够提高以混合型存储器为存储介质的数据库的性能。并且，能够使快速存取的数据掉电不丢失，可实现写入完成后即可断电，节省功耗。
如图1所示，本申请实施例提供一种混合型存储器100。混合型存储器100可以包括存储控制器(controller)001、易失型存储介质002、非易失型存储介质003、总线004、基板(substrate)005、封装外壳(package)006和总线接口007。其中，易失型存储介质002和非易失型存储介质003可以连接到存储控制器001上。存储控制器001、易失型存储介质002和非易失型存储介质003可以集成在基板005上。易失型存储介质002和非易失型存储介质003之间可以通过总线004连接。存储控制器001、易失型存储介质002和非易失型存储介质003、总线004以及基板005可以封装在封装外壳006内部，封装外壳006可以对外呈现出总线接口007。
其中，易失型存储介质可以包括DDR内存(简称DDR)，DDR2，DDR3，DDR4，高带宽存储器HBM、动态随机存取存储器DRAM、3D超级DRAM(Super-DRAM)等。例如，易失型存储介质可以是宽度为512bits，容量为1GB的HBM。
非易失型存储介质例如可以是单层式存储闪存/单层单元闪存SLC-NAND，磁性随机存取存储器MRAM，阻变随机存取存储器RRAM，相变随机存取存储器PCRAM、3D-Xpoint存储介质或3D-SLC NAND闪存存储器等等。
混合型存储器100的封装方式例如可以是倒扣封装(flip package)，球栅阵(ball grid array，BGA)封装或晶片级别芯片规模封装(wafer level chip scale package，WLCSP)等。
封装外壳006对外呈现的总线接口007可以是一个接口。例如，可以是符合电子工程设计发展联合会议(joint electron device engineering council，JEDEC)规范的DDR4接口。或者，封装外壳006对外呈现的总线接口007可以包括多个(两个或两个以上)接口。例如，可以包括符合JEDEC规范的两个DDR4接口。
上述混合型存储器可以设置电子设备中，混合型存储器可以作为电子设备的内存来使用，也即程序数据在运行过程中可保存在混合型存储器中。电子设备中还包括处理器(例如，片上系统(system on chip，SoC))。SoC可以作为主器件(HOST)，混合型存储器可以作为从器件(DEVICE)。SoC可以向混合型存储器写入数据或从混合型存储器读出数据。
SoC与混合型存储器可以通过DDR5接口、HBM DDR接口或者PCIeGen5x4接口中的一个或多个连接。即SoC与混合型存储器之间的总线连接是有丰富可选择、可组合性的。
如图2所示，当SoC需要从混合型存储器中读取数据时，SoC可以向存储控制器001 发送读指令，读指令包括第一地址。存储控制器001接收到读指令后，确定第一地址对应的存储空间，从该存储空间读取数据。其中，第一地址可以是第一物理地址，或者可以是第一逻辑地址。若第一地址为第一物理地址，存储控制器001接收到读指令后，直接根据第一物理地址寻址易失型存储介质或非易失型存储介质，确定第一物理地址对应的存储空间，从第一物理地址对应的存储空间读取第一数据。若第一地址为第一逻辑地址，存储控制器001接收到读指令后，根据第一逻辑地址确定第一物理地址，再根据第一物理地址寻址易失型存储介质或非易失型存储介质，确定第一物理地址对应的存储空间，从第一物理地址对应的存储空间读取第一数据。而后，存储控制器001将第一数据发送给SoC。
如图3所示，当SoC需要向混合型存储器写入数据时，SoC可以向存储控制器001发送写指令，写指令包括第二地址和待写入的数据。存储控制器001接收到写指令后，确定第二地址对应的存储空间，将待写入数据写入该存储空间。其中，第二地址可以是第二物理地址，或者可以是第二逻辑地址。若第二地址为第二物理地址，存储控制器001接收到写指令后，根据第二物理地址直接寻址易失型存储介质或非易失型存储介质，确定第二物理地址对应的存储空间，将待写入数据写入第二物理地址对应的存储空间。若第二地址为第二逻辑地址，存储控制器001接收到读指令后，根据第二逻辑地址确定第二物理地址，再根据第二物理地址寻址易失型存储介质或非易失型存储介质，确定第二物理地址对应的存储空间，从第二物理地址对应的存储空间读取第二数据。可选的，存储控制器001可以向SoC发送响应消息，响应消息用于指示写操作已完成。
图4中的(a)示出了混合型存储器的剖面图。图4中的(b)示出了混合型存储器的三维结构图。图4中的(a)中，包括基板501、内部连线502、易失型存储介质组503(易失型存储介质可以包括多个，可以称为易失型存储介质组)、非易失型存储介质组504(非易失型存储介质可以包括多个，可以称为非易失型存储介质组)、存储控制器505、外壳506、BGA焊盘507和总线接口508。图4中的(b)中，包括基板501、易失型存储介质组503、非易失型存储介质组504和BGA焊盘507。
其中，基板501上可以安装有易失型存储介质组503和非易失型存储介质组504。易失型存储介质组503可以通过内部连线502和BGA焊盘507连接。非易失型存储介质组504可以通过内部连线502和BGA焊盘507连接。存储控制器505可以通过焊盘507与基板501连接。
示例性的，基板501的厚度可以为0.15mm。易失型存储介质组503可以包括4个(4pcs)采用1Alphanm工艺节点的MicronDDR4晶片。每个MicronDDR4晶片的存储空间大小可以为8Gb(即1GB)。MicronDDR4晶片之间的绑定线(即内部连线502)可以为金线。非易失型存储介质组504可以包括4个(4pcs)28nm工艺节点的GlobalFoundry MRAM晶片，每个GlobalFoundry MRAM晶片的存储空间大小可以为1Gb。非易失型存储介质之间的绑定线(即内部连线502)可以为金线。存储控制器505负责与HOST器件(例如，SoC)通信，同时负责管理易失型存储介质组503与非易失型存储介质组504。混合型存储器的存储空间大小可以包括，易失型存储介质组503的存储空间大小(32Gb，即4GB)和非易失型存储介质组504的存储空间大小(4Gb，即1GB)的和。存储控制器505可以为以应用型专用集成芯片(application specific integrated chip，ASIC)为基础开发的22nm工艺节点定制控制器。外壳506可以是塑胶材质，其上可以标注器件型号。BGA焊盘507的管脚(pitch) 可以为0.45mm。混合型存储器中还可以包括电源模块、胶与填充物(Filler)等，图4中未示出。混合型存储器封装完成后可以在自动测试系统(auto test equipment，ATE)机台进行封装等级(Package Level)测试，以保证封装质量。
需要说明的是，当电子设备采用混合型存储器作为内存时，混合型存储器中的易失型存储介质组可以支持高速处理数据，可以实现高读写性能。混合型存储器中的非易失型存储介质组在较低的频率下具有较高性能和较低功耗。因此，采用混合型存储器可以提升电子设备读写性能和降低功耗。可以满足市场上的电子设备的低功耗和高性能的基本诉求。
另外，传统内存(例如，以RAM为内存)在息屏状态下不能完全断电，否则会导致内存中的数据丢失。本申请实施例提供的混合型存储器的非易失型存储介质组的数据不会丢失，可以将有用数据存储在非易失型存储介质组中，这样电子设备在息屏状态下可以完全断电，能够大幅降低功耗。其中，息屏状态也可以称为熄屏状态，电子设备在息屏状态下可以不显示任何信息，或者可以显示有限的信息(例如，当前时间、日期等信息)。并且，传统内存下电时，内存中的数据会丢失。下次开机上电后，需要把运行的程序导入到内存中进行处理，才能引导系统开机。当混合型存储器下电时，混合型存储器中的非易失型存储介质组的数据并不丢失，可以将运行的程序存储在非易失型存储介质组中，这样，下次开机时可以快速恢复待运行的程序，可以更好地降低待机功耗和提升启动性能。
上述混合型存储器可以采用不同的地址分配模式。地址分配模式可以包括并行模式、影子模式和混合模式等。下面分别对并行模式、影子模式、混合模式进行说明。
在并行模式下，易失型存储介质和非易失型存储介质分别对应的物理地址段不重合(不相同)。当SoC访问混合型存储器时，可以分别寻址易失型存储介质和非易失型存储介质。
并行模式下，易失型存储介质和非易失型存储介质的存储空间大小可以相等或不等。例如，易失型存储介质对应的物理地址的数量可以等于非易失型存储介质对应的物理地址的数量。如图5所示，易失型存储介质和非易失型存储介质可以分别对应物理地址段1和物理地址段2。物理地址段1包括0x1-0x4；物理地址段2包括0x5-0x8。或者，易失型存储介质对应的物理地址的数量可以多于非易失型存储介质对应的物理地址的数量。如图7所示，易失型存储介质和非易失型存储介质可以分别对应物理地址段1和物理地址段2。物理地址段1包括0x1-0x5；物理地址段2包括0x6-0x8。本申请不做限定。或者，易失型存储介质对应的物理地址的数量可以少于非易失型存储介质对应的物理地址的数量。如图6所示，易失型存储介质和非易失型存储介质可以分别对应物理地址段1和物理地址段2。物理地址段1包括0x1-0x3；物理地址段2包括0x4-0x8。
并行模式下，混合型存储器掉电后再上电，非易失型存储介质中的数据不会丢失。对于一些预设类型的数据，预设类型的数据例如可以包括即时训练的人工智能(artificial intelligence，AI)数据、模型(pattern)与训练结果等等。可以将预设类型的数据写入混合型存储器的非易失型存储介质(例如，FastNVM)。这些数据保存在FastNVM中可以随时访问取用，即使系统掉电数据也不会丢失，无需重复计算。相比现有技术，上电后需要重新计算预设类型的数据导致功耗消耗，或者从慢速的Storage读取预设类型的数据导致效率低下。本申请实施例中，SoC可以从作为内存的混合型存储器中直接读取预设类型的数据，其花费的时间远小于重新计算的时间资源消耗，也远小于从慢速的Storage读取所 花费的时间。
并行模式的混合型存储器硬件实现简单，内部设计简单，更易实现，成本更低。
影子模式下，易失型存储介质和非易失型存储介质的物理地址段是相同的(重合的)。即同一个物理地址，既可以指向易失型存储介质，也可以指向非易失型存储介质。影子模式下，易失型存储介质和非易失型存储介质的大小相等。即易失型存储介质对应的物理地址的数量等于非易失型存储介质对应的物理地址的数量。示例性的，如图8所示，易失型存储介质和非易失型存储介质可以分别对应物理地址段1和物理地址段2。物理地址段1包括0x1-0x4；物理地址段2也包括0x1-0x4。
当地址分配模式为影子模式时，混合型存储器通过存储控制器可以实现多种数据存储模式，包括功耗/性能自动平衡(power/performance auto balance)模式和数据影子(data shadow)模式。如表1所示，功耗/性能自动平衡模式和数据影子模式可通过模式寄存器(mode register，MR)来配置。
表1
模式寄存器 数据存储模式 上电默认
1 功耗性能自动平衡模式 √
0 数据影子模式  
当上电初始化后，混合型存储器可以默认处于某一种模式。例如，可以定义混合型存储器上电后默认处于数据影子模式。或者，默认处于功耗/性能自动平衡模式。表1中默认混合型存储器上电后处于功耗/性能自动平衡模式。
在功耗/性能自动平衡模式下：当SoC处于高主频(即CPU工作的时钟频率(CPU Clock Speed)高于非易失型存储介质的最高读写频率)时，由于非易失型存储介质的最高读写频率小于主频(即非易失型存储介质的处理数据的速度低于处理器处理数据的速度)，因此数据被写入易失型存储介质，以满足快速动作的要求。当SoC的主频降低时，非易失型存储介质的最高读写频率大于或等于主频，即非易失型存储介质的处理数据的速度可以达到处理器处理数据的速度，因此数据可以被写入非易失型存储介质，以获得更低的功耗表现。此时易失型存储介质可以进入极低功耗状态，以降低功耗。上述过程可以由混合存储器的存储控制器完成，无需由SoC将数据写到两个不同类型的存储子单元，可以降低SoC侧的负载，提高SoC的处理性能。
在数据影子模式下，当SoC处于高主频时，数据先被写入易失型存储介质后，再由存储控制器自动将数据转写到速率较低的非易失型存储介质；当系统处于非易失型存储介质能够匹配的低速率范围时，数据先被写入非易失型存储介质后，再由存储控制器自动将数据转写入易失型存储介质。上述过程可以由混合存储器的存储控制器完成，无需SoC处理，可以降低SoC侧的负载，提高SoC的处理性能。
在数据影子模式下，混合型存储器掉电后再上电，混合存储器的易失型存储介质数据丢失，非易失型存储介质的数据依然保持，由于易失型存储介质和非易失型存储介质中记录的数据相同，因此数据不会真正丢失，有效避免了数据丢失。
混合模式下，混合型存储器的部分物理地址段，既可以指向易失型存储介质，也可以指向非易失型存储介质；而另一些物理地址段，仅指向易失型或者非易失型存储介质中的 一种。如表2所示，易失型存储介质对应的物理地址和非易失型存储介质对应的物理地址可以有多种组合方式。例如，组合方式可以分别包括组合1、组合2和组合3。
表2
Figure PCTCN2022072416-appb-000001
需要说明的是，独立的地址可以通过直接寻址的方式访问。重叠的地址需要通过模式寄存器配置进行访问。即重叠的地址需要由存储控制器确定如何进行访问。例如，可以以功耗/性能自动平衡模式和数据影子模式进行访问。这样既可以保证数据的处理速率，也可以防止数据丢失。
重叠的地址可以根据电子设备需要处理的重要数据(例如“用户画像”训练数据、关键的上下文信息(context)、AI即时训练数据等)的数量灵活设置。若电子设备需要处理的重要数据较多，可以设置较多的重叠地址，以保证重要数据的处理速率，且可以避免重要数据丢失。若电子设备需要处理的重要数据较少，可以设置较少的重叠地址，避免存储空间浪费。
示例性的，如表3所示，组合方式为组合1时，易失型存储介质和非易失型存储介质均有一部分独立地址，同时还有一部分地址重合。其中，易失型存储介质包括的独立地址和非易失型存储介质包括的独立地址的数量可以相同或不同，本申请不做限定。
表3
Figure PCTCN2022072416-appb-000002
示例性的，如图9所示，易失型存储介质和非易失型存储介质可以分别对应物理地址 段1和物理地址段2。物理地址段1包括0x1-0x4。物理地址段1包括独立地址和重合地址，独立地址包括0x1-0x2；重合地址包括0x3-0x4。物理地址段2包括0x3-0x6。物理地址段2包括独立地址和重合地址，独立地址包括0x5-0x6；重合地址包括0x3-0x4。当然，物理地址段1包括的独立地址和物理地址段2包括的独立地址的数量可以不同，本申请不做限定。
组合1适用于例如手机、平板等复杂的多核电子设备。电子设备的CPU在高主频时可以在易失型存储介质的独立地址指示的存储空间(例如，4～8GB)进行读写，以满足数据的快速处理需求。可以在重合地址(例如，128MB)指示的存储空间存放重要数据(例如“用户画像”训练数据、关键的上下文信息(context)、AI即时训练数据等)，以获得掉电不丢失、无需重复训练、快速恢复的效果。可以在非易失存储介质的独立地址指示的存储空间(例如，128MB)存放Boot阶段的引导代码，以实现快速启动。
又例如，如表4所示，组合方式为组合2时，仅易失型存储介质有一部分独立地址，非易失型存储介质与易失型存储介质一部分地址完全重合。
表4
Figure PCTCN2022072416-appb-000003
示例性的，如图10所示，易失型存储介质和非易失型存储介质可以分别对应物理地址段1和物理地址段2。物理地址段1包括0x1-0x6。物理地址段1包括独立地址和重合地址，独立地址包括0x1-0x2以及0x5-0x6；重合地址包括0x3-0x4。物理地址段2包括0x3-0x4。物理地址段2仅包括重合地址，即0x3-0x4。
组合2同样适用于手机、平板等复杂的多核电子设备。且混合存储器采用组合2时，相对于采用组合1的制造成本更低。由于非易失型存储介质没有独立地址，因此Boot阶段的引导代码需要存放在重叠地址指示的存储空间，这样在Boot阶段引导电子设备启动时，易失型存储介质需要处于准备状态，增加了易失型存储介质的电流消耗。然而，与电子设备日常应用的大部分时间都处于的工作状态相比，此处增加的额外功耗消耗微小，而芯片成本降低收益更好。
又例如，如表5所示，组合方式为组合3时，非易失型存储介质有一部分独立地址，非易失型存储介质与易失型存储介质一部分地址完全重合。
表5
Figure PCTCN2022072416-appb-000004
Figure PCTCN2022072416-appb-000005
示例性的，如图11所示，易失型存储介质和非易失型存储介质可以分别对应物理地址段1和物理地址段2。物理地址段1包括0x1-0x2。物理地址段1仅包括重合地址，即0x1-0x2。物理地址段2包括独立地址和重合地址，独立地址包括0x3-0x4以及0x5-0x6；重合地址包括0x1-0x2。
组合3适用于穿戴设备、物联网设备等。穿戴设备、物联网设备的处理器的主频通常低于非易失型存储介质的最高读写频率，因此大部分数据可以在非易失存储介质的独立地址指示的存储空间(例如，256MB)进行读写处理。需要高速处理的数据(例如语音识别等即时训练数据)可以在重合地址(例如，128MB)指示的存储空间进行处理，即可以在易失存储介质的存储空间进行处理，以获得掉电不丢失、无需重复训练、快速恢复的效果。处理后的运算结果可以存放于非易失存储器，避免丢失。
混合模式下，混合型存储器掉电后再上电，非易失型存储介质的物理地址段的数据依然保持。如果存在独立的易失存储地址段，则上电后之前的数据丢失。
混合模式允许易失型存储介质和非易失型存储介质根据实际的需求对物理地址进行复用，更加灵活方便。
另外，Soc可以通过软件的方式，根据实际的需求将并行模式的混合型存储器用作影子模式或者混合模式，本申请不做限定。
本申请实施例还提供一种电子设备，该电子设备中可以设置上述混合型存储器，电子设备例如可以为手机、平板电脑、桌面型、膝上型笔记本电脑、超级移动个人计算机(ultra-mobile personal computer，UMPC)、手持计算机、上网本、个人数字助理(personal digital assistant，PDA)等设备。
示例性的，如图12所示，，对本申请实施例提供的电子设备(例如，手机)的结构进行举例说明。电子设备200可以包括：处理器210，外部存储器接口220，混合存储器221，通用串行总线(universal serial bus，USB)接口230，充电管理模块240，电源管理模块241，电池242，天线1，天线2，移动通信模块250，无线通信模块260，音频模块270，扬声器270A，受话器270B，麦克风270C，耳机接口270D，传感器模块280，按键290，马达291，指示器292，摄像头293，显示屏294，以及用户标识模块(subscriber identification module，SIM)卡接口295等。
其中，上述传感器模块280可以包括压力传感器，陀螺仪传感器，气压传感器，磁传感器，加速度传感器，距离传感器，接近光传感器，指纹传感器，温度传感器，触摸传感 器，环境光传感器和骨传导传感器等传感器。
可以理解的是，本实施例示意的结构并不构成对电子设备200的具体限定。在另一些实施例中，电子设备200可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
处理器210可以包括一个或多个处理单元，例如：处理器210可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，存储器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
控制器可以是电子设备200的神经中枢和指挥中心。控制器可以根据指令操作码和时序信号，产生操作控制信号，完成取指令和执行指令的控制。
处理器210中还可以设置存储器，用于存储指令和数据。在一些实施例中，处理器210中的存储器为高速缓冲存储器。该存储器可以保存处理器210刚用过或循环使用的指令或数据。如果处理器210需要再次使用该指令或数据，可从所述存储器中直接调用。避免了重复存取，减少了处理器210的等待时间，因而提高了系统的效率。
在一些实施例中，处理器210可以包括一个或多个接口。接口可以包括集成电路(inter-integrated circuit，I2C)接口，集成电路内置音频(inter-integrated circuit sound，I2S)接口，脉冲编码调制(pulse code modulation，PCM)接口，通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口，移动产业处理器接口(mobile industry processor interface，MIPI)，通用输入输出(general-purpose input/output，GPIO)接口，用户标识模块(subscriber identity module，SIM)接口，和/或通用串行总线(universal serial bus，USB)接口等。
可以理解的是，本实施例示意的各模块间的接口连接关系，只是示意性说明，并不构成对电子设备200的结构限定。在另一些实施例中，电子设备200也可以采用上述实施例中不同的接口连接方式，或多种接口连接方式的组合。
充电管理模块240用于从充电器接收充电输入。其中，充电器可以是无线充电器，也可以是有线充电器。充电管理模块240为电池242充电的同时，还可以通过电源管理模块241为电子设备供电。
电源管理模块241用于连接电池242，充电管理模块240与处理器210。电源管理模块241接收电池242和/或充电管理模块240的输入，为处理器210，混合存储器221，外部存储器，显示屏294，摄像头293，和无线通信模块260等供电。在一些实施例中，电源管理模块241和充电管理模块240也可以设置于同一个器件中。
电子设备200的无线通信功能可以通过天线1，天线2，移动通信模块250，无线通信模块260，调制解调处理器以及基带处理器等实现。在一些实施例中，电子设备200的天线1和移动通信模块250耦合，天线2和无线通信模块260耦合，使得电子设备200可以通过无线通信技术与网络以及其他设备通信。
天线1和天线2用于发射和接收电磁波信号。电子设备200中的每个天线可用于覆盖 单个或多个通信频带。不同的天线还可以复用，以提高天线的利用率。例如：可以将天线1复用为无线局域网的分集天线。在另外一些实施例中，天线可以和调谐开关结合使用。
移动通信模块250可以提供应用在电子设备200上的包括2G/3G/4G/5G等无线通信的解决方案。移动通信模块250可以包括至少一个滤波器，开关，功率放大器，低噪声放大器(low noise amplifier，LNA)等。移动通信模块250可以由天线1接收电磁波，并对接收的电磁波进行滤波，放大等处理，传送至调制解调处理器进行解调。
移动通信模块250还可以对经调制解调处理器调制后的信号放大，经天线1转为电磁波辐射出去。在一些实施例中，移动通信模块250的至少部分功能模块可以被设置于处理器210中。在一些实施例中，移动通信模块250的至少部分功能模块可以与处理器210的至少部分模块被设置在同一个器件中。
无线通信模块260可以提供应用在电子设备200上的包括WLAN(如(wireless fidelity，Wi-Fi)网络)，蓝牙(bluetooth，BT)，全球导航卫星系统(global navigation satellite system，GNSS)，调频(frequency modulation，FM)，近距离无线通信技术(near field communication，NFC)，红外技术(infrared，IR)等无线通信的解决方案。
无线通信模块260可以是集成至少一个通信处理模块的一个或多个器件。无线通信模块260经由天线2接收电磁波，将电磁波信号调频以及滤波处理，将处理后的信号发送到处理器210。无线通信模块260还可以从处理器210接收待发送的信号，对其进行调频，放大，经天线2转为电磁波辐射出去。
电子设备200通过GPU，显示屏294，以及应用处理器等实现显示功能。GPU为图像处理的微处理器，连接显示屏294和应用处理器。GPU用于执行数学和几何计算，用于图形渲染。处理器210可包括一个或多个GPU，其执行程序指令以生成或改变显示信息。
显示屏294用于显示图像，视频等。该显示屏294包括显示面板。
电子设备200可以通过ISP，摄像头293，视频编解码器，GPU，显示屏294以及应用处理器等实现拍摄功能。ISP用于处理摄像头293反馈的数据。摄像头293用于捕获静态图像或视频。在一些实施例中，电子设备200可以包括1个或N个摄像头293，N为大于1的正整数。
外部存储器接口220可以用于连接外部存储卡，例如Micro SD卡，实现扩展电子设备200的存储能力。外部存储卡通过外部存储器接口220与处理器210通信，实现数据存储功能。例如将音乐，视频等文件保存在外部存储卡中。
混合存储器221可以用于存储计算机可执行程序代码，所述可执行程序代码包括指令。处理器210通过运行存储在混合存储器221的指令，从而执行电子设备200的各种功能应用以及数据处理。例如，在本申请实施例中，处理器210可以通过执行存储在混合存储器221中的指令，混合存储器221可以包括存储程序区和存储数据区。
其中，存储程序区可存储操作系统，至少一个功能所需的应用程序(比如声音播放功能，图像播放功能等)等。存储数据区可存储电子设备200使用过程中所创建的数据(比如音频数据，电话本等)等。此外，混合存储器221可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件，闪存器件，通用闪存存储器(universal flash storage，UFS)等。
电子设备200可以通过音频模块270，扬声器270A，受话器270B，麦克风270C，耳 机接口270D，以及应用处理器等实现音频功能。例如音乐播放，录音等。
按键290包括开机键，音量键等。按键290可以是机械按键。也可以是触摸式按键。马达291可以产生振动提示。马达291可以用于来电振动提示，也可以用于触摸振动反馈。指示器292可以是指示灯，可以用于指示充电状态，电量变化，也可以用于指示消息，未接来电，通知等。SIM卡接口295用于连接SIM卡。SIM卡可以通过插入SIM卡接口295，或从SIM卡接口295拔出，实现和电子设备200的接触和分离。电子设备200可以支持1个或N个SIM卡接口，N为大于1的正整数。SIM卡接口295可以支持Nano SIM卡，Micro SIM卡，SIM卡等。
可以理解的是，上述手机100可以具有比图12中所示出的更多的或者更少的部件，可以组合两个或更多的部件，或者可以具有不同的部件配置。图12中所示出的各种部件可以在包括一个或多个信号处理或专用集成电路在内的硬件、软件、或硬件和软件的组合中实现。
本实施例还提供一种计算机存储介质，该计算机存储介质中存储有计算机指令，当该计算机指令在电子设备上运行时，使得电子设备执行上述相关方法步骤实现上述实施例中的方法。
本实施例还提供了一种计算机程序产品，当该计算机程序产品在计算机上运行时，使得计算机执行上述相关步骤，以实现上述实施例中的方法。
另外，本申请的实施例还提供一种装置，这个装置具体可以是芯片，组件或模块，该装置可包括相连的处理器和存储器；其中，存储器用于存储计算机执行指令，当装置运行时，处理器可执行存储器存储的计算机执行指令，以使芯片执行上述各方法实施例中的方法。
其中，本实施例提供的电子设备、计算机存储介质、计算机程序产品或芯片均用于执行上文所提供的对应的方法，因此，其所能达到的有益效果可参考上文所提供的对应的方法中的有益效果，此处不再赘述。
通过以上实施方式的描述，所属领域的技术人员可以了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是一个物理单元或多个物理单元，即可以位于一个地方，或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既 可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该软件产品存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本申请各个实施例方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read only memory，ROM)、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上内容，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (21)

  1. 一种混合型存储器，其特征在于，所述混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；所述易失性存储介质的物理地址段与所述非易失性存储介质的物理地址段不同；
    所述存储控制器用于从处理器接收读/写指令，所述读/写指令中携带第一地址；
    若所述第一地址对应所述易失型存储介质的存储空间，所述存储控制器用于将数据写入所述易失型存储介质的存储空间或者从所述易失型存储介质的存储空间读取数据；
    若所述第一地址对应所述非易失型存储介质的存储空间，所述存储控制器用于将数据写入所述非易失型存储介质的存储空间或者从所述非易失型存储介质的存储空间读取数据。
  2. 一种混合型存储器，其特征在于，所述混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；所述易失性存储介质的物理地址段与所述非易失性存储介质的物理地址段相同；
    所述存储控制器从处理器接收读/写指令，所述读/写指令中携带第一地址；
    若所述处理器的主频大于所述非易失型存储介质的最高读写频率，所述存储控制器用于将数据写入所述易失型存储介质的存储空间或者从所述易失型存储介质的存储空间读取数据；
    若所述处理器的主频小于或等于所述非易失型存储介质的最高读写频率，所述存储控制器用于将数据写入所述非易失型存储介质的存储空间或者从所述非易失型存储介质的存储空间读取数据。
  3. 一种混合型存储器，其特征在于，
    所述混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；所述易失性存储介质的物理地址段与所述非易失性存储介质的物理地址段部分相同；
    所述存储控制器从处理器接收读/写指令，所述读/写指令中携带第一地址；
    在所述第一地址同时对应所述非易失性存储介质和所述易失性存储介质的存储空间的情况下，若所述处理器的主频大于所述非易失型存储介质的最高读写频率，所述存储控制器用于将数据写入所述易失型存储介质的存储空间或者从所述易失型存储介质的存储空间读取数据；若所述处理器的主频小于或等于所述非易失型存储介质的最高读写频率，所述存储控制器用于将数据写入所述非易失型存储介质的存储空间或者从所述非易失型存储介质的存储空间读取数据；
    在所述第一地址对应所述非易失性存储介质或所述易失性存储介质的存储空间的情况下，若所述第一地址对应所述易失型存储介质的存储空间，所述存储控制器用于将数据写入所述易失型存储介质的存储空间或者从易失型存储介质的存储空间读取数据；若所述第一地址对应所述非易失型存储介质的存储空间，所述存储控制器用于将数据写入所述非易失型存储介质的存储空间或者从非易失型存储介质的存储空间读取数据。
  4. 根据权利要求2或3所述的混合型存储器，其特征在于，
    若所述处理器的主频大于所述非易失型存储介质的最高读写频率，所述存储控制器还用于将写入所述易失型存储介质的存储空间的数据写入所述非易失型存储介质的存储空间；
    若所述处理器的主频小于或等于所述非易失型存储介质的最高读写频率，所述存储控制器还用于将写入所述非易失型存储介质的存储空间的数据写入所述易失型存储介质的存储空间。
  5. 根据权利要求1-4任一项所述的混合型存储器，其特征在于，所述混合型存储器还包括总线、基板、封装外壳和总线接口中的至少一项；
    其中，所述存储控制器、所述易失型存储介质和所述非易失型存储介质集成在所述基板上，所述易失型存储介质和所述非易失型存储介质之间通过所述总线连接，所述存储控制器、所述易失型存储介质和所述非易失型存储介质、所述总线以及所述基板封装在所述封装外壳内部，所述封装外壳006对外呈现所述总线接口，所述总线接口用于与处理器连接。
  6. 根据权利要求1-5任一项所述的混合型存储器，其特征在于，
    所述易失型存储介质包括双倍数据速率DDR内存，DDR2，DDR3，DDR4，高带宽存储器HBM、动态随机存取存储器DRAM或3D超级DRAM中的至少一种；
    所述非易失型存储介质包括单层式存储闪存SLC-NAND，磁性随机存取存储器MRAM，阻变随机存取存储器RRAM，相变随机存取存储器PCRAM、3D-Xpoint存储介质或3D-SLC NAND闪存存储器中的至少一种。
  7. 根据权利要求1-6任一项所述的混合型存储器，其特征在于，
    所述混合型存储器作为内存安装在电子设备中。
  8. 根据权利要求7所述的混合型存储器，其特征在于，
    所述电子设备息屏时，所述混合存储器下电。
  9. 根据权利要求1-8任一项所述的混合型存储器，其特征在于，
    所述非易失性存储介质用于存储预设类型的数据，所述预设类型的数据包括即时训练的人工智能AI数据、模型与训练结果中的至少一项。
  10. 根据权利要求1-9任一项所述的混合型存储器，其特征在于，
    所述第一地址为物理地址或逻辑地址；
    若所述第一地址为逻辑地址，所述存储控制器还用于将所述逻辑地址转换为物理地址。
  11. 一种数据读写方法，其特征在于，应用于混合型存储器，所述混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；所述易失性存储介质的物理地址段与所述非易失性存储介质的物理地址段不同；所述方法包括：
    所述存储控制器从处理器接收读/写指令，所述读/写指令中携带第一地址；
    若所述第一地址对应所述易失型存储介质的存储空间，所述存储控制器将数据写入所述易失型存储介质的存储空间或者从所述易失型存储介质的存储空间读取数据；
    若所述第一地址对应所述非易失型存储介质的存储空间，所述存储控制器将数据写入所述非易失型存储介质的存储空间或者从所述非易失型存储介质的存储空间读取数据。
  12. 一种数据读写方法，其特征在于，应用于混合型存储器，所述混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；所述易失性存储介质的物理地址段与所述非易失性存储介质的物理地址段相同；所述方法包括：
    所述存储控制器从处理器接收读/写指令，所述读/写指令中携带第一地址；
    若所述处理器的主频大于所述非易失型存储介质的最高读写频率，所述存储控制器将 数据写入所述易失型存储介质的存储空间或者从所述易失型存储介质的存储空间读取数据；
    若所述处理器的主频小于或等于所述非易失型存储介质的最高读写频率，所述存储控制器将数据写入所述非易失型存储介质的存储空间或者从所述非易失型存储介质的存储空间读取数据。
  13. 一种数据读写方法，其特征在于，应用于混合型存储器，所述混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；所述易失性存储介质的物理地址段与所述非易失性存储介质的物理地址段部分相同；所述方法包括：
    所述存储控制器从处理器接收读/写指令，所述读/写指令中携带第一地址；
    在所述第一地址同时对应所述非易失性存储介质和所述易失性存储介质的存储空间的情况下，若所述处理器的主频大于所述非易失型存储介质的最高读写频率，所述存储控制器将数据写入所述易失型存储介质的存储空间或者从所述易失型存储介质的存储空间读取数据；若所述处理器的主频小于或等于所述非易失型存储介质的最高读写频率，所述存储控制器将数据写入所述非易失型存储介质的存储空间或者从所述非易失型存储介质的存储空间读取数据；
    在所述第一地址对应所述非易失性存储介质或所述易失性存储介质的存储空间的情况下，若所述第一地址对应所述易失型存储介质的存储空间，所述存储控制器将数据写入所述易失型存储介质的存储空间或者从易失型存储介质的存储空间读取数据；若所述第一地址对应所述非易失型存储介质的存储空间，所述存储控制器将数据写入所述非易失型存储介质的存储空间或者从非易失型存储介质的存储空间读取数据。
  14. 根据权利要求12或13所述的方法，其特征在于，若所述处理器的主频大于所述非易失型存储介质的最高读写频率，所述方法还包括：
    所述存储控制器将写入所述易失型存储介质的存储空间的数据写入所述非易失型存储介质的存储空间；
    若所述处理器的主频小于或等于所述非易失型存储介质的最高读写频率，所述方法还包括：
    所述存储控制器将写入所述非易失型存储介质的存储空间的数据写入所述易失型存储介质的存储空间。
  15. 根据权利要求11-14任一项所述的方法，其特征在于，所述混合型存储器还包括总线、基板、封装外壳和总线接口中的至少一项；
    其中，所述存储控制器、所述易失型存储介质和所述非易失型存储介质集成在所述基板上，所述易失型存储介质和所述非易失型存储介质之间通过所述总线连接，所述存储控制器、所述易失型存储介质和所述非易失型存储介质、所述总线以及所述基板封装在所述封装外壳内部，所述封装外壳006对外呈现所述总线接口，所述总线接口用于与处理器连接。
  16. 根据权利要求11-15任一项所述的方法，其特征在于，
    所述易失型存储介质包括双倍数据速率DDR内存，DDR2，DDR3，DDR4，高带宽存储器HBM、动态随机存取存储器DRAM或3D超级DRAM中的至少一种；
    所述非易失型存储介质包括单层式存储闪存SLC-NAND，磁性随机存取存储器 MRAM，阻变随机存取存储器RRAM，相变随机存取存储器PCRAM、3D-Xpoint存储介质或3D-SLC NAND闪存存储器中的至少一种。
  17. 根据权利要求11-16任一项所述的方法，其特征在于，
    所述混合型存储器作为内存安装在电子设备中。
  18. 根据权利要求17所述的方法，其特征在于，
    所述电子设备息屏时，所述混合存储器下电。
  19. 根据权利要求11-18任一项所述的方法，其特征在于，
    所述非易失性存储介质用于存储预设类型的数据，所述预设类型的数据包括即时训练的人工智能AI数据、模型与训练结果中的至少一项。
  20. 根据权利要求11-19任一项所述的方法，其特征在于，
    所述第一地址为物理地址或逻辑地址；
    若所述第一地址为逻辑地址，所述方法还包括：
    所述存储控制器还将所述逻辑地址转换为物理地址。
  21. 一种电子设备，其特征在于，包括处理器、混合型存储器和总线，其中，所述处理器、所述混合型存储器之间通过所述总线互相连接，所述混合型存储器包括存储控制器、易失性存储介质和非易失性存储介质；
    其中，所述混合型存储器用于存储计算机程序代码，所述计算机程序代码包括计算机指令；当所述计算机指令被所述处理器执行时，使得所述处理器和所述混合型存储器执行如权利要求11-20中任一项所述的方法。
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