WO2022170537A1 - Electronic device having through hole with high aspect ratio and forming method therefor, and electronic device - Google Patents

Abstract

Embodiments of the present application provide an electronic device having a through hole with a high aspect ratio and a forming method therefor, and an electronic device, relate to the technical field of electronic devices, and are used for providing a method for forming a through hole with a high aspect ratio. The method of forming the electronic device comprises: stacking a first dielectric layer on a substrate having a first transistor; forming a first section through hole penetrating through the first transistor in the first dielectric layer; filling a material at a location within the first section through hole at least close to an aperture of the first section through hole, such that the filled material forms a temporary fill layer blocking the aperture of the first section through hole; stacking a second dielectric layer on the first dielectric layer, the second dielectric layer being the same as the material of the first dielectric layer; and forming in the second dielectric layer a second section through hole communicated with the first section through hole, the first section through hole and the second section through hole that are communicated with each other being through holes for accommodating a capacitor. Moreover, a hole opening process with a low aspect ratio can be adopted for opening each time.

Description

Electronic device with high aspect ratio through hole, method for forming the same, and electronic device technical field

The present application relates to the field of storage technologies, and in particular, to an electronic device with a high aspect ratio through hole, a method for forming the same, and an electronic device.

Background technique

In a computing system, dynamic random access memory (DRAM), as a memory structure, can be used to temporarily store the operation data of the central processing unit (CPU) and exchange it with external memory such as hard disks. Data is a very important part of a computing system.

In order to increase the storage capacity of the DRAM, the DRAM may include multiple word lines (WL) and multiple bit lines (bit lines, BL). A memory cell is provided at the intersection of a WL and a BL, as shown in Figure 1. A structure diagram of a memory cell is shown, the memory cell includes a transistor (transistor) and a capacitor (capacitor) electrically connected to the transistor, the transistor (transistor) is electrically connected to BL3 and WL4, wherein the transistor is used to control the relationship between BL3 and the capacitor. On or off between, capacitors are used to store charge.

During the preparation of the above DRAM, as shown in FIG. 2a, transistors 12 are first prepared in the logic area and the storage area of the substrate 11, wherein the logic area is responsible for functions such as logic control and signal processing, and the storage area is responsible for data storage. Then, a wiring layer 14 is formed on the logic region, and the transistors 12 of the logic region and the wiring layer 14 of the logic region are connected to form a circuit structure. However, only the dielectric layer 13 is formed in the memory region. As shown in FIG. 2b, after the wiring layer 14 of the logic region is completed, the through hole 8 is formed in the dielectric layer 13 of the storage region. In conjunction with FIG. 2 c , the capacitor 2 is formed in the through hole 8 .

In this way, in the storage area, capacitors are connected to transistors located in this area to form 1T (transistor) 1C (capacitor) memory cells, and further, an embedded DRAM compatible with existing logic processes can be formed.

With the continuous shrinking of process nodes, the storage capacity per unit area of the storage area increases, that is, the integration density of transistors and through holes in the storage area is increasing. Therefore, it is necessary to choose to reduce the opening size of the capacitor through hole and increase the hole depth. , that is, the aspect ratio of the above-mentioned through hole (the ratio of h to d in Fig. 2b) needs to be made larger and larger, for example, d is several tens of nanometers, and h is about 1 micrometer. However, it is difficult for the existing processes of FIGS. 2a to 2c to achieve through holes with such an aspect ratio, and it will become more and more difficult to continue to shrink the process.

SUMMARY OF THE INVENTION

Embodiments of the present application provide an electronic device with a high aspect ratio through hole, a method for forming the same, and an electronic device, and the main purpose is to provide a method for opening a through hole with a high aspect ratio.

To achieve the above object, the embodiments of the present application adopt the following technical solutions:

In a first aspect, the present application provides a method for forming an electronic device, the method for forming an electronic device comprising: a first transistor on a substrate, where the first transistors may be multiple, and the first transistors may be fin transistors ; stacking a first dielectric layer on the substrate with the first transistor, the first dielectric layer may be one layer, or multiple layers stacked in sequence; opening through the first dielectric layer to the first transistor The first section of the through hole; filling material at least at a position close to the orifice of the first section of the through hole in the first section of the through hole, so that the filled material forms a temporary block for the orifice of the first section of the through hole Filling layer; stacking a second dielectric layer on the first dielectric layer, the second dielectric layer can be of the same material as the first dielectric layer; opening in the second dielectric layer to communicate with the first section of through holes remove the temporary filling layer, for example, by an etching process; and form a capacitor electrically connected to the first transistor in the connected first through hole and the second through hole.

In the method for forming an electronic device provided by the embodiment of the present application, when forming the through hole, a first section of through hole is first opened in the first dielectric layer, and then the first section of through hole is at least close to the first section of through hole in the first section of through hole. A temporary filling layer is filled at the position of the hole, that is, the hole of the first section of the through hole is blocked, and then a second dielectric layer is formed on the first dielectric layer, and then the second dielectric layer is opened and The second section of through holes communicated with the first section of through holes.

Based on the above description, the present application includes at least two opening processes. In this case, when the finally formed through hole is a high aspect ratio through hole, each opening here can use a low aspect ratio opening technology, for example, When opening the first section of through holes, you can first etch from the surface of the first dielectric layer to form the top shape of the first section of through holes, and you can use etching gas with more carbon content during etching, So that the polymer generated by the etching gas is deposited on the sidewall of the through hole, so that when continuing to etch towards the substrate, the polymer deposited on the sidewall of the through hole can protect the diameter of the etched through hole It will not be enlarged, and the excess polymer can be discharged in time during the etching process to ensure the formation of the bottom topography, and finally, the first section of through holes with low aspect ratio are formed.

Therefore, when the through hole is formed by the multiple opening technology of the present application, even with the further improvement of the aspect ratio of the through hole, the opening process will not pose a great challenge.

In a possible implementation manner of the first aspect, opening a first segment of through hole in the first dielectric layer that penetrates to the first transistor includes: using dry etching from a surface of the first dielectric layer away from the substrate toward The first transistor opens a hole to form a first section of through hole with a conical structure, and the aperture size of the first section of through hole gradually decreases along the direction close to the substrate; a second section of through hole is opened in the second dielectric layer and communicated with the first section of through hole. The second section of through holes includes: using dry etching to open holes from the surface of the second dielectric layer away from the first dielectric layer toward the first section of through holes to form a second section of through holes with a conical structure, the second section of through holes having a conical structure. The aperture size of the segment through holes gradually decreases along the direction close to the substrate; wherein, the aperture diameter of one end of the second segment through hole close to the first segment through hole is smaller than the aperture diameter of the first segment through hole close to the second segment through hole. , so as to form a step at the junction of the through hole of the first section and the through hole of the second section.

That is, when dry etching the first-stage through-holes and the second-stage through-holes, compared with the existing one-time opening process, the obvious difference is the difference between the first-stage through-holes and the second-stage through-holes. Steps are formed at the junction.

In a possible implementation manner of the first aspect, the thickness of the first dielectric layer is equal to the thickness of the second dielectric layer.

In this way, the process parameters for opening the first stage of through holes and the process parameters for opening the second stage of through holes can be substantially the same, so that the entire opening process can be simplified.

In a possible implementation manner of the first aspect, the substrate is provided with a storage area, and when the first transistor is formed, the process includes: forming the first transistor on the storage area; the substrate is further provided with a logic area, the storage area and the logic area are separated by isolation trenches; the forming method further includes: forming a second transistor on the logic region to obtain a memory, wherein the process of forming the second transistor is the same as the process of forming the first transistor.

In this case, using compatible logic processes to fabricate the first transistor in the memory region and the second transistor in the logic region will also simplify the process.

In a possible implementation manner of the first aspect, after forming the second transistor on the logic region and before opening the first segment of through holes in the first dielectric layer, the forming method further includes:

A first wiring layer is stacked on the logic region, the first wiring layer includes a third dielectric layer, and multiple metal layers formed in the third dielectric layer until the first metal layer is formed; forming on the first metal layer A first cover layer; wherein, the distance from the surface of the first cover layer away from the substrate to the surface of the second transistor away from the substrate is a first preset distance, and the first preset distance is equal to the first segment to be formed The depth of the via.

Here, the first wiring layer on the logic region and the first dielectric layer on the storage region can be formed at the same time or not at the same time. After the first metal layer is formed, the first cover layer is formed on the first metal layer. , the first cover layer can avoid contamination or damage to the first metal layer when the first section of through holes are formed.

In a possible implementation manner of the first aspect, the material of the first cover layer and the material of the third dielectric layer are the same.

Directly using the first capping layer of the same material as the third dielectric layer can simplify the manufacturing process.

In a possible implementation manner of the first aspect, the thickness of the first cover layer is smaller than the thickness of the third dielectric layer.

In a possible implementation manner of the first aspect, before opening the second via hole in the second dielectric layer, the forming method further includes: stacking a second wiring layer on the first cover layer, and the second wiring layer includes a fourth dielectric layer. an electrical layer, and a multi-layer metal layer formed in the fourth dielectric layer until a second metal layer is formed; a second capping layer is formed on the second metal layer; wherein, the surface of the second capping layer away from the substrate reaches The distance between the surfaces of the first cover layer away from the substrate is a second preset distance, and the second preset distance is equal to the depth of the second through hole to be formed.

The same as the purpose of forming the first covering layer described above, the second covering layer formed here can also have the effect of protecting the second metal layer.

In a possible implementation manner of the first aspect, after the opening of the second section of through holes and before removing the temporary filling layer, the forming method further includes: in the second section of through holes at least close to the orifices of the second section of through holes Filling material at the position, so that the filled material forms a temporary filling layer that blocks the opening of the second section of through holes; stacking a fifth dielectric layer on the second dielectric layer; opening and closing in the fifth dielectric layer The third section of through holes communicated with the second section of through holes.

That is to say, the through hole for accommodating the capacitor can also be formed through the three-time opening process.

In a possible implementation manner of the first aspect, the material of the temporary filling layer is polysilicon, carbon or metal.

In a possible implementation manner of the first aspect, removing the temporary filling layer includes: using an etching process to remove the temporary filling layer. For example, when polysilicon is used as the material for the temporary filling layer, the material can be removed by wet etching; when carbon is used as the material for the temporary filling layer, the material can be removed by dry etching; when metal is used as the material When the material of the layer is temporarily filled, the material may be removed by a wet etching process.

In a possible implementation manner of the first aspect, when the capacitor is formed in the connected first section of through holes, the second section of through holes and the third section of through holes, it includes: A first electrode layer is formed on the side of the second-stage through hole and the side of the third-stage through hole, respectively, a capacitor dielectric layer is formed on the first electrode layer, a second electrode layer is formed on the capacitor dielectric layer, and the first electrode layer is formed. is electrically connected to the first transistor.

In a possible implementation manner of the first aspect, the aspect ratio of the first via hole formed in the first dielectric layer is less than or equal to 5:1; and/or, the second via hole formed in the second dielectric layer has an aspect ratio of less than or equal to 5:1; The aspect ratio of the segment vias is less than or equal to 5:1.

Thus, the first stage of through holes and the second stage of through holes may be formed using a low aspect ratio process.

In a second aspect, the present application provides an electronic device, the electronic device includes a substrate, a first transistor, a first dielectric layer, a second dielectric layer and a capacitor; wherein, the first transistor is disposed on the substrate, and the first transistor is disposed on the substrate. A dielectric layer is stacked on the substrate with the first transistor, the first dielectric layer has a first segment of vias penetrating through the first transistor, the second dielectric layer is stacked on the first dielectric layer, the second The dielectric layer has a second section of through holes that communicate with the first section of through holes, and has a step at the junction of the first section of through holes and the second section of through holes, and the capacitor is formed in the first section of through holes that are connected. the hole and the second through hole, and the capacitor is electrically connected with the first transistor.

In the electronic device provided by the embodiment of the present application, the through hole includes a first section of through hole and a second section of through hole that communicate with each other, and there is a step at the junction of the first section of through hole and the second section of through hole. That is to say, the through-holes in the electronic device are not obtained by one-time opening, but are obtained by at least two opening-hole processes. , first through the first opening technology to obtain the first section of through holes, and then through another opening technology to form the second through holes. A low aspect ratio opening technique can be used for the primary opening, and in turn, a high aspect ratio through hole for accommodating the capacitor can be formed.

In a possible implementation manner of the second aspect, the first-stage through-holes and the second-stage through-holes are both conical structures whose aperture sizes gradually decrease in the direction close to the substrate, and the second-stage through-holes close to the first-stage through-holes are conical structures. The diameter of one end of the hole is smaller than the diameter of one end of the through hole of the first section close to the through hole of the second section, so as to form a step at the junction of the through hole of the first section and the through hole of the second section.

In a possible implementation manner of the second aspect, along the stacking direction, the depth of the through holes in the first section is equal to the depth of the through holes in the second section. Of course, the depth of the through holes in the first section may not be equal to the depth of the through holes in the second section.

In a possible implementation manner of the second aspect, along the stacking direction, the depth of the through holes in the first section or the depth of the through holes in the second section is equal to half the depth of the through holes.

In a possible implementation manner of the second aspect, the capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer, the first electrode layer is formed on the side and bottom surfaces of the first section of the through hole, and is formed on the second section of the through hole On the side of the hole, a capacitor dielectric layer is formed on the first electrode layer, a second electrode layer is formed on the capacitor dielectric layer, and the first electrode layer is electrically connected to the first transistor.

In a possible implementation manner of the second aspect, the material of the capacitor dielectric layer may be made of a material with a high dielectric constant, so as to prolong the retention time of the stored data.

In a possible implementation manner of the second aspect, the electronic device further includes a third dielectric layer, the third dielectric layer is stacked on the second dielectric layer, and the third dielectric layer has holes in the third dielectric layer that communicate with the second section of through holes The third section of the through hole has a step at the junction of the second section of the through hole and the third section of the through hole; the capacitor is also formed in the third section of the through hole, and a first electrode layer is formed on the side of the third section of through hole, A capacitor dielectric layer is formed on the first electrode layer in the third through hole, a second electrode layer is formed on the capacitor dielectric layer in the third through hole, and the first electrode layer and the capacitor in the third through hole are formed on the first electrode layer. The dielectric layer and the second electrode layer are respectively connected with the corresponding first electrode layer, the capacitor dielectric layer and the second electrode layer in the second through hole. That is, the through holes may be formed by connecting the first section of through holes, the second section of through holes and the third section of through holes.

In a possible implementation manner of the second aspect, the electronic device is a memory, the substrate is provided with a storage area, and the first transistor is provided in the storage area.

In a possible implementation manner of the second aspect, the substrate is further provided with a logic region, and the storage region and the logic region are separated by an isolation trench; the electronic device further includes: a plurality of second transistors and wiring layers, a plurality of second transistors The transistors are arranged in the logic region; the wiring layer is stacked on the logic region having the second transistor.

During specific implementation, the second transistor in the logic region and the first transistor in the storage region can be formed simultaneously, or can be produced by the same process.

The function of the circuit structure formed by the plurality of second transistors and the wiring layer here can be to control the storage function of the storage area, such as read and write address decoding, read and write action execution, data cache, etc., and can also include data calculation, graphics data processing and other functions.

In a possible implementation manner of the second aspect, the wiring layer includes stacked metal layers, and a dielectric layer for isolating two adjacent metal layers, and the interface between the first section of through holes and the second section of through holes is located in the same phase between two adjacent metal layers.

In a possible implementation manner of the second aspect, the first transistor and the second transistor are fabricated using the same process. In this case, the formation method for forming the electronic device can be simplified.

In a possible implementation manner of the second aspect, the electronic device further includes: a word line and a bit line formed on the storage region, the word line and the bit line are respectively connected to the first transistor, the word line, the bit line, the first dielectric layer The same process as the second dielectric layer and the wiring layer is used. Likewise, the preparation process can be simplified.

In a possible implementation manner of the second aspect, the through holes of the first section and the through holes of the second section are connected to form a through hole for accommodating the capacitor; or, the through holes of the first section and the through holes of the second section that are communicated are formed. The hole forms part of a through hole for accommodating the capacitor, wherein the aspect ratio of the through hole for accommodating the capacitor is greater than or equal to 10:1. As such, the vias used to accommodate the capacitors may be referred to as high aspect ratio vias.

In a third aspect, the present application also provides an electronic device, comprising a printed circuit board and an electronic device made in any implementation manner of the above-mentioned first aspect or an electronic device of any implementation manner of the above-mentioned second aspect, the printed circuit The board is electrically connected to the electronic device.

The electronic device provided by the embodiment of the present application includes the electronic device of the first aspect embodiment or the second aspect embodiment. Therefore, the electronic device provided by the embodiment of the present application and the electronic device of the above technical solution can solve the same technical problems and achieve the same expected effect.

In a possible implementation manner of the third aspect, the electronic device further includes a logic processing circuit, and the logic processing circuit and the electronic device are integrated in the same chip. Thereby, the electronic device forms an embedded electronic device.

In a possible implementation manner of the third aspect, the electronic device further includes a logic processing circuit, the logic processing circuit is integrated in the first chip, the electronic device is integrated in the second chip, the first chip and the second chip are stacked and electrically connected, The stacked first chip and the second chip are arranged on the printed circuit board. so that the electronic device forms a self-contained electronic device.

In a possible implementation manner of the third aspect, the electronic device further includes a logic processing circuit, the logic processing circuit is integrated in the first chip, the electronic device is integrated in the second chip, and the first chip and the second chip are respectively arranged on the printed circuit board. on the circuit board and are electrically connected through the printed circuit board. so that the electronic device forms a self-contained electronic device.

Description of drawings

Fig. 1 is the structural representation of a memory cell in DRAM;

Figure 2a, Figure 2b and Figure 2c are schematic structural diagrams corresponding to the completion of each step in the method for forming a memory in the prior art;

FIG. 3 is a partial structural schematic diagram of an electronic device according to an embodiment of the application;

4 is a schematic partial structure diagram of another electronic device according to an embodiment of the application;

5 is a schematic partial structure diagram of another electronic device according to an embodiment of the present application;

6 is a schematic diagram of a partial structure of a memory according to an embodiment of the present application;

7 is a process flow diagram of a method for forming an electronic device according to an embodiment of the present application;

FIG. 8 is a cross-sectional view after each step of the process flow of FIG. 7 is completed;

9a, 9b, 9c, 9d, 9e, 9f, 9g, 9h, 9i, 9j, 9k, and 9l are the steps in the method for forming a memory according to the embodiment of the present application after completion of each step The corresponding structure diagram;

10 is a schematic structural diagram of a first section of through holes, a second section of through holes and a third section of through holes formed in an embodiment of the application;

FIG. 11 is a schematic diagram of a partial structure of a memory according to an embodiment of the present application.

Reference number:

01-PCB; 02-chip; 021-first chip; 022-second chip;

11-substrate; 12-transistor; 121-first transistor; 1-1-drain; 1-2-gate; 1-3-source; 122-second transistor; 13-dielectric layer; 14- wiring layer; 141-first wiring layer; 142-second wiring layer; 143-third wiring layer; 15-step; 2-capacitor; 3-bit line; 4-word line; 5-isolation trench; 6- metal layer; 61-first metal layer; 62-second metal layer; 63-third metal layer; 71-first dielectric layer; 72-second dielectric layer; 73-third dielectric layer; 74- Fourth dielectric layer; 75 - fifth dielectric layer; 8 - through hole; 81 - first through hole; 82 - second through hole; 83 - third through hole; 9 - temporary filling layer; 101 - first electrode layer; 102 - capacitive dielectric layer; 103 - second electrode layer; 111 - first cover layer; 112 - second cover layer; 113 - third cover layer.

Detailed ways

Embodiments of the present application provide an electronic device. The electronic device may include a mobile phone (mobile phone), a tablet computer (pad), a smart wearable product (eg, a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR), It can also be home appliances, automobiles, artificial intelligence and other equipment, and can also be servers, data centers, and so on. The embodiments of the present application do not specifically limit the specific form of the above electronic device.

In the above-mentioned electronic device, a memory, a central processing unit (central processing unit, CPU), or an image graphics processing unit (graphic processing unit, GPU), etc. may be included. Among them, the memory is used to store the operation data of the CPU or the GPU.

In memory, because DRAM has a simpler structure than other memories, for example, compared with Static Random-Access Memory (SRAM), one memory cell in SRAM has six transistors, while one memory cell in DRAM has six transistors. Has only one transistor. In this case, DRAM has very high density, high capacity per unit volume, and low cost. Furthermore, DRAM is widely used in electronic equipment.

Fig. 3 shows a partial structure diagram of an electronic device, the electronic device may include a printed circuit board (PCB) 01 and a chip package structure integrated on the PCB 01, and the chip package structure can pass through a ball array ( ball grid array, BGA) is connected to PCB01.

In FIG. 3, the chip package structure includes a stacked first chip 021 and a second chip 022, one of the first chip 021 and the second chip 022 is a logic chip, such as a CPU or GPU, and the other chip is a DRAM, In addition, the first chip 021 and the second chip 022 can be connected through a through silicon via (TSV) and a redistribution layer (RDL). In FIG. 3 , since the logic chip and the DRAM are two independent chips, the DRAM can be called a stand-alone DRAM.

FIG. 4 shows a partial structure diagram of another electronic device. The electronic device also includes a PCB01 and a first chip 021 and a second chip 022 respectively integrated on the PCB01. The first chip 021 and the second chip 022 can be respectively Connect with PCB01 through BGA. Wherein, one of the first chip 021 and the second chip 022 is a logic chip, and the other chip is a DRAM, and the logic chip and the DRAM can be electrically connected through metal wires arranged on the PCB01. Like FIG. 3 , since the logic chip and the DRAM are two independent chips, the DRAM can be called a standalone DRAM.

FIG. 5 is a partial structure diagram of another electronic device, which also includes a PCB01 and a chip 02 including a system on a chip (SOC) integrated on the PCB01. The chip 02 integrates the DRAM and the logic processing circuit into the same chip, so the DRAM can be called an embedded DRAM.

Figure 6 shows a partial structure diagram of the DRAM. In the DRAM, there are multiple WLs and multiple BLs. The multiple WLs are arranged in parallel along the first direction (X direction in Figure 6), and the multiple BLs are arranged along the first The two directions (the Y direction in FIG. 6 ) are arranged in parallel. The X direction and the Y direction here may be perpendicular, and may also have included angles in other ranges.

At a position where a line of WL and a line of BL intersect, a memory cell is provided. Since there are a plurality of WLs and a plurality of BLs, thus, a plurality of memory cells arranged in an array are formed, and two adjacent memory cells are separated by a partition wall (not shown in the figure).

Continuing with reference to FIG. 6 , a memory cell includes a transistor and a capacitor, and the transistor may be a fin transistor (FinFET), such as a tri-gate transistor (TG). The transistor has a gate 1-2, a source 1-3 and a drain 1-1. A gate (gate) 1-2 is connected to WL, a drain (drain) 1-1 is connected to BL, and a source (source) 1-3 is connected to the capacitor 2. The drain (drain) 1-1 may be connected to the capacitor 2, and the source (source) 1-3 may be connected to BL.

During specific operation, the voltage signal on the WL controls the on or off of the transistor, and then reads the data information stored in the capacitor through the BL, or writes the data signal into the capacitor for storage through the BL, so as to realize the read and write operation.

With the development of semiconductor technology, in order to improve the integration per unit area, it is necessary to reduce the width of the capacitor. For example, if the capacitor is cylindrical, it is necessary to reduce the radial size of the capacitor, and in order not to reduce the capacity of the capacitor, ensure For data storage time, it is necessary to lengthen the depth dimension of the capacitor. In this case, a capacitor with a high aspect ratio will be formed. For example, the radial dimension of the capacitor has now been developed to several tens of nanometers, and the depth dimension has reached 1 micron. .

When forming a capacitor, a through hole can be opened in the dielectric layer, a first electrode layer can be formed on the wall surface of the through hole, a capacitor dielectric layer can be formed on the first electrode layer, and a second electrode layer can be formed on the capacitor dielectric layer. The electrode layer is formed, thereby forming a capacitor arranged in the through hole.

When the through hole is etched in the dielectric layer by the dry etching process, the top shape of the through hole is formed first, and when the bottom shape is etched continuously, the diameter of the top through hole will be enlarged. In order to ensure that the top and bottom diameters of the via holes are the same as possible, methods of etching, redepositing, and re-etching are required. The realization method is to use etching gas with more carbon content in dry etching, such as octafluorocyclobutane (C4F8), and the resulting polymer (Polymer) will be deposited on the sidewall of the through hole to protect the etched gas. The diameter of the via hole is not enlarged, and the excess polymer needs to be drained out of the via hole to avoid affecting the subsequent etching process.

In the etching process of low aspect ratio (for example, the aspect ratio is within 7:1 to 10:1), the polymer is easier to discharge, but as the aspect ratio increases (for example, the aspect ratio is greater than 10:1), the polymer It is easy to deposit a large amount at the bottom of the through hole, which blocks the subsequent etching process, resulting in the phenomenon that the through hole is not etched to the bottom. The capacitive etching process of DRAM has the characteristics of high aspect ratio and small via size at the same time, so it is a great challenge to the etching process.

The present application proposes a method for forming an electronic device, wherein a through hole in the electronic device has a high aspect ratio, and the forming method includes using a low aspect ratio opening process to form a through hole with a high depth ratio, which is combined below The accompanying drawings illustrate the formation method of the electronic device in detail.

With reference to FIG. 7 and FIG. 8 , the method for forming the electronic device is described in detail. FIG. 7 is a process flow diagram of the method for forming the electronic device, and FIG. 8 is a cross-sectional view of each step of the process flow diagram of FIG. 7 after completion.

Referring to the structure diagram of step S1 in FIG. 7 and FIG. 8( a ), FIG. 8( a ) is the structure diagram after step S1 is completed. Step S1 includes: forming the first transistor 121 on the substrate 1 . The first transistor 121 in (a) of FIG. 8 is an exemplary structure, and in some alternative embodiments, the first transistor 121 may be formed by a gate electrode, a source electrode and a drain electrode provided on the substrate 1 .

The substrate here may be a semiconductor material, for example, a single crystal silicon substrate, a single crystal germanium substrate, or a silicon-on-insulator (SOI) substrate. Those skilled in the art can select a suitable material as the substrate according to actual needs, which is not limited in this application.

In addition, the first transistor here may be a low-voltage metal-oxide-semiconductor field-effect transistor (MOSFET), such as a tri-gate transistor (TG). Also, when the first transistors are formed on the substrate, a plurality of first transistors arranged in an array as shown in FIG. 6 may be formed.

Continue to refer to the structural diagram of step S2 in FIG. 7 and (b) in FIG. 8 , (b) in FIG. 8 is the structural diagram after completing step S2, and step S2 includes: stacking on the substrate having the first transistor 121 The first dielectric layer 71 . It can also be understood that the first dielectric layer 71 covers the substrate having the plurality of first transistors 121 .

The first dielectric layer can be a multi-layer stack structure or a single-layer structure as shown in (b) in FIG. 8 , and the dielectric material of the first dielectric layer can be silicon oxide, silicon nitride, silicon oxynitride, One or a combination of at least two of fluorine-doped silica, boron-doped silica, phosphorus-doped silica, or boron-phosphorus-doped silica.

Continue to refer to the structure diagram of step S3 in FIG. 7 and (c) in FIG. 8 , (c) in FIG. 8 is the structure diagram after step S3 is completed, and step S3 includes: opening through to the first dielectric layer 71 The first segment of the through hole 81 of the first transistor 121 .

It should be noted that when there are multiple first transistors 121 , there are also multiple first-segment through holes 81 , and the multiple first-segment through-holes 81 and the multiple first transistors 121 are arranged one-to-one, that is, A first transistor 121 corresponds to a first segment through hole 81 . (c) in FIG. 8 exemplarily depicts a first transistor 121 and a first segment corresponding to the first transistor 121 Through hole 81 .

The first section of through holes may be formed by a dry etching process capable of forming low aspect ratio (eg, aspect ratio less than or equal to 5:1) through holes. When a dry etching process is used to open the first section of through holes, the opening process steps may be as follows: first, the top shape of the first section of through holes is formed on the part of the first dielectric layer away from the substrate, and the top section of the first section of through holes is formed by using Etching gas with high carbon content, such as octafluorocyclobutane (C ₄ F ₈ ), the polymer (Polymer) generated in this way will be deposited on the sidewall of the through hole to protect the diameter of the etched through hole from being enlarged , and discharge the excess polymer out of the through hole, continue to etch the bottom topography, and finally form the first section of through hole.

Continue to refer to the structure diagram of step S4 in FIG. 7 and (d) in FIG. 8 , (d) in FIG. 8 is the structure diagram after completing step S4, step S4: in the first section of the through hole 81 at least close to the first Materials are filled at the positions of the openings of the through holes 81 of the first section, so that the filled materials form a temporary filling layer 9 that blocks the openings of the through holes of the first section.

The temporary filling layer here may be as shown in (d) of FIG. 8 , only filling the positions of the first-stage through holes away from the orifice of the substrate, or filling the entire first-stage through-holes.

The material of the temporary filling layer 9 may have various choices, for example, polysilicon, carbon, or metal (eg, copper, iron, tungsten), etc. may be used.

Continue to refer to the structural diagram of step S5 in FIG. 7 and (e) in FIG. 8 , (e) in FIG. 8 is the structural diagram after step S5 is completed, and step S5 includes: stacking a second dielectric layer on the first dielectric layer 71 Dielectric layer 72 .

The second dielectric layer can also be a multi-layer stack structure or a single-layer structure as shown in (e) in FIG. 8 , and the dielectric material of the second dielectric layer can also be silicon oxide, silicon nitride, silicon oxynitride , one of fluorine-doped silica, boron-doped silica, phosphorus-doped silica, or boron-phosphorus-doped silica, or a combination of at least two of them.

Continue to refer to the structure diagram of step S6 in FIG. 7 and (f) in FIG. 8 , (f) in FIG. 8 is the structure diagram after step S6 is completed, and step S6 includes: opening and first in the second dielectric layer 72 A second section of through holes 82 communicated with one section of through holes 81 .

A dry etching process may also be used to open the second through hole 82 in the second dielectric layer 72 , and the specific process steps are the same as the above-mentioned process of opening the first through hole 81 .

Based on the above, the purpose of forming the temporary filling layer 9 in the first through hole 81 in step S4 is to prevent the dielectric material from being filled in the first dielectric layer 71 when the second dielectric layer 72 is formed on the first dielectric layer 71. In the through hole 81 of the first section, that is, the position of the through hole 81 of the first section is occupied first by the temporary filling layer 9, so at least the position of the hole of the through hole of the first section can be filled.

Continue to refer to the structure diagram of step S7 in FIG. 7 and (g) in FIG. 8 , (g) in FIG. 8 is the structure diagram after step S7 is completed, and step S7 includes: removing the temporary filling layer 9 .

The process for removing the temporary filling layer may be different depending on the filling material. For example, if polysilicon is used as the filling material, wet etching may be used to remove the polysilicon. If metal is used as the filling material, the metal can also be removed by wet etching. If carbon is used as the filling material, the carbon can be removed by dry etching. Of course, other removal processes may also be employed.

Continue to refer to the structural diagram of step S8 in FIG. 7 and (h) in FIG. 8 , (h) in FIG. 8 is the structural diagram after completing step S8, and step S8 includes: connecting the first section of through holes 81 and The capacitor 2 electrically connected to the first transistor 121 is formed in the second through hole 82 .

In the above steps S1 to S8, only two sections of through holes are shown. If a third section of through holes is also included, before the temporary filling layer is removed, after the second section of through holes is opened in the second dielectric layer, The forming method further includes the following steps: filling a material at least at a position close to an opening of the second-stage through-hole in the second-stage through-hole to form a temporary filling layer; stacking a third dielectric layer on the second dielectric layer layer; a third section of through hole is opened in the third dielectric layer and communicated with the second section of through hole. Then, the temporary filling layer is removed. The removal of the temporary filling layer here not only needs to remove the temporary filling layer in the first section of through holes, but also needs to remove the temporary filling layer in the second section of through holes.

If the fourth stage of through holes is also included, the method can be performed according to the above-mentioned method for forming the third stage of through holes, which will not be repeated here.

Combining the above steps S1 to S8, it can be seen that when forming a through hole through the dielectric layer, at least two opening processes are required, and each opening process can use a low aspect ratio opening process, That is to say, compared with the one-time opening of the prior art, the present application utilizes at least two low-aspect-ratio opening techniques to realize through-holes with high aspect ratios. The aspect ratio continues to increase, and it will not increase the difficulty of the opening process. Exemplarily, when the aspect ratio is greater than or equal to 10:1, it can be formed by the method shown in FIG. 7 and FIG. 8 , and the hole depth in the aspect ratio of the through hole here can be 300 nanometers (nm) to 1. The pore size in the aspect ratio of the via may be between 30 nanometers (nm) and 40 nanometers (nm). Of course, further reduced through holes can also be formed using the methods shown in FIG. 7 and FIG. 8 .

When the above-mentioned electronic device is a DRAM, it can also be formed by the method shown in the above-mentioned FIGS. 7 and 8 . Of course, other electronic devices that have capacitors and need to open through holes for accommodating capacitors can also be formed by the methods shown in FIGS. 7 and 8 . method is formed.

A specific implementation manner of a DRAM provided by the present application will be described in detail below with reference to the accompanying drawings. The DRAM may be a stand-alone DRAM or an embedded DRAM.

As shown in FIG. 9a, the substrate 1 is provided with a storage area and a logic area, and the storage area and the logic area are separated by an isolation trench 5. FIG. 9a is a cross-section of a memory after the first step in the formation process. In the first step, the first transistor 121 is formed in the storage area, and the second transistor 122 is formed in the logic area. Here, there are multiple first transistors 121 and second transistors 122 respectively. In FIG. 9a, only an example is shown. A first transistor 121 and a second transistor 122 are provided.

It should be noted that, only a method for forming one memory cell (including a first transistor and a capacitor connected to it) is illustrated in FIGS. 9a to 9k of the present application, and the rest of the memory cells are the same as those described in FIGS. 9a to 9k . The memory cells are formed in the same way.

The function of the storage area here is an area for storing data. During chip design, the substrate 1 can be designed to have a memory area for storing data, or a logic area to have a data processing function. In one embodiment, the substrate 1 may also be divided into a plurality of regions, including memory regions and logic regions. The above-mentioned logic area may also have other functions, such as generating control signals. These control signals may be read and write control signals for controlling read and write operations of data in the storage area.

Continuing with reference to FIG. 9a , the first transistor 121 includes a drain electrode 1-1, a gate electrode 1-2 and a source electrode 1-3 all formed on the substrate 1, and between the drain electrode 1-1 and the source electrode 1-3 can be communicated through the substrate 1 . Similarly, the second transistor 122 may also include a drain electrode 1-1, a gate electrode 1-2 and a source electrode 1-3, which are all formed on the substrate 1, and the space between the drain electrode 1-1 and the source electrode 1-3 may be communicated through the substrate 1 .

When forming the first transistor 121 and the second transistor 122, the same logic process can be used to manufacture the first transistor and the second transistor. Taking FIG. 9a as an example, a planar gate logic process technology can be used to manufacture the first transistor and the second transistor. , it can also be fabricated by high K dielectric metal gate (HKMG) logic process technology, or it can be fabricated by Fin field-efffect transistor (FinFET) logic process technology.

In this way, the first transistor of the storage area and the second transistor of the logic area can be formed by using compatible logic process means, and further, the fabrication process of the entire storage area can be simplified.

FIG. 9b is a cross-sectional view of the structure shown in FIG. 9a after completing the second step. In the second step, the bit line 3 and the word line 4 are formed in the storage area, and the bit line 3 is connected to the drain 1-1. , the word line 4 is connected to the gate electrode 1-2, and the bit line 3 may also be connected to the source electrode 1-3.

Similarly, in FIG. 9b, only one bit line 3 and one word line 4 are shown, in practice, a plurality of parallel bit lines 3 and a plurality of parallel word lines 4 are formed.

9c is a cross-sectional view of the structure shown in FIG. 9b after completing the third step. In the third step, the first wiring layer 141 is stacked on the logic region with the second transistor 122, and the first wiring layer 141 is stacked on the logic region with the first transistor, the word A first dielectric layer 71 is stacked on the memory regions of the lines and bit lines.

The above-mentioned first dielectric layer 71 on the storage region and the first wiring layer 141 on the logic region can be formed simultaneously. Alternatively, the first dielectric layer 71 may be formed first, and then the first wiring layer 141 may be formed. Alternatively, the first wiring layer 141 may be formed first, and then the first dielectric layer 71 may be formed.

If the first dielectric layer 71 and the first wiring layer 141 are formed at the same time, the optional forming process includes: forming a dielectric layer on both the logic area and the storage area at the same time; and then only forming a dielectric layer on the logic area forming a metal layer; and simultaneously forming a dielectric layer on both the dielectric layer in the storage area and the dielectric layer with the metal layer in the logic area. That is, a dielectric layer is formed on the logic region and the memory region at the same time.

Repeating the above steps, with reference to FIG. 9c, a first dielectric layer 71 formed by stacking multiple layers of dielectric layers can be fabricated in the storage area, and a third layer formed by stacking multiple layers of dielectric layers in the logic area. The dielectric layer 73 has multiple metal layers in the third dielectric layer 73 . Here, the material of the first dielectric layer 71 and the material of the third dielectric layer 73 may be the same, or of course, may be different.

It should be noted that when the above-mentioned multi-layer metal layers are formed, not only the metal layers arranged in parallel with the substrate, but also the conductive paths for connecting different parallel metal layers are included. The conductive channel can be a through hole filled with conductive material, a metal column, or other conductive structures.

When the above-mentioned method for forming the first wiring layer is performed, until the first metal layer 61 as shown in FIG. 9c is formed, the first capping layer 111 is formed on the first metal layer 61, and when the first metal layer 61 is formed on the first metal layer 61 After the first capping layer 111 is formed on the storage region 61, the formation of the first dielectric layer 71 on the storage region is stopped.

As shown in FIG. 9c , the distance H1 from the surface of the first cover layer 111 away from the substrate 1 to the surface of the second transistor 122 away from the substrate 1 is a first preset distance, and the first preset distance here can be is the depth of the first through hole to be formed.

The above-mentioned material of the first capping layer 111 may be the same as that of the third dielectric layer 73 , for example, both may be silicon oxide or both may be silicon nitride. Of course, the material of the first cover layer 111 may also be different from the material of the third dielectric layer 73 .

Continuing with reference to FIG. 9c, the circuit structure formed by the first wiring layer 141 and the plurality of second transistors 122 is only a part of the circuit structure of the logic region, and the remaining circuit structures are formed later.

FIG. 9d is a cross-sectional view of the structure shown in FIG. 9c after the fourth step is completed. In the fourth step, a first through hole 81 penetrating to the first transistor is formed in the first dielectric layer 71 . Specifically, when the source electrode 1-3 is connected to the BL, the through hole 81 of the first segment penetrates to the drain electrode 1-1, and when the drain electrode 1-1 is connected to the BL, the through hole 81 of the first segment penetrates to the source electrode 1-3.

When forming the through holes 81 in the first section, a dry etching process with a low aspect ratio can be used. As shown in FIG. 9d , along the direction close to the substrate 1 (the direction P1 in FIG. 9d ), the radial dimension of the through holes 81 of the first section gradually decreases.

Because the stacking of the first dielectric layer is stopped after the first capping layer 111 is formed, in this case, referring to FIG. 9c , the depth h1 of the first through hole 81 formed is equal to the first preset height H1.

In addition, when the first through hole 81 is etched in the first dielectric layer 71 , the first cover layer 111 on the first metal layer 61 can protect the first metal layer 61 and prevent the first metal layer 61 Contaminated with other impurities, or prevent the first metal layer 61 from being damaged.

In some optional embodiments, the thickness of the first cover layer 61 may be smaller than the thickness of the third dielectric layer 73 between two adjacent metal layers, or may be the same as the thickness of the third dielectric layer 73 between two adjacent metal layers. The thicknesses of the dielectric layers 73 are equal.

FIG. 9e is a cross-sectional view after the fifth step is completed on the basis of the structure shown in FIG. 9d. In the fifth step, a material is filled in the first-stage through-hole 81 at least at a position close to the orifice of the first-stage through-hole , so that the filled material forms a temporary filling layer 9 that blocks the openings of the through holes of the first section. The orifice of the through hole of the first section here refers to the orifice of the through hole of the first section that is far away from the substrate 1 . In Fig. 9e, the temporary filling layer 9 is only formed at the opening of the first section of through holes 81, and the entire first section of through holes 81 is not filled.

In some alternative embodiments, physical vapor deposition (Physical Vapor Deposition, PVD) or chemical vapor deposition (Chemical Vapor Deposition, CVD) can be used to form the temporary filling layer 9, in this case, it will also be in the logic area. A temporary filling layer 9 is formed on the surface away from the substrate 1 and the surface of the storage region away from the substrate 1 .

9f is a cross-sectional view after the sixth step is completed on the basis of the structure shown in FIG. 9e. In the sixth step, the temporary filling layer on the surface of the storage area away from the substrate 1 and the surface of the logic area away from the substrate 1 are removed. Temporary filling layer on the surface.

When removing the above-mentioned temporary filling layer, an etching or chemical mechanical polishing process can be used to remove it.

9g is a cross-sectional view of the structure shown in FIG. 9f after the seventh step is completed. In the seventh step, the second dielectric layer 72 is stacked on the first dielectric layer 71 and the first cover layer 111 is stacked The second wiring layer 142 .

The above-mentioned stacking of the second wiring layer 142 directly on the first capping layer 111 refers to the case where the material of the first capping layer 111 and the material of the third dielectric layer 73 are the same. If the material of the first capping layer 111 and the material of the third dielectric layer 73 are different, the first capping layer 111 needs to be removed before stacking the second wiring layer 142 .

The above-mentioned second dielectric layer 72 on the storage region and the second wiring layer 142 on the logic region can be formed simultaneously. Alternatively, the second dielectric layer 72 may be formed first, and then the second wiring layer 142 may be formed. Alternatively, the second wiring layer 142 may be formed first, and then the second dielectric layer 72 may be formed.

The second wiring layer 142 here includes the fourth dielectric layer 74 , and a multi-layer metal layer formed in the fourth dielectric layer 74 .

The process of forming the second dielectric layer 72 and the second wiring layer 142 at the same time may be the same as the process of forming the first dielectric layer 71 and the first wiring layer 141 at the same time, and the specific process steps of the simultaneous formation will not be repeated here. Repeat.

In addition, the formation process of the bit line 3 and the word line 4, the first dielectric layer 71, the second dielectric layer 72, the first wiring layer 141 and the second wiring layer 142 can be the same, which can simplify the manufacturing process of the entire electronic device .

The material of the fourth dielectric layer 74 in the second wiring layer 142 may be the same as or different from the material of the second dielectric layer 72 , the material of the first dielectric layer 71 and the material of the third dielectric layer 73 .

Continuing with reference to FIG. 9g, when the second wiring layer 142 is formed, until the second metal layer 62 as shown in FIG. 9g is formed, the second capping layer 112 is formed on the second metal layer 62. After the second capping layer 112 is formed on the layer 62, the formation of the second dielectric layer 72 in the storage region may be stopped.

As shown in FIG. 9c , the distance H2 from the surface of the second cover layer 112 away from the substrate 1 to the surface of the first cover layer 111 away from the substrate 1 is a second preset distance, and the second preset distance here may be The depth of the second through hole to be formed.

9h is a cross-sectional view after the eighth step is completed on the basis of the structure shown in FIG. 9g. In the eighth step, a second section of through holes connected to the first section of through holes 81 are formed in the second dielectric layer 72 82. When forming the second-stage through holes 82, the same as the first-stage through-holes 81, a dry etching process with a low aspect ratio can be used to form, and in some optional embodiments, the second-stage through-holes 82 The topography is also a conical structure, that is, as shown in FIG. 9h , along the direction close to the substrate 1 (the P1 direction shown in FIG. 9h ), the radial dimension of the second through hole 82 gradually decreases.

Because the stacking of the second dielectric layer is stopped after the second capping layer 112 is formed, in this case, referring to FIG. 9h , the depth h2 of the second via hole 82 is equal to the second predetermined height H2 .

Based on the above-mentioned two-stage opening process, compared with the existing one-stage opening process, as shown in FIG.

When forming the second-stage through holes 82, the depth of the second-stage through-holes 82 may be equal to the depth of the first-stage through-holes 81, for example, equal to one-half or one-third of the final through-holes. In this way, the same process conditions can be used when etching the first-stage through holes 81 and the second-stage through holes 82 , for example, the flow rate, temperature, pressure in the etching chamber, bias power, etc. of the etching gas are the same. Further, the entire opening process is simplified.

If the above-mentioned first-stage through holes 81 and second-stage through-holes 82 form the final through-holes, the step shown in FIG. 9i can be continued. In the ninth step shown in FIG. 9i, the first-stage through-holes are removed. Temporary fill layer within 81.

9j is a cross-sectional view after the tenth step is completed on the basis of the structure shown in FIG. 9i. In the tenth step, the first electrode layer 101 is formed in the first section of through holes 81 and the second section of through holes 82 that communicate with each other. , the capacitor dielectric layer 102 and the second electrode layer 103 .

For example, the first electrode layer 101 is respectively formed on the side surface and the bottom surface of the through hole 81 of the first stage, and the first electrode layer 101 is formed on the side surface of the through hole 82 of the second stage; A capacitor dielectric layer 102 is formed on an electrode layer 101, on the first electrode layer 101 on the side of the through hole 81 of the first section, and on the first electrode layer 101 on the side of the through hole 82 in the second section; A second electrode layer 103 is formed on the capacitive dielectric layer 102 on the bottom surface of the through hole 81 , on the capacitive dielectric layer 102 on the side surface of the first through hole 81 , and on the capacitive dielectric layer 102 on the side surface of the second through hole 82 . In this way, the through hole filled with the first electrode layer 101 , the capacitor dielectric layer 102 and the second electrode layer 103 forms a capacitor, and the first electrode layer on the bottom surface of the first segment of through hole 81 is electrically connected to the first transistor.

It should be noted that: forming the capacitor dielectric layer 102 on the first electrode layer 101 on the side surface of the through hole 81 of the first section means that the capacitor dielectric layer is along the radial direction of the through hole 81 of the first section (as shown in the Q direction of FIG. 9j ). ) is formed on the first electrode layer.

Forming the second electrode layer 103 on the capacitor dielectric layer 102 on the side surface of the through hole 81 of the first stage means that the second electrode layer is formed on the capacitor along the radial direction of the through hole 81 of the first stage (the Q direction in FIG. 9j ). on the dielectric layer.

Forming the capacitor dielectric layer 102 on the first electrode layer 101 on the side surface of the second through hole 82 means that the capacitor dielectric layer is formed on the first electrode layer 101 along the radial direction of the second through hole 82 (the Q direction in FIG. 9j ). on the electrode layer.

Forming the second electrode layer 103 on the capacitor dielectric layer 102 on the side of the second through hole 82 means that the second electrode layer is formed on the capacitor along the radial direction of the second through hole 82 (the Q direction in FIG. 9j ). on the dielectric layer.

Here, the first electrode layer 101 and the second electrode layer 103 are both metal layers, and the capacitor dielectric layer 102 can be made of high dielectric constant K (HK) material to prolong the retention time of stored data.

When forming the first electrode layer 101 , the capacitor dielectric layer 102 and the second electrode layer 103 , PVD or CVD deposition can be used, and after the first electrode layer 101 is formed, the second dielectric layer 72 can be separated from the lining. After the surface of the bottom 1 and the first electrode layer 101 on the surface of the second cover layer 112 away from the substrate 1 are removed, the capacitor dielectric layer 102 and the second electrode layer 103 are formed in sequence. Therefore, as shown in FIG. 9j, A capacitor dielectric layer 102 and a second electrode layer 103 are deposited on the surfaces of the logic region and the storage region away from the substrate.

9k is a cross-sectional view of the structure shown in FIG. 9j after completing the eleventh step. In the eleventh step, the capacitor dielectric layer 102 and the second electrode layer 103 on the surface of the logic region away from the substrate are removed.

91 is a cross-sectional view after the twelfth step is completed on the basis of the structure shown in FIG. 9k. In the twelfth step, the second electrode layer 103 of the storage area and the second cover layer 112 of the logic area are formed Three wiring layers 143, in this case, the second electrode layer 103 serving as the capacitor can be electrically connected to the logic region through the third wiring layer, and the second electrode layer 103 can be powered by a power supply located in the logic region.

What is shown in FIG. 10 is that when the through holes include a third section of through holes 83 in addition to the first section of through holes 81 and the second section of through holes 81 , the method for forming the memory also includes: after completing FIG. 9h , filling material at least at a position close to the orifice of the second-stage through-hole 82 in the second-stage through-hole 82, so that the filled material forms a temporary filling layer 9 that blocks the orifice of the first-stage through-hole 82, The fifth dielectric layer 75 is further formed on the second dielectric layer 72 in the storage area, and the fourth dielectric layer 75 is formed on the second capping layer 112 (the material of the second capping layer 112 here is the same as that of the fourth dielectric layer) The wiring layer 144 is formed until the third metal layer 63 is formed, and then the third cover layer 113 is formed on the third metal layer. The distance between the surfaces is a third preset distance H3, and the third preset distance H3 is equal to the depth of the third section of through holes to be formed.

Continuing with reference to FIG. 10 , a third through hole 83 is formed in the third dielectric layer 73 , and the third through hole 83 is communicated with the second through hole 82 . In this case, the depth h3 of the formed third-stage through holes 83 is equal to the third preset distance H3.

If the fourth through hole is not to be formed, the temporary filling layer in the first through hole 81 and the second through hole 82 is removed, and then the first through hole, the second through hole and the second through hole in the connected first through hole, the second through hole and the second through hole are removed. A capacitor is formed in the three-segment through hole.

Continuing with reference to FIG. 10 , a step 15 is also formed at the interface between the second through hole 82 and the third through hole 83 .

When a via hole with a high aspect ratio is formed by a double opening process, the structure shown in FIG. 91 is a memory including a first stage of through hole and a second stage of through hole, and the memory is compared with the existing one-time opening. The memory of the holes, the obvious difference is that there is a step at the interface of the first section of through holes 81 and the second section of through holes 82 .

If a through hole having N (N is a positive integer greater than or equal to 2) segments is obtained by using the method for forming a memory, there are steps at the interface between every two adjacent segments of through holes.

Also, as shown in FIG. 91 , along the stacking direction, the depth of the through holes 81 of the first stage or the depth of the through holes 82 of the second stage is equal to one-half the depth of the through holes.

Continuing as shown in FIG. 91 , after the first metal layer is formed, the first through hole is opened, so the interface between the first through hole and the second through hole is located between two adjacent metal layers.

In some alternative embodiments, when the process conditions for etching the first-stage through-holes 81 and the second-stage through-holes 82 are the same, the area of the cross-section of the first-stage through-holes 81 away from the opening of the substrate 1 may be It is equal to the area of the cross section of the opening of the second section of through holes 82 away from the substrate, and may also be close to the area of the cross section of the opening of the second section of through holes 82 away from the substrate.

FIG. 11 is a structural diagram of a memory, which shows a plurality of capacitors 2 . When forming the memory of this structure, a plurality of through holes can be formed at the same time, and when the first electrode layer, the capacitor dielectric layer and the second electrode layer are respectively formed in the formed plurality of through holes, the first electrode layer can also be formed at the same time , forming a capacitor dielectric layer and a second electrode layer at the same time, and then, as shown in FIG. 11 , the second electrode layers 103 of a plurality of through holes can be connected together as a common second electrode layer, in this case, the power supply through the common The second electrode layer supplies power to the plurality of capacitors.

In some optional embodiments, when PVD or CVD deposition method is used to form a plurality of capacitors 2, as shown in FIG. After the first electrode layer 101 is formed, before the capacitor dielectric layer 102 is formed, the first electrode layer 101 deposited on the surface of the second dielectric layer 72 away from the substrate 1 needs to be removed to prevent the formation of multiple capacitors 2 connected in series.

However, after the capacitor dielectric layer 102 and the second electrode layer 103 are formed by PVD or CVD deposition, it is not necessary to remove the capacitor dielectric layer 102 and the second electrode layer 103 formed on the second dielectric layer 72. A structure in which a capacitor dielectric layer 102 and a second electrode layer 103 are formed on the second dielectric layer 71 as shown in FIG. 11 will be formed, and the second electrode layer 103 is shared by a plurality of capacitors here.

It should be noted that: in the description of “equal” or “equal” involved in this application, for example, the depth of the through hole in the first section is equal to the depth of the through hole in the second section, and for example, the thickness of the first dielectric layer is equal to The thickness of the second dielectric layer, etc., "equal" here can be completely equal or nearly equal, and "equal" can be completely equal or nearly equal.

In the description of this specification, the particular features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims (25)

1. An electronic device, characterized in that, comprising:

   substrate;

   a first transistor, disposed on the substrate;

   a first dielectric layer, stacked on the substrate with the first transistor, the first dielectric layer having a first segment of through hole penetrating through the first transistor;

   a second dielectric layer stacked on the first dielectric layer, the second dielectric layer has a second segment of through holes connected to the first segment of through holes, and the first segment There is a step at the junction of the through hole and the second section of through hole;

   A capacitor is formed in the connected first through hole and the second through hole, and the capacitor is electrically connected with the first transistor.
2. The electronic device according to claim 1, wherein the first section of through holes and the second section of through holes are both conical structures with a gradually decreasing aperture size along a direction close to the substrate, and the The hole diameter of the end of the second section of through holes close to the first section of through holes is smaller than the hole diameter of the first section of through holes close to the second section of through holes, so as to pass through the first section of through holes. The step is formed at the junction of the hole and the through hole of the second section.
3. The electronic device according to claim 1 or 2, wherein, along the stacking direction, the depth of the through holes of the first section is equal to the depth of the through holes of the second section.
4. The electronic device according to any one of claims 1 to 3, wherein the capacitor comprises a first electrode layer, a capacitor dielectric layer and a second electrode layer, and the first electrode layer is formed on the first electrode layer. The side and bottom surfaces of the segment via holes, and the side surfaces of the second segment via holes, the capacitive dielectric layer is formed on the first electrode layer, and the second electrode layer is formed on the capacitive dielectric layer, and the first electrode layer is electrically connected to the first transistor.
5. The electronic device according to claim 4, wherein the electronic device further comprises:

   A third dielectric layer is stacked on the second dielectric layer, and the third dielectric layer has a third section of through holes in communication with the second section of through holes. There is a step at the junction of the through hole and the third section of through hole;

   the capacitor is also formed in the third segment of the through hole;

   The first electrode layer is formed on the side surface of the through hole of the third section, and the capacitor dielectric layer is formed on the first electrode layer in the through hole of the third section. The second electrode layer is formed on the capacitor dielectric layer, and the first electrode layer, the capacitor dielectric layer and the second electrode layer in the third through hole are respectively connected with the first electrode layer. The corresponding first electrode layer, the capacitor dielectric layer and the second electrode layer in the two-stage through hole are connected.
6. The electronic device according to any one of claims 1 to 5, wherein the electronic device is a memory, the substrate is provided with a storage area, and the first transistor is provided in the storage area.
7. The electronic device according to claim 6, wherein the substrate is further provided with a logic area, and the storage area and the logic area are separated by an isolation trench;

   The electronic device also includes:

   a plurality of second transistors, arranged in the logic region;

   a wiring layer stacked on the logic region having the plurality of second transistors.
8. 8. The electronic device according to claim 7, wherein the wiring layer comprises stacked metal layers, and a dielectric layer for isolating two adjacent metal layers, the first through-hole and The interface of the second through hole is located between two adjacent metal layers.
9. The electronic device according to claim 7 or 8, wherein the first transistor and the second transistor are manufactured by the same process.
10. The electronic device according to any one of claims 7 to 9, wherein the electronic device further comprises: word lines and bit lines formed on the storage region, the word lines and the bit lines Connected to the first transistor respectively, the word line, the bit line, the first dielectric layer, the second dielectric layer, and the wiring layer are fabricated by the same process.
11. The electronic device according to any one of claims 1 to 10, wherein the first through-holes and the second through-holes are connected to form through-holes for accommodating the capacitors; or , the connected first section of through holes and the second section of through holes form a part of a through hole for accommodating the capacitor, wherein the aspect ratio of the through hole for accommodating the capacitor is greater than Or equal to 10:1.
12. A method for forming an electronic device, comprising:

    forming a first transistor on the substrate;

    stacking a first dielectric layer on the substrate with the first transistor;

    opening a first segment of through hole through the first transistor in the first dielectric layer;

    A material is filled at a position in the first section of through holes at least close to the orifice of the first section of through hole, so that the filled material forms a hole that blocks the orifice of the first section of through hole. Temporary filling layer;

    stacking a second dielectric layer on the first dielectric layer;

    opening a second section of through holes connected to the first section of through holes in the second dielectric layer;

    removing the temporary filling layer;

    A capacitor electrically connected to the first transistor is formed in the first through hole and the second through hole that are connected to each other.
13. The method for forming an electronic device according to claim 12, wherein the opening of the first segment of through holes in the first dielectric layer that penetrates to the first transistor comprises:

    Dry etching is used to open holes from the surface of the first dielectric layer away from the substrate toward the first transistor to form the first section of through holes in the conical structure, and the first section of through holes The aperture size gradually decreases along the direction close to the substrate;

    Opening the second section of through holes in the second dielectric layer and communicating with the first section of through holes includes:

    Dry etching is used to open holes from the surface of the second dielectric layer away from the first dielectric layer toward the first section of through holes to form the second section of through holes in a conical structure. The aperture size of the second section of through holes gradually decreases along the direction close to the substrate;

    Wherein, the hole diameter of the end of the second section of through holes close to the first section of through holes is smaller than the hole diameter of the first section of through holes close to the second section of through holes, so that in the first section of through holes A step is formed at the junction of one section of through holes and the second section of through holes.
14. The method for forming an electronic device according to claim 12 or 13, wherein the thickness of the first dielectric layer is equal to the thickness of the second dielectric layer.
15. The method for forming an electronic device according to any one of claims 12-14, wherein the substrate is provided with a storage area, and when the first transistor is formed, the method includes: forming on the storage area the first transistor;

    The substrate is further provided with a logic area, and the storage area and the logic area are separated by isolation trenches;

    The forming method also includes:

    A second transistor is formed on the logic region to produce a memory, wherein the process of forming the second transistor is the same as the process of forming the first transistor.
16. The method for forming an electronic device according to claim 15, wherein after forming the second transistor on the logic region and before opening the first through hole in the first dielectric layer, The forming method also includes:

    stacking a first wiring layer on the logic region, the first wiring layer including a third dielectric layer, and multiple metal layers formed within the third dielectric layer until the first metal layer is formed;

    A first capping layer is formed on the first metal layer; wherein, the distance from the surface of the first capping layer away from the substrate to the surface of the second transistor away from the substrate is the first A preset distance, the first preset distance is equal to the depth of the through hole of the first segment to be formed.
17. The method for forming an electronic device according to claim 16, wherein the material of the first cover layer and the material of the third dielectric layer are the same.
18. The method for forming an electronic device according to claim 17, wherein before opening the second through hole in the second dielectric layer, the forming method further comprises:

    A second wiring layer is stacked on the first capping layer, the second wiring layer includes a fourth dielectric layer, and multiple metal layers formed within the fourth dielectric layer until the second metal layer is formed ;

    A second capping layer is formed on the second metal layer; wherein, the distance from the surface of the second capping layer far away from the substrate to the surface of the first capping layer far away from the substrate is The second preset distance is equal to the depth of the through hole of the second segment to be formed.
19. The method for forming an electronic device according to any one of claims 12-18, characterized in that, after opening the second section of through holes, before removing the temporary filling layer, the forming method further comprises:

    A material is filled at a position in the second-stage through-hole at least close to the opening of the second-stage through-hole, so that the filled material forms a material that blocks the opening of the second-stage through-hole Temporary filling layer;

    stacking a fifth dielectric layer on the second dielectric layer;

    A third section of through holes communicated with the second section of through holes is opened in the fifth dielectric layer.
20. The method for forming an electronic device according to any one of claims 12 to 19, wherein the material of the temporary filling layer is polysilicon, carbon or metal.
21. The method for forming an electronic device according to claim 19, wherein the capacitor is formed in the connected through holes of the first section, the through holes of the second section and the through holes of the third section. ,include:

    A first electrode layer is formed on the side surface and bottom surface of the first through hole, the side surface of the second through hole, and the side surface of the third through hole, and a capacitor is formed on the first electrode layer. A dielectric layer, a second electrode layer is formed on the capacitor dielectric layer, and the first electrode layer is electrically connected to the first transistor.
22. The method for forming an electronic device according to any one of claims 12-21, wherein removing the temporary filling layer comprises:

    The temporary filling layer is removed by an etching process.
23. The method for forming an electronic device according to any one of claims 12 to 22, wherein the aspect ratio of the first segment of through holes formed in the first dielectric layer is less than or equal to 5:1; and/ or,

    The aspect ratio of the second via hole formed in the second dielectric layer is less than or equal to 5:1.
24. An electronic device, comprising:

    printed circuit boards;

    The electronic device according to any one of claims 1 to 11, or the electronic device obtained by the method for forming an electronic device according to any one of claims 12 to 23;

    The printed circuit board is electrically connected to the electronic device.
25. The electronic device according to claim 24, wherein the electronic device further comprises:

    A logic processing circuit, the logic processing circuit and the electronic device are integrated in the same chip.

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