WO2022168475A1

WO2022168475A1 - Control device

Info

Publication number: WO2022168475A1
Application number: PCT/JP2021/047276
Authority: WO
Inventors: 好博中谷
Original assignee: オムロン株式会社
Priority date: 2021-02-04
Filing date: 2021-12-21
Publication date: 2022-08-11

Abstract

This control device is provided with a first unit and a second unit. A first hardware circuit of the first unit has a first counter, a signal output part that outputs a synchronization signal to the second unit, and a time information output part that outputs a first value of the first counter to the second unit when the synchronization signal has been output. A second hardware circuit of the second unit has a second counter, a difference calculation part that calculates a first difference between the first value and a second value of the second counter when the synchronization signal has been received, and a correction part that corrects the second counter on the basis of the first difference. This allows for a reduction in the time required to determine the cause of an error that may have occurred before startup of the firmware.

Description

Control device

The present disclosure relates to a control device.

FA (Factory Automation) technology using control devices such as PLCs (Programmable Logic Controllers) is widely used in various production sites. A PLC generally includes a basic unit (CPU (Central Processing Unit) unit) and an expansion unit. A counter (timer) of the CPU unit and a counter of the expansion unit are synchronized so that there is no time lag between the data acquired from the CPU unit and the data acquired from the expansion unit.

For example, Japanese Patent Application Laid-Open No. 2017-79009 (Patent Document 1) discloses a technique for synchronizing the time of the CPU unit timer and the time of the expansion unit timer. Specifically, a synchronization signal is transmitted from the CPU unit to the expansion unit. The expansion unit synchronizes the time of the expansion unit timer with the time of the CPU unit timer according to the synchronization signal.

JP 2017-79009 A

In the technique described in Japanese Patent Application Laid-Open No. 2017-79009, the CPU of the CPU unit executes the process of transmitting the synchronization signal by executing firmware. Therefore, the CPU unit timer and the expansion unit timer cannot be synchronized until after the firmware has started. Therefore, the CPU unit timer and the expansion unit timer are out of sync before the firmware starts. As a result, if a problem occurs before the firmware is started, it becomes difficult to arrange the order of occurrence of events among a plurality of units, and it takes time to investigate the cause of the problem.

The present disclosure has been made in view of the above problems, and its purpose is to provide a control device that can shorten the time required to investigate the cause of a problem that occurred before starting the firmware.

According to one example of the present disclosure, the control device includes a first unit and a second unit that exchange data. The first unit includes a first hardware circuit. A second unit includes a second hardware circuit. A first hardware circuit includes a first counter, a signal output section for outputting a synchronization signal to the second unit, and a first value of the first counter when the synchronization signal is output to a second unit. and a time information output unit for outputting to the unit. The second hardware circuit includes: a second counter; a difference calculator that calculates a first difference between a second value and a first value of the second counter when receiving the synchronization signal; and a correction unit that corrects the second counter based on the difference of 1.

According to the above disclosure, synchronization processing between the first counter and the second counter is performed by the first hardware circuit of the first unit and the second hardware circuit of the second unit. Therefore, immediately after the control device is powered on, synchronization processing between the first counter and the second counter is started. Therefore, the first and second counters are synchronized before the firmware is activated. Therefore, even before the firmware is activated, it becomes easy to arrange the order of occurrence of events in the first unit and the second unit. As a result, it is possible to shorten the time required to investigate the cause of a problem that occurred before the firmware was started.

In the above disclosure, the first hardware circuit further comprises a third counter. The second hardware circuit further has a fourth counter. The signal output section repeatedly outputs the synchronization signal. The time information output unit further outputs a second difference between the value of the third counter when the previous synchronization signal was output and the value of the third counter when the current synchronization signal was output as a second difference. output to the unit of The difference calculation unit further calculates a third difference between the value of the fourth counter when receiving the previous synchronization signal and the value of the fourth counter when receiving the synchronization signal this time. Compute a fourth difference between the difference of and the third difference. The correction unit corrects the second counter based on the fourth difference.

According to the above disclosure, the fourth difference is the count number of the third counter and the count number of the fourth counter in the target period from the output of the previous synchronization signal to the output of the current synchronization signal. Show the difference with the number. Since the first counter and the third counter are included in the same hardware circuit, they count up in the same period according to the clock from the same clock oscillation source. Similarly, since the second counter and the fourth counter are included in the same hardware circuit, they count up in the same cycle according to the clock from the same clock oscillation source. Therefore, the difference between the count number of the first counter and the count number of the second counter in the target period is also the fourth difference. The correction unit corrects the second counter based on the fourth difference, thereby correcting the difference between the values of the first counter and the second counter caused by the oscillation error of the clock source.

Alternatively, the signal output unit may output the synchronization signal each time the value of the first counter increases by a constant value. The time information output section also outputs a constant value to the second unit. The second hardware circuit measures a second difference between the value of the second counter when the previous synchronization signal was output and the value of the second counter when the current synchronization signal was output. It further has a measurement part. The difference calculator further calculates a third difference between the second difference and the constant value. The correction unit corrects the second counter based on the third difference.

According to the above disclosure, the third difference is the difference between the count number of the first counter and the count number of the second counter in the target period in which the value of the first counter increases by a constant value. The correction unit corrects the second counter based on the third difference, thereby correcting the difference between the values of the first counter and the second counter caused by the oscillation error of the clock source. Also, the scale of the first and second hardware circuits can be reduced as compared with the form having the third and fourth counters.

In the above disclosure, the first unit further includes a first light emitting element that blinks according to the value of the first counter. The second unit further comprises a second light emitting element that blinks according to the value of the second counter.

According to the above disclosure, the blinking cycles of the first light emitting element and the second light emitting element are synchronized, and a sense of unity can be given to the user. Conversely, the user can recognize that some kind of abnormality has occurred by visually confirming that the blinking cycles of the first light emitting element and the second light emitting element are not synchronized.

In the above disclosure, the first unit further comprises a processor executing firmware. The firmware includes instructions for setting the timing of outputting the synchronization signal to the signal output section. The signal output unit outputs a synchronization signal when the value of the first counter reaches the timing. The firmware further includes instructions to calculate a fifth difference between the second value and the timing, and instructions to correct the second counter based on the fifth difference. The processor disables the operation of the time information output section after starting the firmware.

According to the above disclosure, after the firmware is activated, the processor can synchronize the first counter and the second counter according to the firmware.

In the above disclosure, the first hardware circuit is an ASIC or FPGA. The second hardware circuit is an ASIC or FPGA.

According to this disclosure, it is possible to reduce the time required to investigate the cause of a problem that occurred before the firmware was started.

It is a figure which shows typically an example of a structure of the control apparatus which concerns on this Embodiment. It is a figure which shows typically the structure of the control apparatus which concerns on a reference form. 3 is a schematic diagram showing a configuration example of a unit of the control device according to the embodiment; FIG. It is a figure which shows the signal waveform using UART. FIG. 4 is a diagram showing a signal waveform corresponding to time information (value X1); FIG. 4 is a diagram showing the flow of data accompanying the waveform of a synchronizing signal; FIG. 5 is a diagram schematically showing the configuration of a control device according to modification 1; FIG. 11 is a diagram schematically showing the configuration of a control device according to modification 2; FIG. 13 is a diagram schematically showing the configuration of a control device 1C according to Modification 3; FIG. 10 is a diagram showing a data flow accompanying a waveform of a synchronization signal in Modification 3; FIG. 10 is a diagram showing a signal distribution method when there are a plurality of extension units;

Embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated.

§1 Application Example First, an example of a scene to which the present invention is applied will be described. FIG. 1 is a diagram schematically showing an example of the configuration of a control device 1 according to this embodiment. The control device 1 corresponds to a PLC, for example. In the following description, a PLC will be described as a specific example as a typical example of the "control device", but the technical idea disclosed in this specification is not limited to the PLC, and can be applied to any control device. Applicable.

As shown in FIG. 1, the control device 1 includes a CPU unit 100 and an expansion unit 200 that exchange data. In addition, although the control device 1 includes one expansion unit 200 in FIG. 1 , it may be provided with a plurality of expansion units 200 . CPU unit 100 is connected to expansion unit 200 via data bus 2 and

signal lines

3 and 4 .

The CPU unit 100 has a program execution section that executes a program created according to the object to be controlled. More specifically, the CPU unit 100 corresponds to an arithmetic processing section that executes system programs and various user programs.

The extension unit 200 can be detachably externally attached to the CPU unit 100 in order to extend the functions of the control device 1 . The expansion unit 200 is arranged to mediate between the network and the control device 1, for example performing communication processing or information processing.

The CPU unit 100 includes a CPU 10, a memory 11, a storage 12, and a hardware circuit 13. Expansion unit 200 includes CPU 20 , memory 21 , storage 22 and hardware circuit 23 .

The CPU 10 reads the firmware and various user programs stored in the storage 12, develops them in the memory 11, and executes them. Similarly, the CPU 20 reads various programs stored in the storage 22, develops them in the memory 21, and executes them.

The hardware circuit 13 and the hardware circuit 23 are, for example, FPGA (Field-Programmable Gate Array) or ASIC (Application Specific Integrated Circuit).

The hardware circuit 13 has a free-running counter (hereinafter referred to as "FRC") 131, a synchronization signal output section 132, and a latch section 133.

The FRC 131 is a counter that counts up at regular intervals. FRC 131 is, for example, a 64-bit counter. Various counters may be employed instead of the FRC 131 .

The synchronization signal output section 132 uses the signal line 3 to output the synchronization signal to the expansion unit 200 at arbitrary timing. The synchronization signal output unit 132 arbitrarily generates the output timing of the synchronization signal. Alternatively, the synchronization signal output unit 132 may set the timing at which the value of the FRC 131 reaches the set value as the timing for outputting the synchronization signal. The synchronization signal output from the synchronization signal output section 132 is also input to the latch section 133 .

The latch section 133 latches the value X1 of the FRC 131 when the synchronization signal is output. Furthermore, the latch section 133 outputs the held value X1 to the expansion unit 200 using the signal line 4 . The value X1 latched by the latch section 133 is time information indicating the time when the synchronization signal was output.

The hardware circuit 23 has an FRC 231 , a latch section 232 , a difference calculation section 233 and an FRC correction section 234 .

The FRC 231 is a counter that counts up at regular intervals. FRC 231 is, for example, a 64-bit counter. Various counters may be employed instead of the FRC 231 .

The latch section 232 latches the value X2 of the FRC 231 when receiving the synchronization signal from the signal line 3 . The latch section 232 outputs the held value X2 to the difference calculation section 233 .

The difference calculation unit 233 calculates the value X2 output from the latch unit 232 (that is, the value of the FRC 231 when the synchronization signal is received) and the value X1 received from the signal line 4 (that is, the value of the FRC 131 when the synchronization signal is output). ) and the difference Y1 (=X2-X1) is calculated. The difference calculator 233 outputs the difference Y1 to the FRC corrector 234 .

The FRC correction unit 234 corrects the FRC 231 based on the difference Y1. That is, the FRC correction unit 234 corrects the value of the FRC231 by the difference Y1 so that the FRC131 and the FRC231 are synchronized.

Next, the flow of synchronization processing of the

FRCs

131 and 231 executed by the control device 1 will be described.

First, the synchronous signal output section 132 of the CPU unit 100 outputs the synchronous signal to the extension unit 200 . The synchronization signal is also output to the latch section 133 (see (1) in the figure).

Next, the latch section 133 of the CPU unit 100 latches the value X1 of the FRC 131 when the synchronization signal was output according to the input of the synchronization signal (see (2) in the figure). The latch section 232 of the extension unit 200 latches the value X2 of the FRC 231 when receiving the synchronization signal in response to the input of the synchronization signal (see (3) in the figure).

The latch unit 133 outputs the held value X1 (time information indicating the timing at which the synchronization signal was output) to the extension unit 200 (see (4) in the figure). That is, the latch section 133 outputs to the extension unit 200 the value X1 of the FRC 131 when the synchronization signal is output.

The latch unit 232 outputs the held value X2 to the difference calculation unit 233 (see (5) in the figure). The difference calculation section 233 calculates the difference Y1 between the value X2 held by the latch section 232 and the value X1 received from the CPU unit 100 (see (6) in the drawing). The difference calculator 233 outputs the calculated difference Y1 to the FRC corrector 234 (see (7) in the figure).

The FRC correction unit 234 corrects the FRC 231 based on the difference Y1 (see (8) in the figure). Thereby, FRC231 and FRC131 are synchronized. The processes (1) to (8) are repeatedly executed.

Thus, according to the present embodiment, the synchronization processing between the FRC231 and the FRC131 is executed by the hardware circuit 13 of the CPU unit 100 and the hardware circuit 23 of the expansion unit 200. Therefore, synchronization processing between the FRC231 and the FRC131 is started immediately after the control device 1 is powered on. Therefore, the FRC231 and the FRC131 are synchronized before the firmware stored in the storage 12 is activated.

FIG. 2 is a diagram schematically showing the configuration of the control device 1Z according to the reference embodiment. As shown in FIG. 2, the controller 1Z differs from the controller 1 shown in FIG. 1 in that it includes a CPU unit 100Z and an expansion unit 200Z instead of the CPU unit 100 and the expansion unit 200. .

The CPU unit 100Z differs from the CPU unit 100 in that it includes a hardware circuit 13Z instead of the hardware circuit 13. The hardware circuit 13Z differs from the hardware circuit 13 in that it does not have the latch section 133. FIG.

The extension unit 200Z differs from the extension unit 200 in that it includes a hardware circuit 23Z instead of the hardware circuit 23. The hardware circuit 23Z is different from the hardware circuit 23 in that it does not have the difference calculator 233 .

Thus, in the control device 1Z, the

hardware circuits

13Z and 23Z do not include the latch section 133 and the difference calculation section 233, so the FRC 231 and the FRC 131 are not synchronized with the

hardware circuits

13Z and 23Z alone. Therefore, the firmware stored in the storage 12 is used to synchronize the FRC231 and the FRC131.

The firmware includes an instruction to set the timing X1 for outputting the synchronization signal to the synchronization signal output section 132 of the hardware circuit 13Z and an instruction to read the value X1 held in the latch section 232. Further, the firmware includes an instruction to calculate the difference Y1 between the value X2 and the timing X1, and an instruction to cause the FRC corrector 234 to correct the FRC 231 based on the difference Y1. The CPU 10 executes synchronization processing as follows according to firmware including such instructions.

First, the CPU 10 of the CPU unit 100Z sets the synchronization signal output timing X1 in the synchronization signal output section 132 (see (11) in the figure). When the value of FRC131 reaches timing X1, the synchronization signal output section 132 outputs the synchronization signal to the expansion unit 200Z (see (12) in the figure).

The latch section 232 of the expansion unit 200Z latches the value X2 of the FRC 231 when receiving the synchronization signal in response to the input of the synchronization signal (see (13) in the figure).

The CPU 10 reads out the value X2 held in the latch section 232 via the data bus 2 (see (14) in the figure). The CPU 10 calculates the difference Y1 (=X2-X1) between the read X2 and the timing X1 set in the synchronization signal output section 132, and sets the difference Y1 in the FRC correction section 234 (see (15) in the drawing).

The FRC correction unit 234 corrects the FRC 231 based on the difference Y1 (see (16) in the figure). Thereby, FRC231 and FRC131 are synchronized. The processes (11) to (16) are repeatedly executed.

The CPU 10 performs the processes (11), (14) and (15) in the figure by executing the firmware. That is, after the firmware is activated, the synchronization processing between the FRC231 and the FRC131 is started. Therefore, the FRC131 and the FRC231 are not synchronized from when the control device 1Z is powered on until the firmware is activated. As a result, if a problem occurs during this period, it becomes difficult to arrange the order of occurrence of events in the CPU unit 100Z and the expansion unit 200Z, and it takes time to investigate the cause of the problem.

On the other hand, in the control device 1 according to the present embodiment, the FRC231 and the FRC131 are synchronized before the firmware is activated. Therefore, it becomes easy to arrange the order of occurrence of events in the CPU unit 100 and the expansion unit 200 even after the power is turned on until the firmware is activated. As a result, it is possible to shorten the time required to investigate the cause of a problem that occurred before the firmware was started.

§2 Concrete example <A. Configuration example of unit of control device>
FIG. 3 is a schematic diagram showing a configuration example of units of the control device 1 according to the present embodiment. As shown in FIG. 3 , the control device 1 includes a CPU unit 100 , one or more expansion units 200 and one or more functional units 300 . CPU unit 100 is connected to one or more expansion units 200 via data bus 2 and

signal lines

3 and 4 . The CPU unit 100 also connects with one or more functional units 300 via the data bus 5 .

The functional unit 300 has the function of a so-called I/O unit that exchanges signals between equipment and devices to be controlled and various devices (sensors, actuators, etc.) arranged therein.

The data bus 2 is, but not limited to, an I/O serial interface bus conforming to PCIe (PCI Express), for example.

The signal line 3 is an optical fiber cable or an electrical signal cable and transmits a synchronous signal. Signal line 3 is connected between signal port 110 P of CPU unit 100 and signal port 210 P of expansion unit 200 . The CPU unit 100 uses the signal line 3 to transmit the synchronization signal to the extension unit 200 .

The signal line 4 is an optical fiber cable or an electrical signal cable, and transmits time information (value X1). Signal line 4 is connected between signal port 111P of CPU unit 100 and signal port 211P of expansion unit 200 . The CPU unit 100 uses the signal line 4 to transmit the time information (value X1) to the expansion unit 200 .

<B. Transmission of time information>

Hardware circuits

13 and 23 communicate time information (value X1) using, for example, an asynchronous serial communication UART (Universal Asynchronous Receiver Transmitter).

FIG. 4 is a diagram showing signal waveforms using UART. As shown in FIG. 4, the UART communicates in units of 8-bit data chunks. A Start bit and a Stop bit are respectively communicated before and after the 8-bit data block.

FIG. 5 is a diagram showing a signal waveform corresponding to time information (value X1). When the value X1 of the FRC 131 is represented by 64 bits, eight 8-bit data chunks are transmitted as shown in FIG.

<C. Example of signal waveform>
FIG. 6 is a diagram showing the flow of data accompanying the waveform of the synchronization signal. In the example shown in FIG. 6, the synchronization signal is output at regular intervals. The constant period is, for example, several ms to several tens of ms.

At the timing when the synchronization signal is asserted, the latch section 133 latches the value X1 of the FRC131 and the latch section 232 latches the value X2 of the FRC231.

The time information indicating the value X1 held in the latch section 133 is transmitted to the expansion unit 200 using, for example, UART.

The difference calculation unit 233 calculates the difference Y1 (=X2-X1) between the value X2 held in the latch unit 232 and the value X1 indicated by the transmitted time information. The value of the FRC 231 is corrected by the FRC corrector 234 using the difference Y1.

<D. FRC Correction Method>
The FRC correction unit 234 corrects the FRC231 value by subtracting the difference Y1 from the FRC231 value.

Note that the FRC correction unit 234 may collectively subtract the difference Y1 from the value of the FRC231. Alternatively, the FRC correction unit 234 may divide the difference Y1 into a plurality of correction units, and subtract the correction units from the value of the FRC 231 multiple times in the correction period. A correction unit and a correction cycle are set in advance. For example, if the difference Y1 is 2 ns, the correction unit is 1 ns, and the correction period is 100 ns, the FRC correction unit 234 subtracts 1 ns from the FRC 231 value at time t1 immediately after the difference Y1 is calculated. Then, the FRC corrector 234 subtracts 1 ns from the value of the FRC 231 at time t1+100 ns. As a result, FRC231 and FRC131 are gradually synchronized. As a result, extreme changes in the value of FRC231 can be suppressed.

<E. Processing after starting the firmware>
If the storage 12 of the CPU unit 100 stores firmware containing instructions for the processes (11), (14) and (15) shown in FIG. Synchronization processing according to (11) to (16) is executed. Therefore, when the storage 12 stores the firmware, the CPU 10 disables the output operation of the time information by the latch unit 133 after starting the firmware. For example, the latch unit 133 has a flag, and is set to output the time information when the flag is "1" and not to output the time information when the flag is "0". be. The CPU 10 may switch the flag to "0" after starting the firmware. When the flag is switched to "0", time information is not output from the CPU unit 100 to the extension unit 200, so the operation of the difference calculation section 233 is also disabled in the extension unit 200. FIG. As a result, synchronization processing according to (1) to (8) shown in FIG. 1 is not executed after the firmware is started.

In this way, before the firmware is activated, the synchronization processes according to (1) to (8) shown in FIG. Synchronization processing is executed repeatedly.

<F. Modification 1>
In the CPU unit 100 , the FRC 131 included in the hardware circuit 13 counts up according to a clock generated using a clock oscillation source (not shown) outside the hardware circuit 13 . Similarly, in expansion unit 200 , FRC 231 included in hardware circuit 23 counts up according to a clock generated using a clock oscillation source (not shown) outside hardware circuit 23 . Therefore, due to an oscillation error (also referred to as static jitter) between the clock oscillation source of the CPU unit 100 and the clock oscillation source of the expansion unit 200, the period in which the FRC 131 counts up and the period in which the FRC 231 counts up may differ. There may be slight deviations in between. As a result, even when the values of FRC131 and FRC231 are once synchronized, they gradually deviate after that. The control device according to Modification 1 corrects the difference between the values of FRC131 and FRC231 (hereinafter referred to as "clock deviation") caused by static jitter.

FIG. 7 is a diagram schematically showing the configuration of a control device 1A according to Modification 1. As shown in FIG. As shown in FIG. 7, the control device 1A includes a CPU unit 100A and an extension unit 200A. The CPU unit 100A differs from the CPU unit 100 shown in FIG. 1 in that it includes a hardware circuit 13A instead of the hardware circuit 13. FIG. Expansion unit 200A is different from expansion unit 200 shown in FIG. 1 in that it includes hardware circuit 23A instead of hardware circuit 23 . Note that the

memories

11 and 21 and the

storages

12 and 22 are omitted from FIG.

The hardware circuit 13A differs from the hardware circuit 13 in that it has a latch section 133A instead of the latch section 133 and further has an FRC 134. Note that the synchronization signal output unit 132 of the hardware circuit 13A repeatedly outputs the synchronization signal.

The FRC 134 is a counter that counts up at regular intervals, such as a 64-bit counter. Various counters may be employed instead of the FRC 134 .

FRCs

131 and 134 count up according to a clock generated using a clock oscillation source (not shown) provided in CPU unit 100A. Therefore, the

FRCs

131 and 134 count up in the same period.

In addition to the operation of the latch section 133, the latch section 133A performs the following operations. That is, the latch section 133A latches the value X3 of the FRC 134 when the synchronization signal is output. Further, the latch unit 133A calculates the difference dX3 (=X3-X3') between the value X3' of the FRC 134 latched when the synchronization signal was output last time and the newly latched value X3, and extends the difference dX3. Output to unit 200A.

The hardware circuit 23A has a latch section 232A, a difference calculation section 233A and an FRC correction section 234A in place of the latch section 232, the difference calculation section 233 and the FRC correction section 234 compared to the hardware circuit 23. It is different in that it has

The FRC 235 is a counter that counts up at regular intervals, such as a 64-bit counter. Various counters may be employed instead of the FRC 235 .

FRCs

231 and 235 count up according to a clock generated using a clock oscillation source (not shown) provided in expansion unit 200A. Therefore, the

FRCs

231 and 235 count up in the same period.

In addition to the operation of the latch section 232, the latch section 232A performs the following operations. That is, the latch section 232A latches the value X4 of the FRC 235 when receiving the synchronization signal from the signal line 3. FIG. The latch section 232A calculates the difference dX4 (=X4-X4') between the value X4' of the FRC 235 latched when the synchronization signal was received last time and the newly latched value X4, and the difference dX4 is calculated by the difference calculation section 233A. output to

In addition to the operation of the difference calculation unit 233, the difference calculation unit 233A performs the following operations. That is, the difference calculation section 233A calculates the difference Y2 (=dX4-dX3) between the difference dX4 output from the latch section 232A and the difference dX3 received from the signal line 4. FIG. The difference calculator 233A outputs the difference Y2 to the FRC corrector 234A.

The FRC correction unit 234A performs the following operations in addition to the operations of the FRC correction unit 234. That is, the FRC corrector 234A corrects the FRC 231 based on the difference Y2.

Next, the flow of correction processing for clock deviation caused by static jitter, which is executed in the control device 1A, will be described.

First, the synchronization signal output section 132 of the CPU unit 100A outputs the synchronization signal to the expansion unit 200A. The synchronization signal is also output to the latch section 133A (see (21) in the figure).

Next, the latch section 133A of the CPU unit 100A latches the value X3 of the FRC 134 when the synchronization signal was output in response to the synchronization signal input (see (22) in the figure). The latch section 232A of the extension unit 200A latches the value X4 of the FRC 235 when the synchronization signal is received (see (23) in the figure) in response to the synchronization signal input.

The latch unit 133A calculates the difference dX3 between the value X3′ of the FRC 134 latched when the synchronization signal was output last time and the value X3 newly latched, and outputs the difference dX3 to the expansion unit 200A ((24 )reference).

The latch unit 232A calculates the difference dX4 between the value X4' of the FRC 235 latched when the previous synchronization signal was input and the newly latched value X4, and outputs the difference dX4 to the difference calculation unit 233A (( 25)). The difference calculator 233A calculates the difference Y2 between the difference dX4 and the difference dX3 (see (26) in the figure). The difference calculator 233A outputs the calculated difference Y2 to the FRC corrector 234 (see (27) in the figure).

The FRC correction unit 234A corrects the FRC 231 based on the difference Y2 (see (28) in the figure).

The difference Y2 indicates the difference between the count number of FRC134 and the count number of FRC235 in the target period from the output of the previous synchronization signal to the output of the current synchronization signal. As described above,

FRCs

131 and 134 count up in the same period. Furthermore,

FRCs

231 and 235 count up in the same cycle. Therefore, the difference between the FRC131 count number and the FRC231 count number in the target period is also the difference Y2. The FRC corrector 234A corrects the value of the FRC 231 by the difference Y2, thereby correcting the clock deviation caused by the static jitter.

Also in the control device 1A, the FRC231 is once synchronized with the FRC131 according to the synchronization processes (1) to (7) shown in FIG. However, clock deviation due to static jitter continues to occur. Therefore, the FRC correction unit 234A continues to periodically correct the FRC 231 based on the difference Y2. For example, the FRC corrector 234 corrects the clock deviation at a predetermined correction cycle. Assuming that the target period from the output of the previous synchronization signal to the output of the current synchronization signal is T1, and the correction period is T2, the FRC correction unit 234 performs (Y2/T1)×T2 for each correction period. FRC231 should be corrected. This always cancels clock deviations due to static jitter.

In addition to static jitter, there is dynamic jitter as a cause of the difference between the values of FRC131 and FRC231. Dynamic jitter includes, for example, transmission delay of synchronization signals. According to Modification 1, the clock deviation caused by static jitter is always cancelled. Therefore, even if the output cycle of the synchronization signal is lengthened, it is possible to avoid excessive deviation between the values of FRC131 and FRC231 due to dynamic jitter. This reduces the load required for the synchronization processing by the CPU 10 when the synchronization processing according to (11) to (16) shown in FIG. 2 is repeatedly executed after the firmware is activated.

After the firmware is activated, the CPU 10 may disable only the output operation of the time information by the latch section 133A and enable the output operation of the difference dX3 by the latch section 133A. This allows the

hardware circuits

13A and 23A to continue correcting clock deviations caused by static jitter even after the firmware has started.

Alternatively, the CPU 10 may disable the operation of outputting the difference dX3 by the latch section 133A after the firmware is activated. In this case, the firmware includes an instruction to calculate the difference Y2 between the difference dX3 calculated by the latch section 133A and the difference dX4 calculated by the latch section 232A, and an instruction to correct the FRC 231 based on the difference Y2. The CPU 10 may correct the FRC 231 based on the difference Y2 according to these commands of the firmware. This allows the CPU 10 to continue correcting the clock deviation caused by static jitter after the firmware is started. However, in this case, modification of the firmware is required. In order to omit modification of the firmware, the CPU 10 preferably enables the output operation of the difference dX3 by the latch section 133A after the firmware is started.

<G. Modification 2>
FIG. 8 is a diagram schematically showing the configuration of a control device 1B according to Modification 2. As shown in FIG. As shown in FIG. 8, the control device 1B includes a CPU unit 100B and an expansion unit 200B. The CPU unit 100B differs from the CPU unit 100 shown in FIG. 1 in that it includes a hardware circuit 13B instead of the hardware circuit 13. FIG. Expansion unit 200B is different from expansion unit 200 shown in FIG. 1 in that it includes hardware circuit 23B instead of hardware circuit 23 . Note that the

memories

11 and 21 and the

storages

12 and 22 are omitted from FIG. Also, Modification 2 may be combined with Modification 1. FIG.

The hardware circuit 13B differs from the hardware circuit 13 in that it includes a light emitting element 135. The hardware circuit 23B differs from the hardware circuit 23 in that it includes a light-emitting element 236 .

The

light emitting elements

135, 236 are, for example, light emitting diodes. Light-emitting

elements

135 and 236 blink according to the values of

FRC

131 and 231, respectively. Specifically, the

light emitting elements

135 and 236 emit light when the

FRCs

131 and 231 reach preset values. Before starting the firmware, the

FRCs

131 and 231 are synchronized by the processes (1) to (7) shown in FIG. After starting the firmware, the

FRCs

131 and 231 are synchronized by the processes (11) to (15) shown in FIG. Therefore, the

light emitting elements

135 and 236 emit light at the same timing. As a result, in the control device 1B, the blinking cycles of the light emitting elements of the units are synchronized, and a sense of unity can be given to the user. Conversely, the user can recognize that some kind of abnormality has occurred by visually confirming that the blinking cycles of the light emitting elements of the units are not synchronized.

<H. Modification 3>
In Modification 1, each of the CPU unit 100A and the expansion unit 200A has two FRCs. Therefore, the scale of the hardware circuit increases. Modification 3 is a mode in which the clock deviation caused by static jitter is continuously corrected while suppressing an increase in the scale of the hardware circuit.

FIG. 9 is a diagram schematically showing the configuration of a control device 1C according to Modification 3. As shown in FIG. As shown in FIG. 9, the control device 1C includes a CPU unit 100C and an expansion unit 200C. The CPU unit 100C differs from the CPU unit 100A shown in FIG. 7 in that it includes a hardware circuit 13C instead of the hardware circuit 13A. Expansion unit 200C differs from expansion unit 200A shown in FIG. 7 in that it includes hardware circuit 23C instead of hardware circuit 23A. 9, the

memories

11 and 21 and the

storages

12 and 22 are omitted in the same manner as in FIG.

The hardware circuit 13C differs from the hardware circuit 13A in that it has a synchronization signal output section 132C, a latch section 133C and a signal interval counting section 136 instead of the synchronization signal output section 132, the latch section 133A and the FRC 134. do.

The signal interval counting unit 136 includes a counter that counts up according to a clock generated using a clock oscillation source (not shown) provided in the CPU unit 100C. The signal interval counting section 136 outputs an output instruction to the synchronization signal output section 132C at the timing when the counter value reaches a certain value T. FIG. The signal interval counting section 136 resets the counter value to 0 when outputting the output instruction to the synchronization signal output section 132C.

The value T corresponds to a constant cycle for outputting the synchronization signal and is set in advance. If the frequency of the clock generated using the clock oscillation source (not shown) is 125 MHz, the value T is, for example, 125000 (corresponding to 1 ms). In this case, the signal interval counting section 136 may include a 16-bit counter. That is, the signal interval counting unit 136 includes a counter smaller in scale than the 64-bit FRC 134 (see FIG. 7). Therefore, as compared with Modification 1, an increase in the scale of the hardware circuit 13C is suppressed.

The synchronization signal output section 132C outputs the synchronization signal to the expansion unit 200C in response to receiving the output instruction from the signal interval counting section 136. The synchronization signal output from the synchronization signal output section 132C is also input to the latch section 133C.

The FRC 131 also counts up according to a clock generated using a clock oscillation source (not shown) provided in the CPU unit 100C. Therefore, the counter included in the signal interval counting unit 136 and the FRC 131 count up at the same period.

The latch section 133C performs the same operation as the latch section 133 shown in FIG. That is, the latch section 133C latches the value X1 of the FRC 131 when the synchronization signal is output, and outputs time information including the held value X1 to the extension unit 200C. Furthermore, the latch section 133C causes the value T set in the signal interval counting section 136 to be included in the time information.

Compared to the hardware circuit 23A, the hardware circuit 23C includes a latch unit 232A, a difference calculation unit 233A, an FRC correction unit 234A and a latch unit 232 instead of the FRC correction unit 235, a difference calculation unit 233C, an FRC correction unit 234C, and a signal interval measurement. It differs in that it has a portion 237 .

The signal interval measuring section 237 includes a counter that counts up according to a clock generated using a clock oscillation source (not shown) provided in the expansion unit 200C. The signal interval measurement unit 237 outputs the counter value T1 to the difference calculation unit 233C at the timing of receiving the synchronization signal, and resets the counter value to 0. As a result, the value T1 output from the signal interval measuring section 237 represents the count-up from the timing at which the previous synchronization signal was received to the timing at which the current synchronization signal was received.

The value T1 almost coincides with the constant period in which the synchronization signal is output. The value T1 is comparable to the value T. Therefore, the signal interval measuring section 237 may include a counter of the same scale as the signal interval counting section 136 . That is, the signal interval measurement unit 237 may include a counter smaller in scale than the 64-bit FRC 235 (see FIG. 7). Therefore, as compared with Modification 1, an increase in the scale of the hardware circuit 23C is suppressed.

The FRC 231 also counts up according to a clock generated using a clock oscillation source (not shown) provided in the expansion unit 200C. Therefore, the counter included in signal interval measuring section 237 and FRC 231 count up at the same period. Therefore, the signal interval measuring section 237 measures the value T1 as the difference between the value of the FRC 231 when the previous synchronization signal was output and the value of the FRC 231 when the current synchronization signal was output.

The difference calculation unit 233C performs the same operation as the difference calculation unit 233 shown in FIG. That is, the difference calculation unit 233C calculates the value X2 output from the latch unit 232 (that is, the value of the FRC 231 when the synchronization signal is received) and the value X1 received from the CPU unit 100C (that is, when the synchronization signal is output). FRC131 value of ) and the difference Y1 (=X2-X1) is calculated. Further, the difference calculation section 233C calculates the difference Z (=T1-T) between the value T1 received from the signal interval measurement section 237 and the value T received from the CPU unit 100C. The difference calculator 233C outputs the differences Y1 and Z to the FRC corrector 234C.

The FRC correction unit 234C corrects the FRC 231 based on the difference Z in addition to the operation of the FRC correction unit 234 shown in FIG.

Next, the flow of correction processing executed by the control device 1C will be described. First, the signal interval counting section 136 of the CPU unit 100C outputs an output instruction to the synchronization signal output section 132C at the timing when the counter value reaches a preset value T, and resets the counter value to 0 (see (31)).

Next, the synchronization signal output section 132C outputs the synchronization signal to the expansion unit 200C according to the output instruction. The synchronization signal is also output to the latch section 133C of the CPU unit 100C (see (32) in the figure).

The latch unit 133C latches the value X1 of the FRC 131 when the synchronization signal is output in response to the input of the synchronization signal, and extends the time information including the value X1 and the value T set in the signal interval counting unit 136. Output to the unit 200C (see (33) in the figure).

The latch section 232 of the extension unit 200C latches the value X2 of the FRC 231 when receiving the synchronization signal in response to the input of the synchronization signal, and outputs the value X2 to the difference calculation section 233C (see (34) in the figure). .

The signal interval measuring section 237 of the extension unit 200C measures the value T1, which is the count-up from the timing at which the previous synchronization signal is received to the timing at which the current synchronization signal is received, in response to the input of the synchronization signal. T1 is output to the difference calculator 233C (see (35) in the figure).

Next, the difference calculator 233C calculates the difference Y1 between the values X2 and X1 and the difference Z between the values T1 and T (see (36) in the figure). The difference calculator 233C outputs the calculated differences Y1 and Z to the FRC corrector 234C (see (37) in the figure).

Next, the FRC correction unit 234C corrects the FRC 231 based on the differences Y1 and Z (see (38) in the figure). The method of correcting the FRC 231 based on the difference Y1 is as described above.

The method of correcting FRC231 based on difference Z is the same as the method of correcting FRC231 based on difference Y2.

The difference Z indicates the difference between the count number of the signal interval counting section 136 and the count number of the signal interval measuring section 237 in the target period from the output of the previous synchronization signal to the output of the current synchronization signal. As described above, the counter included in the signal interval counting section 136 and the FRC 131 count up at the same period. Furthermore, the counter included in the signal interval measuring section 237 and the FRC 231 count up at the same period. The difference Z is therefore the clock deviation due to static jitter.

　Clock deviation caused by static jitter continues to occur. Therefore, the FRC correction unit 234C continues to periodically correct the FRC 231 based on the difference Z. For example, the FRC corrector 234C corrects the clock deviation at a predetermined correction period. Assuming that the target period from the output of the previous synchronization signal to the output of the current synchronization signal is T1, and the correction period is T2, the FRC correction unit 234C performs (Z/T1)×T2 for each correction period. FRC231 should be corrected. This always cancels clock deviations due to static jitter.

FIG. 10 is a diagram showing the flow of data accompanying the waveform of the synchronization signal in Modification 3. FIG. FIG. 10 shows the data flow for correction of clock deviation due to static jitter.

As shown in FIG. 10, the synchronizing signal is output at a constant cycle indicated by the value T. At the timing at which the synchronization signal is asserted, time information including the value T is output from the CPU unit 100C to the extension unit 200C.

The signal interval measuring section 237 of the extension unit 200C measures a value T1 that is the count-up from the timing at which the previous synchronization signal was received to the timing at which the current synchronization signal is received. For example, when a synchronization signal is received at timing t1, _a value T11 is measured which is a count-up from timing t0 at which the previous synchronization signal was received to timing t1. Then, the difference Z1 between the value _T11 and the value T is calculated, and the FRC 231 is corrected based _on the difference _Z1 .

The clock deviation caused by static jitter also depends on temperature and other factors. Therefore, the value T1 measured each time the synchronization signal is received may change depending on the environment. Therefore, by measuring the value T1 at regular intervals, the clock deviation caused by the static jitter is appropriately corrected according to the environment.

<I. If there are multiple expansion units >
FIG. 11 is a diagram showing a signal distribution method when there are a plurality of extension units. As shown in FIG. 11, each of

signal lines

3 and 4 connects CPU unit 100 and a plurality of expansion units 200 in a multi-drop configuration. Therefore, the synchronizing signal and time information output from the CPU unit 100 are distributed to the plurality of expansion units 200 via the

signal lines

3 and 4, respectively.

On the other hand, the data bus 2 conforming to PCIe connects the CPU unit 100 and each of the plurality of expansion units 200 on a one-to-one basis.

Note that in FIG. 11, the CPU unit 100 may be replaced with any one of the

CPU units

100A, 100B, and 100C. Also, each of the plurality of expansion units 200 may be replaced with one of

expansion units

200A, 200B, and 200C.

§3 Supplementary Note As described above, the present embodiment includes the following disclosures.

(Configuration 1)
A control device (1, 1A, 1B, 1C),
A first unit (100, 100A, 100B, 100C) and a second unit (200, 200A, 200B, 200C) for exchanging data,
said first unit includes a first hardware circuit (13, 13A, 13B, 13C);
the second unit includes a second hardware circuit (23, 23A, 23B, 23C);
The first hardware circuit comprises:
a first counter (131);
a signal output unit (132, 132C) that outputs a synchronization signal to the second unit;
a time information output unit (133, 133A, 133C) that outputs a first value of the first counter when the synchronization signal is output to the second unit;
The second hardware circuit comprises:
a second counter (231);
a difference calculator (233, 233A, 233C) for calculating a first difference between the second value of the second counter and the first value when the synchronization signal is received;
and a correction unit (234, 234A, 234C) that corrects the second counter based on the first difference.

(Configuration 2)
said first hardware circuit (13A) further comprising a third counter (134);
The second hardware circuit (23A) further comprises a fourth counter (235),
The signal output unit (132) repeatedly outputs the synchronization signal,
The time information output unit (133A) further outputs the value of the third counter when the previous synchronization signal was output and the value of the third counter when the current synchronization signal was output. outputting the second difference of to the second unit (200A),
The difference calculator (233A) further
calculating a third difference between the value of the fourth counter when receiving the previous synchronization signal and the value of the fourth counter when receiving the synchronization signal this time;
calculating a fourth difference between the second difference and the third difference;
The control device (1A) according to Configuration 1, wherein the correction section (234A) corrects the second counter based on the fourth difference.

(Composition 3)
The signal output unit (132C) outputs the synchronization signal each time the value of the first counter increases by a constant value,
The time information output section (133C) further outputs the constant value to the second unit,
The second hardware circuit (23C) stores the value of the second counter when the previous synchronization signal was output and the value of the second counter when the current synchronization signal was output. further comprising a measurement unit (237) for measuring the second difference of
The difference calculator (233C) further calculates a third difference between the second difference and the constant value,
The control device (1C) according to claim 1, wherein said correction section (234C) corrects said second counter based on said third difference.

(Composition 4)
The first unit (100B) further comprises a first light emitting element (135) that blinks according to the value of the first counter,
4. The control device (1B) according to any one of configurations 1 to 3, wherein the second unit (100C) further comprises a second light emitting element (236) that blinks according to the value of the second counter.

(Composition 5)
said first unit further comprising a processor (10) executing firmware,
The firmware includes an instruction for setting the timing for outputting the synchronization signal to the signal output unit,
The signal output unit outputs the synchronization signal when the value of the first counter reaches the timing,
The firmware further:
instructions for calculating a fifth difference between the second value and the timing;
an instruction to correct the second counter based on the fifth difference;
The control device according to configuration 1, wherein the processor disables the operation of the time information output unit after the firmware is activated.

(Composition 6)
the first hardware circuit is an ASIC or FPGA;
6. The controller of any of configurations 1-5, wherein the second hardware circuit is an ASIC or FPGA.

Although the embodiment of the present invention has been described, it should be considered that the embodiment disclosed this time is illustrative in all respects and not restrictive. The scope of the present invention is indicated by the claims, and is intended to include all changes within the meaning and range of equivalents to the claims.

1, 1A, 1B, 1C, 1Z control device, 2, 5 data bus, 3, 4 signal line, 10, 20 CPU, 11, 21 memory, 12, 22 storage, 13, 13A, 13B, 13C, 13Z, 23 , 23A, 23B, 23C, 23Z hardware circuits, 100, 100A, 100B, 100C, 100Z CPU units, 110P, 111P, 210P, 211P signal ports, 132, 132C synchronization signal output units, 133, 133A, 133C, 232, 232A latch section, 135, 236 light emitting elements, 136 signal interval counting section, 200, 200A, 200B, 200C, 200Z expansion unit, 233, 233A, 233C difference calculating section, 234, 234A, 234C correcting section, 237 signal interval measuring section , 300 functional units.

Claims

a controller,
comprising a first unit and a second unit for exchanging data;
the first unit includes a first hardware circuit;
the second unit includes a second hardware circuit;
The first hardware circuit comprises:
a first counter;
a signal output unit that outputs a synchronization signal to the second unit;
a time information output unit that outputs a first value of the first counter when the synchronization signal is output to the second unit;
The second hardware circuit comprises:
a second counter;
a difference calculator that calculates a first difference between the second value of the second counter and the first value when the synchronization signal is received;
and a correction unit that corrects the second counter based on the first difference.
the first hardware circuit further comprising a third counter;
the second hardware circuit further comprises a fourth counter;
The signal output unit repeatedly outputs the synchronization signal,
The time information output unit further outputs a second value between the value of the third counter when the previous synchronization signal was output and the value of the third counter when the current synchronization signal was output. outputting the difference of to the second unit;
The difference calculation unit further
calculating a third difference between the value of the fourth counter when receiving the previous synchronization signal and the value of the fourth counter when receiving the synchronization signal this time;
calculating a fourth difference between the second difference and the third difference;
The control device according to claim 1, wherein said correction unit corrects said second counter based on said fourth difference.
The signal output unit outputs the synchronization signal each time the value of the first counter increases by a constant value;
The time information output unit further outputs the constant value to the second unit,
The second hardware circuit stores a second value between the value of the second counter when the previous synchronization signal was output and the value of the second counter when the current synchronization signal was output. further having a measuring unit for measuring the difference of
The difference calculation unit further calculates a third difference between the second difference and the constant value,
The control device according to claim 1, wherein said correction unit corrects said second counter based on said third difference.
The first unit further comprises a first light emitting element that blinks according to the value of the first counter;
4. The control device according to any one of claims 1 to 3, wherein said second unit further comprises a second light emitting element that blinks according to the value of said second counter.
the first unit further comprising a processor executing firmware;
The firmware includes an instruction for setting the timing for outputting the synchronization signal to the signal output unit,
The signal output unit outputs the synchronization signal when the value of the first counter reaches the timing,
The firmware further:
instructions for calculating a fifth difference between the second value and the timing;
and an instruction to correct the second counter based on the fifth difference;
2. The control device according to claim 1, wherein said processor disables operation of said time information output unit after starting said firmware.
the first hardware circuit is an ASIC or FPGA;
6. The control device according to any one of claims 1 to 5, wherein said second hardware circuit is an ASIC or FPGA.