WO2022165350A3 - Architecture for multiplier accumulator using unit elements for multiplication, bias, accumulation, and analog to digital conversion over a shared charge transfer bus - Google Patents

Architecture for multiplier accumulator using unit elements for multiplication, bias, accumulation, and analog to digital conversion over a shared charge transfer bus Download PDF

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Publication number
WO2022165350A3
WO2022165350A3 PCT/US2022/014586 US2022014586W WO2022165350A3 WO 2022165350 A3 WO2022165350 A3 WO 2022165350A3 US 2022014586 W US2022014586 W US 2022014586W WO 2022165350 A3 WO2022165350 A3 WO 2022165350A3
Authority
WO
WIPO (PCT)
Prior art keywords
charge transfer
analog
ues
bias
adc
Prior art date
Application number
PCT/US2022/014586
Other languages
French (fr)
Other versions
WO2022165350A2 (en
Inventor
Martin Kraemer
Ryan Boesch
Wei Xiong
Original Assignee
Redpine Signals Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US17/163,556 external-priority patent/US11567730B2/en
Priority claimed from US17/163,494 external-priority patent/US12026479B2/en
Priority claimed from US17/163,493 external-priority patent/US11469770B2/en
Priority claimed from US17/163,588 external-priority patent/US20220244915A1/en
Priority claimed from US17/164,689 external-priority patent/US11476866B2/en
Application filed by Redpine Signals Inc filed Critical Redpine Signals Inc
Publication of WO2022165350A2 publication Critical patent/WO2022165350A2/en
Publication of WO2022165350A3 publication Critical patent/WO2022165350A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4814—Non-logic devices, e.g. operational amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspects of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in AND-groups, each AND gate coupled to a charge transfer bus through a charge transfer capacitor Cu to form an analog multiplication product. Each UE transfers differential charge to the charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.
PCT/US2022/014586 2021-01-31 2022-01-31 Architecture for multiplier accumulator using unit elements for multiplication, bias, accumulation, and analog to digital conversion over a shared charge transfer bus WO2022165350A2 (en)

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US17/163,494 2021-01-31
US17/163,556 US11567730B2 (en) 2021-01-31 2021-01-31 Layout structure for shared analog bus in unit element multiplier
US17/163,493 2021-01-31
US17/163,494 US12026479B2 (en) 2021-01-31 Differential unit element for multiply-accumulate operations on a shared charge transfer bus
US17/163,493 US11469770B2 (en) 2021-01-31 2021-01-31 Architecture for multiplier accumulator using unit elements for multiplication, bias, accumulation, and analog to digital conversion over a shared charge transfer bus
US17/163,556 2021-01-31
US17/164,689 2021-02-01
US17/163,588 US20220244915A1 (en) 2021-02-01 2021-02-01 Layout Structure for Shared Analog Bus in Unit Element Multiplier
US17/164,689 US11476866B2 (en) 2021-02-01 2021-02-01 Successive approximation register using switched unit elements
US17/163,588 2021-02-01

Publications (2)

Publication Number Publication Date
WO2022165350A2 WO2022165350A2 (en) 2022-08-04
WO2022165350A3 true WO2022165350A3 (en) 2022-09-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2022/014586 WO2022165350A2 (en) 2021-01-31 2022-01-31 Architecture for multiplier accumulator using unit elements for multiplication, bias, accumulation, and analog to digital conversion over a shared charge transfer bus

Country Status (1)

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WO (1) WO2022165350A2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9281834B1 (en) * 2012-09-05 2016-03-08 IQ-Analog Corporation N-path interleaving analog-to-digital converter (ADC) with offset gain and timing mismatch calibration
US20190042199A1 (en) * 2018-09-28 2019-02-07 Intel Corporation Compute in memory circuits with multi-vdd arrays and/or analog multipliers
US10417460B1 (en) * 2017-09-25 2019-09-17 Areanna Inc. Low power analog vector-matrix multiplier
US20200192971A1 (en) * 2018-12-18 2020-06-18 Macronix International Co., Ltd. Nand block architecture for in-memory multiply-and-accumulate operations
US20200401206A1 (en) * 2018-07-29 2020-12-24 Redpine Signals, Inc. Method and system for saving power in a real time hardware processing unit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9281834B1 (en) * 2012-09-05 2016-03-08 IQ-Analog Corporation N-path interleaving analog-to-digital converter (ADC) with offset gain and timing mismatch calibration
US10417460B1 (en) * 2017-09-25 2019-09-17 Areanna Inc. Low power analog vector-matrix multiplier
US20200401206A1 (en) * 2018-07-29 2020-12-24 Redpine Signals, Inc. Method and system for saving power in a real time hardware processing unit
US20190042199A1 (en) * 2018-09-28 2019-02-07 Intel Corporation Compute in memory circuits with multi-vdd arrays and/or analog multipliers
US20200192971A1 (en) * 2018-12-18 2020-06-18 Macronix International Co., Ltd. Nand block architecture for in-memory multiply-and-accumulate operations

Also Published As

Publication number Publication date
WO2022165350A2 (en) 2022-08-04

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