WO2022160469A1 - 一种液晶像素的控制电路及控制方法 - Google Patents

一种液晶像素的控制电路及控制方法 Download PDF

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Publication number
WO2022160469A1
WO2022160469A1 PCT/CN2021/087387 CN2021087387W WO2022160469A1 WO 2022160469 A1 WO2022160469 A1 WO 2022160469A1 CN 2021087387 W CN2021087387 W CN 2021087387W WO 2022160469 A1 WO2022160469 A1 WO 2022160469A1
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Prior art keywords
liquid crystal
transistor
crystal pixel
gate
order programming
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PCT/CN2021/087387
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English (en)
French (fr)
Inventor
张锦
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上海树泉信息技术有限公司
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Publication date
Priority claimed from CN202110121466.7A external-priority patent/CN114822427A/zh
Priority claimed from CN202110179350.9A external-priority patent/CN114913823A/zh
Application filed by 上海树泉信息技术有限公司 filed Critical 上海树泉信息技术有限公司
Publication of WO2022160469A1 publication Critical patent/WO2022160469A1/zh
Priority to US18/226,795 priority Critical patent/US20230367150A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0235—Field-sequential colour display
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/08—Arrangements within a display terminal for setting, manually or automatically, display parameters of the display terminal
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/772—Field effect transistors
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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the invention belongs to the technical field of liquid crystal screen display, and in particular relates to a control circuit and a control method of a liquid crystal pixel.
  • the display principle of an ordinary liquid crystal screen is: after each line of thin film transistors in the display device of the liquid crystal screen is turned on by the gate circuit, the source circuit is responsible for charging. During this period, the backlight on the back of the liquid crystal screen is responsible for providing light source illumination, and the liquid crystal Each pixel is responsible for the passing of light and the size of the number of passing light, so as to form a color image with the cooperation of color filters; it is characterized by the presence of color filters, and the backlight is always on.
  • the principle of sequential field display liquid crystal has been proposed; its basic logic is to use a single-color LCD screen with only grayscale control, with different colors of backlight, to achieve color display by mixing colors in time.
  • the three light sources of RGB are turned on in sequence without interval, and the image is decomposed into three sub-pictures of red, green and blue.
  • the red image is output, the red light is turned on, and the liquid crystal pixel controls the gray scale to allow a certain proportion of the red light to pass through.
  • the green light is turned on, and the liquid crystal pixel controls the gray scale to allow a certain percentage of the green light to pass through. The same goes for blue.
  • the liquid crystal pixel can achieve 180Hz refresh
  • the red, green and blue backlight can also achieve 180Hz refresh coordination, and each screen can be controlled.
  • all the red, green and blue lines are matched in every three fields, and every three fields constitute a frame of color image.
  • a refresh rate of 180Hz a 60Hz color picture can be achieved with the refresh of the light source and the liquid crystal pixels matched with the timing.
  • the display driving of the liquid crystal is to scan line by line in turn, and turn on the liquid crystal pixel charging circuit, and then another circuit charges the liquid crystal pixels. After the charging is completed, the liquid crystal is twisted to realize the passage of light and realize the image display.
  • the resolution of the displayed image is getting higher and higher, the scanning time from the first line to the last line is getting longer and longer, and the requirements for the driving circuit are getting higher and higher; taking 1080P as an example, it is necessary to scan at each subframe time. 1080 lines of scans are completed within, so the time for each line is very short. After all scans are completed, turn on the backlight. From this, it can be found that under the condition that the total display time of each sub-frame picture is constant, the time left for the backlight source to drive and turn on the backlight source is less.
  • the total time of each sub-frame is 5.6 milliseconds; if the charging of the first line starts and the charging of the last line is completed, if the required time is 5.4 milliseconds, it means that the human eye has already watched the image of the first line for 5.4 milliseconds. , the last line under this screen is displayed, so there will be tearing and dislocation of the image.
  • the backlight display color of each subfield is different; for example, the backlight is turned on in the order of red, blue and green. If it takes 5.4 milliseconds for the first line to start charging and display to the last line, that is, line 1080, then after 0.2 milliseconds, the first line has begun to display the next screen, that is, blue; but at the current time point, the last line is still. The data of the red screen is still retained, and the data of the blue screen has not been charged; in this case, the color of the image is disordered; to solve this problem, either start with the backlight, separate the driving sub-regions of the backlight, and separate the driving sub-regions from the LCD.
  • the charging data is completely synchronized and displayed in time and area; and this idea of solving the problem will lead to huge design difficulties and cost increase; This leads to an increase in the cost of the driver chip and difficulty in circuit design.
  • the present invention provides a control circuit for liquid crystal pixels, which can realize the synchronous operation of liquid crystal pixels under the premise that the existing liquid crystal pixels scan and input the image display content through the gate and the source, thereby effectively improving the process from the first Color confusion and screen tearing caused by time delay from line to last line.
  • Another object of the present invention is to provide a method for controlling a liquid crystal pixel, which is implemented based on the above control circuit for a liquid crystal pixel.
  • a control circuit of a liquid crystal pixel comprising a preset charging module, a second-order programming module and a first-order programming module connected in sequence;
  • the preset charging module is used to charge the liquid crystal pixel capacitor through a high level, and preset the liquid crystal pixel to a high level state;
  • the second-order programming module discharges the preset charging module according to the programming data of the first-order programming module, so that the electric charge reaches the maintenance voltage required by the liquid crystal pixel to display the image;
  • the first-order programming module receives and saves the electric charge sent from the external control unit for displaying the next frame of image.
  • the preset charging module includes a liquid crystal pixel capacitor Cls, one end of the liquid crystal pixel capacitor Cls is connected to the reference voltage of the liquid crystal screen, and the other end is connected to the second-order programming module.
  • the second-level programming module includes a double-gate transistor T4, one end of the liquid crystal pixel capacitor Cls is connected to the reference voltage of the liquid crystal screen, and the other end is connected to the drain of the double-gate transistor T4.
  • the first-order programming module includes a first transistor T1, the source of the dual-gate transistor T4 is coupled to the first synchronization signal Vst1, and one of the gates of the dual-gate transistor T4 is coupled to the second synchronization signal Vst2 , the other gate is coupled to the first transistor T1; the gate of the first transistor T1 is coupled to the external gate driver GATE DRIVER, and the source of the first transistor T1 is coupled to the external source driver SOURCE DRIVER.
  • the first transistor T1 is a dual-gate transistor.
  • both gates of the first transistor T1 are connected to Vscan.
  • the first transistor T1 is a dual-gate transistor
  • one gate of the first transistor T1 is connected to Vscan, and the other gate is connected to the first synchronization signal Vst1.
  • the first transistor T1 is a dual-gate transistor
  • one gate of the first transistor T1 is connected to Vscan, and the other gate is connected to the other gate of the dual-gate transistor T4.
  • the first transistor T1 is a dual-gate transistor
  • one gate of the first transistor T1 is connected to Vscan, and the other gate is connected to one of the gates of the dual-gate transistor T4.
  • the first transistor T1 is a dual-gate transistor
  • one gate of the first transistor T1 is connected to Vscan, and the other gate is connected to the liquid crystal pixel capacitor Cls.
  • the preset charging module further includes a second transistor T2, the gate of the second transistor T2 is coupled to the external level Vpre, the drain is coupled to the external level VH, and the source passes through the internal node Vpx and the liquid crystal pixel. Capacitor Cls is connected.
  • the second-order programming module includes a storage capacitor Cs and a third transistor T3, the drain of the third transistor T3 is coupled to the upper end of the liquid crystal pixel capacitor Cls and the source of the second transistor T2, the third transistor T3 The source stage of the three transistors T3 is coupled to the second synchronization signal Vst2, the gate of the third transistor T3 is coupled to one end of the storage capacitor Cs through the internal node, and the other end of the storage capacitor Cs is connected to the first synchronization signal Vst1 .
  • the gate of the first transistor T1 is connected to a gate used for driving the entire liquid crystal screen.
  • the source level of the first transistor T1 is connected to the source driver source for driving the entire LCD screen driver, the drain of the first transistor T1 is coupled to the storage capacitor Cs and the third transistor T3 through the internal node Q.
  • each pixel unit is connected to at least one first synchronization signal electrode line and one second synchronization signal electrode line, and the two electrode lines are global common electrode lines used to control all pixels.
  • the layout of the global common electrode lines The way is: arranging along the lateral gate direction, arranging along the vertical source direction, or arranging crosswise.
  • two adjacent rows or two columns can share a global common electrode line of the same nature, so as to reduce the occupation of the opening area.
  • a method for controlling a liquid crystal pixel which applies the above-mentioned control circuit for a liquid crystal pixel, and is specifically implemented according to the following steps:
  • preset charging link charge the liquid crystal pixel capacitor through a high level, and preset the liquid crystal pixel to a high level state;
  • the second-level programming link programming through the second-level programming module to discharge the preset charging module, so that the charge reaches the maintenance voltage required by the liquid crystal pixel to display the image;
  • the first-order programming link maintain the charge voltage of the liquid crystal pixel, and at the same time receive and save the charge sent from the external control unit through the first-order programming module for the display of the next frame of image.
  • all the liquid crystal pixels constituting the liquid crystal screen are preset to a high level at one time and synchronously through a high level.
  • all the liquid crystal pixels constituting the liquid crystal screen are preset to a high level at one time and synchronously through a high level, specifically:
  • the liquid crystal pixel capacitance is preset to the external high level VH through the cooperation of the first synchronization signal Vst1 and the second synchronization signal Vst2;
  • all the liquid crystal pixels constituting the liquid crystal screen are preset to a high level at one time and synchronously through a high level, specifically:
  • the liquid crystal pixel capacitor is preset to the external high level VH through the cooperation of the external level Vpre and the liquid crystal pixel VH.
  • the second-order programming module is used for programming in S2, so that the preset charging module is discharged so that the charge reaches the maintenance voltage required by the liquid crystal pixel to display the image, specifically:
  • the double-gate transistor T4 When the second-level programming module only includes the double-gate transistor T4, the double-gate transistor T4 is turned on through the cooperation of the first synchronization signal Vst1 and the second synchronization signal Vst2, and the liquid crystal pixel capacitor Cls is discharged; When the pixel capacitor Cls discharges, its discharge time depends on the time when the high and low levels of the first synchronizing signal Vst1 and the second synchronizing signal Vst2 cooperate with each other. stored charge.
  • the second-order programming module includes the storage capacitor Cs and the third transistor T3
  • the third transistor T3 is turned on through the cooperation of the first synchronization signal Vst1 and the second synchronization signal Vst2, and the liquid crystal pixel capacitor Cls is turned on.
  • Discharge, the conduction capability and conduction duration of the third transistor T3 are determined by the charge stored in the storage capacitor Cs in the S3, the first synchronization signal Vst1 and the second synchronization signal Vst2, and the liquid crystal
  • the power of the pixel capacitor Cls is released from the high-level state to a required power, and then the voltage of the liquid crystal pixel capacitor Cls is programmed to a maintenance voltage required by the liquid crystal pixel to display an image.
  • the discharge time depends on the time when the high and low levels of the first synchronization signal Vst1 and the second synchronization signal Vst2 cooperate with each other.
  • liquid crystal pixel capacitor Cls when discharged, its discharge capacity depends on the charge stored in S3.
  • the second-order programming of all the pixels constituting the liquid crystal screen is synchronously completed at one time.
  • the backlight is turned on, and the first-order programming is started synchronously.
  • the backlight is turned on, and first-order programming is performed after buffering, wherein the first-order programming can be extended to the preset charging link of the next frame, but It cannot be extended to second-order programming.
  • the charge voltage of the liquid crystal pixel is maintained in S3, and at the same time, the first-order programming module receives and saves the charge from the external control unit for displaying the next frame of image.
  • the second-order programming module includes a storage capacitor Cs , specifically:
  • buffering stage the buffering stage delays the charging time of the first-order programming work on the first line of the liquid crystal screen, thereby adjusting the retention time of the storage capacitor Cs in the second-order programming module, and determining the first-order programming from the first line. to the end time of the last line;
  • S32 first-order programming stage: the LCD screen performs charging operations in sequence from the first row to the last row, the gate driver of the LCD screen cooperates with the source driver source driver, from the first row to the last row, for each LCD The pixel is charged by first-order programming; wherein, the charging data is related to the displayed image and controlled by the source driver;
  • the second-order programming module does not include the storage capacitor Cs, it is specifically:
  • the buffering stage delays the time when the first line of the liquid crystal screen starts charging for the first-order programming, and then adjusts the retention time of the top and bottom gates of the dual-gate transistor T4 in the second-order programming module by delaying the liquid crystal.
  • the first line of the screen starts the charging time of the first-order programming work, and then adjusts the holding time of the storage capacitor Cs in the second-order programming module, and determines the end time of the first-order programming from the first line to the last line;
  • the first-order programming stage the LCD screen performs charging operations in sequence from the first row to the last row.
  • First order programming charging where the charging data is related to the displayed image and is controlled by the source driver.
  • the time of the buffering stage in S31 depends on the manufacturing process of the liquid crystal screen, and the maximum time is not greater than the time used for one frame of images.
  • the first-order programming time of all liquid crystal pixels can be completed in the current frame, and can also be extended to the S1 stage of the next frame, but cannot be extended to the S2 stage.
  • the method further includes: sequentially turning on and off the backlight of the liquid crystal screen, and sequentially performing the first-order programming process in the first-order programming stage, forming a pipeline-type driving logic.
  • the operating voltage Vpx of the liquid crystal pixel Cls is in the range of 0 ⁇ Vpx ⁇ VH, where VH is the capacitance of the liquid crystal pixel being preset. voltage when it is set to the highest level.
  • the dual-gate transistors maintain the high-level state of the liquid crystal pixel capacitor for a certain period of time and then conduct, and discharge the liquid crystal pixel capacitor to zero level.
  • the time for maintaining the high level depends on the charge in the S3 and the parameters of the ramp wave.
  • the liquid crystal pixel capacitor is first charged with a high level, and the liquid crystal pixel is preset to a high level state; Set the charging module to discharge, so that the charge reaches the maintenance voltage required by the liquid crystal pixel to display the image; finally, the charge voltage of the liquid crystal pixel is maintained, and at the same time, the first-order programming module receives and saves the charge from the external control unit for the next Display of frame images; by first presetting the liquid crystal pixel unit to a high level, and then discharging to the level required to display the image, the speed is faster than charging from a low level to a high level;
  • the internal design of the liquid crystal pixel is significantly changed, the opaque area occupied by the capacitor is saved, the aperture ratio is improved, and the brightness is improved;
  • the data used for display is programmed into the display, and the traditional driving mode of the gate scanning of the LCD screen can be used, because from the first row It takes a long time to scan the driving mode to the last line, and has the advantages of lower requirements for driving capability;
  • the buffer design logic is better to reduce the leakage current and cause the capacitor voltage to drop too much, some programming data is inaccurate, and the display inaccurate circumstances;
  • the more preferred embodiment only needs two transistors and one capacitor to realize the above functions, and the volume is controllable, the process is controllable, and the cost is controllable. application value.
  • FIG. 1 is a circuit diagram of a control circuit of a liquid crystal pixel according to Embodiment 1 of the present invention.
  • FIG. 2a is a diagram of a first connection mode of the first transistor T1 when the first transistor T1 is a dual-gate transistor in a control circuit for a liquid crystal pixel provided in Embodiment 1 of the present invention
  • FIG. 2b is a diagram of a second connection mode of the first transistor T1 when the first transistor T1 is a dual-gate transistor in a control circuit for a liquid crystal pixel provided in Embodiment 1 of the present invention
  • FIG. 2c is a diagram of a third connection mode of the first transistor T1 when the first transistor T1 is a dual-gate transistor in a control circuit for a liquid crystal pixel provided in Embodiment 1 of the present invention;
  • FIG. 2d is a diagram of a fourth connection mode of the first transistor T1 when the first transistor T1 is a dual-gate transistor in a control circuit for a liquid crystal pixel provided in Embodiment 1 of the present invention
  • FIG. 2e is a diagram of a fifth connection mode of the first transistor T1 when the first transistor T1 is a dual-gate transistor in a control circuit for a liquid crystal pixel provided in Embodiment 1 of the present invention
  • FIG. 3a is another circuit diagram of a control circuit of a liquid crystal pixel provided in Embodiment 1 of the present invention.
  • FIG. 3b is a circuit diagram of a liquid crystal pixel control circuit provided in Embodiment 1 of the present invention, when the liquid crystal pixel capacitor is charged by an external timing control circuit;
  • 3c is a circuit diagram of a control circuit of a liquid crystal pixel provided in Embodiment 1 of the present invention, when a preset charging module is in a charging stage;
  • 3d is a circuit diagram of a second-order programming module in a programming stage in a control circuit for a liquid crystal pixel provided in Embodiment 1 of the present invention
  • FIG. 3e is a circuit diagram of a control circuit for a liquid crystal pixel provided in Embodiment 1 of the present invention, when the second-order programming module is a double-gate structure;
  • FIG. 4 is a schematic diagram of the design of the interior of the IGZO liquid crystal screen when the second-order programming module adopts dual gate design logic in a control circuit for a liquid crystal pixel provided in Embodiment 1 of the present invention
  • FIG. 5 is a mode diagram of a dual threshold voltage of a dual gate transistor in a control circuit for a liquid crystal pixel provided in Embodiment 1 of the present invention
  • FIG. 6 is a circuit diagram of a first-order programming module in a programming stage in a control circuit for a liquid crystal pixel provided in Embodiment 1 of the present invention
  • FIG. 7a is a schematic diagram of the internal design of an IGZO liquid crystal screen when the second-order programming module adopts a dual-gate design logic in a control circuit for a liquid crystal pixel provided in Embodiment 1 of the present invention
  • FIG. 7b is a schematic representation of a dual-gate transistor T4 in a control circuit for a liquid crystal pixel provided in Embodiment 1 of the present invention.
  • FIG. 8 is a flowchart of a method for controlling a liquid crystal pixel according to Embodiment 2 of the present invention.
  • FIG. 9 is a schematic diagram of a pipeline-type field-sequential light-emitting and programming mode of a method for controlling a liquid crystal pixel provided in Embodiment 2 of the present invention.
  • FIG. 10 is a schematic diagram of a pipeline-type preferred field sequential lighting and programming mode of a liquid crystal pixel control method provided in Embodiment 2 of the present invention.
  • FIG. 11 is a liquid crystal driving timing diagram of a method for controlling a liquid crystal pixel provided in Embodiment 2 of the present invention.
  • Vst1 and Vst2 are square wave signals in a method for controlling a liquid crystal pixel according to Embodiment 2 of the present invention, and the entire liquid crystal adopts an analog modulation method.
  • Preset charging module 2.
  • Second-order programming module 3.
  • First-order programming module 3.
  • bottom gate control and the top gate control in the text are relative, and the source electrode and the drain electrode are also relative; those skilled in the art can make adjustments according to conventional means;
  • the first synchronization signal, the second synchronization signal, and the external high-level VH signal belong to global public data of different natures, and the naming is relative, which may be different for different habits.
  • the electrodes corresponding to the global voltage are named differently under different driving methods and calculation methods, in order to take into account the habits of those skilled in the art;
  • the LTPS process and the expression habit are adopted, but the method in the present invention is equally applicable to the liquid crystal screen produced by the technical process of different liquid crystal screens such as IGZO, a-Si, OTFT;
  • the present invention is to solve the problem of the field sequential color realization method
  • the name of the field-sequentially driven liquid crystal screen used in the present invention is also called the timing method, the color-sequential method, etc. in different occasions.
  • Embodiment 1 of the present invention provides a control circuit for a liquid crystal pixel, as shown in FIG. 1 , which includes a preset charging module 1 , a second-order programming module 2 and a first-order programming module 3 connected in sequence;
  • the preset charging module 1 is used to charge the liquid crystal pixel capacitor through a high level, and preset the liquid crystal pixel to a high level state;
  • the second-order programming module 2 discharges the preset charging module 1 according to the programming data of the first-order programming module 3, so that the electric charge reaches the maintenance voltage required by the liquid crystal pixel to display the image;
  • the first-order programming module 3 receives and saves the electric charge transmitted from the external control unit for the display of the next frame of image;
  • the liquid crystal pixel capacitor of the preset charging module 1 is first charged at a high level, and the liquid crystal pixel is preset to a high level state;
  • the charging module is preset to discharge, so that its charge reaches the maintenance voltage required by the liquid crystal pixel to display the image;
  • the first-order programming module 3 receives and saves the charge from the external control unit for use.
  • the display of the next frame of image; that is, while the current image is displayed, the power required for the display of the next frame of image is prepared in advance. This way of displaying and storing in advance saves time and effectively improves the LCD grid. Color confusion and screen tearing caused by the time delay from the first line to the last line in extreme scan drive mode.
  • the preset charging module 1 includes a liquid crystal pixel capacitor Cls, one end of the liquid crystal pixel capacitor Cls is connected to the reference voltage of the liquid crystal screen, and the other end is connected to the second-order programming module 2;
  • liquid crystal pixel capacitor Cls can be directly charged by the external timing-controlled circuit VH.
  • the second-order programming module 2 includes a double-gate transistor T4, one end of the liquid crystal pixel capacitor Cls is connected to the reference voltage of the liquid crystal screen, and the other end is connected to the drain of the double-gate transistor T4;
  • the first-order programming module 1 includes a first transistor T1, the source of the dual-gate transistor T4 is coupled to the first synchronization signal Vst1, one of the gates of the dual-gate transistor T4 is coupled to the second synchronization signal Vst2, and the other is coupled to the second synchronization signal Vst2.
  • One gate is coupled to the first transistor T1; the gate of the first transistor T1 is coupled to the external gate driver GATE DRIVER, and the source of the first transistor T1 is coupled to the external source driver SOURCE DRIVER;
  • the liquid crystal pixel capacitor Cls is charged at a high level to preset the liquid crystal pixel to a high level state; then the double-gate transistor T4 is turned on to program the charge to realize discharge and make the charge Reach the working voltage required for the liquid crystal pixel to display the image; finally, while maintaining the charge voltage of the liquid crystal pixel, the first transistor T1 receives and saves the charge sent from the external control unit for the display of the next frame of image;
  • the method effectively improves the traditional LCD gate scan driving mode, the time from the first line to the last line is very long, the brightness caused by the compression of the backlight illumination time is not enough, or when the liquid crystal pixels have not been charged to the data of this frame. , the backlight has been turned on, so the color confusion and picture tearing will be caused by too long non-this frame brightness;
  • this embodiment only needs two transistors (the first transistor T1 and the double-gate transistor T4) and one capacitor (the liquid crystal pixel capacitor Cls) to realize the above functions, and the volume is controllable, the process is controllable, and the cost is controllable. Controllable, and because of its small size, the aperture ratio and light transmittance are high, and the backlight illumination time is long, which has good application value.
  • the first transistor T1 is a dual gate transistor.
  • the transistor T1 can be connected in the following five ways:
  • both gates of the first transistor T1 are connected to Vscan, as shown in FIG. 2a;
  • the first transistor T1 is a dual-gate transistor, one gate of the first transistor T1 is connected to Vscan, and the other gate is connected to the first synchronization signal Vst1, as shown in FIG. 2b;
  • first transistor T1 when the first transistor T1 is a dual-gate transistor, one gate of the first transistor T1 is connected to Vscan, and the other gate is connected to the other gate of the dual-gate transistor T4, as shown in Figure 2c shown;
  • transistor T1 when the transistor T1 is a dual-gate transistor, one gate of the first transistor T1 is connected to Vscan, and the other gate is connected to one of the gates of the dual-gate transistor T4, as shown in FIG. 2d ;
  • the first transistor T1 is a dual-gate transistor, one gate of the first transistor T1 is connected to Vscan, and the other gate is connected to the liquid crystal pixel capacitor Cls, as shown in FIG. 2e;
  • This wiring method has the effect of enhancing feedback, specifically:
  • the auxiliary gate potential is also a high-level voltage, which reduces the Vth value of the first transistor T1 and increases its programming speed;
  • the auxiliary gate potential is a low level voltage, which makes the Vth value of the first transistor T1 higher, so that programming enters the voltage on the gate node of the dual-gate transistor T4 better maintained;
  • Vscan is the gate driving voltage generated by the external gate driver
  • Vdata is the source driving voltage generated by the external source driver
  • Vth is the threshold voltage of the first transistor T1.
  • the preset charging module 1 not only includes the liquid crystal pixel capacitor Cls, but also further includes a second transistor T2, the gate of the second transistor T2 is coupled to the external level Vpre, and the drain is coupled to the external power Flat VH, the source is connected to the liquid crystal pixel capacitor Cls through the internal node Vpx.
  • the second-order programming module 2 has two structures:
  • the second-level programming module 2 includes a storage capacitor Cs and a third transistor T3, the drain of the third transistor T3 is coupled to the upper end of the liquid crystal pixel capacitor Cls and the drain of the second transistor T2
  • the source stage, the source stage of the third transistor T3 is coupled to the second synchronization signal Vst2
  • the gate of the third transistor T3 is coupled to one end of the storage capacitor Cs through an internal node, and the other end of the storage capacitor Cs is connected to the first synchronization signal Vst1;
  • the external level Vpre is set to a high-level voltage
  • the first synchronization signal Vst1 is set to a low-level voltage
  • the second synchronization signal Vst2 is a high-level voltage
  • the gate data of the first transistor T1 The signal Vg[n] is a low-level voltage; then the second transistor T2 is turned on, and the first transistor T1 and the third transistor T3 are both off.
  • all the liquid crystal pixel capacitors in the pixel array Both Cls are pulled up to the high-level voltage VH synchronously, so as to charge the preset charging module 1 .
  • the internal node Vpx when the preset charging module 1 is working, the internal node Vpx is at a high level; after secondary programming by the second-level programming module 2, the internal node Vpx is the maintenance voltage required by the liquid crystal pixel to display an image .
  • the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on. As shown in FIG. 3d , the turned-on third transistor T3 discharges the liquid crystal pixel capacitor Cls.
  • the second-level programming module 2 of this structure includes a double-gate transistor T4 (same as the previous embodiment), as shown in FIG. 3e, the drain of the double-gate transistor T4 is connected in parallel with the liquid crystal pixel capacitor through the internal node Vpx
  • the source of the dual-gate transistor T4 is coupled to the second synchronization signal Vst2
  • one gate of the dual-gate transistor T4 is connected to the first synchronization signal Vst1
  • the other gate is connected to the first synchronization signal Vst1. Coupled with the first-order programming module 3 through the internal node Q;
  • the second-order programming module 2 of this structure adopts dual gate logic and reduces one capacitor Cs, and has an optimized design of saving circuit area and improving aperture ratio, which is a preferred design of the present invention
  • the arrangement of the double-gate transistor reduces a light-shielding area significantly after reducing a capacitance; this is a significant change for the interior of the liquid crystal pixel.
  • ESL is the SiOx dielectric protection layer
  • TG is the top gate, the top gate signal line of the transistor
  • BG is the bottom gate, the bottom gate signal line of the transistor
  • IGZO is the IGZO layer of the liquid crystal screen
  • GLASS is the glass substrate layer of the liquid crystal screen
  • S is the transistor source
  • D is the drain of the transistor
  • the common structure in IGZO TFT pixel design is back-channel protection type (ESL type) as an example.
  • ESL type back-channel protection type
  • the IGZO active layer is controlled by the bottom gate insulating layer to form the first gate control, that is, bottom gate control.
  • the IGZO active layer is protected by the SiOx dielectric layer (ie, the ESL layer) on the back side, a top gated structure can be designed to form a second gated structure with the IGZO active layer, that is, a top gated structure.
  • the top gate control structure may be composed of a source-drain metal layer, an ESL layer, and an IGZO layer.
  • a dual-threshold voltage mode can be formed, and a liquid crystal LCD display pixel circuit under two-stage programming charging logic can be formed.
  • top gate control structure can also be composed of a top ITO metal layer, an ESL layer, and an IGZO layer;
  • the transition from the first-order programming state completed in the previous sequence to the second-order programming state of the current sequence depends on the change of the top gate control voltage in the double-gate transistor T4, that is, connected to The voltage of the first synchronization signal Vst1 is switched between high and low.
  • the first synchronization signal Vst1 is at a low voltage level, so the threshold voltage of the dual-gate transistor T4 is relatively large, and the third transistor T3 is turned off, maintaining the display data of the previous frame.
  • the first synchronization signal Vst1 is high, so the threshold voltage of the dual-gate transistor T4 is small, the third transistor T3 enters the conducting state, and the second-level programming mode is performed.
  • the upper end of the liquid crystal pixel capacitor Cls The voltage Vpx is updated to the final desired voltage state.
  • the double-gate transistor T4 due to the device conduction performance of the double-gate transistor T4, it can be switched between various operating modes due to the top gate control.
  • the top gate control voltage When the top gate control voltage is low, it works in a high threshold voltage mode; and When the top gate control voltage is high, it works in a low threshold voltage mode, as shown in Figure 5;
  • the other gate is bottom gated/top gated.
  • the conduction stage of the double-gate transistor T4 from the Vpx terminal to the Vst2 terminal, is an equivalent circuit of a linear resistance. Therefore, the turn-on capability and turn-on time of the entire circuit are jointly determined by the charge amount stored in the double-gate transistor T4 and Vst1 and Vst2. Thus, the charge of the pixel capacitor Cls can be discharged to an appropriate voltage, so as to achieve the final display target.
  • the first-order programming module 3 includes a first transistor T1, and the gate of the first transistor T1 is connected to a gate driver gate for driving the entire liquid crystal screen driver, the source level of the first transistor T1 is connected to the source driver source for driving the entire LCD screen driver, the drain of the first transistor T1 is coupled to the storage capacitor Cs and the third transistor T3 through the internal node Q;
  • the first synchronization signal Vst1 is set to be a low-level voltage
  • the second synchronization signal Vst2 is a high-level voltage
  • Vpre is set to a low-level voltage
  • the source data signal Vdata is in a high-level voltage state
  • the gate data signal Vg[n] is in a high-level voltage state, and at this time it enters a first-order programming state; that is, according to the basic principle of liquid crystal, several rows of first transistors T1 is scanned and opened by the gate circuit Vg[n] in turn, the storage capacitor Cs is in the state of receiving external charges, and the source data circuit of the liquid crystal performs charging work, that is, programming work. Display for the next cycle.
  • the first synchronization signal Vst1, the second synchronization signal Vst2, Vpre and VH in this embodiment all act on all the pixels of the entire liquid crystal screen.
  • the magnitude and nature of these global data signals are all the same.
  • the pixel circuit further includes at least two global common electrode lines for controlling all the pixels, and the layout of the global common electrode lines is: along the lateral gate direction, along the vertical source direction, or cross-arranged;
  • the global common electrode lines between two adjacent rows or two columns of liquid crystal pixels can be shared so that the arrangement of one line can be reduced, so as to increase the size of the liquid crystal screen. opening rate;
  • each liquid crystal pixel applying the circuit is connected to a plurality of common global electrode lines, the electrode lines are arranged in parallel or crosswise in rows or columns in the liquid crystal screen, and adjacent upper and lower rows or left and right columns
  • the liquid crystal pixels can all share the same common electrode line, so that one common electrode line can be saved in every two rows or every two columns, and a group of electrode lines can be reduced, so that the surface machine occupied by the wiring can be reduced. Increase the aperture ratio of the LCD screen.
  • FIG. 7a the cross-sectional view of the structure of the liquid crystal pixel unit including the double gate transistor T4 is shown in FIG. 7a, wherein Glass is the glass substrate layer of the liquid crystal screen; S is the source of the transistor; D is the drain of the transistor; TG is the top gate , the top gate signal line of the transistor; SHIELDING METAL is used as a protective layer and is defined as a bottom gate; LTPS represents the semiconductor layer under the LTPS process;
  • the LTPS active layer is controlled by the bottom gate insulating layer to form the first gate control, that is, the bottom gate control. And since the LTPS active layer is protected by the SiOx dielectric layer on the back side, a top gate control structure can be designed to form a second gate control structure with the LTPS active layer, that is, top gate control.
  • a dual-threshold voltage mode can be formed, and a liquid crystal LCD display pixel circuit under two-stage programming charging logic can be formed.
  • FIG. 7b the schematic diagram of the symbol of the double-gate transistor T4 is shown in FIG. 7b, wherein S is the source of the transistor; D is the drain of the transistor; TG and Shielding Metal represent the two gates, respectively.
  • the internal design of the liquid crystal pixel is significantly changed, the opaque area occupied by the capacitor is saved, the aperture ratio is improved, and the brightness is improved;
  • the data used for display is programmed into the display, and the traditional driving mode of the gate scanning of the LCD screen can be used, because from the first row It takes a long time to scan the driving mode to the last line, and has the advantages of lower requirements for driving capability;
  • the buffer design logic is better to reduce the leakage current and cause the capacitor voltage to drop too much, some programming data is inaccurate, and the display inaccurate circumstances;
  • the more preferred embodiment only needs two transistors and one capacitor to realize the above functions, and the volume is controllable, the process is controllable, and the cost is controllable. application value.
  • Embodiment 2 of the present invention provides a method for controlling a liquid crystal pixel, which applies the control circuit of the liquid crystal pixel described in Embodiment 1, as shown in FIG. 8 , and is specifically implemented according to the following steps:
  • preset charging link charge the liquid crystal pixel capacitor through a high level, and preset the liquid crystal pixel to a high level state; specifically:
  • the second-level programming link programming through the second-level programming module to discharge the preset charging module, so that the charge reaches the maintenance voltage required by the liquid crystal pixel to display the image; specifically:
  • the double-gate transistor T4 is turned on to discharge the liquid crystal pixel capacitor Cls;
  • the first synchronizing signal Vst1 and the second synchronizing signal Vst2 are the global voltages shared by the entire LCD screen, the second-order programming links of all the pixels constituting the LCD screen are synchronously completed at one time;
  • S3, first-order programming link maintain the charge voltage of the liquid crystal pixel, and at the same time receive and save the charge from the external control unit through the first-order programming module for the display of the next frame of image; specifically:
  • the entire LCD screen is charged in sequence from the first row to the last row.
  • the gate driver gate driver of the LCD screen and the source driver source driver cooperate with each other to perform first-order programming for each LCD pixel from the first row to the last row. Charge;
  • the charging data is related to the displayed image and is controlled by the source driver.
  • the liquid crystal pixels are turned on row by row and controlled by the gate driver.
  • the liquid crystal pixel capacitance is preset to the external high level VH through the cooperation of the first synchronization signal Vst1 and the second synchronization signal Vst2;
  • the liquid crystal pixel capacitor is preset to the external high level VH through the cooperation of the external level Vpre and the liquid crystal pixel VH.
  • the dual-gate transistor T4 When the second-level programming module 2 only includes the dual-gate transistor T4, the dual-gate transistor T4 is turned on through the cooperation of the first synchronization signal Vst1 and the second synchronization signal Vst2 to discharge the liquid crystal pixel capacitor Cls; When the liquid crystal pixel capacitor Cls is discharged, its discharge time depends on the time when the high and low levels of the first synchronization signal Vst1 and the second synchronization signal Vst2 cooperate with each other;
  • the second-order programming module 2 includes the storage capacitor Cs and the third transistor T3
  • the third transistor T3 is turned on through the cooperation of the first synchronization signal Vst1 and the second synchronization signal Vst2, and the liquid crystal pixel capacitor C1s is discharged
  • the turn-on capability and turn-on duration of the third transistor T3 are jointly determined by the charge stored in the storage capacitor Cs in the S3, the first synchronization signal Vst1 and the second synchronization signal Vst2, and the liquid crystal pixel capacitance is determined.
  • the power of Cls is released from the high-level state to the required power, and then the voltage of the liquid crystal pixel capacitor Cls is programmed to the maintenance voltage required by the liquid crystal pixel to display an image.
  • the second-order programming link in the S2 has two forms, which are voltage bootstrap digital programming and analog programming;
  • the range of the operating voltage Vpx of the liquid crystal pixel Cls is 0 ⁇ Vpx ⁇ VH , where VH is The voltage at which the liquid crystal pixel capacitance is preset to the highest level.
  • the working voltage is at a high level, but the time for maintaining the high level is determined by programming parameters , depending on the charge in S3 and the parameters of the ramp.
  • the first-order programming link of the S3 is specifically:
  • the second-order programming module includes the storage capacitor Cs, it is specifically:
  • buffering stage the buffering stage delays the charging time of the first-order programming work on the first line of the liquid crystal screen, thereby adjusting the retention time of the storage capacitor Cs in the second-order programming module, and determining the first-order programming from the first line. to the end time of the last line;
  • the first-order programming stage the entire LCD screen is charged in sequence from the first row to the last row.
  • the gate driver gate driver and the source driver source driver of the LCD screen cooperate with each other. From the first row to the last row, for each Each liquid crystal pixel is charged for first-order programming;
  • the charging data is related to the displayed image and is controlled by the source driver;
  • the second-order programming module does not include the storage capacitor Cs, it is specifically:
  • the buffering stage delays the time when the first line of the liquid crystal screen starts charging for the first-order programming, and then adjusts the retention time of the top and bottom gates of the dual-gate transistor T4 in the second-order programming module by delaying the liquid crystal.
  • the first line of the screen starts the charging time of the first-order programming work, and then adjusts the holding time of the storage capacitor Cs in the second-order programming module, and determines the end time of the first-order programming from the first line to the last line;
  • the first-order programming stage the LCD screen performs charging operations in sequence from the first row to the last row.
  • First order programming charging where the charging data is related to the displayed image and is controlled by the source driver.
  • the time of the buffer stage depends on the manufacturing process of the liquid crystal screen, and the maximum time is not greater than the time used for one frame of images.
  • the display control system controls the first transistor T1 to turn on through the gate driver GATE DRIVER, that is, by setting Vg[n] to a high level, that is, it can drive the gate data line of each row to turn on the first transistor T1; the source driver SOURCE DRIVER will display The voltage signal Vdata for the image is supplied to the storage capacitor Cs through the first transistor T1.
  • the first-order programming module in the S3 receives and saves the charges sent from the external control unit for the display of the next frame of image, because the LCD screen has many rows of liquid crystal pixel units, and programming starts from the first row until the end, longer time.
  • the first-order programming process can be continued to the preset charging link of the next frame, that is, the S1 process.
  • the liquid crystal display can display the correct image. ;
  • the buffer stage is used for the buffer period and preparation period in the driving process. Considering the actual situation when the liquid crystal gate circuit is activated, a certain period of preparation period needs to be set.
  • the preparation period ranges from 10 microseconds to 1 millisecond, depending on the performance of the liquid crystal. and gate driver GATE of LCD The performance of DRIVER is adjusted and fixed, and different applications are different.
  • the first synchronization signal Vst1 is set to be a low-level voltage
  • the second synchronization signal Vst2 is a high-level voltage
  • Vpre is a low-level voltage
  • both the second transistor T2 and the third transistor T3 are in an off state.
  • the source data signal Vdata is in a high-level voltage state
  • the gate data signal Vg[n] is in a high-level voltage state.
  • the first-order programming state is entered; that is, according to the basic principle of liquid crystal, several rows of liquid crystals are sequentially programmed.
  • the gate circuit Vg[n] scans to open the storage capacitor Cs, and the source data circuit of the liquid crystal performs charging work, that is, programming work. At this time, the storage capacitor Cs will obtain an appropriate state of charge for the display of the next cycle.
  • the backlight of the liquid crystal screen is turned off; in the S3 and buffer stages, the backlight of the liquid crystal screen is turned on.
  • the backlight of the liquid crystal screen in the S1 and S2 is turned off, and this period is called the black field;
  • the backlight of the liquid crystal screen in the S3 and buffer stages is turned on, and this period is called the light field;
  • the backlight source is turned off and the backlight source is turned on alternately to form a pipeline-type field sequence driving sequence.
  • the law-driven mode is an example:
  • FIG. 9 it is a pipeline-type field-sequential light-emitting and programming mode, wherein Disp indicates that the backlight is turned on to display an image; Prog is the sequential scanning of all pixels of the LCD screen to perform sequential first-order programming actions; 1 Frame Time is the display time of a frame including three sub-fields of red, green and blue; K is the black field, that is, the backlight is turned off.
  • these three subfields are R red subfield, G green subfield and B blue subfield, the color of the backlight matches the data of this subfield, and are also R red, G green and B blue ;
  • the first-order programming charging data is completed.
  • the programming data is used for the display of the next subfield.
  • the green field is the B subfield, and so on.
  • a further preferred pipelined field sequential display liquid crystal driving backlight sequence can be optimized to the logic shown in Figure 10: in this preferred mode, the first-order programming process continues until the S1 stage of the next subfield, that is, the preset charging stage, However, it is not extended to the S2 stage, that is, the second-order programming stage; the specific reason is: if the source data driver SOURCE of the liquid crystal The driving ability of the driver or the ability of the gate data driver GATE DRIVER is insufficient, or due to the large number of liquid crystal scanning lines, it takes longer to perform the first-order programming charging behavior from the first line of scanning to the completion of the last line.
  • the preferred pipelined backlight drive and programming mode as shown in Figure 10 can then be used. Under this logic, first-order programming can continue until the K field, ie, the black field.
  • the external level Vpre is set to a high-level voltage
  • the first synchronization signal Vst1 is set to a low-level voltage
  • the second synchronization signal Vst2 is a high-level voltage
  • the gate data signal Vg of the first transistor T1 [n] is the low level voltage
  • the second transistor T2 is turned on, the first transistor T1 and the third transistor T3 are both turned off, and all the liquid crystal pixel capacitors Cls in the pixel array are pulled up synchronously.
  • the preset charging module can be charged;
  • the VH and Vpre of the liquid crystal pixel are outside the liquid crystal screen, and each is controlled by the same set of circuits.
  • the preset charging voltage VH is pulled up synchronously, and the liquid crystal pixel capacitance Cls is also high. Sync charged.
  • the first synchronization signal Vst1 is set to be a high-level voltage
  • the second synchronization signal Vst2 is a low-level voltage
  • Vpre is a low-level voltage
  • the gate data signal Vg[n] is low. level voltage
  • the first transistor T1 and the second transistor T2 are turned off, the third transistor T3 is turned on, and the turned-on third transistor T3 discharges the liquid crystal pixel capacitor Cls.
  • the main function of this step is to release a part of the charge in the liquid crystal pixel capacitor Cls that is pre-charged in the S1 stage to achieve the voltage for finally displaying the correct image.
  • the capacitance data of the storage capacitor Cs, as well as the high and low level states of Vst1 and Vst2 affect the turn-on capability and turn-on time of T3, so as to realize the proper charge release of the liquid crystal pixel capacitor Cls.
  • the second-order programming is realized, so that the voltage of the liquid crystal pixel capacitor Cls is adjusted to the voltage and charge state required for the final display, and the correct image can be displayed when the backlight is driven to enter the light field timing link.
  • the voltage to which the liquid crystal pixel capacitor Cls is discharged depends on the conduction capability of the third transistor T3, and the conduction capability of the third transistor T3 depends on the voltage coupled to the gate of the third transistor T3 in the previous cycle.
  • the amount of charge stored on the storage capacitor Cs specifically:
  • the voltage of the liquid crystal pixel capacitor Cls is programmed to the maintenance voltage required for displaying the image on the liquid crystal screen, wherein the voltage to which the liquid crystal pixel capacitor Cls is discharged also depends on the duration of the S2, specifically:
  • the liquid crystal pixel capacitor Cls When the duration of S2 is longer, the liquid crystal pixel capacitor Cls is pulled down to a lower voltage; otherwise, the voltage on the liquid crystal pixel capacitor Cls is higher.
  • the entire LCD screen is charged in sequence from the first row to the last row, and the gate driver of the LCD screen gate
  • the driver and the source driver cooperate with each other, from the first row to the last row, perform first-order programming charging for each liquid crystal pixel; among them, the charging data is related to the displayed image, and the source driver source driver control.
  • the method further includes: sequentially turning on and off the backlight of the liquid crystal screen, and sequentially performing a first-order programming process in the first-order programming stage, forming a pipeline-type driving sequential logic.
  • the first synchronization signal Vst1 and the second synchronization signal Vst2 are both high-level voltages, and the threshold voltage of the dual-gate transistor T4 is reduced after modulation and enters the conduction region, so all pixels are synchronously grounded is set to a high level, which is to prepare for the subsequent pulse width modulation process;
  • the programming signal Vdata is input to the gate node of the dual-gate transistor T4 through the transistor T1.
  • the gates of the double-gate transistors are programmed to Vd1 and Vscan[2] successively.
  • Vd2 voltage with different charge levels;
  • Vth0 is the initial threshold voltage of the dual-gate transistor T4
  • Vdata is the source data voltage of the first-order programming
  • Vramp is the voltage of the ramp signal line, that is, Vst2, and k1 and k2 are coefficients;
  • Vth Vth0-Vdata- ⁇ *t; that is, the Vth value of the dual-gate transistor T4 is in dynamic change.
  • Vth0 1V
  • Vdata -2V
  • the display time can be realized as 5ms.
  • the Vgs is the voltage value between the source and the drain of the transistor.
  • the first-level programming data for each pixel remains on the busbar and does not change until the next first-level programming begins.
  • the first-order programming stage and the light field stage do not overlap, so the overall light field time is relatively short.
  • Fig. 11 is the driving sequence realized by adopting the pixel design circuit of Fig. 3a by adopting this method
  • Fig. 12 is the driving sequence realized by adopting the pixel design circuit of Fig. 1 and adopting this method;
  • FIG. 12 is an analog driving pixel circuit diagram and an operation timing diagram.
  • the first-order programming and second-order programming of the green G subframe and the light field L are described by taking the red R subframe and the green G subframe as an example. stage and black field K stage.
  • the red R subframe When displaying the red R subframe, on the one hand, the red R subframe is displayed normally, and on the other hand, the first-order programming of the green G subframe is synchronously expanded; it is worth pointing out that although the data signal of the G subframe passes through the transistor T1 It has entered the top gate of the dual-gate transistor T4, that is, the main gate, but since the voltage of the bottom gate of the dual-gate transistor T4, that is, the auxiliary gate Vst2 is low, the dual-gate transistor T4 is still in a higher threshold voltage Vth state, Therefore, the first-order programming of the green G subframe does not affect the normal display of the red R subframe, and the liquid crystal pixel capacitor Cls of the pixel circuit maintains the voltage required for displaying the red R subframe.
  • the black field includes two stages of the preset charging stage S1 and the second-order programming stage S2 in Figure 8, namely the S1 stage and the S2 stage in this Figure 12.
  • the charging stage first the second synchronization signal Vst2, that is, Vctrl in this figure, becomes a high level, and the first synchronization signal Vst1, that is, Vst in this figure, is also a high level, so the working voltage of the liquid crystal pixel capacitor Cls Vpx goes high VH synchronously;
  • the S3 stage that is, the S3 link described in Figure 8.
  • Different backlight colors represent different colors of the light field; in the S3 stage, that is, the light-emitting display state when the backlight is lit, because Vctrl has also become low. level, the threshold voltage Vth of the double-gate transistor T4 becomes high and is in an off state, so the voltage Vpx of the liquid crystal pixel capacitor Cls maintains the working voltage after the second-level programming is completed.
  • ⁇ T is the discharge time, that is, the duration of the second-order programming of P2
  • V H is the preset voltage when the liquid crystal pixel is preset to a high level
  • Tf is the discharge characteristic time of the liquid crystal pixel capacitor Cls, which depends on the characteristics of the liquid crystal pixel itself
  • Clc is the capacitance value of the liquid crystal pixel capacitor Cls
  • Req is the equivalent impedance of the drive transistor
  • L and W are the channel length and channel width of the double-gate transistor T4 respectively
  • ⁇ is the electron mobility
  • CI is the capacitance value of the gate dielectric layer per unit area of the TFT
  • Vt is the threshold voltage Vth of the TFT
  • Vdata is The data voltage value input by the source driver SOURCE DRIVER in the first-order programming stage.
  • each liquid crystal pixel capacitor represents a different liquid crystal pixel operating voltage Vpx, which is a constant constant for the same liquid crystal screen and the same image data.
  • Vpx liquid crystal pixel operating voltage
  • the time of second-order programming S2 can be defined according to the actual situation.
  • ⁇ T is the discharge time, that is, the duration of the second-order programming of S2 It is also a constant; therefore, the first-order programming data Vdata that needs to be input in the first-order programming stage can be calculated through the above method, so as to realize the image display and realize the simulation programming result.
  • the first-order programming data of each pixel continues to remain on the busbar, and does not change until the next first-order programming begins.
  • the second-order programming stage S2 enter the S3 stage, that is, the light field L field.
  • the L field is the green field G Frame
  • the backlight is on.
  • the first-order programming stage S32 is performed, as shown in Figure 8. S31 link and S32 link.
  • the maintaining range of the maintaining voltage V is 0 ⁇ V maintaining ⁇ Vfull bright , wherein Vfull Bright is the voltage at which the liquid crystal pixel is preset to the highest level.
  • data programming and lighting are performed in parallel pipeline operations.
  • the data programming action required for the next subframe G is also being performed synchronously. Therefore, the data writing action will not occupy the effective display time, which significantly increases the effective time, improves the field sequential display time, and reduces the driving capability requirements for programming devices;
  • the above-mentioned functions can be realized by only two transistors and one capacitor in this embodiment, and the volume is controllable, the process is controllable, and the cost is controllable, and because The small volume makes the aperture ratio and light transmittance high, and has good application value;
  • the above-mentioned functions can be realized by only two transistors in this embodiment, and the volume is controllable, the process is controllable, and the cost is controllable.
  • the aperture ratio and light transmittance are high, which has good application value;
  • the technical solution provided in this embodiment can be used not only for a liquid crystal screen using the field sequential method for display, but also for a traditional liquid crystal screen, that is, an ordinary liquid crystal screen in the background art.
  • the optimized double-gate transistor has a simpler pixel structure. It omits the capacitive element that consumes the most area in the original circuit, and only 3 TFTs are needed for the unit pixel. Therefore, the aperture ratio of its pixels is higher, and the efficiency of backlight conversion to actual display light conversion is higher;
  • TFT itself has a certain parasitic capacitance, especially for ESL type devices, its parasitic capacitance is relatively large, the actual programming voltage value is strongly affected by parasitic capacitance, due to the parasitic capacitance between process batches, etc. There is inevitably a certain deviation, which leads to the fact that the actual programming voltage value of the original pixel circuit may have deviations with different process batches;

Abstract

一种液晶像素的控制电路及控制方法，其中，液晶像素的控制电路包括依次连接的预置充电模块（1）、二阶编程模块（2）和一阶编程模块（3）；首先对预置充电模块（1）进行充电；之后通过二阶编程模块（2）对预置充电模块（1）进行编程，使其电压达到液晶屏显示图像所需的维持电压；最后当液晶屏在维持电压下显示当前图像时，一阶编程模块（3）为下一帧图像的显示存储电量；即在当前图像显示的同时，为下一帧图像显示所需的电量提前做准备，通过这种显示和提前存储共同进行的方式节省了时间，有效改善了液晶显示器栅极扫描驱动模式下，从第一行到最后一行的时间延迟导致的色彩混乱和画面撕裂现象。

Description

一种液晶像素的控制电路及控制方法 技术领域
本发明属于液晶屏显示技术领域，具体涉及一种液晶像素的控制电路及控制方法。
 背景技术
普通的液晶屏的显示原理为：液晶屏的显示装置中的每一行薄膜晶体管由栅极电路打开后，源极电路负责充电，此期间，在液晶屏的背面的背光源负责提供光源照明，液晶的每个像素负责光线的通过与否和通过光线的数量的大小，从而在彩色滤光片的配合下，形成彩色图像；其特点在于有彩色滤光片，背光源一直常亮。
随着技术进步，时序场显示液晶原理被提了出来；其基本逻辑是，采用单色只有灰阶控制的液晶屏，配合不同颜色的背光源，通过颜色在时间上混合的方法实现彩色显示。一般而言，采用RGB三种光源无间隔顺序打开，将图像分解为红绿蓝三色子画面，输出红色图像的时候，红色光线打开，液晶像素控制灰阶让一定比例的红光通过，需要绿色的时候，绿色光线打开，液晶像素控制灰阶让一定比例的绿光通过。对蓝色也如此控制。当液晶像素的动作和背光源的动作都可以实现一个比较高的开关速度，比如液晶像素实现180Hz的刷新，红绿蓝三色背光源也同样实现180Hz的刷新配合，就可以实现每场画面控制一种颜色，每三场画面完成全部的红绿蓝光线配合，每三场画面构成一帧彩色图像。对于180Hz的刷新速度而言，该时序配合的光源和液晶像素的刷新，就可以实现60Hz的彩色画面。
 技术问题
但是实际上，由于液晶的打开和关断都有一定的动作时间，液晶的显示驱动是一行接着一行依次扫描，并打开液晶像素充电电路，然后另外的电路对液晶像素进行充电。充电完成后液晶扭转，实现光线通过，实现图像显示。由于显示图像分辨率都越来越高，从第一行到最后一行扫描所花费的时间越来越长，对驱动电路要求越来越高；以1080P为例，就需要在每一个子帧时间内完成1080行扫描，所以每行时间很短，全部扫描完成后，再打开背光源。由此可以发现，每一子帧画面的总显示时间一定的情况下，留给背光源驱动点亮背光源的时间，在分辨率越高的情况下，这个时间是越少的。
比如：180Hz下，每子帧画面总时间是5.6毫秒；第一行充电开始，到最后一行充电完成，需要的时间如果是5.4毫秒，意味着人眼睛观看第一行的图像已经进行了5.4毫秒，这个画面下的最后一行才显示出来，这样就会出现图像的撕裂和错位。
如果刷新率更高，这个问题就更严重，对于如果需要场序显示的产品而言，每个子场的画面背光显示颜色不一样；比如按照红色蓝色绿色的顺序依次点亮背光源，如果从第1行开始充电显示到最后一行即1080行需要5.4毫秒的话，那么在0.2毫秒后，第一行已经开始进行下一场画面的显示，即蓝色；可是在当下的时间点，最后一行还依然保留着红色画面的数据，还未进行蓝色画面的数据充电；这种情况下，图像颜色是错乱的；要解决这样的问题，要么从背光入手，将背光的驱动分区域分开，和液晶的充电数据完全同步起来，分时分区域进行显示；而这个解决问题的思路，将导致巨大的设计困难和成本提升；要么就压缩从第一行开始充电到最后一行充电完成的时间，这也将导致驱动芯片成本提升和电路设计困难。
 技术解决方案
为了解决上述问题，本发明提供一种液晶像素的控制电路，能在现有液晶像素通过栅极和源极配合扫描输入图像显示内容的前提下，实现液晶像素同步工作，从而有效改善从第一行到最后一行的时间延迟导致的色彩混乱和画面撕裂现象。
本发明的另一目的是提供一种液晶像素的控制方法，其是基于以上的用于液晶像素的控制电路而实现的方法。
本发明所采用的技术方案是：
一种液晶像素的控制电路，其包括依次连接的预置充电模块、二阶编程模块和一阶编程模块；
所述预置充电模块，用于通过高电平向液晶像素电容充电，将液晶像素预置到高电平状态；
所述二阶编程模块，根据一阶编程模块的编程数据，实现对预置充电模块进行放电，使其电荷达到液晶像素显示图像所需的维持电压；
所述一阶编程模块，接收并保存来自外部控制单元输送的电荷，用于下一帧图像的显示。
优选地，预置充电模块包括液晶像素电容Cls，所述液晶像素电容Cls的一端和液晶屏的基准电压连接，另一端和二阶编程模块连接。
优选地，所述二阶编程模块包括双栅晶体管T4，所述液晶像素电容Cls的一端和液晶屏的基准电压连接，另一端与双栅晶体管T4的漏极连接。
优选地，所述一阶编程模块包括第一晶体管T1，所述双栅晶体管T4的源极耦合到第一同步信号Vst1，所述双栅晶体管T4的其中一个栅极耦合到第二同步信号Vst2，另一个栅极与第一晶体管T1耦合；所述第一晶体管T1的栅极耦合到外部栅极驱动器GATE DRIVER，第一晶体管T1的源极耦合到外部的源极驱动器SOURCE DRIVER。
优选地，所述第一晶体管T1为双栅晶体管。
优选地，当所述第一晶体管T1为双栅晶体管时，所述第一晶体管T1的两个栅极均连接到Vscan。
优选地，当所述第一晶体管T1为双栅晶体管时，所述第一晶体管T1的一个栅极连接到Vscan，另一栅极连接到第一同步信号Vst1。
优选地，当所述第一晶体管T1为双栅晶体管时，所述第一晶体管T1的一个栅极连接到Vscan，另一栅极与双栅晶体管T4的另一个栅极连接。
优选地，当所述第一晶体管T1为双栅晶体管时，所述第一晶体管T1的一个栅极连接到Vscan，另一个栅极与双栅晶体管T4的其中一个栅极连接。
优选地，当第一晶体管T1为双栅晶体管时，所述第一晶体管T1的一个栅极连接到Vscan，另一个栅极与液晶像素电容Cls连接。
优选地，所述预置充电模块进一步包括第二晶体管T2，所述第二晶体管T2的栅极耦合到外部电平Vpre，漏极耦合到外部电平VH，源极通过内部节点Vpx和液晶像素电容Cls连接。
优选地，所述所述二阶编程模块包括存储电容Cs和第三晶体管T3，所述第三晶体管T3的漏级耦合到液晶像素电容Cls的上端和第二晶体管T2的源级，所述第三晶体管T3的源级耦合到第二同步信号Vst2，所述第三晶体管T3的栅极通过内部节点耦合到存储电容Cs的一端连接，所述存储电容Cs的另一端连接到第一同步信号Vst1。
优选地，当所述一阶编程模块包括第一晶体管T1，所述二阶编程模块包括存储电容Cs和第三晶体管T3时，所述第一晶体管T1的栅极连接用于驱动整个液晶屏的栅极驱动器gate driver，所述第一晶体管T1的源级连接用于驱动整个液晶屏的源极驱动器source driver，所述第一晶体管T1的漏级通过内部节点Q与存储电容Cs和第三晶体管T3耦合。
优选地，每个像素单元至少连接一条第一同步信号电极线和一条第二同步信号电极线，该两条电极线是用于控制全部像素的全局公共电极线，所述全局公共电极线的布局方式为：沿横向栅极方向布置、沿纵向源极方向布置或者交叉布置。
优选地，该液晶像素控制电路的全局公共电极线，相邻的两行或者两列均可共用一条同性质的全局公共电极线，以减少开口面积占用。
一种液晶像素的控制方法，其应用上述的液晶像素的控制电路，具体按照如下步骤实施：
S1，预置充电环节：通过高电平向液晶像素电容充电，将液晶像素预置到高电平状态；
S2，二阶编程环节：通过二阶编程模块进行编程，实现对预置充电模块进行放电，使其电荷达到液晶像素显示图像所需的维持电压；
S3，一阶编程环节：维持液晶像素的电荷电压，并同时通过一阶编程模块接收并保存来自外部控制单元输送的电荷，用于下一帧图像的显示。
优选地，在所述S1的预置充电环节中中，通过高电平将组成液晶屏的所有液晶像素一次性地、同步地预置到高电平。
优选地，通过高电平将组成液晶屏的所有液晶像素一次性地、同步地预置到高电平，具体为：
当所述二阶编程模块仅包括双栅晶体管T4时，通过第一同步信号Vst1和第二同步信号Vst2的配合，将液晶像素电容预置到外部高电平VH；
优选地，通过高电平将组成液晶屏的所有液晶像素一次性地、同步地预置到高电平，具体为：
当所述二阶编程模块包括存储电容Cs和第三晶体管T3时，通过外部电平Vpre和液晶像素VH的配合，将液晶像素电容预置到外部高电平VH。
优选地，所述S2中通过二阶编程模块进行编程，实现对预置充电模块进行放电，使其电荷达到液晶像素显示图像所需的维持电压，具体为：
当所述二阶编程模块仅包括双栅晶体管T4时，通过第一同步信号Vst1和第二同步信号Vst2的配合，使双栅晶体管T4导通，对液晶像素电容Cls进行放电；所述对液晶像素电容Cls进行放电时，其放电时间取决于第一同步信号Vst1和第二同步信号Vst2高低电平相互配合的时间，其放电速度取决于双栅晶体管T4存储的电量，其放电能力取决于S3中保存的电荷。
优选地，当所述二阶编程模块包括存储电容Cs和第三晶体管T3时，通过第一同步信号Vst1和第二同步信号Vst2的配合，使第三晶体管T3导通，对液晶像素电容Cls进行放电，所述第三晶体管T3的导通的能力和导通的持续时间，由所述S3中保存在存储电容Cs中的电荷、第一同步信号Vst1和第二同步信号Vst2共同决定，将液晶像素电容Cls的电量从高电平状态释放到所需的电量，进而将液晶像素电容Cls的电压编程为液晶像素显示图像所需的维持电压。
优选地，所述对液晶像素电容Cls进行放电时，其放电时间取决于第一同步信号Vst1和第二同步信号Vst2高低电平相互配合的时间。
优选地，所述对液晶像素电容Cls进行放电时，其放电能力取决于S3中保存的电荷。
优选地，在所述S2的二阶编程环节中，组成液晶屏的所有像素的二阶编程是同步一次性完成的。
优选地，在所述S2的二阶编程环节之后，背光灯点亮，同步开始进行一阶编程。
优选地，在所述S2的二阶编程环节之后，背光灯点亮，缓冲之后进行一阶编程，其中，所述的一阶编程，可延申至下一帧画面的预置充电环节，但不可延伸至二阶编程环节。
优选地，所述S3中维持液晶像素的电荷电压，并同时通过一阶编程模块接收并保存来自外部控制单元输送的电荷，用于下一帧图像的显示，当二阶编程模块包括存储电容Cs时，具体为：
S31，缓冲阶段：所述缓冲阶段通过延迟液晶屏的第一行开始进行一阶编程工作充电的时间，进而调整二阶编程模块中存储电容Cs的保持时间，以及决定一阶编程从第一行到最后一行的结束时间；
S32，一阶编程阶段：液晶屏从第一行至最后一行，依次进行充电操作，液晶屏的栅极驱动器gate driver和源极驱动器source driver配合，从第一行到最后一行，对每个液晶像素进行一阶编程充电；其中，充电数据与所显示图像相关，由源极驱动器控制；
当二阶编程模块不包括存储电容Cs时，具体为：
缓冲阶段：所述缓冲阶段通过延迟液晶屏的第一行开始进行一阶编程工作充电的时间，进而调整二阶编程模块中双栅晶体管T4的顶栅和底栅存储电量的保持时间通过延迟液晶屏的第一行开始进行一阶编程工作充电的时间，进而调整二阶编程模块中存储电容Cs的保持时间，以及决定一阶编程从第一行到最后一行的结束时间；
一阶编程阶段：液晶屏从第一行至最后一行，依次进行充电操作，液晶屏的栅极驱动器gate driver和源极驱动器source driver配合，从第一行到最后一行，对每个液晶像素进行一阶编程充电；其中，充电数据与所显示图像相关，由源极驱动器控制。
优选地，所述S31中缓冲阶段的时间取决于液晶屏的制作工艺，且其最大时间不大于一帧画面所用的时间。
优选地，全部液晶像素的一阶编程时间，可在本帧画面中完成，也可延申到下一帧的S1阶段，但不能延伸至S2阶段。
优选地，该方法进一步包括：所述液晶屏的背光源依次打开和关闭、以及所述一阶编程阶段依次进行的一阶编程过程，形成了流水线型的驱动逻辑。
优选地，当所述第一同步信号Vst1和第二同步信号Vst2为方波时，所述的液晶像素Cls的工作电压Vpx的范围为0≤Vpx≤VH，其中，VH为液晶像素电容被预置到最高电平时的电压。
优选地，当所述第一同步信号Vst1和第二同步信号Vst2为斜波电压信号时，双栅晶体管将液晶像素电容的高电平状态维持一定时间后导通，将液晶像素电容放电到零电平。
优选地，当所述工作电压为高电平时，所述高电平维持的时间取决于所述S3中的电荷以及斜波的参数。
与现有技术相比，本发明使用时，首先通过高电平向液晶像素电容充电，将液晶像素预置到高电平状态；之后通过二阶编程模块对所述电荷进行编程，实现对预置充电模块进行放电，使其电荷达到液晶像素显示图像所需的维持电压；最后维持液晶像素的电荷电压，并同时通过一阶编程模块接收并保存来自外部控制单元输送的电荷，用于下一帧图像的显示；通过先将液晶像素单元预置到高电平，再放电到显示图像所需要的电平，比从低电平充电到高电平，速度更快；
其次，通过每帧画面都预置到高电平，消除了液晶电容在特定画面下会出现的残影现象；同时，在当前图像进行显示的同时，为下一帧图像显示所需的电量进行编程充电，因为这时候的编程充电是需要一行一行依次进行充电的，时间很长，通过这种当前画面显示和下一帧画面的电量数据的提前存储同时进行的方式，极大地降低了对外部栅极驱动器和源极驱动器的驱动能力的要求，也极大地延长了画面显示背光照明的时间，有效改善了液晶显示器栅极扫描驱动模式下，从第一行到最后一行的时间很长，压缩背光源照明时间导致的亮度不够，或者背光源时间过长会导致的色彩混乱和画面撕裂现象。
 有益效果
本实施例的有益效果如下：
首先，液晶屏的所有液晶像素，可以同步的进行正常显示；
其次，通过双栅晶体管的设计，显著的改变了液晶像素的内部设计，节省了电容占用的不透光的面积，改善了开口率，有利于提高亮度；
并且，本实施例通过在正常显示阶段，进行栅极电路和源极电路的配合，把显示所用的数据编程进去，可以采用传统方式下，液晶屏栅极扫描的驱动模式，因为从第一行到最后一行扫描驱动模式时间比较长，对驱动能力要求比较低的优点；
另外，通过每一帧画面里，设置一定时间的黑场，与背光点亮的光场的交替，改善了拖影现象，提升了画面质量；
通过特定的缓冲设计逻辑，对于不同制作工艺的液晶屏，由于TFT工艺不同，其泄露电流能力不同，缓冲设计逻辑比较好的减少了泄露电流导致电容电压下降过多，部分编程数据不准确，显示不准确的情况；
并且，更优选的实施例仅需两个晶体管和一个电容即可实现上述功能，其体积可控，工艺可控，成本可控，且因为体积小使得开口率和透光率高，具有很好的应用价值。
 附图说明
图1是本发明实施例1提供的一种液晶像素的控制电路的电路图。
图2a是本发明实施例1提供的一种液晶像素的控制电路中，当第一晶体管T1为双栅晶体管时，第一晶体管T1的第一种连接方式图；
图2b是本发明实施例1提供的一种液晶像素的控制电路中，当第一晶体管T1为双栅晶体管时，第一晶体管T1的第二种连接方式图；
图2c是本发明实施例1提供的一种液晶像素的控制电路中，当第一晶体管T1为双栅晶体管时，第一晶体管T1的第三种连接方式图；
图2d是本发明实施例1提供的一种液晶像素的控制电路中，当第一晶体管T1为双栅晶体管时，第一晶体管T1的第四种连接方式图；
图2e是本发明实施例1提供的一种液晶像素的控制电路中，当第一晶体管T1为双栅晶体管时，第一晶体管T1的第五种连接方式图；
图3a是本发明实施例1提供的一种液晶像素的控制电路另外一种电路图；
图3b是本发明实施例1提供的一种液晶像素的控制电路中，通过外部时序控制电路对液晶像素电容进行充电时的电路图；
图3c是本发明实施例1提供的一种液晶像素的控制电路路中，预置充电模块处于充电阶段时的电路图；
图3d是本发明实施例1提供的一种液晶像素的控制电路中，二阶编程模块处于编程阶段时的电路图；
图3e是本发明实施例1提供的一种液晶像素的控制电路中，二阶编程模块为双栅结构时的电路图；
图4是本发明实施例1提供的一种液晶像素的控制电路中，二阶编程模块采用双栅设计逻辑时，IGZO液晶屏内部的设计示意图；
图5是本发明实施例1提供的一种液晶像素的控制电路中，双栅晶体管的双阈值电压模式图；
图6是本发明实施例1提供的一种液晶像素的控制电路中，一阶编程模块处于编程阶段时的电路图；
图7a是本发明实施例1提供的一种液晶像素的控制电路中，二阶编程模块采用双栅设计逻辑时，IGZO液晶屏内部设计示意图；
图7b是本发明实施例1提供的一种液晶像素的控制电路中，一种双栅晶体管T4的表达示意图；
图8是本发明实施例2提供的一种液晶像素的控制方法的流程图；
图9是本发明实施例2提供的一种液晶像素的控制方法的流水线型的场序发光和编程模式示意图；
图10是本发明实施例2提供的一种液晶像素的控制方法的流水线型的优选场序发光和编程模式示意图；
图11是本发明实施例2提供的一种液晶像素的控制方法的液晶驱动时序图；
图12是本发明实施例2提供的一种液晶像素的控制方法中，Vst1和Vst2为方波信号时，整个液晶采取模拟模拟调制方法下，各驱动电压，外部全局电压的驱动时序图。
其中：1.预置充电模块，2.二阶编程模块，3.一阶编程模块。
 本发明的最佳实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本发明的描述中，需要明确的是，术语“垂直”、“横向”、“纵向”、“前”、“后”、“左”、“右”、“上”、“下”、“水平”等指示方位或位置关系为基于附图所示的方位或位置关系，仅仅是为了便于描述本发明，而不是意味着所指的装置或元件必须具有特有的方位或位置，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
在本发明的描述中，还需要说明的是，文本中的底栅控和顶栅控是相对的，源极和漏极也是相对的；本领域技术人员可根据常规手段进行调整；
本文发明中，第一同步信号，第二同步信号，以及外部高电平VH信号，属于不同性质的全局公用数据，命名是相对的，可能不同习惯会有不同。
并且，在本发明的描述中，针对不同的电路，全局电压对应的电极在不同的驱动方法和计算方法下，为照顾本领域技术人员的习惯，命名会有所不同；
在本发明的描述中，采用LTPS工艺和表述习惯，但是，本发明中的方法同样适用与采用IGZO、a-Si、OTFT等不同液晶屏的技术工艺生产的液晶屏；
本发明一方面是为了解决场序彩色实现方法下的问题，另一方面，也可以应用于传统的背光常亮的液晶屏；
本发明所用的场序驱动液晶屏的名称，在不同的场合也被称为时序法、色序法等。
实施例1
本发明实施例1提供一种液晶像素的控制电路，如图1所示，其包括依次连接的预置充电模块1、二阶编程模块2和一阶编程模块3；
所述预置充电模块1，用于通过高电平向液晶像素电容充电，将液晶像素预置到高电平状态；
所述二阶编程模块2，根据一阶编程模块3的编程数据，实现对预置充电模块1进行放电，使其电荷达到液晶像素显示图像所需的维持电压；
所述一阶编程模块3，接收并保存来自外部控制单元输送的电荷，用于下一帧图像的显示；
这样，采用上述结构，首先通过高电平向预置充电模块1的液晶像素电容充电，将液晶像素预置到高电平状态；然后通过二阶编程模块2对所述电荷进行编程，实现对预置充电模块进行放电，使其电荷达到液晶像素显示图像所需的维持电压；最后在液晶像素显示图像的过程中，通过一阶编程模块3接收并保存来自外部控制单元输送的电荷，用于下一帧图像的显示；即在当前图像显示的同时，为下一帧图像显示所需的电量提前做准备，通过这种显示和提前存储共同进行的方式节省了时间，有效改善了液晶显示器栅极扫描驱动模式下，从第一行到最后一行的时间延迟导致的色彩混乱和画面撕裂现象。
在具体实施例方式中：
所述预置充电模块1包括液晶像素电容Cls，所述液晶像素电容Cls的一端和液晶屏的基准电压连接，另一端和二阶编程模块2连接；
这样，通过外部时序控制的电路VH可实现对液晶像素电容Cls进行直接充电。
在其中一个实施例中：
所述二阶编程模块2包括双栅晶体管T4，所述液晶像素电容Cls的一端和液晶屏的基准电压连接，另一端与双栅晶体管T4的漏极连接；
所述一阶编程模块1包括第一晶体管T1，所述双栅晶体管T4的源极耦合到第一同步信号Vst1，所述双栅晶体管T4的其中一个栅极耦合到第二同步信号Vst2，另一个栅极与第一晶体管T1耦合；所述第一晶体管T1的栅极耦合到外部栅极驱动器GATE DRIVER，第一晶体管T1的源极耦合到外部的源极驱动器SOURCE DRIVER；
这样，采用上述结构，首先通过高电平向液晶像素电容Cls充电，将液晶像素预置到高电平状态；之后双栅晶体管T4导通，对所述电荷进行编程，实现放电，使其电荷达到液晶像素显示图像所需的工作电压；最后在维持液晶像素的电荷电压的同时，通过第一晶体管T1接收并保存来自外部控制单元输送的电荷，用于下一帧图像的显示；通这种方式有效改善了传统液晶显示器栅极扫描驱动模式下，从第一行到最后一行的时间很长，压缩背光源照明时间导致的亮度不够，或者在液晶像素还没有被充电到本帧数据的时候，背光源已经打开，从而过长的非本帧亮度会导致的色彩混乱和画面撕裂现象；
更为重要的是：本实施例仅需两个晶体管（第一晶体管T1和双栅晶体管T4）和一个电容（液晶像素电容Cls）即可实现上述功能，其体积可控，工艺可控，成本可控，且因为体积小使得开口率和透光率高，背光照明时间长，具有很好的应用价值。
在具体实施方式中：
所述第一晶体管T1为双栅晶体管。
为了有更好的开口效果，当所述第一晶体管T1为双栅晶体管时，所述晶体管T1的连接方式有以下五种：
第一种，当所述第一晶体管T1为双栅晶体管时，所述第一晶体管T1的两个栅极均连接到Vscan，如图2a所示；
第二种，当所述第一晶体管T1为双栅晶体管时，所述第一晶体管T1的一个栅极连接到Vscan，另一栅极连接到第一同步信号Vst1，如图2b所示；
第三种，当所述第一晶体管T1为双栅晶体管时，所述第一晶体管T1的一个栅极连接到Vscan，另一栅极与双栅晶体管T4的另一个栅极连接，如图2c所示；
第四种，当所述晶体管T1为双栅晶体管时，所述第一晶体管T1的一个栅极连接到Vscan，另一个栅极与双栅晶体管T4的其中一个栅极连接，如图2d所示；
第五种，当所述第一晶体管T1为双栅晶体管时，所述第一晶体管T1的一个栅极连接到Vscan，另一个栅极与液晶像素电容Cls连接，如图2e所示；
上述五种接线方式中，优选第三种，这种接线方式具有增强反馈的效果，具体为：
当需要传递较高电压的Vdata信号时，则辅助栅极电位也为高电平电压，这使得第一晶体管T1的Vth值降低，其编程速度被提升；
而当传递较低电位的Vdata信号时，则辅助栅极电位为低电平电压，这就使得第一晶体管T1的Vth值较高，使得编程进入到双栅晶体管T4的栅极节点上的电压更好地被保持；
其中，Vscan为外部栅极驱动器产生的栅极驱动电压，Vdata为外部源极驱动器产生的源极驱动电压，Vth为第一晶体管T1的阈值电压。
在另外一个实施例中：
如图3b所示，所述预置充电模块1不仅包括液晶像素电容Cls，还进一步包括第二晶体管T2，所述第二晶体管T2的栅极耦合到外部电平Vpre，漏极耦合到外部电平VH，源极通过内部节点Vpx和液晶像素电容Cls连接。
在该实施例中：
所述二阶编程模块2有两种结构：
第一种，如图3a所示，所述二阶编程模块2包括存储电容Cs和第三晶体管T3，所述第三晶体管T3的漏级耦合到液晶像素电容Cls的上端和第二晶体管T2的源级，所述第三晶体管T3的源级耦合到第二同步信号Vst2，所述第三晶体管T3的栅极通过内部节点耦合到存储电容Cs的一端连接，所述存储电容Cs的另一端连接到第一同步信号Vst1；
这样，在预置充电环节，外部电平Vpre设置为高电平电压，第一同步信号Vst1设置为低电平电压，第二同步信号Vst2为高电平电压，第一晶体管T1的栅极数据信号Vg[n]为低电平电压；于是第二晶体管T2被导通，第一晶体管T1和第三晶体管T3均为断开状态，如图3c所示，全部的像素阵列中的液晶像素电容Cls，均被同步地上拉到高电平电压VH，实现对对预置充电模块1进行充电。
并且，在所述预置充电模块1工作时，所述内部节点Vpx为高电平；经过二阶编程模块2进行二次编程后，所述内部节点Vpx为液晶像素显示图像所需的维持电压。
在二阶编程环节，设置第一同步信号Vst1为高电平电压，第二同步信号Vst2为低电平电压，Vpre为低电平电压，栅极数据信号Vg[n]为低电平电压；于是第一晶体管T1和第二晶体管T2断开，第三晶体管T3被导通，如图3d所示，导通着的第三晶体管T3给液晶像素电容Cls进行放电。
第二种，这种结构的二阶编程模块2包括双栅晶体管T4（和上个实施例相同），如图3e所示，所述双栅晶体管T4的漏级通过内部节点Vpx并联液晶像素电容Cls的上端和第二晶体管T2的源级，所述双栅晶体管T4的源级耦合第二同步信号Vst2，所述双栅晶体管T4其中一个栅极连接到第一同步信号Vst1，另一个栅极通过内部节点Q与一阶编程模块3耦合；
这种结构的二阶编程模块2采用双栅逻辑，减少一个电容Cs的方法，具有节省电路面积，提高开口率的优化设计，作为本发明的优选设计；
并且，双栅晶体管的设置在减少一个电容后，就显著减少了一个遮光的面积；这对于液晶像素内部来说，是一个显著的变化。
采用双栅晶体管T4设计逻辑，其液晶像素内部的设计示意图如图4所示，为方便起见，本示例采用IGZO液晶屏为示例表述；
其中，图4中各参数的含义为：
ESL 为SiOx介质保护层；TG为 顶栅、晶体管顶部栅极信号线；BG 为底栅、晶体管底部栅极信号线；IGZO为液晶屏的IGZO层；GLASS为液晶屏玻璃基板层；S为晶体管源极；D为晶体管漏极；
IGZO TFT像素设计中常见的结构是背沟道保护型（ESL型）为例说明，该结构下，IGZO有源层受到底栅绝缘层控制，形成第一栅极控制，即底栅控。且由于IGZO有源层受到背面的SiOx介质层（即ESL层）的保护，可设计顶栅控结构，与IGZO有源层形成第二栅控结构构，即顶栅控。其中，对于ESL型器件而言，顶栅控结构可以由源漏金属层、ESL层、IGZO层构成。
顶栅控的电压高低不同时，能形成双阈值电压模式，可形成两阶编程充电逻辑下的液晶LCD显示像素电路。
进一步的，顶栅控结构也可以由顶层ITO金属层、ESL层、IGZO层来构成；
在一阶编程充电和二阶编程充电过程中，从前一个时序完成的一阶编程态到本时序的二阶编程态的转化，取决于双栅晶体管T4中的顶栅控电压变化，即连接着的第一同步信号Vst1的电压高低转换。
在一阶编程充电状态时，第一同步信号Vst1为低电压电平状态，于是双栅晶体管T4的阈值电压较大，第三晶体管T3不导通，维持着前一帧的显示数据。
而进入到二阶编程充电状态时，第一同步信号Vst1为高，从而双栅晶体管T4的阈值电压较小，第三晶体管T3进入导通状态，进行二阶编程模式，液晶像素电容Cls的上端电压Vpx更新到最终所需要的电压状态。
进一步的， 由于双栅晶体管T4的器件导通性能，受到顶栅控的作用，可以在多种工作模式之间进行切换，当顶栅控电压较低时，其工作于高阈值电压模式；而当顶栅控电压较高时，其工作于低阈值电压模式，如图5所示；
其中，图5中各参数的含义为：
V TG为顶栅的电压；V GH为外部设定的高电压；V GL为外部设定的低电压；High V TH为高电压下的阈值电压；Low V TH为低电压下的阈值电压；Log I DS为漏极和源极电流的对数值；V BG为底栅---源极的电压；
另外，当所述其中一个栅极为顶栅控/底栅控时，所述另一个栅极为底栅控/顶栅控。
在具体的工作逻辑下，双栅晶体管T4导通阶段，从Vpx端到Vst2端，是一个线性电阻的等效电路。所以，整个的电路的导通能力和导通时间，由双栅晶体管T4存储的电荷电量，以及Vst1和Vst2共同决定。从而能将像素电容Cls的电荷放电到合适的电压，实现最终显示的目标。
在具体实施例中：
所述一阶编程模块3包括第一晶体管T1，所述第一晶体管T1的栅极连接用于驱动整个液晶屏的栅极驱动器gate driver，所述第一晶体管T1的源级连接用于驱动整个液晶屏的源极驱动器source driver，所述第一晶体管T1的漏级通过内部节点Q与存储电容Cs和第三晶体管T3耦合；
这样，设置第一同步信号Vst1为低电平电压，第二同步信号Vst2为高电平电压， Vpre为低电平电压，于是第二晶体管T2和第三晶体管T3均处于断开状态，如图6所示；
进一步的，源极数据信号Vdata为高电平电压状态，栅极数据信号Vg[n]处于高电平电压状态，此时进入一阶编程状态；即按照液晶的基本原理，若干行第一晶体管T1依次被栅极电路Vg[n]扫描打开，存储电容Cs处于接收外部电荷状态，液晶的源极数据电路进行充电工作即编程工作，这时存储电容Cs将从Vdata获得合适的电量电荷状态，用于下一个周期的显示。
另外，需要说明的是，本实施例中的第一同步信号Vst1、第二同步信号Vst2、Vpre以及VH均是作用于整个液晶屏的全部像素，对整个液晶屏的任何一个像素单元而言，这些全局数据信号的大小性质都是一样的。
在具体实施例中：
该像素电路进一步包括至少两条用于控制全部像素的全局公共电极线，所述全局公共电极线的布局方式为：沿横向栅极方向布置、沿纵向源极方向布置或者交叉布置；
该像素电路在进行如上所述的全局公共电极线的布置时，相邻的两行或者两列液晶像素之间的全局公共电极线，可以共用从而可以减少一条线的布置，以增大液晶屏的开口率；
具体地，当全局公共电极线为两条时，其为Vst1 和Vst2，因为是全局电路，所以，相邻的两行扫描线或者相邻的两列数据线，都可以共用这个线路，从而可以减少在空间上的占用，进而提高开口率。
即在具体的电路设计以及液晶像素的设计过程中，为了减少空间占用，也为了降低整个电路设计的电阻电容负载，提高传输能力，采取相邻两行共用电极线的逻辑；
这样，应用该电路的每一个液晶像素都连接了多个公用的全局电极线，该电极线在液晶屏中按行或者按列平行排列或者交叉排列，且相邻的上下两行或者左右两列液晶像素，都可以共用一条相同的共用电极线，从而可以按每两行或者每两列可以节省一根公用电极线的方式，减少一组电极线，从而可以减少布线所占用的面机，以增加液晶屏的开口率。
更具体地，包含了双栅晶体管T4的液晶像素单元的结构剖面图如图7a所示，其中，Glass为液晶屏玻璃基板层；S为晶体管源极；D为晶体管漏极；TG为顶栅、晶体管顶部栅极信号线；SHIELDING METAL作为保护层，被定义用作为底栅；LTPS为则代表了在LTPS工艺下的半导体层；
LTPS有源层受到底栅绝缘层控制，形成第一栅极控制，即底栅控。且由于LTPS有源层受到背面的SiOx介质层的保护，可设计顶栅控结构，与LTPS有源层形成第二栅控结构构，即顶栅控。顶栅控的电压高低不同时，能形成双阈值电压模式，可形成两阶编程充电逻辑下的液晶LCD显示像素电路。
更具体地，双栅晶体管T4的符号示意图如图7b所示，其中，S为晶体管源极；D为晶体管漏极；TG和Shielding Metal分别代表了两个栅极。
本实施例的有益效果如下：
首先，液晶屏的所有液晶像素，可以同步的进行正常显示；
其次，通过双栅晶体管的设计，显著的改变了液晶像素的内部设计，节省了电容占用的不透光的面积，改善了开口率，有利于提高亮度；
并且，本实施例通过在正常显示阶段，进行栅极电路和源极电路的配合，把显示所用的数据编程进去，可以采用传统方式下，液晶屏栅极扫描的驱动模式，因为从第一行到最后一行扫描驱动模式时间比较长，对驱动能力要求比较低的优点；
另外，通过每一帧画面里，设置一定时间的黑场，与背光点亮的光场的交替，改善了拖影现象，提升了画面质量；
通过特定的缓冲设计逻辑，对于不同制作工艺的液晶屏，由于TFT工艺不同，其泄露电流能力不同，缓冲设计逻辑比较好的减少了泄露电流导致电容电压下降过多，部分编程数据不准确，显示不准确的情况；
并且，更优选的实施例仅需两个晶体管和一个电容即可实现上述功能，其体积可控，工艺可控，成本可控，且因为体积小使得开口率和透光率高，具有很好的应用价值。
实施例2
本发明实施例2提供一种液晶像素的控制方法，其应用实施例1所述的液晶像素的控制电路，如图8所示，具体按照如下步骤实施：
S1，预置充电环节：通过高电平向液晶像素电容充电，将液晶像素预置到高电平状态；具体为：
通过全局公用电极线输入高电平将组成液晶屏的所有液晶像素电容Cls一次性地、同步地预置到高电平状态；
S2，二阶编程环节：通过二阶编程模块进行编程，实现对预置充电模块进行放电，使其电荷达到液晶像素显示图像所需的维持电压；具体为：
通过第一同步信号Vst1和第二同步信号Vst2的配合，使双栅晶体管T4导通，对液晶像素电容Cls进行放电；
需要说明的是：因为第一同步信号Vst1和第二同步信号Vst2是整个液晶屏共用的全局电压，所以组成液晶屏的所有像素的二阶编程环节是同步一次性完成的；
并且，对液晶像素电容Cls进行放电时，其放电时间取决于第一同步信号Vst1和第二同步信号Vst2高低电平相互配合的时间；放电能力取决于S3中保存的电荷；
S3，一阶编程环节：维持液晶像素的电荷电压，并同时通过一阶编程模块接收并保存来自外部控制单元输送的电荷，用于下一帧图像的显示；具体为：
整个液晶屏从第一行至最后一行，依次进行充电操作，液晶屏的栅极驱动器gate driver和源极驱动器source driver相互配合，从第一行到最后一行，对每个液晶像素进行一阶编程充电；
其中，充电数据与所显示图像相关，由源极驱动器source driver控制。
液晶像素一行一行依次打开，由栅极驱动器gate driver控制。
更具体地：
在所述S1中：
当所述二阶编程模块2仅包括双栅晶体管T4时，通过第一同步信号Vst1和第二同步信号Vst2的配合，将液晶像素电容预置到外部高电平VH；
当所述二阶编程模块2包括存储电容Cs和第三晶体管T3时，通过外部电平Vpre和液晶像素VH的配合，将液晶像素电容预置到外部高电平VH。
更具体地：
在所述S2中：
当所述二阶编程模块2仅包括双栅晶体管T4时，通过第一同步信号Vst1和第二同步信号Vst2的配合，使双栅晶体管T4导通，对液晶像素电容Cls进行放电；所述对液晶像素电容Cls进行放电时，其放电时间取决于第一同步信号Vst1和第二同步信号Vst2高低电平相互配合的时间；
当所述二阶编程模块2包括存储电容Cs和第三晶体管T3时，通过第一同步信号Vst1和第二同步信号Vst2的配合，使第三晶体管T3导通，对液晶像素电容Cls进行放电，所述第三晶体管T3的导通的能力和导通的持续时间，由所述S3中保存在存储电容Cs中的电荷、第一同步信号Vst1和第二同步信号Vst2共同决定，将液晶像素电容Cls的电量从高电平状态释放到所需的电量，进而将液晶像素电容Cls的电压编程为液晶像素显示图像所需的维持电压。
所述S2中的二阶编程环节有两种形式，分别为电压自举式的数字化编程和模拟化编程；
在模拟化编程方法中，当所述第一同步信号Vst1和第二同步信号Vst2为方波时，所述的液晶像素Cls的工作电压Vpx的范围为0≤V px≤VH，其中，VH为液晶像素电容被预置到最高电平时的电压。
在数字化编程方法中，当所述第一同步信号Vst1和第二同步信号Vst2为斜波电压信号时，所述的工作电压为高电平，但其维持高电平的时间则受编程参数决定，取决于所述S3中的电荷以及斜波的参数。
另外，所述S3的一阶编程环节具体为：
当二阶编程模块包括存储电容Cs时，具体为：
S31，缓冲阶段：所述缓冲阶段通过延迟液晶屏的第一行开始进行一阶编程工作充电的时间，进而调整二阶编程模块中存储电容Cs的保持时间，以及决定一阶编程从第一行到最后一行的结束时间；
S32，一阶编程阶段：整个液晶屏从第一行至最后一行，依次进行充电操作，液晶屏的栅极驱动器gate driver和源极驱动器source driver相互配合，从第一行到最后一行，对每个液晶像素进行一阶编程充电；
其中，充电数据与所显示图像相关，由源极驱动器source driver控制；
当二阶编程模块不包括存储电容Cs时，具体为：
缓冲阶段：所述缓冲阶段通过延迟液晶屏的第一行开始进行一阶编程工作充电的时间，进而调整二阶编程模块中双栅晶体管T4的顶栅和底栅存储电量的保持时间通过延迟液晶屏的第一行开始进行一阶编程工作充电的时间，进而调整二阶编程模块中存储电容Cs的保持时间，以及决定一阶编程从第一行到最后一行的结束时间；
一阶编程阶段：液晶屏从第一行至最后一行，依次进行充电操作，液晶屏的栅极驱动器gate driver和源极驱动器source driver配合，从第一行到最后一行，对每个液晶像素进行一阶编程充电；其中，充电数据与所显示图像相关，由源极驱动器控制。
更具体地：
在所述S31中：缓冲阶段的时间取决于液晶屏的制作工艺，且其最大时间不大于一帧画面所用的时间。
所述S3中，显示控制系统通过栅极驱动器GATE DRIVER，即设置Vg[n]为高电平，即可以驱动每一行的栅极数据线控制第一晶体管T1打开；源极驱动器SOURCE DRIVER将显示图像所用的电压信号Vdata通过第一晶体管T1输送到存储电容Cs。
所述S3中的通过一阶编程模块接收并保存来自外部控制单元输送的电荷，用于下一帧图像的显示，因为液晶屏有很多行液晶像素单元，从第一行开始编程，直到结束，时间比较长。本实施例中，一阶编程过程，可以延续到下一帧画面的预置充电环节即S1过程中。
更具体地：
在所述S31的缓冲阶段，背光源已经打开，此阶段的液晶像素电容Cls上保持着上一个阶段放电阶段时，放电后得到的维持电压，背光源驱动后，液晶显示能显示出正确的图像；
缓冲阶段用于驱动过程中的缓冲期和准备期，考虑到液晶栅极电路启动时的实际情况，需要设置一定时间的准备期，该准备期从10微秒到1毫秒不等，根据液晶性能和液晶屏的栅极驱动器GATE DRIVER的性能调整并固定，不同应用皆有不同。
更具体地：
在所述S3中，设置第一同步信号Vst1为低电平电压，第二同步信号Vst2为高电平电压， Vpre为低电平电压；
根据上述设置，于是第二晶体管T2和第三晶体管T3均处于断开状态。
进一步的，源极数据信号Vdata为高电平电压状态，栅极数据信号Vg[n]处于高电平电压状态，此时进入一阶编程状态；即按照液晶的基本原理，若干行液晶依次被栅极电路Vg[n]扫描打开存储电容Cs，液晶的源极数据电路进行充电工作即编程工作，这时存储电容Cs将获得合适的电量电荷状态，用于下一个周期的显示。
在所述S1和S2中，所述液晶屏的背光源关闭；在所述S3以及缓冲阶段中，所述液晶屏的背光源打开。
在其中一个实施例中：
所述S1和S2中液晶屏的背光源关闭，这段时间称之为黑场；所述S3以及缓冲阶段液晶屏的背光源打开，这段时间称之为光场；
所述背光源关闭和背光源打开交替进行，形成流水线型的场序驱动时序，为了进行说明，本实施例采用无CF膜滤色层的情况下，红绿蓝RGB三子场显示的场序法驱动模式为示例：
如图9所示，为流水线型的场序发光、编程模式，其中，Disp表示背光打开显示图像；Prog为液晶屏全部像素顺序扫描执行依次一阶编程动作；1 Frame Time是包含了红绿蓝三个子场的一帧画面的显示时间；K为黑场即背光源关闭状态。
对于场序显示的逻辑，这三个子场是R红色子场，G绿色子场和B蓝色子场，背光源的颜色和该子场的数据吻合，也是R红色、G绿色和B蓝色；
进一步的，R红色子场显示的过程中，一阶编程充电数据完成。该编程数据用于下一个子场显示所用，本示意图中是绿场即B子场，以此类推。
进一步优选的流水线型场序显示液晶驱动的背光时序可以优化为如图10所示的逻辑：在该优选模式下，一阶编程过程，持续到了下一子场的S1阶段即预置充电阶段，但是没有延申到S2阶段即二阶编程阶段；具体原因为：如果由于液晶的源极数据驱动器SOURCE driver的驱动能力或者栅极数据驱动器GATE DRIVER的能力不足，或者由于液晶扫描行数多，导致从第一行扫描开始，执行一阶编程充电行为，到最后一行完成，所花费的时间更长，那么可以采用如图10所示的优选的流水线型背光驱动和编程模式。在这个逻辑下，一阶编程可以持续到K场即黑场期间。
并且，也可以主动通过调整缓冲阶段的时间，将下一个子帧的一阶编程充电的环节向后移动，一阶编程充电时间持续到K场即黑场画面的环节；这样能够减少一阶编程充电时间和实际发光子帧之间间隔的时间太长，而导致电荷泄漏造成的部分显示不均匀问题。
更具体地：
在所述S1中，外部电平Vpre设置为高电平电压，第一同步信号Vst1设置为低电平电压，第二同步信号Vst2为高电平电压，第一晶体管T1的栅极数据信号Vg[n]为低电平电压；
根据上述设置，如图3c所示，于是第二晶体管T2被导通，第一晶体管T1和第三晶体管T3均为断开状态，全部的像素阵列中的液晶像素电容Cls，均被同步地上拉到高电平电压VH，实现对对预置充电模块进行充电；
并且在该步骤中，液晶像素的VH和Vpre在液晶屏外部，各自由同一组电路控制，对全部液晶像素而言，其预置充电电压VH是同步被拉高的，其液晶像素电容Cls也是同步被充电的。
更具体地：在所述S2中，设置第一同步信号Vst1为高电平电压，第二同步信号Vst2为低电平电压，Vpre为低电平电压，栅极数据信号Vg[n]为低电平电压；
根据上述设置，于是第一晶体管T1和第二晶体管T2断开，第三晶体管T3被导通，导通着的第三晶体管T3给液晶像素电容Cls进行放电。
该步骤的主要作用是：将S1阶段预置充电的液晶像素电容Cls里的电荷释放一部分出来以达到最终显示正确图像的电压。通过将第三晶体管T3导通，让存储电容Cs电容数据，以及Vst1和Vst2的高低电平状态，影响T3的导通能力以及导通时间，从而实现对液晶像素电容Cls进行适当的电荷释放，实现二阶编程，从而将液晶像素电容Cls的电压调整为最终显示所需要的电压电荷状态，当背光驱动点亮进入光场时序环节时，能显示出正确的图像。
其中，将液晶像素电容Cls被放电到何种电压取决于第三晶体管T3的导通能力，所述第三晶体管T3的导通能力取决于上一周期与第三晶体管T3的栅极耦合着的存储电容Cs上存储的电荷量，具体为：
第三晶体管T3的栅极耦合着的存储电容Cs上存储着的电荷量越多，则第三晶体管T3的导通能力越强，液晶像素电容Cls被下拉到越低的电压；反之，则液晶像素电容Cls上的电压量较高。
所述S2中，将液晶像素电容Cls的电压编程为液晶屏显示图像所需的维持电压，其中，将液晶像素电容Cls被放电到何种电压还取决于所述S2的时长，具体为：
当所述S2持续时间越长，则液晶像素电容Cls被下拉到越低的电压；反之，则液晶像素电容Cls上的电压量较高。
更具体地：在所述S3的一阶编程环节中，整个液晶屏从第一行至最后一行，依次进行充电操作，液晶屏的栅极驱动器gate driver和源极驱动器source driver相互配合，从第一行到最后一行，对每个液晶像素进行一阶编程充电；其中，充电数据与所显示图像相关，由源极驱动器source driver控制。
该方法进一步包括：所述液晶屏的背光源依次打开和关闭、以及所述一阶编程阶段依次进行的一阶编程过程，形成了流水线型的驱动时序逻辑。
本实施例有至少两种形式的二阶编程环节，数字式和模拟式的两种编程方式，以下具体实例分别进行说明。
电压自举式的数字化编程工作时序：
在S1预置充电环节中，第一同步信号Vst1和第二同步信号Vst2均为高电平电压，双栅晶体管T4的阈值电压经过调制后减少，进入导通区，于是所有的像素均同步地被置位为高电平，这是为后续的脉冲宽度调制过程做准备；
在一阶编程环节中的S31中，编程信号Vdata通过晶体管T1输入到双栅晶体管T4的栅极节点上。对于不同行、同一列的像素电路而言，例如对应的Vscan[1]和Vscan[2]控制着的这两行上同一列的像素电路，其双栅晶体管的栅极被先后编程到Vd1和Vd2电压，具有不同的电荷水平；
在二阶编程环节中，当第二同步信号Vst2为斜坡上升时，上升的值达到预先编程的信号Vdatax时，液晶像素电容Cls上的电荷被完全释放掉，即Vpx降低到0。
具体的计算方法如下所述：
双栅晶体管T4的阈值电压Vth=Vth0+ k1*Vdata+k2*Vramp；
其中，Vth0是双栅晶体管T4的初始阈值电压，Vdata是一阶编程的源极数据电压，Vramp是斜坡信号线的电压，也即是Vst2，k1和k2为系数；
优选地，k1=-1，k2=-1；
若Vramp=β*t，则Vth=Vth0-Vdata-β*t；即双栅晶体管T4的Vth值处于动态变化之中。
对于晶体管来说，当其Vgs>Vth时，即满足了开启放电条件；
即：Vdata>Vth0-Vdata-β*t；
即换算得到：t=(Vth0-2*Vdata)/β；
为了更好的进行说明，举例如下：
Vth0=1V，Vdata=-2V，β=1V/ms，则对应着t=5ms,在具体的显示中，则可以在背光源点亮的时候，液晶像素处于高电平全打开状态，此时持续的时间t=5ms,则可以实现显示时间为5ms。
如果Vdata=-3V，则对应着的显示时间变为7ms。
总之，通过一阶编程阶段，对一阶编程数据Vdata进行编程不同的数据，则可以得到不同的高电平打开时间，实现了数字化编程结果。
其中，所述的Vgs是晶体管的源极和漏极之间的电压值。
每个像素的一阶编程数据持续保留在主栅上，直到下一次一阶编程开始才发生变化。
在数字式的编程方法中，一阶编程阶段与光场阶段不发生重叠，所以整体的光场时间相对较短。
模拟化编程方法的时序图如图11和图12所示：
图11是采用图3a的像素设计电路，采用本方法实现的驱动时序，图12是采用图1的像素设计电路，采用本方法实现的驱动时序；
以下实施例详细讲述本电路设计下对应的模拟化编程方法。
具体的，图12为模拟式驱动的像素电路图以及操作时序图，这里以红色R子帧后，绿色G子帧为例，说明绿色G子帧的一阶编程和二阶编程，以及光场L阶段和黑场K阶段。
在显示红色R子帧时，一方面是红色R子帧的正常显示，另一方面则同步展开了绿色G子帧的一阶编程；值得指出的是，虽然G子帧的数据信号通过晶体管T1已经进入到双栅晶体管T4的顶栅，即主栅极，但是由于双栅晶体管T4的底栅即辅助栅极Vst2的电压为低，则双栅晶体管T4仍然处于较高的阈值电压Vth状态，从而绿色G子帧的一阶编程并不会影响到红色R子帧的正常显示，像素电路的液晶像素电容Cls保持着红色R子帧显示所需要的电压。
如图12所示，黑场包括了图8的预置充电环节S1和二阶编程环节S2共两个环节,即本图12中的S1阶段和S2阶段共两个阶段；在S1，即预置充电阶段，首先是第二同步信号Vst2即本图中的Vctrl变成为高电平，而且第一同步信号Vst1即本图中的Vst也为高电平，则液晶像素电容Cls的工作电压Vpx同步地变为高电平VH；
然后，进入S2，即二阶编程阶段，双栅晶体管T4的顶栅和底栅也即主栅极和辅助栅极连接的Vst和Vctrl发生变化，使双栅晶体管T4处于较低阈值电压Vth工作状态，即导通状态开始放电，液晶像素电容Cls的放电量取决于上一子帧中一阶编程通过Vdata输入到双栅晶体管T4的主栅极的电荷；当Vdata转移到双栅晶体管T4主栅极的电压越高输入电荷越多，则导通能力强，放电能力越强；液晶像素电容的工作电压Vpx能被放电下拉到越低的电压；反之，则工作电压Vpx上被放电到一个较高的电压；双栅晶体管T4的顶栅和底栅也即主栅极和辅助栅极连接的Vst和Vctrl发生变化，其相互持续的时间，决定了P2阶段二阶编程持续的时间，也会影响液晶像素电容的工作电压Vpx;持续时间长，则放电时间长，工作电压Vpx则会被拉低到更低的电压水平；反之则会电压水平相对较高；
最后，进入光场即S3阶段，即图8所述的S3环节，不同的背光颜色代表了光场不同的颜色；在S3阶段，即背光源点亮的发光显示状态，由于Vctrl也已经成为低电平，双栅晶体管T4的阈值电压Vth则变高，处于关断状态，于是液晶像素电容Cls的电压Vpx保持二阶编程完成后的工作电压。
在上述过程中，工作原理与计算方法如下：
                     
Figure 968655dest_path_image001
其中，ΔT为放电时间即P2二阶编程的持续时间，V H为液晶像素被预置到高电平时的预置电压，Tf为液晶像素电容Cls放电特征时间，取决于液晶像素本身的特质；Clc是液晶像素电容Cls的电容值；
                        
Figure 314186dest_path_image002
其中，Req是驱动晶体管的等效阻抗；
Figure 464544dest_path_image003
上式中，L，W分别为双栅晶体管T4的沟道长度、沟道宽度，μ为电子迁移率，CI为TFT单位面积的栅介质层电容值，Vt为TFT的阈值电压Vth，Vdata为一阶编程阶段通过源极驱动器SOURCE DRIVER输入的数据电压值。
综合以上情况，Vpx的完整表达式为：
Figure 997157dest_path_image004
。
通过以上方式，对每一个液晶像素电容而言，根据图像的数据，即代表着不同的液晶像素工作电压Vpx,该电压针对同一个液晶屏，对于相同的图像数据而言，是不变的常数，可查表或者通过其他计算获得；二阶编程S2的时间可以根据实际情况进行定义，对于整个液晶屏和所有像素而言，一旦确定工作模式，ΔT为放电时间即S2二阶编程的持续时间也是常数；因此即可通过以上的方式计算出一阶编程阶段需要输入的一阶编程数据Vdata，从而实现图像显示，实现模拟化编程结果。
其中:每个像素的一阶编程数据持续保留在主栅上，直到下一次一阶编程开始才发生变化。
二阶编程阶段S2之后，进入S3阶段即光场L场，本示例中L场是绿场G Frame，背光灯点亮，经过S31缓冲阶段后进行一阶编程S32阶段,如图8所述的S31环节和S32环节。
如图所示，由于两个像素Vdata[1]和Vdata[2]不同的数据输入，则会产生不同的Vpx[1]和Vpx[2]。
另外，在本实施例中，当所述第一同步信号Vst1和第二同步信号Vst2为方波时，所述的维持电压V 维持的范围为0≤V 维持≤V 全亮，其中，V 全亮为液晶像素被预置到最高电平时的电压。
本实施例的有益效果如下：
（1）在本实施例中，数据编程与发光呈并行化流水线操作，例如在显示红色R子帧的环节，同步地也在进行着下一个子帧G所需要的数据编程动作。于是，数据写入动作并不会挤占掉有效显示时间，这就较显著地增加了有效时间，提升了场序显示的时间以及降低对编程器件的驱动能力要求；
当采用图3a的像素电路设计，并采用本实施例的方法时，本实施例仅需两个晶体管和一个电容即可实现上述功能，其体积可控，工艺可控，成本可控，且因为体积小使得开口率和透光率高，具有很好的应用价值；
当采用图1的像素电路设计，并采用本实施例的方法时，本实施例仅需两个晶体管即可实现上述功能，其体积可控，工艺可控，成本可控，且因为体积小使得开口率和透光率高，具有很好的应用价值；
当然，本实施例提供的技术方案不仅可用于采用场序法进行显示的液晶屏，其还可以用于传统的液晶屏，即背景技术中的普通液晶屏。
（2）在图3a所示的像素电路设计中，在采用存储电容Cs的情况下，存在的主要不足在于元件数量较多，液晶像素中花费较多的面积用于电容，实际用于显示的空间减少，故显示像素的开口率低、光线透过效率低;
优化方案的双栅晶体管具有更简单的像素结构。其省略了原电路最消耗面积的电容元件，单元像素只需要用到3颗TFT。因此，其像素的开口率更高，背光转化到实际显示的光转化的效率更高；
（3）原电路的编程工作过程，取决于电容的电荷分配关系，由于IGZO TFT本身具有一定的寄生电容，尤其对于ESL型器件来说，它的寄生电容相对较大，则实际编程的电压值，较强烈地受到寄生电容的影响，由于工艺批次之间，寄生电容等不可避免地存在一定的偏差，这就导致了原像素电路的实际编程电压值可能随工艺批次的不同而存在着偏差；
（4）本实施例通过特定的缓冲设计逻辑，对于不同制作工艺的液晶屏，由于TFT工艺不同，其泄露电流能力不同，缓冲设计逻辑比较好的减少了泄露电流导致电容电压下降过多，部分编程数据不准确，显示不准确的情况；
（5）本实施例还通过每帧画面都预置到高电平，消除了液晶电容在特定画面下会出现的残影现象；同时，在当前图像进行显示的同时，为下一帧图像显示所需的电量进行编程充电，因为这时候的编程充电是需要一行一行依次进行充电的，时间很长，通过这种当前画面显示和下一帧画面的电量数据的存储同时进行的方式，极大地降低了对外部栅极驱动器和源极驱动器的驱动能力的要求，也极大地延长了画面显示背光照明的时间，有效改善了液晶显示器栅极扫描驱动模式下，从第一行到最后一行的时间很长，压缩背光源照明时间导致的亮度不够，或者背光源时间过长会导致的色彩混乱和画面撕裂现象。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (31)

  1. 一种液晶像素的控制电路，其特征在于，其包括依次连接的预置充电模块（1）、二阶编程模块（2）和一阶编程模块（3）；
    所述预置充电模块（1），用于通过高电平向液晶像素电容充电，将液晶像素预置到高电平状态；
    所述二阶编程模块（2），根据一阶编程模块（3）的编程数据，实现对预置充电模块（1）进行放电，使其电荷达到液晶像素显示图像所需的维持电压；
    所述一阶编程模块（3），接收并保存来自外部控制单元输送的电荷，用于下一帧图像的显示。
  2. 据权利要求1所述的一种液晶像素的控制电路，其特征在于，所述预置充电模块（1）包括液晶像素电容Cls，所述液晶像素电容Cls的一端和液晶屏的基准电压连接，另一端和二阶编程模块（2）连接。
  3. 根据权利要求2所述的一种液晶像素的控制电路，其特征在于，所述二阶编程模块（2）包括双栅晶体管T4，所述液晶像素电容Cls的一端和液晶屏的基准电压连接，另一端与双栅晶体管T4的漏极连接。
  4. 根据权利要求3所述的一种液晶像素的控制电路，其特征在于，所述一阶编程模块（1）包括第一晶体管T1，所述双栅晶体管T4的源极耦合到第一同步信号Vst1，所述双栅晶体管T4的其中一个栅极耦合到第二同步信号Vst2，另一个栅极与第一晶体管T1耦合；所述第一晶体管T1的栅极耦合到外部栅极驱动器GATE DRIVER，第一晶体管T1的源极耦合到外部的源极驱动器SOURCE DRIVER。
  5. 根据权利要求4所述的一种液晶像素的控制电路，其特征在于，所述第一晶体管T1为双栅晶体管。
  6. 根据权利要求5所述的一种液晶像素的控制电路，其特征在于，当所述第一晶体管T1为双栅晶体管时，所述第一晶体管T1的两个栅极均连接到Vscan。
  7. 根据权利要求5所述的一种液晶像素的控制电路，其特征在于，当所述第一晶体管T1为双栅晶体管时，所述第一晶体管T1的一个栅极连接到Vscan，另一栅极连接到第一同步信号Vst1。
  8. 根据权利要求5所述的一种液晶像素的控制电路，其特征在于，当所述第一晶体管T1为双栅晶体管时，所述第一晶体管T1的一个栅极连接到Vscan，另一栅极与双栅晶体管T4的另一个栅极连接。
  9. 根据权利要求5所述的一种液晶像素的控制电路，其特征在于，当所述第一晶体管T1为双栅晶体管时，所述第一晶体管T1的一个栅极连接到Vscan，另一个栅极与双栅晶体管T4的其中一个栅极连接。
  10. 根据权利要求5所述的一种液晶像素的控制电路，其特征在于，当所述第一晶体管T1为双栅晶体管时，所述第一晶体管T1的一个栅极连接到Vscan，另一个栅极与液晶像素电容Cls连接。
  11. 根据权利要求1或2所述的一种液晶像素的控制电路，其特征在于，所述预置充电模块（1）进一步包括第二晶体管T2，所述第二晶体管T2的栅极耦合到外部电平Vpre，漏极耦合到外部电平VH，源极通过内部节点Vpx和液晶像素电容Cls连接。
  12. 根据权利要求11所述的一种液晶像素的控制电路，其特征在于，所述所述二阶编程模块（2）包括存储电容Cs和第三晶体管T3，所述第三晶体管T3的漏级耦合到液晶像素电容Cls的上端和第二晶体管T2的源级，所述第三晶体管T3的源级耦合到第二同步信号Vst2，所述第三晶体管T3的栅极通过内部节点耦合到存储电容Cs的一端连接，所述存储电容Cs的另一端连接到第一同步信号Vst1。
  13. 根据权利要求4所述的一种液晶像素的控制电路，其特征在于，当所述一阶编程模块（1）包括第一晶体管T1，所述二阶编程模块（2）包括存储电容Cs和第三晶体管T3时，所述第一晶体管T1的栅极连接用于驱动整个液晶屏的栅极驱动器gate driver，所述第一晶体管T1的源级连接用于驱动整个液晶屏的源极驱动器source driver，所述第一晶体管T1的漏级通过内部节点Q与存储电容Cs和第三晶体管T3耦合。
  14. 根据权利要求1-10、12-13任一项所述的一种液晶像素的控制电路，其特征在于，每个像素单元至少连接一条第一同步信号电极线和一条第二同步信号电极线，该两条电极线是用于控制全部像素的全局公共电极线，所述全局公共电极线的布局方式为：沿横向栅极方向布置、沿纵向源极方向布置或者交叉布置。
  15. 根据权利要求14所述的一种液晶像素的控制电路，其特征在于，该液晶像素控制电路的全局公共电极线，相邻的两行或者两列均可共用一条同性质的全局公共电极线，以减少开口面积的占用。
  16. 一种液晶像素的控制方法，其特征在于，其应用权利要求1-15任一项所述的液晶像素的控制电路，具体按照如下步骤实施：
    S1，预置充电环节：通过高电平向液晶像素电容充电，将液晶像素预置到高电平状态；
    S2，二阶编程环节：通过二阶编程模块进行编程，实现对预置充电模块进行放电，使其电荷达到液晶像素显示图像所需的维持电压；
    S3，一阶编程环节：维持液晶像素的电荷电压，并同时通过一阶编程模块接收并保存来自外部控制单元输送的电荷，用于下一帧图像的显示。
  17. 根据权利要求16所述的一种液晶像素的控制方法，其特征在于，在所述S1的预置充电环节中，通过高电平将组成液晶屏的所有液晶像素一次性地、同步地预置到高电平。
  18. 根据权利要求17所述的一种液晶像素的控制方法，其特征在于，通过高电平将组成液晶屏的所有液晶像素一次性地、同步地预置到高电平，具体为：
    当所述二阶编程模块（2）仅包括双栅晶体管T4时，通过第一同步信号Vst1和第二同步信号Vst2的配合，将液晶像素电容预置到外部高电平VH。
  19. 根据权利要求17所述的一种液晶像素的控制方法，其特征在于，通过高电平将组成液晶屏的所有液晶像素一次性地、同步地预置到高电平，具体为：
    当所述二阶编程模块（2）包括存储电容Cs和第三晶体管T3时，通过外部电平Vpre和液晶像素VH的配合，将液晶像素电容预置到外部高电平VH。
  20. 根据权利要求18所述的一种液晶像素的控制方法，其特征在于，所述S2中通过二阶编程模块进行编程，实现对预置充电模块进行放电，使其电荷达到液晶像素显示图像所需的维持电压，具体为：
    当所述二阶编程模块（2）仅包括双栅晶体管T4时，通过第一同步信号Vst1和第二同步信号Vst2的配合，使双栅晶体管T4导通，对液晶像素电容Cls进行放电；所述对液晶像素电容Cls进行放电时，其放电时间取决于第一同步信号Vst1和第二同步信号Vst2高低电平相互配合的时间，其放电速度取决于双栅晶体管T4存储的电量，其放电能力取决于S3中保存的电荷。
  21. 根据权利要求19所述的一种液晶像素的控制方法，其特征在于，所述S2中通过二阶编程模块进行编程，实现对预置充电模块进行放电，使其电荷达到液晶像素显示图像所需的维持电压，具体为：
    当所述二阶编程模块（2）包括存储电容Cs和第三晶体管T3时，通过第一同步信号Vst1和第二同步信号Vst2的配合，使第三晶体管T3导通，对液晶像素电容Cls进行放电，所述第三晶体管T3的导通的能力和导通的持续时间，由所述S3中保存在存储电容Cs中的电荷、第一同步信号Vst1和第二同步信号Vst2共同决定，将液晶像素电容Cls的电量从高电平状态释放到所需的电量，进而将液晶像素电容Cls的电压编程为液晶像素显示图像所需的维持电压。
  22. 根据权利要求17-21任一项所述的一种液晶像素的控制方法，其特征在于，在所述S2的二阶编程环节中，组成液晶屏的所有像素的二阶编程是同步一次性完成的。
  23. 根据权利要求22所述的一种液晶像素的控制方法，其特征在于，在所述S2的二阶编程环节之后，背光灯点亮，同步开始进行一阶编程。
  24. 根据权利要求23所述的一种液晶像素的控制方法，其特征在于，在所述S2的二阶编程环节之后，背光灯点亮，缓冲之后进行一阶编程，其中，所述的一阶编程，可延申至下一帧画面的预置充电环节，但不可延伸至二阶编程环节。
  25. 根据权利要求17所述的一种液晶像素的控制方法，其特征在于，所述S3中维持液晶像素的电荷电压，并同时通过一阶编程模块接收并保存来自外部控制单元输送的电荷，用于下一帧图像的显示，当二阶编程模块包括存储电容Cs时，具体为：
    S31，缓冲阶段：所述缓冲阶段通过延迟液晶屏的第一行开始进行一阶编程工作充电的时间，进而调整二阶编程模块中存储电容Cs的保持时间，以及决定一阶编程从第一行到最后一行的结束时间；
    S32，一阶编程阶段：液晶屏从第一行至最后一行，依次进行充电操作，液晶屏的栅极驱动器gate driver和源极驱动器source driver配合，从第一行到最后一行，对每个液晶像素进行一阶编程充电；其中，充电数据与所显示图像相关，由源极驱动器控制；
    当二阶编程模块不包括存储电容Cs时，具体为：
    缓冲阶段：所述缓冲阶段通过延迟液晶屏的第一行开始进行一阶编程工作充电的时间，进而调整二阶编程模块中双栅晶体管T4的顶栅和底栅存储电量的保持时间通过延迟液晶屏的第一行开始进行一阶编程工作充电的时间，进而调整二阶编程模块中存储电容Cs的保持时间，以及决定一阶编程从第一行到最后一行的结束时间；
    一阶编程阶段：液晶屏从第一行至最后一行，依次进行充电操作，液晶屏的栅极驱动器gate driver和源极驱动器source driver配合，从第一行到最后一行，对每个液晶像素进行一阶编程充电；其中，充电数据与所显示图像相关，由源极驱动器控制。
  26. 根据权利要求25所述的一种液晶像素的控制方法，其特征在于，所述S31中缓冲阶段的时间取决于液晶屏的制作工艺，且其最大时间不大于一帧画面所用的时间。
  27. 根据权利要求26所述的一种液晶像素的控制方法，其特征在于，全部液晶像素的一阶编程时间，可在本帧画面中完成，也可延申到下一帧的S1阶段，但不能延伸至S2阶段。
  28. 根据权利要求27所述的一种液晶像素的控制方法，其特征在于，该方法进一步包括：所述液晶屏的背光源依次打开和关闭、以及所述一阶编程阶段依次进行的一阶编程过程，形成了流水线型的驱动逻辑。
  29. 根据权利要求23所述的一种液晶像素的控制方法，其特征在于，当所述第一同步信号Vst1和第二同步信号Vst2为方波时，所述的液晶像素Cls的工作电压Vpx的范围为0≤Vpx≤VH，其中，VH为液晶像素电容被预置到最高电平时的电压。
  30. 根据权利要求23或19所述的一种液晶像素的控制方法，其特征在于，当所述第一同步信号Vst1和第二同步信号Vst2为斜波电压信号时，液晶像素电容的高电平状态维持一定时间后导通，将液晶像素电容放电到零电平。
  31. 根据权利要求30所述的一种液晶像素的控制方法，其特征在于，当所述工作电压为高电平时，所述高电平维持的时间取决于所述S3中的电荷以及斜波的参数。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115665926A (zh) * 2022-11-14 2023-01-31 灿芯半导体(成都)有限公司 一种二阶充放电电路的led驱动芯片

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1346450A (zh) * 1999-12-03 2002-04-24 三菱电机株式会社 液晶显示装置
JP2007272243A (ja) * 2007-04-10 2007-10-18 National Chiao Tung Univ 画素駆動回路とその駆動方法、及びそれを用いた液晶表示装置
US20080170022A1 (en) * 2007-01-11 2008-07-17 Industrial Technology Research Institute Pixel driving circuit
CN105425488A (zh) * 2015-12-28 2016-03-23 友达光电股份有限公司 一种用于蓝相液晶显示装置的像素驱动电路
CN106652935A (zh) * 2016-10-18 2017-05-10 友达光电股份有限公司 显示控制电路及其操作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1346450A (zh) * 1999-12-03 2002-04-24 三菱电机株式会社 液晶显示装置
US20080170022A1 (en) * 2007-01-11 2008-07-17 Industrial Technology Research Institute Pixel driving circuit
JP2007272243A (ja) * 2007-04-10 2007-10-18 National Chiao Tung Univ 画素駆動回路とその駆動方法、及びそれを用いた液晶表示装置
CN105425488A (zh) * 2015-12-28 2016-03-23 友达光电股份有限公司 一种用于蓝相液晶显示装置的像素驱动电路
CN106652935A (zh) * 2016-10-18 2017-05-10 友达光电股份有限公司 显示控制电路及其操作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115665926A (zh) * 2022-11-14 2023-01-31 灿芯半导体(成都)有限公司 一种二阶充放电电路的led驱动芯片

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