WO2022155952A1

WO2022155952A1 - Address mapping method and apparatus

Info

Publication number: WO2022155952A1
Application number: PCT/CN2021/073571
Authority: WO
Inventors: 沈桂旭; 刘延昭; 董岚
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2021-01-25
Filing date: 2021-01-25
Publication date: 2022-07-28

Abstract

Provided are an address mapping method and apparatus. The method comprises: when the physical address of a memory needs to be accessed, determining a mapping relationship corresponding to the physical address, a chip implementing address mapping in at least two mapping modes, and the attribute of the mapping relationship being one of the at least two mapping modes (31); and determining a virtual address mapped to the physical address according to the physical address and the mapping relationship (32). According to the method, address mapping performed by a chip has the advantage of having different mapping modes, so that the application requirements can be satisfied.

Description

Address mapping method and device

technical field

The present application relates to the technical field of chip design, and in particular, to an address mapping method and apparatus.

Background technique

Restricted by the address bus of the chip, address mapping is required when the chip accesses the memory space beyond its address bus bit width.

At present, the chip can perform address mapping in a static mapping manner or a dynamic mapping manner. Among them, the static mapping method means that the mapping is established by hard coding when the chip is booted (Boot), and continues until the chip is turned off, which can better avoid memory trampling and protect the security of data and programs. However, the memory utilization rate is low and flexible. Bad sex. The dynamic mapping method means that the mapping is established on demand during the process of the program running, and continues until the demand is reached. Its memory utilization and flexibility are higher than the static mapping method, but the security is poor, and the frequent establishment and destruction of the mapping has a negative impact on performance. will have an impact.

Therefore, there is a problem that the address mapping method in the prior art cannot meet application requirements.

SUMMARY OF THE INVENTION

Embodiments of the present application provide an address mapping method and apparatus, which are used to solve the problem that the address mapping method in the prior art cannot meet application requirements.

In a first aspect, an embodiment of the present application provides an address mapping method, which is applied to a chip, where the chip can access memory by means of address mapping, and the method includes:

When the physical address of the memory needs to be accessed, a mapping relationship corresponding to the physical address is determined, the chip uses at least two mapping methods for address mapping, and the attributes of the mapping relationship are the at least two mapping methods one of the

According to the physical address and the mapping relationship, the virtual address mapped to the physical address is determined.

In a second aspect, an embodiment of the present application provides an address mapping apparatus, which is applied to a chip, where the chip can access a memory by means of address mapping, and the apparatus includes: a memory and a processor;

the memory for storing program codes;

The processor calls the program code, and when the program code is executed, is configured to perform the following operations:

In a third aspect, embodiments of the present application provide a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and the computer program includes at least one piece of code, and the at least one piece of code can be executed by a computer to control all The computer executes the method described in any one of the above first aspects

In a fourth aspect, an embodiment of the present application provides a computer program, which, when the computer program is executed by a computer, is used to implement the method described in any one of the foregoing first aspects.

The embodiments of the present application provide an address mapping method and device. When a physical address of a memory needs to be accessed by a chip, a mapping relationship corresponding to the physical address is determined, and a virtual address mapped to the physical address is determined according to the physical address and the mapping relationship, wherein , the chip uses at least two mapping methods for address mapping, and the attribute of the mapping relationship corresponding to the physical address is one of the at least two mapping methods. Due to the different timings of establishing and destroying the mapping relationship in different mapping methods, different establishment The security, memory utilization, memory flexibility and performance brought by the timing of destroying the mapping relationship have their own advantages. Therefore, the chip adopts at least two mapping methods for address mapping, so that the address mapping performed by the chip can be It has the advantages of different mapping methods to meet application needs.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

1 is a schematic diagram of an application scenario of an address mapping method provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of a mapping relationship provided by an embodiment of the present application;

3 is a schematic flowchart of an address mapping method provided by an embodiment of the present application;

4 is a schematic diagram of a comparison of timings for establishing and destroying a mapping relationship under different mapping modes provided by an embodiment of the present application;

5 is a schematic diagram of a mapping relationship provided by another embodiment of the present application;

6 is a schematic flowchart of an address mapping method provided by another embodiment of the present application;

7 is a schematic flowchart of an address mapping method provided by another embodiment of the present application;

FIG. 8 is a schematic diagram of a division mapping table provided by an embodiment of the present application;

FIG. 9 is a schematic structural diagram of an address mapping apparatus provided by an embodiment of the present application.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

The address mapping method provided in this embodiment of the present application may be applied to the application scenario shown in FIG. 1 . As shown in FIG. 1 , the application scenario may include a chip 11 and a memory 12 , wherein the chip 11 can access the memory 12 by means of address mapping. The chip 11 may be, for example, a digital signal processing (Digital Signal Processing, DSP) chip, a central processing unit (Central Processing Unit, CPU) chip, or a chip capable of running a program and accessing the memory by means of address mapping. The memory 12 may be, for example, a double-rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM) or the like. The methods provided in the embodiments of the present application may be executed by the chip 11 .

Taking the address bus of chip 11 as an example of 32 bits wide, 32 bits can address 4GB of memory space. Suppose the memory size that chip 11 needs to access is 17GB. Since 4GB is less than 17GB, chip 11 needs to use address mapping to access it. Memory.

Referring to Figure 2, the memory address space from the perspective of chip 11 is 0x00000000 to oxFFFFFFFF, and the corresponding memory size is 4GB. 4GB can be divided into 16 memory blocks, which are 0~256MB-1B, 256MB-1B~512MB-1B, … ..., 3.75GB～4GB-1B. The real memory address space is 0x0000000000 to ox43FFFFFFFF, the corresponding memory size is 17GB, 17GB can be divided into 68 memory blocks, 0~256MB-1B, 256MB-1B~512MB-1B, ..., 16.75GB~17GB -1B.

Assuming that 1GB of the 17GB is located in chip 11, and the remaining 16GB is located in memory 12, the 1GB memory of the address space 0x00000000 to 0x3FFFFFFF from the perspective of chip 11 can be recorded as the real 0-1GB of the chip, and can be accessed directly without address mapping. The 3GB memory of the address space 0x40000000 to 0xFFFFFFFF from the perspective of the chip 11 uses the address mapping method to access the memory 12 .

Among them, the 1GB memory of the memory address space 0x40000000 to 0x7FFFFFFF from the perspective of the chip 11 can be recorded as the chip virtual 1-2GB, for example, it can be mapped to the real memory address space 0x03C0000000 to 0x03FFFFFFFF. The 1GB memory of the memory address space 0x80000000 to 0xBFFFFFFF from the perspective of the chip 11 can be recorded as the chip virtual 2-3GB, for example, the real memory address space 0x0040000000 to 0x007FFFFFFF can be accessed through address mapping. The 1GB memory of the memory address space 0xC0000000 to 0xFFFFFFFF from the perspective of the chip 11 can be recorded as the chip virtual 3-4GB, for example, it can be mapped to the real memory address space 0x0400000000 to 0x043FFFFFFF.

It should be noted that the mapping relationship shown in FIG. 2 is only an example.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and features in the embodiments may be combined with each other without conflict.

FIG. 3 is a schematic flowchart of an address mapping method provided by an embodiment of the present application. The execution body of this embodiment may be a chip 11 , and the chip can access memory by means of address mapping. As shown in FIG. 3, the method of this embodiment may include:

Step 31, when the physical address of the memory needs to be accessed, determine the mapping relationship corresponding to the physical address, the chip uses at least two mapping methods to perform address mapping, and the attributes of the mapping relationship are the at least two mapping methods. one of the mapping methods.

In this step, different mapping modes among the at least two mapping modes have different timings for establishing and destroying the mapping relationship. The at least two mapping manners can be flexibly implemented according to actual requirements. In one embodiment, the at least two mapping manners may include at least two of static mapping manners, quasi-static mapping manners or dynamic mapping manners.

Wherein, the static mapping method is a mapping method in which a mapping relationship is established and destroyed in a hard-coded manner. In one embodiment, according to different units of static mapping, the static mapping manner may include a first static mapping manner and/or a second static mapping manner. The first static mapping manner may be a mapping manner in which the mapping relationship is established and destroyed in a hard-coded manner in units of chips. The second static mapping manner may be a mapping manner in which one or more operators are used as a unit to establish and destroy a mapping relationship in a hard-coded manner.

In one embodiment, the dynamic mapping method is a mapping method in which a mapping relationship is established and destroyed according to requirements. The quasi-static mapping method is a mapping method in which a mapping relationship is established according to requirements, and the mapping relationship is destroyed in units of one or more operators.

A comparison of the timing of establishing and destroying the mapping relationship among the first static mapping method, the second static mapping method, the dynamic mapping method, and the quasi-static mapping method can be shown in FIG. 4 . Referring to FIG. 4 , using the first static mapping method, the mapping relationship a with the attribute of the first static mapping method can be established at time 1 when the chip is started, and the mapping relationship a can be destroyed at time 7 when the chip is turned off. Using the second static mapping mode, the mapping relationship b with the attribute of the second static mapping mode can be established at time 2 when an operator starts executing, and the mapping relationship b can be destroyed at time 6 when the operator execution is completed. Using the quasi-static mapping method, the mapping relationship c of the quasi-static mapping method can be established at the moment 3 during the execution of a certain operator according to the requirements, and the mapping relationship c can be destroyed at the moment 6 when the execution of the operator is finished. . Using the dynamic mapping method, the attributes established according to the requirements at the moment 4 during the execution of an operator can be the mapping relationship d in the dynamic mapping method, and the mapping relationship d can be destroyed at the moment 5 when the requirements are made. It should be noted that in FIG. 4, the second static mapping mode and the quasi-static mapping mode are taken as an example in the unit of one operator. It can be understood that when multiple operators are used as the unit, the The attribute established when the first operator of the plurality of operators starts to execute is the mapping relationship of the second static mapping mode, and the attribute established according to the requirements during the execution of the plurality of operators is a quasi-static mapping mode. The mapping relationship can continue until the execution of the last operator among the multiple operators is completed.

Due to the different timings of establishing and destroying the mapping relationship in different mapping methods, the security, memory utilization, memory flexibility and performance brought by different timings of establishing and destroying the mapping relationship have their own advantages, such as the security of static mapping methods. and performance is better than dynamic mapping, the memory utilization and flexibility of dynamic mapping are better than static mapping, the security and performance of quasi-static mapping are better than dynamic mapping, and the memory utilization and flexibility are better than static mapping Therefore, the chip uses at least two mapping methods to perform address mapping, so that the address mapping performed by the chip can have the advantages of different mapping methods, thereby meeting application requirements.

Taking the chip that uses two mapping methods to perform address mapping as an example, a schematic diagram of the mapping from the memory virtual space of the chip to the real memory address space can be shown in Figure 5. In Figure 5, Page 1 to Page N can indicate that the memory virtual space from the chip perspective is divided into N virtual memory blocks, Block1 to Block N can indicate N real memory blocks, and the arrow direction can indicate the virtual memory block to the real memory block. The mapping relationship represented by the solid line arrows may be the mapping relationship established by one mapping method, and the mapping relationship represented by the dotted line arrows may represent the mapping relationship established by using another mapping method. It can be seen that the mapping relationship established by using the two mapping methods can exist at the same time, so that the address mapping performed by the chip can have the advantages of the two mapping methods respectively.

It should be noted that the mapping relationship shown in FIG. 5 is only an example.

It can be understood that, for N virtual memory blocks, N mapping tables may exist, and the N mapping tables are in one-to-one correspondence with the N virtual memory blocks, and are used to record the mapping relationship of the corresponding memory virtual blocks. Among them, the N mapping tables can be recorded as Map 1 to Map N, for example, where Map 1 can be used to record the mapping relationship between the virtual memory block Page 1 and a certain real memory block, and Map 2 can be used to record the virtual memory block Page 2 The mapping relationship to a real memory block, ..., Map N can be used to record the mapping relationship between the virtual memory block Page N and a real memory block.

Assuming that the physical address is 0x0040000000 in the address space shown in Figure 2, and the memory address space 0x80000000 to 0x8FFFFFFF from the perspective of chip 11 is mapped to the real memory address space 0x0040000000 to 0x004FFFFFFF, then the virtual memory blocks 0x80000000 to 0x8FFFFFFF correspond to those recorded in the Map The mapping relationship can be "004" in hexadecimal.

Step 32: Determine a virtual address mapped to the physical address according to the physical address and the mapping relationship.

In this step, it is assumed that the physical address is 0x0040000000 in the address space shown in FIG. 2 , and the mapping relationship corresponding to the physical address is that the memory address space 0x80000000 to 0x8FFFFFFF from the perspective of the chip 11 is mapped to the real memory address space 0x0040000000 to 0x004FFFFFFFF, it can be determined that the virtual address mapped to the physical address is 0x80000000.

Exemplarily, after determining the virtual address mapped to the physical address, the physical address of the memory may be accessed using the virtual address, for example, data may be written to the physical address, or data may be retrieved from the physical address. Read data from the physical address.

Exemplarily, after the virtual address mapped to the physical address is determined, the virtual address may be subjected to offset processing, for example, the virtual address is +1, and the virtual address after the offset processing is used to access the memory.

In the address mapping method provided by the embodiment of the present application, when the chip needs to access the physical address of the memory, the mapping relationship corresponding to the physical address is determined, and the virtual address mapped to the physical address is determined according to the physical address and the mapping relationship, wherein the chip is At least two mapping methods are used for address mapping, and the attribute of the mapping relationship corresponding to the physical address is one of the at least two mapping methods. Due to the different timings for establishing and destroying the mapping relationship in different mapping methods, different mapping methods are established and destroyed. The security, memory utilization, memory flexibility and performance brought by the timing of the relationship have their own advantages. Therefore, the chip uses at least two mapping methods for address mapping, so that the address mapping performed by the chip can have different mappings. The advantages of the method can meet the application requirements.

FIG. 6 is a schematic flowchart of an address mapping method provided by another embodiment of the present application. Based on the embodiment shown in FIG. 3 , this embodiment mainly describes that the at least two mapping modes include a first mapping mode and a third mapping mode. In the case of two mapping modes, the specific mode of the mapping relationship corresponding to the physical address is determined. As shown in FIG. 6 , the method provided by this embodiment may include:

Step 61 , when the physical address of the memory needs to be accessed, and in the case of an existing mapping relationship whose attribute is the first mapping mode, determine whether there is a mapping relationship matching the physical address.

In this step, whether there is a mapping relationship matching the physical address may be determined by querying the mapping table.

In one embodiment, the first mapping manner may include a static mapping manner, and the second mapping manner may include a quasi-static mapping manner, so that the chip can further use a quasi-static mapping manner on the basis that the static mapping manner has been used for address mapping. Static mapping is used for address mapping. In another embodiment, the first mapping manner may include a static mapping manner, and the second mapping manner may include a dynamic mapping manner, so that on the basis of the address mapping performed by the static mapping manner, the chip may further employ a dynamic mapping manner. The mapping method is used for address mapping. In yet another embodiment, the first mapping manner may include a quasi-static mapping manner, and the second mapping manner may include a dynamic mapping manner, so that the chip can further perform address mapping based on the quasi-static mapping manner. A quasi-static mapping method is used for address mapping.

In one embodiment, when the attribute of the mapping relationship corresponding to the physical address is a static mapping mode, before determining the mapping relationship corresponding to the physical address, the method further includes: establishing the attribute as the static mapping mode. of the target mapping relationship.

In the embodiment of the present application, corresponding to the at least two mapping manners, at least two mapping tables may exist in the chip for recording the mapping relationship of the corresponding attributes. Assuming that the at least two mapping modes include static mapping mode, quasi-static mapping mode and dynamic mapping mode, the mapping table in the chip can be divided into three categories, namely, the static mapping table corresponding to the static mapping mode, The quasi-static mapping table corresponding to the quasi-static mapping mode and the dynamic mapping table corresponding to the dynamic mapping mode.

The establishing the target mapping relationship whose attribute is the static mapping mode may specifically include: recording the target mapping relationship in a static mapping table corresponding to the static mapping mode, and enabling the target mapping relationship to be stored in the static mapping mode. The first register of the static mapping table. Optionally, after recording the target mapping relationship in a static mapping table corresponding to the static mapping mode, the method may further include: setting the static mapping table to a locked state. When the static mapping table is in a locked state, it may indicate that modification of the mapping relationship recorded in the static mapping table is prohibited. By setting the static mapping table to a locked state, it is possible to avoid erroneous modification of the static mapping table, which is beneficial to improve the security of the static mapping table.

Optionally, after setting the static mapping table to a locked state, it may further include: when it is determined that the mapping relationship recorded in the static mapping table needs to be modified, setting the static mapping table to an unlocked state. , and disable the first register. Therefore, the mapping relationship recorded in the static mapping table can be updated according to the requirements, which is beneficial to improve flexibility. It should be noted that, in the embodiments of the present application, the mapping relationships whose attributes are in the static mapping mode are all established, destroyed and modified in a hard-coded manner.

Optionally, the number of static mapping tables corresponding to the static mapping mode may be a fixed value, or the number of static mapping tables corresponding to the static mapping mode may be a variable value configured according to usage requirements. The number of static mapping tables corresponding to the static mapping method is a variable value configured according to usage requirements, so that the number of static mapping tables can be flexibly configured according to usage requirements, which is beneficial to improve flexibility.

Step 62, if there is, the mapping relationship matching the physical address is the mapping relationship corresponding to the physical address.

It should be noted that, after step 62 is performed, step 64 is performed.

Step 63, if it does not exist, establish a target mapping relationship whose attribute is the second mapping mode, the target mapping relationship is a mapping relationship between the target virtual address range and the target physical address range, and the target physical address range includes the physical address, and the target mapping relationship is the mapping relationship corresponding to the physical address.

It should be noted that, in the embodiments of the present application, the mapping relationships in which the attribute is a non-static mapping manner are established according to requirements. The difference between the quasi-static mapping method and the dynamic mapping method, which are non-static mapping methods, is mainly in the timing of destroying the mapping relationship between the two. Specifically, the quasi-static mapping method can be destroyed when one or more operators are executed, and the dynamic mapping method can be destroyed when the requirements are met.

In an embodiment, when the second mapping mode includes a dynamic mapping mode, the establishing the target mapping relationship whose attribute is the second mapping mode may specifically include: establishing all the attributes whose attributes are the dynamic mapping mode. Describe the target mapping relationship.

The establishing the target mapping relationship whose attribute is the dynamic mapping mode may specifically include: recording the target mapping relationship in a dynamic mapping table corresponding to the dynamic mapping mode, and enabling the target mapping relationship to be stored in the dynamic mapping mode. The second register of the dynamic mapping table. Afterwards, when the requirement for triggering the creation of the target mapping relationship is fulfilled, the second register may be disabled. By disabling the second register, the target mapping relationship can be destroyed, so that the dynamic mapping table can be destroyed when the requirement is met.

Optionally, the number of dynamic mapping tables corresponding to the dynamic mapping mode may be a fixed value, or the number of dynamic mapping tables corresponding to the dynamic mapping mode may be a variable value configured according to usage requirements. The number of dynamic mapping tables corresponding to the dynamic mapping method is a variable value configured according to usage requirements, so that the number of dynamic mapping tables can be flexibly configured according to usage requirements, which is beneficial to improve flexibility.

In another embodiment, when the second mapping mode includes a quasi-static mapping mode, the establishing the target mapping relationship whose attribute is the second mapping mode may specifically include: establishing an attribute as the quasi-static mapping The target mapping relationship of the mode.

The establishment of the target mapping relationship whose attribute is the quasi-static mapping mode may specifically include: determining whether there is a quasi-static mapping table in an unlocked state; if so, recording the target mapping relationship in an unlocked state. In the quasi-static mapping table, the quasi-static mapping table is set to a locked state, and the third register for storing the dynamic mapping table is enabled. When the static mapping table is in a locked state, it may indicate that modification of the mapping relationship recorded in the static mapping table is prohibited. By setting the static mapping table to a locked state, it can be avoided that the static mapping table is incorrectly modified before the execution of one or more operators is completed, which is beneficial to improve the security of the static mapping table.

Further optionally, if it is determined that there is no quasi-static mapping table in the unlocked state, the target mapping relationship whose attribute is a dynamic mapping mode can be established.

Optionally, after setting the quasi-static mapping table to a locked state, it may further include: in the case that the execution of one or more operators is completed, setting the quasi-static mapping table to an unlocked state, and The third register is disabled. By setting the static mapping table to an unlocked state and disabling the third register, the target mapping relationship can be destroyed, so that the static mapping table can be destroyed in units of one or more operators.

Optionally, the number of quasi-static mapping tables corresponding to the quasi-static mapping mode may be a fixed value, or the number of quasi-static mapping tables corresponding to the quasi-static mapping mode may be a variable value configured according to usage requirements. The number of quasi-static mapping tables corresponding to the quasi-static mapping method is a variable value configured according to usage requirements, so that the number of quasi-static mapping tables can be flexibly configured according to usage requirements, which is beneficial to improve flexibility.

In yet another embodiment, in the case that the number of the second mapping modes is multiple, the establishing the target mapping relationship whose attribute is the second mapping mode may specifically include: determining a plurality of the first mapping modes. The second mapping mode of the target in the two mapping modes is established, and the target mapping relationship whose attribute is the target mapping mode is established. Therefore, it is possible to flexibly select one of the multiple second mapping manners according to requirements to establish the target mapping relationship.

Exemplarily, the plurality of second mapping modes may include the quasi-static mapping mode and the dynamic mapping mode, and the target second mapping mode may be the quasi-static mapping mode and the dynamic mapping mode. one of the. Optionally, the determining the target second mapping mode among the plurality of second mapping modes includes: determining whether there is a quasi-static mapping table in an unlocked state; if so, the quasi-static mapping mode is the target second mapping mode. Mapping mode, if not, the dynamic mapping mode is the target second mapping mode. Therefore, it is possible to establish a mapping relationship in a quasi-static mapping manner of attributes preferentially.

In one embodiment, the characteristics of the static mapping table, the quasi-static mapping table and the dynamic mapping table are compared as shown in Table 1 below.

Table 1

	静态映射表static mapping table	准静态映射表Quasi-static mapping table	动态映射表dynamic mapping table
根据需求创建Create on demand	NN	YY	YY
根据需求修改Modify as needed	NN	NN	YY
加锁lock	YY	YY	NN
硬编码方式创建Hardcoded to create	YY	NN	NN
硬编码方式修改hard-coded modification	YY	NN	NN
硬编码方式解锁Hardcoded to unlock	YY	NN	NN
整体销毁total destruction	NN	YY	YY
数量可配Quantity available	YY	YY	YY

Note, "N" means no, "Y" means yes.

As can be seen in conjunction with Table 1, in an embodiment of the present application, the characteristics of the static mapping table can be: the mapping relationship recorded in the static mapping table is created in a hard-coded manner, the static mapping table supports locking and unlocking, and the unlocking is based on Hard-coded, the number of static mapping tables can be configured, and the static mapping tables are destroyed separately. The characteristics of the quasi-static mapping table may be: the mapping relationship recorded in the quasi-static mapping table is created according to the requirements, the quasi-static mapping table supports locking, the number of the quasi-static mapping table is configurable, and the quasi-static mapping table is destroyed as a whole. The characteristics of the dynamic mapping table can be: the mapping relationship recorded in the dynamic mapping table is created and modified according to the requirements, the dynamic mapping table does not support locking, the number of dynamic mapping tables can be configured, and the dynamic mapping table can be destroyed as a whole. Among them, taking an operator as an example, the overall destruction of the quasi-static mapping table may refer to destroying all the mapping relationships currently recorded in the quasi-static mapping table when the execution of the operator is completed, and the dynamic mapping table is completely destroyed. The overall destruction may refer to destroying all the mapping relationships currently recorded in the dynamic mapping table when the execution of the operator is completed.

In one embodiment, when the first mapping mode includes a quasi-static mapping mode and the second static mapping mode includes a dynamic mapping mode, the establishment attribute in step 63 is the target mapping relationship of the second mapping mode. , which may specifically include: determining whether there is a quasi-static mapping table in an unlocked state; and, if not, establishing the target mapping relationship whose attribute is a dynamic mapping manner. Further, if there is a quasi-static mapping table in an unlocked state, the target mapping relationship can be recorded in a quasi-static mapping table in an unlocked state, the quasi-static mapping table is set to a locked state, and the A third register that can be used to store the dynamic mapping table. It should be noted that, for a specific manner of establishing a target mapping relationship whose attribute is a dynamic mapping manner or a static mapping manner, reference may be made to the foregoing description, which will not be repeated here.

Step 64: Determine the virtual address mapped to the physical address according to the physical address and the mapping relationship.

It should be noted that step 64 is similar to step 32, and details are not repeated here.

The address mapping method provided in this embodiment determines whether there is a mapping relationship that matches the physical address when there is a mapping relationship whose attribute is the first mapping mode. If there is, the mapping relationship that can match the physical address is the same as If the mapping relationship corresponding to the physical address does not exist, the target mapping relationship with the attribute as the second mapping mode can be established, so that on the basis of the existing mapping relationship with the attribute as the first mapping mode, the attribute as the second mapping mode can be further established. The mapping relationship of the mode, thus meeting the requirements for the mapping relationship of different mapping modes.

Taking the at least two mapping modes including static mapping mode, dynamic mapping mode and quasi-static mapping mode as an example, as shown in FIG. 7 , the process of performing address mapping on a chip is illustrated by an example.

Step 71: Configure the respective numbers of the static mapping table, the dynamic mapping table and the quasi-static mapping table.

For example, the number of mapping tables can be configured by calling void config_map(size_t static_map, size_t qstatic_map, size_t dynamic_map). In config_map, static_map can be used as the number of static mapping tables, qstatic_map can be used as the number of quasi-static mapping tables, and dynamic_map can be used as the number of dynamic mapping tables. In config_map, the sum of the static mapping table, the quasi-static mapping table and the dynamic mapping table can also be restricted to be smaller than the total number of mapping tables (for example, N).

Here, it can be assumed that the number of static mapping tables and quasi-static mapping tables is 4, and the number of dynamic mapping tables is N-8, as shown in FIG. 8 , Map 1 to Map 4 can be, for example, static mapping tables, Map 5 to Map 8 can be, for example, a quasi-static mapping table, and Map 9 to Map N can be, for example, a dynamic mapping table. The N Maps correspond one-to-one with the N Pages shown in FIG. 5 , and Map i corresponds to Page i.

Step 72, establishing a mapping relationship in which the attribute is a static mapping mode.

For example, by calling int32_t config_lock_mapX(uint64_t physical_addr), a mapping table whose attribute is static mapping can be established, where X can correspond to a static mapping table Map X, and Map X can be one of Map 1 to Map 4. , physical_addr can represent a physical address. In config_lock_mapX, the mapping relationship between PageX and the physical memory block represented by uint64_t physical_addr can be recorded in Map X, set Map X to the locked state, and enable the register used to store Map X.

After that, when you need to modify the mapping relationship recorded in a static mapping table, you can also call void release_mapX() to destroy the mapping table whose attributes are static mapping, where X can correspond to a static mapping table Map X. In release_mapX, Map X can be set to the unlocked state and the registers used to store Map X are disabled. After that, config_lock_mapX can be further called to establish the mapping relationship, so as to realize the updating of the mapping relationship in the static mapping table.

Step 73 , in the process of executing a certain operator, when it is necessary to access a certain physical address of the memory, determine whether there is a mapping relationship matching the physical address.

If there is a mapping relationship matching the physical address, step 77 may be executed, and it can be understood that the mapping relationship matching the physical address is the mapping relationship corresponding to the physical address. If there is no mapping relationship matching the physical address, step 74 may be performed.

Step 74, determine whether there is a quasi-static mapping table in an unlocked state.

If there is a quasi-static mapping table in an unlocked state, step 75 may be performed. If there is no quasi-static mapping table in the unlocked state, step 76 may be performed.

Step 75: Record the target mapping relationship in a quasi-static mapping table in an unlocked state, set the quasi-static mapping table to a locked state, and enable a register for storing the quasi-static mapping table.

It should be noted that, after step 75 is performed, step 77 is further performed.

Step 76: Record the target mapping relationship in a dynamic mapping table, and enable a register for storing the dynamic mapping table.

It should be noted that after step 76 is performed, step 77 is further performed. It can be understood that the target mapping relationship is the mapping relationship corresponding to the physical address.

Step 77: Determine the virtual address mapped to the physical address according to the mapping relationship corresponding to the physical address.

In step 78, the address space corresponding to the physical address in the memory is accessed using the virtual address mapped to the physical address.

It should be noted that, in step 78, the memory access using the virtual address mapped to the physical address is used as an example.

Step 79, if the target mapping relationship is recorded in the dynamic mapping table, destroy the dynamic mapping table when the requirement is met.

For example, you can call void release_dynamic_map() to destroy the mapping relationship whose attributes are in dynamic mapping mode. Registers used to store the dynamic mapping table can be disabled in release_dynamic_map.

In step 710, if the target mapping relationship is recorded in the quasi-static mapping table, in the case that the execution of the operator is completed, destroy the quasi-static mapping table.

For example, the quasi-static mapping of attributes can be destroyed by calling void release_qstatic_map(). In release_qstatic_map, all static mapping tables can be set to an unlocked state, and the registers used to store each static mapping table are prohibited.

Optionally, when the physical address corresponding to a certain virtual address needs to be determined, for example, it can be implemented by calling uint64_t get_physical_address(uint32_t virtual_addr), where virtual_addr represents a virtual address. In get_physical_address, the physical address to which the logical address is mapped may be determined based on the logical address and the corresponding mapping relationship.

FIG. 9 is a schematic structural diagram of an address mapping apparatus provided by an embodiment of the present application. The apparatus is applied to a chip, and the chip can access memory by means of address mapping. As shown in FIG. 9 , the apparatus 90 may include: a processor 91 and memory 92.

The memory 92 is used to store program codes;

The processor 91 calls the program code, and when the program code is executed, is configured to perform the following operations:

The address mapping apparatus provided in this embodiment can be used to implement the technical solutions of the foregoing method embodiments, and the implementation principles and technical effects thereof are similar to those of the method embodiments, which will not be repeated here.

Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by program instructions related to hardware. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps including the above method embodiments are executed; and the foregoing storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present application. scope.

Claims

An address mapping method, applied to a chip, wherein the chip can access memory by means of address mapping, wherein the method comprises:

When the physical address of the memory needs to be accessed, a mapping relationship corresponding to the physical address is determined, the chip uses at least two mapping methods for address mapping, and the attributes of the mapping relationship are the at least two mapping methods one of the

According to the physical address and the mapping relationship, the virtual address mapped to the physical address is determined.
The method according to claim 1, wherein the at least two mapping modes include a first mapping mode and a second mapping mode, and the determining the mapping relationship corresponding to the physical address includes:

In the case of an existing mapping relationship whose attribute is the first mapping mode, determine whether there is a mapping relationship matching the physical address;

If there is, the mapping relationship matching the physical address is the mapping relationship corresponding to the physical address;

If it does not exist, establish a target mapping relationship whose attribute is the second mapping mode, where the target mapping relationship is a mapping relationship in which the target virtual address range is mapped to the target physical address range, and the target physical address range includes the physical address, The target mapping relationship is the mapping relationship corresponding to the physical address.
The method according to claim 2, wherein the first mapping manner includes a static mapping manner, and the static mapping manner is a mapping manner in which a mapping relationship is established and destroyed in a hard-coded manner.
The method according to claim 3, wherein the static mapping method includes a first static mapping method, and the first static mapping method is a mapping method in which a mapping relationship is established and destroyed by hard coding in a chip unit. .
The method according to claim 3, wherein the static mapping method includes a second static mapping method, and the second static mapping method is established and destroyed in a hard-coded manner in units of one or more operators. The mapping method of the mapping relationship.
The method according to claim 3, wherein, when the attribute of the mapping relationship corresponding to the physical address is a static mapping mode, before the determining the mapping relationship corresponding to the physical address, the method further comprises: The target mapping relationship whose attribute is the static mapping mode is established.
The method according to claim 6, wherein the establishing the target mapping relationship whose attribute is the static mapping mode comprises: recording the target mapping relationship in a static mapping corresponding to the static mapping mode table and enable the first register for storing the static mapping table.
The method according to claim 7, wherein after recording the target mapping relationship in a static mapping table corresponding to the static mapping mode, the method further comprises: setting the static mapping table to be locked state.
The method according to claim 8, wherein after setting the static mapping table to a locked state, the method further comprises: when a mapping relationship recorded in the static mapping table needs to be modified, The static mapping table is set to an unlocked state and the first register is disabled.
The method according to claim 7, wherein the number of static mapping tables corresponding to the static mapping mode is a fixed value.
The method according to claim 7, wherein the number of static mapping tables corresponding to the static mapping mode is a variable value configured according to usage requirements.
The method according to any one of claims 3-11, wherein the second mapping mode comprises: a dynamic mapping mode; the dynamic mapping mode is a mapping mode in which a mapping relationship is established and destroyed according to requirements;

The establishing the target mapping relationship whose attribute is the second mapping mode includes: establishing the target mapping relationship whose attribute is the dynamic mapping mode.
The method according to claim 12, wherein the establishing the target mapping relationship whose attribute is the dynamic mapping mode comprises: recording the target mapping relationship in a dynamic mapping corresponding to the dynamic mapping mode table and enable a second register for storing the dynamic mapping table.
The method according to claim 13, wherein the method further comprises: disabling the second register when the requirement is met.
The method according to claim 13, wherein the number of dynamic mapping tables corresponding to the dynamic mapping mode is a fixed value.
The method according to claim 13, wherein the number of the dynamic mapping table corresponding to the dynamic mapping mode is a variable value configured according to usage requirements.
The method according to claim 2 or 12, wherein the second mapping method includes a quasi-static mapping method; the quasi-static mapping method is to establish a mapping relationship according to requirements, and use one or more operators as a unit Destroy the mapping method of the mapping relationship;

The establishing the target mapping relationship whose attribute is the second mapping mode includes: establishing the target mapping relationship whose attribute is the quasi-static mapping mode.
The method according to claim 17, wherein the establishing the target mapping relationship whose attribute is the quasi-static mapping method comprises:

Determine if there is a quasi-static mapping table in the unlocked state;

If so, record the target mapping relationship in a quasi-static mapping table in an unlocked state, set the quasi-static mapping table to a locked state, and enable a third mapping table for storing the dynamic mapping table register.
The method according to claim 18, wherein after setting the quasi-static mapping table to a locked state, the method further comprises: in the case that the execution of one or more operators is completed, setting the quasi-static mapping table to a locked state. The mapping table is set to an unlocked state and the third register is disabled.
The method according to claim 18, wherein the method further comprises: if it is determined that there is no quasi-static mapping table in an unlocked state, establishing the target mapping relationship whose attribute is a dynamic mapping mode.
The method according to claim 18, wherein the number of quasi-static mapping tables corresponding to the quasi-static mapping mode is a fixed value.
The method according to claim 18, wherein the number of quasi-static mapping tables corresponding to the quasi-static mapping mode is a variable value configured according to usage requirements.
The method according to claim 2, wherein, when the number of the second mapping modes is multiple, the establishing the target mapping relationship whose attribute is the second mapping mode comprises:

A plurality of target mapping modes in the second mapping modes are determined, and the target mapping relationship whose attribute is the target mapping mode is established.
The method according to claim 2, wherein the first mapping mode includes a quasi-static mapping mode, and the second mapping mode includes a dynamic mapping mode; wherein, the quasi-static mapping mode is to establish a mapping relationship according to requirements , and destroy the mapping method of the mapping relationship with one or more operators as a unit; the dynamic mapping method is a mapping method of establishing and destroying the mapping relationship according to the requirements.
The method according to claim 24, wherein the establishing a target mapping relationship whose attribute is the second mapping mode comprises:

Determine if there is a quasi-static mapping table in the unlocked state;

If not, establish the target mapping relationship whose attribute is the dynamic mapping mode.
The method of claim 25, wherein the method further comprises:

If there is a quasi-static mapping table in an unlocked state, record the target mapping relationship in a quasi-static mapping table in an unlocked state, set the quasi-static mapping table in a locked state, and enable the quasi-static mapping table to be used for storage the third register of the dynamic mapping table.
An address mapping device, applied to a chip, wherein the chip can access memory by means of address mapping, characterized in that the device comprises: a memory and a processor;

the memory for storing program codes;

The processor calls the program code, and when the program code is executed, is configured to perform the following operations:

When the physical address of the memory needs to be accessed, a mapping relationship corresponding to the physical address is determined, the chip uses at least two mapping methods for address mapping, and the attributes of the mapping relationship are the at least two mapping methods one of the

According to the physical address and the mapping relationship, the virtual address mapped to the physical address is determined.
The apparatus according to claim 27, wherein the at least two mapping modes include a first mapping mode and a second mapping mode, and the processor is configured to determine the mapping relationship corresponding to the physical address, specifically including:

In the case of an existing mapping relationship whose attribute is the first mapping mode, determine whether there is a mapping relationship matching the physical address;

If there is, the mapping relationship matching the physical address is the mapping relationship corresponding to the physical address;

If it does not exist, establish a target mapping relationship whose attribute is the second mapping mode, where the target mapping relationship is a mapping relationship in which the target virtual address range is mapped to the target physical address range, and the target physical address range includes the physical address, The target mapping relationship is the mapping relationship corresponding to the physical address.
The apparatus according to claim 28, wherein the first mapping mode includes a static mapping mode, and the static mapping mode is a mapping mode in which a mapping relationship is established and destroyed in a hard-coded manner.
The device according to claim 29, wherein the static mapping method includes a first static mapping method, and the first static mapping method is a mapping method in which the mapping relationship is established and destroyed by hard coding in a chip unit. .
The apparatus according to claim 29, wherein the static mapping method includes a second static mapping method, and the second static mapping method is established and destroyed in a hard-coded manner in units of one or more operators. The mapping method of the mapping relationship.
The apparatus according to claim 29, wherein, in a case where the attribute of the mapping relationship corresponding to the physical address is in a static mapping manner, the processor is further configured to: establish an attribute whose attribute is in the static mapping manner the target mapping relationship.
The apparatus according to claim 32, wherein the processor is configured to establish the target mapping relationship whose attribute is the static mapping mode, specifically comprising: recording the target mapping relationship in the corresponding static mapping mode in a static mapping table, and enable the first register for storing the static mapping table.
The apparatus according to claim 33, wherein the processor is further configured to: set the static mapping table to a locked state.
The apparatus according to claim 34, wherein the processor is further configured to: before the mapping relationship recorded in the static mapping table needs to be modified, set the static mapping table to an unlocked state, and disable the the first register.
The apparatus according to claim 33, wherein the number of static mapping tables corresponding to the static mapping mode is a fixed value.
The apparatus according to claim 33, wherein the number of static mapping tables corresponding to the static mapping mode is a variable value configured according to usage requirements.
The device according to any one of claims 29-37, wherein the second mapping mode comprises: a dynamic mapping mode; the dynamic mapping mode is a mapping mode in which a mapping relationship is established and destroyed according to requirements;

The processing is used to establish the target mapping relationship whose attribute is the second mapping mode, and specifically includes: establishing the target mapping relationship whose attribute is the dynamic mapping mode.
The apparatus according to claim 38, wherein the processor is configured to establish the target mapping relationship whose attribute is the dynamic mapping mode, specifically comprising: recording the target mapping relationship in the dynamic mapping mode corresponding to the in a dynamic mapping table, and enable a second register for storing the dynamic mapping table.
The apparatus of claim 39, wherein the processor is further configured to disable the second register if the requirement is met.
The apparatus according to claim 39, wherein the number of dynamic mapping tables corresponding to the dynamic mapping mode is a fixed value.
The device according to claim 39, wherein the number of dynamic mapping tables corresponding to the dynamic mapping mode is a variable value configured according to usage requirements.
The apparatus according to claim 28 or 38, wherein the second mapping mode includes a quasi-static mapping mode; the quasi-static mapping mode is to establish a mapping relationship according to requirements, and use one or more operators as a unit Destroy the mapping method of the mapping relationship;

The processor is configured to establish the target mapping relationship whose attribute is the second mapping mode, and specifically includes: establishing the target mapping relationship whose attribute is the quasi-static mapping mode.
The apparatus according to claim 43, wherein the processor is configured to establish the target mapping relationship whose attribute is the quasi-static mapping mode, and specifically includes:

Determine if there is a quasi-static mapping table in the unlocked state;

If so, record the target mapping relationship in a quasi-static mapping table in an unlocked state, set the quasi-static mapping table to a locked state, and enable a third mapping table for storing the dynamic mapping table register.
The apparatus according to claim 44, wherein the processor is further configured to: set the quasi-static mapping table to an unlocked state and disable the third register.
The apparatus according to claim 44, wherein the processor is further configured to: if it is determined that there is no quasi-static mapping table in an unlocked state, establish the target mapping relationship whose attribute is a dynamic mapping mode.
The apparatus according to claim 44, wherein the number of quasi-static mapping tables corresponding to the quasi-static mapping mode is a fixed value.
The apparatus according to claim 44, wherein the number of quasi-static mapping tables corresponding to the quasi-static mapping mode is a variable value configured according to usage requirements.
The apparatus according to claim 28, wherein when the number of the second mapping modes is multiple, the processor is configured to establish the target mapping relationship whose attribute is the second mapping mode, Specifically include:

A plurality of target mapping modes in the second mapping modes are determined, and the target mapping relationship whose attribute is the target mapping mode is established.
The apparatus according to claim 28, wherein the first mapping manner includes a quasi-static mapping manner, and the second mapping manner includes a dynamic mapping manner; wherein, the quasi-static mapping manner is to establish a mapping relationship according to requirements , and destroy the mapping method of the mapping relationship in units of one or more operators; the dynamic mapping method is the mapping method of establishing and destroying the mapping relationship according to the requirements.
The apparatus according to claim 50, wherein the processor is configured to establish a target mapping relationship whose attribute is the second mapping mode, comprising:

Determine if there is a quasi-static mapping table in the unlocked state;

If not, establish the target mapping relationship whose attribute is the dynamic mapping mode.
The apparatus of claim 51, wherein the processor is further configured to:

If there is a quasi-static mapping table in an unlocked state, record the target mapping relationship in a quasi-static mapping table in an unlocked state, set the quasi-static mapping table to a locked state, and enable the quasi-static mapping table to be used for storage the third register of the dynamic mapping table.
A computer-readable storage medium, characterized in that, the computer-readable storage medium stores a computer program, and the computer program includes at least one piece of code, and the at least one piece of code can be executed by a computer, so as to control the computer to execute as claimed in the claim. The method of any one of claims 1-26.
A computer program, characterized in that, when the computer program is executed by a computer, it is used to implement the method according to any one of claims 1-26.