WO2022148298A1 - 一种测试方法及多处理器soc芯片 - Google Patents

一种测试方法及多处理器soc芯片 Download PDF

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Publication number
WO2022148298A1
WO2022148298A1 PCT/CN2021/143261 CN2021143261W WO2022148298A1 WO 2022148298 A1 WO2022148298 A1 WO 2022148298A1 CN 2021143261 W CN2021143261 W CN 2021143261W WO 2022148298 A1 WO2022148298 A1 WO 2022148298A1
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command
slave
slave system
main system
interrupt
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PCT/CN2021/143261
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English (en)
French (fr)
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刘文涛
吴睿振
沈欣舞
张辉
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苏州浪潮智能科技有限公司
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Priority to US18/259,675 priority Critical patent/US20240054059A1/en
Publication of WO2022148298A1 publication Critical patent/WO2022148298A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4831—Task transfer initiation or dispatching by interrupt, e.g. masked with variable priority
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G06F11/2242—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors in multi-processor systems, e.g. one processor becoming the test master
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4818—Priority circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

Definitions

  • the present application relates to the technical field of SOC chips, and in particular, to a testing method and a multiprocessor SOC chip.
  • SOC System On Chip
  • CPUs Central Processing Unit, central processing unit
  • the architecture of such a multi-processor SOC chip is generally composed of a main system including a main CPU and a plurality of other subsystems including sub-CPUs.
  • main system including a main CPU and a plurality of other subsystems including sub-CPUs.
  • performance requirements for the CPU are also different.
  • CPU IP Intellectual Property, a hardware description language program with specific circuit functions
  • IDE Integrated Development Environment
  • testing is an extremely important link, which ensures the correctness of the chip design.
  • the testing tasks of such multiprocessor SOC chips are usually divided according to each system, and different testers are responsible for testing the main system and other subsystems. Due to the different CPU architectures of each system, in general, the test case development environments used by each system are also different, which are generally based on the IDE provided by the CPU IP manufacturer. Different testers develop test cases in different development environments, so there is a high possibility that the development of test cases for the entire SOC chip will lose the unity and consistency, which will eventually lead to test loopholes and low test efficiency.
  • the purpose of the present application is to provide a test method and a multiprocessor SOC chip, which can ensure the uniformity and consistency of multiprocessor SOC chip testing, thereby improving test efficiency and reducing the occurrence rate of test loopholes. Its specific plan is as follows:
  • the present application discloses a test method, which is applied to a multiprocessor SOC chip, where the multiprocessor SOC chip includes a master system and at least one slave system, and the method includes:
  • the first command line in the input cache of the main system is parsed by the main system to obtain the corresponding first command and the first parameter. If the first command is a command of the main system in the main system command set, all the first command, if the first command is a command corresponding to the subsystem, the first parameter is sent to the corresponding slave system input buffer as the second command line;
  • the second command line is parsed by the slave system to obtain the corresponding second command and second parameter. If the second command is a command in the slave system command set of the slave system, the second command is executed. Order.
  • the method further includes:
  • the corresponding first output information is written into the corresponding main system output buffer
  • the corresponding second output information is written into the corresponding slave system output buffer
  • the second interrupt signal corresponding to the slave system in the master system is triggered by the interrupt trigger module of the slave system, so that the master system calls the interrupt service routine corresponding to the second interrupt signal to process the second output information .
  • the method further includes:
  • the corresponding interrupt service routine is called to process the corresponding output information.
  • the method before writing the corresponding second output information into the corresponding slave system output cache, the method further includes:
  • the slave system monitors whether the corresponding slave system output cache is currently in an idle state, and if so, writes the second output information into the corresponding slave system output cache.
  • the invoking an interrupt service routine corresponding to the second interrupt signal to process the second output information includes:
  • the interrupt service program corresponding to the second interrupt signal is called, and the second output information is printed to the terminal display interface for display.
  • the method further includes:
  • the master system input buffer, the slave system input buffer, the master system output buffer, and the slave system output buffer are respectively allocated in shared storage for the master system and the slave system in advance.
  • the method further includes:
  • the first command is not a command of the main system in the main system command set, and is not a command corresponding to a subsystem, clearing the main system input cache;
  • the slave system input cache is cleared.
  • the present application discloses a multiprocessor SOC chip, the multiprocessor SOC chip includes a master system and at least one slave system, wherein,
  • the main system is used to parse the first command line in the input cache of the main system to obtain the corresponding first command and the first parameter. If the first command is a command of the main system in the main system command set, then Execute the first command, if the first command is a command corresponding to the subsystem, send the first parameter as a second command line to the corresponding slave system input buffer;
  • the slave system is used to parse the second command line to obtain the corresponding second command and second parameter, if the second command is a command in the slave system command set of the slave system, execute the second command Second order.
  • the main system is further configured to write the corresponding first output information into the corresponding main system output buffer after executing the first command, and trigger the corresponding first output through the interrupt triggering module of the main system.
  • an interrupt signal to call an interrupt service routine corresponding to the first interrupt signal to process the first output information;
  • the slave system is further configured to write the corresponding second output information into the corresponding slave system output buffer after executing the second command, and trigger the slave system in the master system through the interrupt trigger module of the slave system. the second interrupt signal corresponding to the system, so that the main system calls the interrupt service routine corresponding to the second interrupt signal to process the second output information.
  • the multiprocessor SOC chip further includes:
  • the shared storage is used for allocating the master system input buffer, the slave system input buffer, the master system output buffer, and the slave system output buffer to the master system and the slave system.
  • the present application parses the first command line in the main system input cache through the main system to obtain the corresponding first command and first parameter. If the first command is the main system command set in the main system command , then execute the first command, if the first command is a command corresponding to the subsystem, send the first parameter as a second command line to the corresponding slave system input cache; The second command line is used to obtain the corresponding second command and the second parameter. If the second command is a command in the slave system command set of the slave system, the second command is executed. That is, the present application unifies the command processing methods of the master system and the slave system, and reduces the differences in processing commands of each system. In this way, the unity and consistency of multi-processor SOC chip testing can be guaranteed, thereby improving test efficiency and reducing Test for the occurrence of vulnerabilities.
  • Fig. 2 is a kind of specific command execution flow chart disclosed by the application
  • FIG. 4 is a specific multi-processor SOC chip architecture diagram disclosed in the application.
  • 5a is a schematic diagram of a specific input buffer allocation disclosed in the application.
  • 5b is a schematic diagram of a specific output buffer allocation disclosed in the application.
  • FIG. 6 is a working flow chart of a specific information output system disclosed in the application.
  • Fig. 7 is a specific main system interrupt processing flowchart disclosed in the application.
  • FIG. 8 is a schematic structural diagram of a multiprocessor SOC chip disclosed in the present application.
  • testing is an extremely important link, which ensures the correctness of the chip design.
  • the testing tasks of such multiprocessor SOC chips are usually divided according to each system, and different testers are responsible for testing the main system and other subsystems. Due to the different CPU architectures of each system, in general, the test case development environments used by each system are also different, which are generally based on the IDE provided by the CPU IP manufacturer. Different testers develop test cases in different development environments, so there is a high possibility that the development of the entire SOC chip test case will lose the unity and consistency, which will eventually lead to test loopholes and low test efficiency. To this end, the present application provides a SOC chip testing solution, which can ensure the uniformity and consistency of multi-processor SOC chip testing, thereby improving testing efficiency and reducing the occurrence rate of testing vulnerabilities.
  • an embodiment of the present application discloses a test method, which is applied to a multiprocessor SOC chip, where the multiprocessor SOC chip includes a master system and at least one slave system, and the method includes:
  • Step S11 Parse the first command line in the input cache of the main system by the main system to obtain the corresponding first command and the first parameter, if the first command is a command of the main system in the main system command set, The first command is executed, and if the first command is a command corresponding to the subsystem, the first parameter is sent to the corresponding slave system input buffer as a second command line.
  • the commands of the slave system may be named based on the name of the slave system. For example, sub_a, sub_b, sub_c are added to the command set of the main system.
  • the main system parses the command, when the command name is sub_a, sub_b, sub_c, the main system distributes the parameters after the command name as the commands of the subsystem to the subsystems to execute.
  • the main system input cache is cleared.
  • the main system input cache of the main system receives the inputted first command line
  • the first command line is parsed through a preset command parsing function to obtain the corresponding first command and its first command line.
  • a parameter the main system inquires the first command in the main system command set, if it cannot be queried, then clears the main system input cache and waits for the input of the next command line. Named command, execute the first command, after the execution is completed, clear the input cache of the main system, and wait for the input of the next command line. If it is a command named after the subsystem name, the first parameter is used as the first parameter.
  • the second command line is sent to the corresponding slave system input buffer.
  • Step S12 Parse the second command line through the slave system to obtain the corresponding second command and second parameter, if the second command is a command in the slave system command set of the slave system, execute the command. the second command.
  • the slave system input cache is cleared.
  • FIG. 2 is a specific command execution flowchart disclosed in this application.
  • Use the input buffer (input buffer) of the main system and each subsystem to realize the input of commands implement a set of command processing mechanism in the main system, execute the main system commands through this command processing mechanism, and distribute the commands of each subsystem to each Subsystem execution.
  • a set of command processing mechanism is implemented in each subsystem to execute the subsystem commands distributed from the main system.
  • a naming method with the subsystem name as the command name is established.
  • the input buffer of the main system When the input buffer of the main system receives the input command line, it parses the command line through the command parsing function, and obtains the command and its parameters represented by the command line. This command is queried in the command set of the main system. Command, this command is an unknown command, the main system clears the input buffer and waits for the input of the next command line. If the command is queried, and the command is not named after the subsystem name, this command is executed. When the command is executed, it is cleared. input buffer and wait for input on the next command line.
  • the main system sends the parameters after the command as the command line of the subsystem to the input buffer of the corresponding subsystem, and the subsystem command parsing process is consistent with the main system command parsing process , the subsystem parses the command line through the command parsing function, and obtains the command and its parameters represented by the command line, and queries the command in the command set of the subsystem. If the command is not queried, the command is an unknown command. The system clears the input buffer and waits for the input of the next command line. If the command is queried, it executes the command. When the command is executed, it clears the input buffer and waits for the input of the next command line.
  • the embodiment of the present application can establish a command processing mechanism for the main system and each subsystem, that is, which commands the main system should support, which commands should each subsystem support, and how each system handles these commands.
  • the command list of the main system is established in the main system, the respective command lists are established in each subsystem, and the functions of the functions to be implemented by these commands are created, and the calling relationship between the commands and the functions is established.
  • the system will query the command list according to the input command, and call its corresponding function to execute to complete the command.
  • the main system parses the first command line in the input cache of the main system to obtain the corresponding first command and first parameter. command, execute the first command, if the first command is a command corresponding to the subsystem, send the first parameter as a second command line to the corresponding slave system input buffer;
  • the second command line is parsed to obtain the corresponding second command and the second parameter, and if the second command is a command in the slave system command set of the slave system, the second command is executed. That is, the embodiment of the present application unifies the command processing methods of the master system and the slave system, and reduces the difference in processing commands of each system. In this way, the uniformity and consistency of multi-processor SOC chip testing can be guaranteed, thereby improving test efficiency. As well as reducing the incidence of test bugs.
  • an embodiment of the present application discloses a specific test method, which is applied to a multiprocessor SOC chip, where the multiprocessor SOC chip includes a master system and at least one slave system, and the method includes:
  • Step S21 parsing the first command line in the input cache of the main system by the main system to obtain the corresponding first command and the first parameter, if the first command is a command of the main system in the main system command set, The first command is executed, and if the first command is a command corresponding to the subsystem, the first parameter is sent to the corresponding slave system input buffer as a second command line.
  • Step S22 After executing the first command through the host system, write the corresponding first output information into the corresponding output buffer of the host system.
  • the main system may monitor whether the corresponding main system output buffer is currently in an idle state, and if so, write the first output information into the corresponding main system output buffer.
  • Step S23 Trigger the corresponding first interrupt signal through the interrupt triggering module of the main system, so as to call the interrupt service routine corresponding to the first interrupt signal, and process the first output information.
  • an interrupt service program corresponding to the first interrupt signal may be called to print the first output information to a terminal display interface for display.
  • Step S24 Parse the second command line through the slave system to obtain the corresponding second command and second parameter, if the second command is a command in the slave system command set of the slave system, execute the command. the second command.
  • Step S25 After executing the second command by the slave system, write the corresponding second output information into the corresponding output buffer of the slave system.
  • the slave system may monitor whether the corresponding slave system output cache is currently in an idle state, and if so, write the second output information into the corresponding slave system output cache.
  • Step S26 Trigger the second interrupt signal corresponding to the slave system in the master system through the interrupt trigger module of the slave system, so that the master system calls the interrupt service routine corresponding to the second interrupt signal to process the first interrupt signal. Second output information.
  • an interrupt service program corresponding to the second interrupt signal may be called to print the second output information to a terminal display interface for display.
  • the corresponding interrupt service routine can be called according to the priority of the interrupt signal to process the corresponding output information.
  • the embodiment of the present application can determine the interrupt resource allocated by the subsystem in the multiprocessor SOC chip in the interrupt system of the main system, that is, the ICC (Inter Chip Communication) interrupt signal.
  • the ICC interrupt number may be selected and used for each subsystem.
  • multiple ICC interrupt numbers may also be allocated to one subsystem in the interrupt system of the main system.
  • the main system and each subsystem if the information output of each system needs to have priority requirements, you can configure the corresponding priority level for the interrupt number of the respective system in the interrupt module of the host system, so as to achieve the respective priority. The priority of information output.
  • the master system input buffer, the slave system input buffer, the master system output buffer, and the slave system may be allocated in shared storage for the master system and the slave system in advance, respectively. output cache.
  • the master system input buffer, the slave system input buffer, the master system output buffer, and the slave system output buffer may be allocated based on consecutive spatial addresses. In this way, only one base address is needed for cache allocation and address adjustment is facilitated.
  • each CPU core (core) in the master system and the slave system can be allocated a corresponding output cache, and the output of each system information takes the core of the CPU in each system as a unit, and on any core, the execution of the command. Information and result information are written to the output cache corresponding to the core through the system where the core is located.
  • FIG. 4 is a specific architecture diagram of a multiprocessor SOC chip disclosed in an embodiment of the present application
  • the processors of the main system HOST and the subsystems SUB_A, SUB_B, and SUB_C are all 4-core CPUs.
  • shared RAM ie Random Access Memory, random access memory
  • the main system HOST and subsystems SUB_A, SUB_B, and SUB_C in this embodiment can use this shared RAM to implement the input buffer (output buffer) and output buffer (output buffer) of each system.
  • the main system and each subsystem are allocated A piece of RAM space, the input buffer of each system is used to receive and store the input command line. Generally, the command line does not exceed a few hundred bytes, so the allocated size is generally a few hundred bytes.
  • the CPU of each system is a 4-core CPU, so a piece of RAM space should be allocated for each core of the CPU in each system.
  • the output buffer of each system is used to store the output information of each core of the CPU of the system. Its size generally ranges from several hundred bytes to several Kbytes, and the size is jointly determined according to the actual shared RAM size and actual needs.
  • the main system and each subsystem will independently use the memory management method of their own system.
  • the memory cache consistency problem between each system must be considered. Therefore, the shared RAM address space needs to be configured in non-cacheable mode in each system to ensure the consistency of data between the systems, so as to ensure the correctness of the data exchanged between the systems.
  • FIG. 5a is a schematic diagram of a specific input buffer allocation disclosed in an embodiment of the present application.
  • FIG. 5b is a schematic diagram of a specific input buffer allocation disclosed in an embodiment of the present application.
  • Figure 5a and Figure 5b show the allocation of the input buffer and output buffer of each system in the shared RAM. In a specific implementation, it can be allocated to the continuous address space of the shared RAM, so as to adjust its address space position in the shared RAM in actual use.
  • FIG. 6 is a working flowchart of a specific information output system disclosed by an embodiment of the present application
  • FIG. 7 is a specific main system interrupt disclosed by an embodiment of the present application Process flow chart.
  • the main system and each subsystem will output the relevant information and final result information of the command execution, which are written into the main system and each subsystem by the main system and each subsystem respectively output buffer.
  • the output of each system information is based on the core of the CPU in each system, that is, each core is assigned an output buffer. On this core, the execution information and result information of the command will be written to its corresponding output by the system where the core is located. buffer.
  • the main system can call the printing function to print the information to the terminal and present it to the tester.
  • the system first checks whether the status of the output buffer of this core is idle. If the status is not idle, wait for the information in the output buffer to be processed by the main system. After completion, if the status is idle, the system first updates the status of the output buffer to non-idle, and then writes the information that needs to be output to the output buffer, and then triggers the system in the main system by operating the ICC module in the system.
  • the interrupt signal in the system is interrupted, after which the system continues to perform other services.
  • the main system receives the interrupt signal and enters the interrupt service routine corresponding to the interrupt signal.
  • the main system starts to process the information in the output buffer, calls the print function, and outputs the information to the terminal display system of the main system. superior. After processing, update the output buffer status to idle, and finally clear the interrupt information and exit the interrupt service routine, after which the main system continues to perform other services.
  • the embodiment of the present application allocates exclusive input buffers and output buffers to the main system of the multiprocessor SOC chip and each subsystem, which are used for command line input and information output, thereby reducing the need for each system to share a buffer.
  • the complexity of software development the command processing methods of the main system and each subsystem in the multi-processor SOC chip test system are unified, so that the command input and information output of the main system and each subsystem are consistent, thereby reducing the difference in processing commands of each system.
  • the adhesion of each system in the development of test cases is enhanced, the efficiency of test case development is improved, and the complexity of test case development is reduced.
  • the ICC interrupt resource of the multi-processor SOC chip is used to realize the processing request of the output message of each system in the main system, and it is not necessary to increase the hardware design of the chip to support this function.
  • testing method disclosed in the embodiments of the present application is not limited to be applied to a multi-processor chip, but can also be applied to a circuit system including multiple processors.
  • an embodiment of the present application discloses a multi-processor SOC chip, the multi-processor SOC chip includes a master system 11 and at least one slave system 12 , wherein,
  • the main system 11 is used to parse the first command line in the main system input cache to obtain the corresponding first command and the first parameter. If the first command is a command of the main system in the main system command set, then execute the first command, and if the first command is a command corresponding to the subsystem, send the first parameter as a second command line to the corresponding slave system input buffer;
  • the slave system 12 is used to parse the second command line to obtain the corresponding second command and second parameter. If the second command is a command in the slave system command set of the slave system, execute all the commands. the second command.
  • the main system parses the first command line in the input cache of the main system to obtain the corresponding first command and first parameter. command, execute the first command, if the first command is a command corresponding to the subsystem, send the first parameter as a second command line to the corresponding slave system input buffer;
  • the second command line is parsed to obtain the corresponding second command and the second parameter, and if the second command is a command in the slave system command set of the slave system, the second command is executed. That is, the embodiment of the present application unifies the command processing methods of the master system and the slave system, and reduces the difference in processing commands of each system. In this way, the uniformity and consistency of multi-processor SOC chip testing can be guaranteed, thereby improving test efficiency. As well as reducing the incidence of test bugs.
  • the main system 11 is further configured to write the corresponding first output information into the corresponding main system output buffer after executing the first command, and trigger the corresponding first interrupt signal through the interrupt trigger module of the main system , to call the interrupt service routine corresponding to the first interrupt signal to process the first output information.
  • the slave system 12 is further configured to write the corresponding second output information into the corresponding slave system output buffer after executing the second command, and trigger the interrupt trigger module in the master system through the interrupt trigger module of the slave system.
  • the second interrupt signal corresponding to the slave system so that the master system calls the interrupt service routine corresponding to the second interrupt signal to process the second output information.
  • the main system invokes the corresponding interrupt service routine according to the priority of the interrupt signal to process the corresponding output information.
  • the slave system is specifically configured to monitor whether the corresponding output cache of the slave system is currently in an idle state, and if so, write the second output information into the corresponding output cache of the slave system.
  • the main system is specifically configured to call an interrupt service program corresponding to the second interrupt signal, and print the second output information to a terminal display interface for display.
  • the main system is further configured to clear the main system input cache if the first command is not a command of the main system in the main system command set and is not a command corresponding to a subsystem.
  • the master system is further configured to clear the slave system input cache if the second command is not a command in the slave system command set.
  • the multiprocessor SOC chip also includes:
  • the shared storage 13 is used to allocate the master system input buffer, the slave system input buffer, the master system output buffer, and the slave system output buffer to the master system and the slave system.
  • a software module can be placed in random access memory (RAM), internal memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other in the technical field. in any other known form of storage medium.
  • RAM random access memory
  • ROM read only memory
  • electrically programmable ROM electrically erasable programmable ROM
  • registers hard disk, removable disk, CD-ROM, or any other in the technical field. in any other known form of storage medium.

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Abstract

本申请公开了一种测试方法及多处理器SOC芯片，包括：通过主系统解析主系统输入缓存中的第一命令行，以得到对应的第一命令和第一参数，若所述第一命令为主系统命令集中所述主系统的命令，则执行所述第一命令，若所述第一命令为子系统对应的命令，则将所述第一参数作为第二命令行发送至对应的从系统输入缓存；通过从系统解析所述第二命令行，以得到对应的第二命令和第二参数，若所述第二命令为所述从系统的从系统命令集中的命令，则执行所述第二命令。这样，能够保障多处理器SOC芯片测试的统一性和一致性，从而提升测试效率以及降低测试漏洞的出现率。

Description

一种测试方法及多处理器SOC芯片
本申请要求在2021年1月7日提交中国专利局、申请号为202110018480.4、发明名称为“一种测试方法及多处理器SOC芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及SOC芯片技术领域，特别涉及一种测试方法及多处理器SOC芯片。
背景技术
随着芯片技术的高速发展，芯片的复杂度也越来越高，之前由几颗芯片一起才能实现的功能，现在可以在一颗芯片上得以实现，这样导致在越来越多的SOC(即System On Chip，片上系统)芯片中，CPU(即Central Processing Unit，中央处理器)数量从之前的一个增加到当前的几个，几十个甚至更多。而此类多处理器SOC芯片的架构一般是由一个包括主CPU的主系统和其他多个包括子CPU的子系统组成。通常由于主系统和各个子系统所需要实现的功能不同，所以对CPU的性能要求也各不相同，所以在CPU IP(即Intellectual Property，一段具有特定电路功能的硬件描述语言程序)的选型上，主CPU和多个子CPU的架构也各不相同。这些CPU IP来自不同的CPU IP厂商的各系列CPU IP，比如ARM，Cadence，Synopsys等CPU IP厂商。而各个CPU IP厂商针对其CPU提供的配套IDE(Integrated Development Environment，集成开发环境)也大不相同。
在芯片开发过程中，测试是极为重要的一个环节，其保证了芯片设计的正确性。对于此类多处理器SOC芯片的测试任务，通常会按照各系统来划分，由不同的测试人员来负责主系统和其他子系统的测试。由于各系统的CPU架构的不同，所以一般情况下，各个系统所使用的测试用例开发环境也不同，一般都是基于CPU IP厂商所提供的IDE。不同的测试人员在不同的开发环境中开发测试用例，这样就有很大的可能性导致整个SOC芯片测试用例开发失去 了统一性和一致性，最终导致测试漏洞以及测试效率低下。
发明内容
有鉴于此，本申请的目的在于提供一种测试方法及多处理器SOC芯片，能够保障多处理器SOC芯片测试的统一性和一致性，从而提升测试效率以及降低测试漏洞的出现率。其具体方案如下：
第一方面，本申请公开了一种测试方法，应用于多处理器SOC芯片，所述多处理器SOC芯片包括主系统和至少一个从系统，所述方法包括：
通过所述主系统解析主系统输入缓存中的第一命令行，以得到对应的第一命令和第一参数，若所述第一命令为主系统命令集中所述主系统的命令，则执行所述第一命令，若所述第一命令为子系统对应的命令，则将所述第一参数作为第二命令行发送至对应的从系统输入缓存；
通过所述从系统解析所述第二命令行，以得到对应的第二命令和第二参数，若所述第二命令为所述从系统的从系统命令集中的命令，则执行所述第二命令。
可选的，所述方法还包括：
通过所述主系统在执行所述第一命令后，将相应的第一输出信息写入对应的主系统输出缓存；
通过所述主系统的中断触发模块触发对应的第一中断信号，以调用所述第一中断信号对应的中断服务程序，处理所述第一输出信息；
通过所述从系统在执行所述第二命令后，将相应的第二输出信息写入对应的从系统输出缓存；
通过所述从系统的中断触发模块触发所述主系统中该从系统对应的第二中断信号，以便所述主系统调用所述第二中断信号对应的中断服务程序，处理所述第二输出信息。
可选的，所述方法还包括：
根据中断信号的优先级调用对应的中断服务程序，处理对应的输出信息。
可选的，所述将相应的第二输出信息写入对应的从系统输出缓存之前，还包括：
通过所述从系统监测对应的所述从系统输出缓存当前是否为空闲状态，若是，则将所述第二输出信息写入对应的从系统输出缓存。
可选的，所述调用所述第二中断信号对应的中断服务程序，处理所述第二输出信息，包括：
调用所述第二中断信号对应的中断服务程序，将所述第二输出信息打印到终端显示界面进行显示。
可选的，所述方法还包括：
预先为所述主系统和所述从系统在共享存储中分别分配所述主系统输入缓存、所述从系统输入缓存、所述主系统输出缓存、所述从系统输出缓存。
可选的，所述方法还包括：
若所述第一命令不为所述主系统命令集中所述主系统的命令，且不为子系统对应的命令，则清空所述主系统输入缓存；
若所述第二命令不为所述从系统命令集中的命令，则清空所述从系统输入缓存。
第二方面，本申请公开了一种多处理器SOC芯片，所述多处理器SOC芯片包括主系统和至少一个从系统，其中，
所述主系统，用于解析主系统输入缓存中的第一命令行，以得到对应的第一命令和第一参数，若所述第一命令为主系统命令集中所述主系统的命令，则执行所述第一命令，若所述第一命令为子系统对应的命令，则将所述第一参数作为第二命令行发送至对应的从系统输入缓存；
所述从系统，用于解析所述第二命令行，以得到对应的第二命令和第二参数，若所述第二命令为所述从系统的从系统命令集中的命令，则执行所述第二命令。
可选的，所述主系统，还用于在执行所述第一命令后，将相应的第一输出信息写入对应的主系统输出缓存，通过所述主系统的中断触发模块触发对应的第一中断信号，以调用所述第一中断信号对应的中断服务程序，处理所述第一输出信息；
所述从系统，还用于在执行所述第二命令后，将相应的第二输出信息写入对应的从系统输出缓存，通过所述从系统的中断触发模块触发所述主系统中该从系统对应的第二中断信号，以便所述主系统调用所述第二中断信号对 应的中断服务程序，处理所述第二输出信息。
可选的，所述多处理器SOC芯片，还包括：
共享存储，用于为所述主系统和所述从系统分配所述主系统输入缓存、所述从系统输入缓存、所述主系统输出缓存、所述从系统输出缓存。
可见，本申请通过所述主系统解析主系统输入缓存中的第一命令行，以得到对应的第一命令和第一参数，若所述第一命令为主系统命令集中所述主系统的命令，则执行所述第一命令，若所述第一命令为子系统对应的命令，则将所述第一参数作为第二命令行发送至对应的从系统输入缓存；通过所述从系统解析所述第二命令行，以得到对应的第二命令和第二参数，若所述第二命令为所述从系统的从系统命令集中的命令，则执行所述第二命令。也即，本申请统一了主系统和从系统的命令处理方式，降低了各系统处理命令的差异性，这样，能够保障多处理器SOC芯片测试的统一性和一致性，从而提升测试效率以及降低测试漏洞的出现率。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本申请公开的一种测试方法流程图；
图2为本申请公开的一种具体的命令执行流程图；
图3为本申请公开的一种具体的测试方法流程图；
图4为本申请公开的一种具体的多处理器SOC芯片架构图；
图5a为本申请公开的一种具体的输入缓存分配示意图；
图5b为本申请公开的一种具体的输出缓存分配示意图；
图6为本申请公开的一种具体的信息输出系统工作流程图；
图7为本申请公开的一种具体的主系统中断处理流程图；
图8为本申请公开的一种多处理器SOC芯片结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在芯片开发过程中，测试是极为重要的一个环节，其保证了芯片设计的正确性。对于此类多处理器SOC芯片的测试任务，通常会按照各系统来划分，由不同的测试人员来负责主系统和其他子系统的测试。由于各系统的CPU架构的不同，所以一般情况下，各个系统所使用的测试用例开发环境也不同，一般都是基于CPU IP厂商所提供的IDE。不同的测试人员在不同的开发环境中开发测试用例，这样就有很大的可能性导致整个SOC芯片测试用例开发失去了统一性和一致性，最终导致测试漏洞以及测试效率低下。为此，本申请提供了一种SOC芯片测试方案，能够保障多处理器SOC芯片测试的统一性和一致性，从而提升测试效率以及降低测试漏洞的出现率。
参见图1所示，本申请实施例公开了一种测试方法，应用于多处理器SOC芯片，所述多处理器SOC芯片包括主系统和至少一个从系统，所述方法包括：
步骤S11：通过所述主系统解析主系统输入缓存中的第一命令行，以得到对应的第一命令和第一参数，若所述第一命令为主系统命令集中所述主系统的命令，则执行所述第一命令，若所述第一命令为子系统对应的命令，则将所述第一参数作为第二命令行发送至对应的从系统输入缓存。
在具体的实施方式中，可以基于从系统的名称对从系统的命令进行命名。例如，sub_a，sub_b，sub_c，添加至主系统命令集中，当主系统解析命令时，当命令名为sub_a,sub_b,sub_c时，主系统则将命令名之后的参数作为子系统的命令分发到子系统中去执行。
并且，若所述第一命令不为所述主系统命令集中所述主系统的命令，且不为子系统对应的命令，则清空所述主系统输入缓存。
具体的，当所述主系统的所述主系统输入缓存接收到输入的所述第一命令行，则通过预设命令解析函数，解析该第一命令行，得到对应的第一命令及其第一参数，主系统在所述主系统命令集中查询所述第一命令，若查询不 到，则清空主系统输入缓存，等待下一条命令行的输入，如果查询到，且不为以子系统名称命名的命令，则执行所述第一命令，执行完成后，清空所述主系统输入缓存，等待下一条命令行的输入，若为以子系统名称命名的命令，则所述第一参数作为第二命令行发送至对应的从系统输入缓存。
步骤S12：通过所述从系统解析所述第二命令行，以得到对应的第二命令和第二参数，若所述第二命令为所述从系统的从系统命令集中的命令，则执行所述第二命令。
在具体的实施方式中，若所述第二命令不为所述从系统命令集中的命令，则清空所述从系统输入缓存。
例如，参见图2所示，图2为本申请公开的一种具体的命令执行流程图。利用主系统和各子系统的input buffer(输入缓存)实现命令的输入，在主系统中实现一套命令处理机制，通过这套命令处理机制来执行主系统命令，并分发各子系统命令到各子系统执行。同时在各子系统中实现一套命令处理机制，用于执行从主系统分发过来的子系统命令。在主系统命令集中，为分发各子系统命令，建立以子系统名为命令名的命名方式。当主系统的input buffer接收到输入命令行时，通过命令解析函数，解析此命令行，并得到此命令行所表示的命令及其参数，在主系统的命令集中查询此命令，如果未查询到此命令，此命令即为未知命令，主系统则清空input buffer等待下一条命令行的输入，如果查询到此命令，且不为子系统名字命名的命令则执行此命令，当命令执行完成后，清空input buffer并等待下一条命令行的输入。而对于以子系统名字命名的命令，主系统则将此命令之后的参数作为子系统的命令行发送到相应的子系统的input buffer中去，而子系统命令解析流程和主系统命令解析流程一致，子系统通过命令解析函数，解析此命令行，并得到此命令行表示的命令及其参数，在子系统的命令集中查询此命令，如果未查询到此命令，此命令即为未知命令，子系统则清空input buffer等待下一条命令行的输入，如果查询到此命令，则执行此命令，当命令执行完成后，清空input buffer并等待下一条命令行的输入。
也即，本申请实施例可以建立主系统和各子系统的命令处理机制，即主系统要支持哪些命令，各子系统要支持哪些命令，各系统如何处理这些命令。在主系统中建立主系统的命令列表，在各子系统中建立各自的命令列表，并 且创建这些命令所要实现功能的函数，并在命令和函数之间建立调用关系。当输入某命令时，系统会根据所输入的命令，查询命令列表，调用其相对应的函数执行，完成此命令。而这些命令集以及其所要实现的功能，基于多处理器SOC芯片测试需求来确定。
可见，本申请实施例通过所述主系统解析主系统输入缓存中的第一命令行，以得到对应的第一命令和第一参数，若所述第一命令为主系统命令集中所述主系统的命令，则执行所述第一命令，若所述第一命令为子系统对应的命令，则将所述第一参数作为第二命令行发送至对应的从系统输入缓存；通过所述从系统解析所述第二命令行，以得到对应的第二命令和第二参数，若所述第二命令为所述从系统的从系统命令集中的命令，则执行所述第二命令。也即，本申请实施例统一了主系统和从系统的命令处理方式，降低了各系统处理命令的差异性，这样，能够保障多处理器SOC芯片测试的统一性和一致性，从而提升测试效率以及降低测试漏洞的出现率。
参见图3所示，本申请实施例公开了一种具体的测试方法，应用于多处理器SOC芯片，所述多处理器SOC芯片包括主系统和至少一个从系统，所述方法包括：
步骤S21：通过所述主系统解析主系统输入缓存中的第一命令行，以得到对应的第一命令和第一参数，若所述第一命令为主系统命令集中所述主系统的命令，则执行所述第一命令，若所述第一命令为子系统对应的命令，则将所述第一参数作为第二命令行发送至对应的从系统输入缓存。
步骤S22：通过所述主系统在执行所述第一命令后，将相应的第一输出信息写入对应的主系统输出缓存。
在具体的实施方式中，本实施例可以通过所述主系统监测对应的所述主系统输出缓存当前是否为空闲状态，若是，则将所述第一输出信息写入对应的主系统输出缓存。
步骤S23：通过所述主系统的中断触发模块触发对应的第一中断信号，以调用所述第一中断信号对应的中断服务程序，处理所述第一输出信息。
在具体的实施方式中，可以调用所述第一中断信号对应的中断服务程序，将所述第一输出信息打印到终端显示界面进行显示。
步骤S24：通过所述从系统解析所述第二命令行，以得到对应的第二命令和第二参数，若所述第二命令为所述从系统的从系统命令集中的命令，则执行所述第二命令。
步骤S25：通过所述从系统在执行所述第二命令后，将相应的第二输出信息写入对应的从系统输出缓存。
在具体的实施方式中，可以通过所述从系统监测对应的所述从系统输出缓存当前是否为空闲状态，若是，则将所述第二输出信息写入对应的从系统输出缓存。
步骤S26：通过所述从系统的中断触发模块触发所述主系统中该从系统对应的第二中断信号，以便所述主系统调用所述第二中断信号对应的中断服务程序，处理所述第二输出信息。
在具体的实施方式中，可以调用所述第二中断信号对应的中断服务程序，将所述第二输出信息打印到终端显示界面进行显示。
进一步的，本实施例可以根据中断信号的优先级调用对应的中断服务程序，处理对应的输出信息。
也即，本申请实施例可以确定多处理器SOC芯片中的子系统在主系统的中断系统中所分配的中断资源，即ICC(即Inter Chip Communication)中断信号。本实施例中，可以为每个子系统选取一个ICC中断号来使用，在另外一些实施例中，也可以一个子系统在主系统的中断系统中分配多个ICC中断号。并且，对于主系统和各子系统，如果各系统的信息输出需要具有优先级的需求，则可以通过在主机系统的中断模块中，为各自系统的中断号配置相应的优先级别，以此达到各自信息输出的优先级。
在具体的实施方式中，可以预先为所述主系统和所述从系统在共享存储中分别分配所述主系统输入缓存、所述从系统输入缓存、所述主系统输出缓存、所述从系统输出缓存。
并且，可以基于连续的空间地址分配所述主系统输入缓存、所述从系统输入缓存、所述主系统输出缓存、所述从系统输出缓存。这样，只需利用一个基地址即可实现缓存分配，并且便于地址调整。
其中，本实施例可以为主系统和从系统中每个CPU core(核心)均分配对应的输出缓存，各系统信息的输出以各系统中CPU的core为单位，在任一core 上，命令的执行信息和结果信息通过该core所在的系统写入该core对应的输出缓存。
例如，参见图4所示，图4为本申请实施例公开的一种具体的多处理器SOC芯片架构图，主系统HOST和子系统SUB_A,SUB_B,SUB_C的处理器均为4核CPU。其中，共享RAM(即Random Access Memory，随机存储器)能够同时被主系统和所有子系统访问，主要用于各个系统之间的通信。本实施例中的主系统HOST和子系统SUB_A,SUB_B,SUB_C可以利用此共享RAM来实现各个系统的input buffer(输出缓存)和output buffer(输出缓存)，对于input buffer，主系统和个子系统各分配一块RAM空间，各个系统的input buffer用于接收储存输入的命令行，一般命令行不会超过几百个字节，所以其分配的大小一般为几百个字节。对于output buffer，各系统的CPU均为4核CPU，所以要为每个系统中CPU的每个核分配一块RAM空间，各系统的output buffer用于储存本系统CPU的每个核的输出信息，其大小一般为几百个字节到几K字节不等，大小根据实际的共享RAM大小以及实际需求共同确定。需要指出的是，多处理器SOC芯片中，主系统和各子系统都会独自使用各自系统的memory管理方式，对于各系统之间的数据交互，必须要考虑到各系统间memory cache一致性问题，因此共享RAM地址空间，在各个系统中需要配置为non-cacheable模式，以确保各系统之间数据的一致性，这样才保证各系统交互数据的正确性。
例如，参见图5a所示，图5a为本申请实施例公开的一种具体的输入缓存分配示意图。参见图5b所示，图5b为本申请实施例公开的一种具体的输入缓存分配示意图。图5a和图5b为各系统的input buffer和output buffer在共享RAM中的分配。在具体的实施方式中，可以分配于共享RAM的连续地址空间，便于在实际使用中调整其在共享RAM中的地址空间位置。
例如，参见图6所示，图6为本申请实施例公开的一种具体的信息输出系统工作流程图，参见图7所示，图7为本申请实施例公开的一种具体的主系统中断处理流程图。在命令执行过程中以及命令执行完成后，主系统和各子系统会有命令执行的相关信息和最终结果信息要输出，这些信息由主系统和各子系统分别写入主系统和各子系统的output buffer。各系统信息的输出以各系统中CPU的core为单位，即每个core分配有一个output buffer，在此core上，命令的执行信息和结果信息会由此core所在的系统写入其对应的output buffer。 所有output buffer的信息最终由主系统处理并输出。具体的，可以由主系统调用打印函数把信息打印到终端，呈现给测试人员。当某个系统中的CPU的某一个core需要输出信息时，此系统首先检查此core的output buffer的状态是否为空闲状态，如果状态为非空闲，则等待此output buffer中的信息由主系统处理完毕，如果状态为空闲，则此系统首先更新此output buffer的状态为非空闲，然后把需要输出的信息写入到此output buffer，再通过操作此系统中的ICC模块触发此系统在主系统的中断系统中的中断信号，之后此系统继续执行其他业务。主系统收到中断信号，并进入此中断信号对应的中断服务程序，在此中断服务程序中，主系统开始处理output buffer中的信息，调用打印函数，把这些信息输出到主系统的终端显示系统上。处理完毕后，更新此output buffer状态为空闲，最后清除中断信息并退出中断服务程序，之后主系统继续执行其他业务。
需要指出的是，本申请实施例为多处理器SOC芯片主系统和各子系统分配独占的输入缓存和输出缓存，用于命令行的输入和信息的输出，从而降低了各系统共享一个缓存所带来的软件开发的复杂度。并且，统一了多处理器SOC芯片测试系统中主系统和各子系统的命令处理方式，使主系统和各子系统的命令输入和信息输出一致化，从而降低了各系统处理命令的差异性，增强了各系统在测试用例开发的粘合度，提高了测试用例开发的效率，降低了测试用例开发的复杂度。进一步的，利用多处理器SOC芯片的ICC中断资源来实现各系统的输出消息在主系统中的处理请求，而不需要增加芯片的硬件设计来支持此功能。
另外，本申请实施例公开的测试方法不限于应用于多处理器芯片，其也可以应用于包含多个处理器的电路系统。
参见图8所示，本申请实施例公开了一种多处理器SOC芯片，所述多处理器SOC芯片包括主系统11和至少一个从系统12，其中，
所述主系统11，用于解析主系统输入缓存中的第一命令行，以得到对应的第一命令和第一参数，若所述第一命令为主系统命令集中所述主系统的命令，则执行所述第一命令，若所述第一命令为子系统对应的命令，则将所述第一参数作为第二命令行发送至对应的从系统输入缓存；
所述从系统12，用于解析所述第二命令行，以得到对应的第二命令和第二参数，若所述第二命令为所述从系统的从系统命令集中的命令，则执行所述第二命令。
可见，本申请实施例通过所述主系统解析主系统输入缓存中的第一命令行，以得到对应的第一命令和第一参数，若所述第一命令为主系统命令集中所述主系统的命令，则执行所述第一命令，若所述第一命令为子系统对应的命令，则将所述第一参数作为第二命令行发送至对应的从系统输入缓存；通过所述从系统解析所述第二命令行，以得到对应的第二命令和第二参数，若所述第二命令为所述从系统的从系统命令集中的命令，则执行所述第二命令。也即，本申请实施例统一了主系统和从系统的命令处理方式，降低了各系统处理命令的差异性，这样，能够保障多处理器SOC芯片测试的统一性和一致性，从而提升测试效率以及降低测试漏洞的出现率。
所述主系统11，还用于在执行所述第一命令后，将相应的第一输出信息写入对应的主系统输出缓存，通过所述主系统的中断触发模块触发对应的第一中断信号，以调用所述第一中断信号对应的中断服务程序，处理所述第一输出信息。
所述从系统12，还用于在执行所述第二命令后，将相应的第二输出信息写入对应的从系统输出缓存，通过所述从系统的中断触发模块触发所述主系统中该从系统对应的第二中断信号，以便所述主系统调用所述第二中断信号对应的中断服务程序，处理所述第二输出信息。
在具体的实施方式中，所述主系统根据中断信号的优先级调用对应的中断服务程序，处理对应的输出信息。
并且，所述从系统，具体用于监测对应的所述从系统输出缓存当前是否为空闲状态，若是，则将所述第二输出信息写入对应的从系统输出缓存。
所述主系统，具体用于调用所述第二中断信号对应的中断服务程序，将所述第二输出信息打印到终端显示界面进行显示。
并且，所述主系统，还用于若所述第一命令不为所述主系统命令集中所述主系统的命令，且不为子系统对应的命令，则清空所述主系统输入缓存。
所述主系统，还用于若所述第二命令不为所述从系统命令集中的命令，则清空所述从系统输入缓存。
进一步的，所述多处理器SOC芯片，还包括：
共享存储13，用于为所述主系统和所述从系统分配所述主系统输入缓存、所述从系统输入缓存、所述主系统输出缓存、所述从系统输出缓存。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似部分互相参见即可。结合本文中所公开的实施例描述的方法或算法的步骤可以直接用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的存储介质中。
以上对本申请所提供的一种测试方法及多处理器SOC芯片进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (10)

  1. 一种测试方法，其特征在于，应用于多处理器SOC芯片，所述多处理器SOC芯片包括主系统和至少一个从系统，所述方法包括：
    通过所述主系统解析主系统输入缓存中的第一命令行，以得到对应的第一命令和第一参数，若所述第一命令为主系统命令集中所述主系统的命令，则执行所述第一命令，若所述第一命令为子系统对应的命令，则将所述第一参数作为第二命令行发送至对应的从系统输入缓存；
    通过所述从系统解析所述第二命令行，以得到对应的第二命令和第二参数，若所述第二命令为所述从系统的从系统命令集中的命令，则执行所述第二命令。
  2. 根据权利要求1所述的测试方法，其特征在于，所述方法还包括：
    通过所述主系统在执行所述第一命令后，将相应的第一输出信息写入对应的主系统输出缓存；
    通过所述主系统的中断触发模块触发对应的第一中断信号，以调用所述第一中断信号对应的中断服务程序，处理所述第一输出信息；
    通过所述从系统在执行所述第二命令后，将相应的第二输出信息写入对应的从系统输出缓存；
    通过所述从系统的中断触发模块触发所述主系统中该从系统对应的第二中断信号，以便所述主系统调用所述第二中断信号对应的中断服务程序，处理所述第二输出信息。
  3. 根据权利要求2所述的测试方法，其特征在于，所述方法还包括：
    根据中断信号的优先级调用对应的中断服务程序，处理对应的输出信息。
  4. 根据权利要求2所述的测试方法，其特征在于，所述将相应的第二输出信息写入对应的从系统输出缓存之前，还包括：
    通过所述从系统监测对应的所述从系统输出缓存当前是否为空闲状态，若是，则将所述第二输出信息写入对应的从系统输出缓存。
  5. 根据权利要求3所述的测试方法，其特征在于，所述调用所述第二中断信号对应的中断服务程序，处理所述第二输出信息，包括：
    调用所述第二中断信号对应的中断服务程序，将所述第二输出信息打印到终端显示界面进行显示。
  6. 根据权利要求2所述的测试方法，其特征在于，所述方法还包括：
    预先为所述主系统和所述从系统在共享存储中分别分配所述主系统输入缓存、所述从系统输入缓存、所述主系统输出缓存、所述从系统输出缓存。
  7. 根据权利要求1至6任一项所述的测试方法，其特征在于，所述方法还包括：
    若所述第一命令不为所述主系统命令集中所述主系统的命令，且不为子系统对应的命令，则清空所述主系统输入缓存；
    若所述第二命令不为所述从系统命令集中的命令，则清空所述从系统输入缓存。
  8. 一种多处理器SOC芯片，其特征在于，所述多处理器SOC芯片包括主系统和至少一个从系统，其中，
    所述主系统，用于解析主系统输入缓存中的第一命令行，以得到对应的第一命令和第一参数，若所述第一命令为主系统命令集中所述主系统的命令，则执行所述第一命令，若所述第一命令为子系统对应的命令，则将所述第一参数作为第二命令行发送至对应的从系统输入缓存；
    所述从系统，用于解析所述第二命令行，以得到对应的第二命令和第二参数，若所述第二命令为所述从系统的从系统命令集中的命令，则执行所述第二命令。
  9. 根据权利要求8所述的多处理器SOC芯片，其特征在于，
    所述主系统，还用于在执行所述第一命令后，将相应的第一输出信息写入对应的主系统输出缓存，通过所述主系统的中断触发模块触发对应的第一中断信号，以调用所述第一中断信号对应的中断服务程序，处理所述第一输出信息；
    所述从系统，还用于在执行所述第二命令后，将相应的第二输出信息写入对应的从系统输出缓存，通过所述从系统的中断触发模块触发所述主系统中该从系统对应的第二中断信号，以便所述主系统调用所述第二中断信号对应的中断服务程序，处理所述第二输出信息。
  10. 根据权利要求9所述的多处理器SOC芯片，其特征在于，还包括：
    共享存储，用于为所述主系统和所述从系统分配所述主系统输入缓存、所述从系统输入缓存、所述主系统输出缓存、所述从系统输出缓存。
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