WO2022145092A1 - Electronic control device and method for diagnosing vehicle-mounted device - Google Patents

Electronic control device and method for diagnosing vehicle-mounted device Download PDF

Info

Publication number
WO2022145092A1
WO2022145092A1 PCT/JP2021/033337 JP2021033337W WO2022145092A1 WO 2022145092 A1 WO2022145092 A1 WO 2022145092A1 JP 2021033337 W JP2021033337 W JP 2021033337W WO 2022145092 A1 WO2022145092 A1 WO 2022145092A1
Authority
WO
WIPO (PCT)
Prior art keywords
test
electronic control
seed value
control device
vehicle
Prior art date
Application number
PCT/JP2021/033337
Other languages
French (fr)
Japanese (ja)
Inventor
貴大 小池
純之 荒田
Original Assignee
日立Astemo株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立Astemo株式会社 filed Critical 日立Astemo株式会社
Priority to JP2022572910A priority Critical patent/JPWO2022145092A1/ja
Publication of WO2022145092A1 publication Critical patent/WO2022145092A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

Definitions

  • the present invention relates to the configuration of an electronic control device and its control, and particularly relates to a technique effective for being applied to an electronic control device having an FPGA random test function.
  • Random tests are used as one of the test methods for FPGA (Field Programmable Gate Array) applicable products in the field of autonomous driving in in-vehicle semiconductor devices. It is known that a random test using a random number can be executed with a random and large number of test patterns by using a TPG (test pattern generator: Test Pattern Generator) equipped with a pseudo-random number generator.
  • TPG test pattern generator: Test Pattern Generator
  • Patent Document 1 proposes a pseudo-random number generator having difficulty in reproduction by combining signals having different periodicities.
  • Random test also has the problem that it is difficult to identify the error location.
  • an object of the present invention is an electronic control device equipped with an FPGA, a highly reliable electronic control device capable of shortening the random test time of the FPGA, and easily identifying an error location, and an in-vehicle use using the electronic control device.
  • the purpose is to provide a diagnostic method for the device.
  • the present invention includes a pseudo-random number generator and a seed value change timing generator, and the seed value change timing generator includes a counter circuit for counting the number of test steps and the counter. It is characterized by having a seed value storage unit that stores the count value of the circuit and the seed value for rewriting the pseudo-random number generator.
  • the present invention also includes an in-vehicle device including (a) a step of counting the number of test steps, and (b) a step of comparing the count value counted in the step (a) with the seed value change count value stored in advance. It is a diagnostic method of.
  • a highly reliable electronic control device capable of shortening the random test time of the FPGA and easily identifying an error location, and an in-vehicle device using the electronic control device.
  • a diagnostic method can be realized.
  • ADAS advanced driver assistance system
  • AD automatic driving
  • FIGS. 1 to 4 A diagnostic method of an electronic control device according to a first embodiment of the present invention and an in-vehicle device using the electronic control device will be described with reference to FIGS. 1 to 4.
  • FIG. 1 is a diagram showing a design flow of an FPGA to which the present invention is applied.
  • step S101 the FPGA logic design is performed in step S101, and when it is completed, the process proceeds to step S102 to perform operation verification and design of the present invention.
  • step S102 a simulation using pseudo-random numbers is performed in the logic designed in step S101. With reference to the test coverage obtained there, the design of the present invention described later is performed.
  • step S102 When the operation verification and the design of the present invention are completed in step S102, the process proceeds to step S103, and the test logic composed of the TPG, the design logic, and the test discrimination circuit of the present invention described later is written in the FPGA. The details of the test logic will be described with reference to FIG.
  • step S104 a random test using the test logic is executed.
  • FIG. 2 is a test logic diagram including the present invention designed in step S102 of FIG.
  • the test pattern generator (TPG) 101 includes a seed value change timing generator 102 and a pseudo-random number generator 105.
  • the seed value change timing generator 102 includes a counter circuit 103 and a seed value storage unit 104.
  • the count value of the counter circuit 103 is input to the seed value storage unit 104, and the seed value of the pseudo-random number generator 105 is rewritten according to the count value.
  • the pseudo-random number generator 105 generates a test pattern according to the seed value and inputs it to the test target logic 106.
  • the output signal of the test target logic 106 is input to the test determination circuit 107, and when the test fails there, an error flag is output to the seed value change timing generator 102.
  • the seed value change timing generator 102 detects an error flag, it notifies the error information including the count value at that time.
  • FIG. 3 is a diagram showing a TPG design example in step S102 of FIG.
  • step S102 the seed value change count value to be stored in the seed value storage unit 104 and the rewrite seed value are determined.
  • a random test is executed using a pseudo-random number generated by a conventional TPG, an unnecessary test pattern that does not increase the test coverage during the test execution is generated, so that the test time increases accordingly.
  • the number of test steps is counted by the counter circuit 103, and the seed value of the pseudo-random number generator 105 is effective when the count values (C 0 ) to (Cn) generate unnecessary test patterns.
  • the seed value change count value and the rewrite seed value of the seed value storage unit 104 include count values (C 0 ) to (C n ) and seed values (X: X 0 to X n ) to (Y: Y 0 to). Y n ) is stored.
  • the seed value storage unit 104 for example, a function of storing the number of test steps in which an unnecessary test pattern is generated as a count value of the counter circuit 103, a function of storing a seed value rewritable into a test pattern effective for the test, a function of storing the seed value. It is provided with a function of storing a rewritable seed value in a test pattern that increases test coverage, a function of storing the number of test steps at which the test coverage increase rate of the test target logic becomes 0, and the like as a count value of the counter circuit 103.
  • FIG. 4 is a diagram showing a test flow of FPGA to which the present invention is applied. The operation of the TPG 101 of FIG. 2 will be described with reference to FIG.
  • step S201 the count value of the counter circuit 103 of the seed value change timing generator 102 is incremented, and the process proceeds to step S202.
  • step S202 it is confirmed whether the count value matches the seed value change count values (C 0 ) to (C n ) stored in the seed value storage unit 104. If they match, the process proceeds to step S203, the seed value of the pseudo-random number generator 105 is rewritten to the rewritten seed value, the test pattern is rewritten, and the process proceeds to step S205. On the other hand, if they are different, the process proceeds to step S204, a test pattern is generated under the same seed value condition without rewriting the seed value, and the process proceeds to step S205.
  • step S205 if the seed value change timing generator 102 does not detect the error flag output when the test fails, the process returns to step S201. On the other hand, when the seed value change timing generator 102 detects the error flag, the process proceeds to step S206, the operation of the TPG 101 is stopped, and the error information including the count value at that time is notified.
  • FIGS. 1, 4 and 5 to 8 A diagnostic method of an electronic control device according to a second embodiment of the present invention and an in-vehicle device using the electronic control device will be described with reference to FIGS. 1, 4 and 5 to 8.
  • FIG. 5 to 8 are diagrams for explaining an example of the design of the present invention in step S102 of FIG.
  • FIG. 5 is a diagram showing an example of the logic to be tested, and the signals A, B, C, and D are input, and the “0” and “1” inversions of the nodes w, x, y, and z are set as test items. The details of the test contents will be described with reference to FIGS. 6 and 7.
  • FIG. 6 is a diagram showing an example of a timing chart of a conventional random test before the application of the present invention in the logic of FIG.
  • test steps 7 to 14 are unnecessary test patterns that do not increase the test coverage. Therefore, the test time increases by the amount of unnecessary test patterns, and 16 test steps are required to complete the test.
  • FIG. 7 is a timing chart of a random test when the present invention is applied in the logic of FIG.
  • the inversion test of "0" ⁇ "1" of the node z can be performed. Therefore, unnecessary test patterns are reduced, and the test is completed in test step 8. Comparing the test completion times of FIGS. 6 and 7, the test time is shortened by 50% before and after the application of the present invention.
  • FIG. 8 is a test logic diagram including the present invention designed in step S102 of FIG. 1, and shows an example of executing the random test of FIG. 7.
  • the TPG 201 is composed of a seed value change timing generator 202 and a pseudo-random number generator 205, and has the same functions as the seed value change timing generator 102 and the pseudo-random number generator 105 in FIG.
  • the seed value change timing generator 202 is composed of a counter circuit 203 and a seed value storage unit 204.
  • the seed value storage unit 204 stores "7" in the seed value change count value and "1110" in the rewrite seed value.
  • the test target logic 206 is the logic shown in FIG.
  • the test determination circuit 207 has the same function as the test determination circuit 107 of FIG.
  • the TPG 201 stops operating and error information including the count value 7. Notify. Since the count value 7 is included in the error information, it is possible to determine that an error has occurred when the node z is inverted from “0” to “1”.
  • the present invention is effective in identifying the location where an error occurs in the logic to be tested.
  • FIG. 9 is a diagram showing an example when an electronic control device to which the present invention is applied is mounted on a vehicle.
  • the vehicle 301 is equipped with a test logic 302 and an in-vehicle display device 303 including the present invention having the same configuration as that of FIG.
  • the in-vehicle display device 303 includes a control unit 304 and a display panel 305 such as an instrument panel.
  • in-vehicle diagnosis diagnosis of in-vehicle device
  • in-vehicle device diagnosis of in-vehicle device
  • the test time can be shortened and it can be applied to in-vehicle diagnosis.
  • the test logic 302 notifies the control unit 304 of the vehicle-mounted display device 303 of the error information including the count value when the error occurs.
  • the control unit 304 receives the error information from the test logic 302, and outputs a control signal (vehicle-mounted diagnosis result) according to the count value included therein to the display panel 305. As a result, it is possible to display the error content on the display panel.
  • the pseudo-random number generator 105 is the number of test steps (count values) in which unnecessary test patterns are generated. By rewriting the seed value of, 205, unnecessary test patterns can be reduced and the test time can be shortened.
  • the test pattern in which the test fails is determined by notifying the error information including the count value of the counter circuit at that time. , It is possible to identify the error location.
  • the present invention is not limited to the above-described embodiment, but includes various modifications.
  • the above embodiments have been described in detail to aid in understanding of the present invention and are not necessarily limited to those comprising all of the described configurations.
  • it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Provided is a highly reliable, FPGA-mounted electronic control device in which FPGA random test times can be shortened and an error location can be easily identified. The present invention is provided with a pseudo-random number generator and a seed-value modification timing generator, and is characterized in that the seed-value modification timing generator has a counter circuit for counting the number of test steps and a seed-value storage unit for storing count values of the counter circuit and seed values with which rewriting by the pseudo-random number generator is carried out.

Description

電子制御装置、車載装置の診断方法Diagnostic method for electronic control devices and in-vehicle devices
　本発明は、電子制御装置の構成とその制御に係り、特に、ＦＰＧＡのランダムテスト機能を有する電子制御装置に適用して有効な技術に関する。 The present invention relates to the configuration of an electronic control device and its control, and particularly relates to a technique effective for being applied to an electronic control device having an FPGA random test function.
　車載用半導体装置において、自動運転分野のＦＰＧＡ（Ｆｉｅｌｄ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）適用製品のテスト手法の１つとしてランダムテストを採用している。乱数を使ったランダムテストは、疑似乱数生成器を備えたＴＰＧ（テストパターン生成器：Ｔｅｓｔ　Ｐａｔｔｅｒｎ　Ｇｅｎｅｒａｔｏｒ）を用いて、無作為かつ大量のテストパターンでテストを実行できることが知られている。 Random tests are used as one of the test methods for FPGA (Field Programmable Gate Array) applicable products in the field of autonomous driving in in-vehicle semiconductor devices. It is known that a random test using a random number can be executed with a random and large number of test patterns by using a TPG (test pattern generator: Test Pattern Generator) equipped with a pseudo-random number generator.
　本技術分野の背景技術として、例えば、特許文献１のような技術がある。特許文献１では、異なる周期性を持つ信号を組み合わせることで、再現困難性を持つ疑似乱数生成器が提案されている。 As a background technique in this technical field, for example, there is a technique such as Patent Document 1. Patent Document 1 proposes a pseudo-random number generator having difficulty in reproduction by combining signals having different periodicities.
特開２００９－３４９５号公報Japanese Unexamined Patent Publication No. 2009-3495
　しかしながら、乱数を使ったランダムテストでは、不要なテストパターンが生成されることにより、テストの途中でテスト対象論理の活性化率が下がり、テストカバレッジの増加率が減少する。そのため、テストカバレッジを十分に得るためにはテスト時間が大きくなり、テストコストが増大するという課題がある。 However, in the random test using random numbers, the activation rate of the logic to be tested decreases in the middle of the test due to the generation of unnecessary test patterns, and the increase rate of test coverage decreases. Therefore, in order to obtain sufficient test coverage, there is a problem that the test time becomes long and the test cost increases.
　また、ランダムテストは、エラー箇所の特定が困難であるという課題もある。 Random test also has the problem that it is difficult to identify the error location.
　そこで、本発明の目的は、ＦＰＧＡを搭載する電子制御装置において、ＦＰＧＡのランダムテストの時間短縮が可能であるとともに、エラー箇所の特定が容易な信頼性の高い電子制御装置及びそれを用いた車載装置の診断方法を提供することにある。 Therefore, an object of the present invention is an electronic control device equipped with an FPGA, a highly reliable electronic control device capable of shortening the random test time of the FPGA, and easily identifying an error location, and an in-vehicle use using the electronic control device. The purpose is to provide a diagnostic method for the device.
　上記課題を解決するために、本発明は、疑似乱数生成器と、シード値変更タイミング生成器と、を備え、前記シード値変更タイミング生成器は、テストステップ数をカウントするカウンタ回路と、前記カウンタ回路のカウント値と前記疑似乱数生成器の書き換えを行うシード値を格納したシード値格納部と、を有することを特徴とする。 In order to solve the above problems, the present invention includes a pseudo-random number generator and a seed value change timing generator, and the seed value change timing generator includes a counter circuit for counting the number of test steps and the counter. It is characterized by having a seed value storage unit that stores the count value of the circuit and the seed value for rewriting the pseudo-random number generator.
　また、本発明は、（ａ）テストステップ数をカウントするステップ、（ｂ）前記（ａ）ステップにおいてカウントしたカウント値と、予め格納されたシード値変更カウント値を比較するステップ、を含む車載装置の診断方法である。 The present invention also includes an in-vehicle device including (a) a step of counting the number of test steps, and (b) a step of comparing the count value counted in the step (a) with the seed value change count value stored in advance. It is a diagnostic method of.
　本発明によれば、ＦＰＧＡを搭載する電子制御装置において、ＦＰＧＡのランダムテストの時間短縮が可能であるとともに、エラー箇所の特定が容易な信頼性の高い電子制御装置及びそれを用いた車載装置の診断方法を実現することができる。 According to the present invention, in an electronic control device equipped with an FPGA, a highly reliable electronic control device capable of shortening the random test time of the FPGA and easily identifying an error location, and an in-vehicle device using the electronic control device. A diagnostic method can be realized.
　これにより、ＡＤＡＳ（先進運転支援システム）やＡＤ（自動運転）の高性能化及び信頼性向上に寄与できる。 This can contribute to higher performance and reliability of ADAS (advanced driver assistance system) and AD (automatic driving).
　上記した以外の課題、構成及び効果は、以下の実施形態の説明により明らかにされる。 Issues, configurations and effects other than those described above will be clarified by the explanation of the following embodiments.
本発明を適用したＦＰＧＡの設計フローを示す図である。It is a figure which shows the design flow of FPGA to which this invention was applied. 本発明の実施例１に係るＦＰＧＡのテスト論理の構成図である。It is a block diagram of the test logic of FPGA which concerns on Example 1 of this invention. 本発明の実施例１に係るＴＰＧの設計例を示す図である。It is a figure which shows the design example of the TPG which concerns on Example 1 of this invention. 本発明を適用したＦＰＧＡのテストフローを示す図である。It is a figure which shows the test flow of FPGA to which this invention was applied. 本発明の実施例２に係るテスト対象論理を示す図である。It is a figure which shows the test object logic which concerns on Example 2 of this invention. 図５の論理において、従来のテストを実施した際のタイミングチャートである。In the logic of FIG. 5, it is a timing chart when a conventional test is carried out. 図５の論理において、本発明によるテストを実施した際のタイミングチャートである。In the logic of FIG. 5, it is a timing chart when the test according to the present invention is carried out. 本発明の実施例２に係るＦＰＧＡのテスト論理の構成図である。It is a block diagram of the test logic of FPGA which concerns on Example 2 of this invention. 本発明の実施例３に係る車両の概略構成を示す図である。It is a figure which shows the schematic structure of the vehicle which concerns on Example 3 of this invention.
　以下、図面を用いて本発明の実施例を説明する。なお、各図面において同一の構成については同一の符号を付し、重複する部分についてはその詳細な説明は省略する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, the same components are designated by the same reference numerals, and the detailed description of the overlapping portions will be omitted.
　また、説明をより明確にするため、図面は実際の態様に比べて模式的に表される場合があるが、あくまで一例であって、本発明の解釈を限定するものではない。 Further, in order to clarify the explanation, the drawings may be represented schematically as compared with the actual embodiment, but this is merely an example and does not limit the interpretation of the present invention.
　図１から図４を参照して、本発明の実施例１に係る電子制御装置とそれを用いた車載装置の診断方法について説明する。 A diagnostic method of an electronic control device according to a first embodiment of the present invention and an in-vehicle device using the electronic control device will be described with reference to FIGS. 1 to 4.
　図１は、本発明を適用したＦＰＧＡの設計フローを示す図である。 FIG. 1 is a diagram showing a design flow of an FPGA to which the present invention is applied.
　初めに、ステップＳ１０１でＦＰＧＡ論理設計を行い、それが完了するとステップＳ１０２に進み、動作検証と本発明の設計を行う。 First, the FPGA logic design is performed in step S101, and when it is completed, the process proceeds to step S102 to perform operation verification and design of the present invention.
　ステップＳ１０２では、ステップＳ１０１で設計した論理に疑似乱数を用いたシミュレーションを実施する。そこで得られたテストカバレッジを参照し、後述する本発明の設計を行う。 In step S102, a simulation using pseudo-random numbers is performed in the logic designed in step S101. With reference to the test coverage obtained there, the design of the present invention described later is performed.
　ステップＳ１０２において、動作検証及び本発明の設計を完了すると、ステップＳ１０３に進み、後述する本発明のＴＰＧ、設計論理、テスト判別回路で構成されているテスト論理をＦＰＧＡに書き込む。テスト論理詳細については図２を用いて説明する。 When the operation verification and the design of the present invention are completed in step S102, the process proceeds to step S103, and the test logic composed of the TPG, the design logic, and the test discrimination circuit of the present invention described later is written in the FPGA. The details of the test logic will be described with reference to FIG.
　最後に、ステップＳ１０４において、テスト論理を使用したランダムテストを実行する。 Finally, in step S104, a random test using the test logic is executed.
　図２は、図１のステップＳ１０２において設計された本発明を含むテスト論理図である。テストパターン生成器（ＴＰＧ）１０１は、シード値変更タイミング生成器１０２と、疑似乱数生成器１０５で構成されている。 FIG. 2 is a test logic diagram including the present invention designed in step S102 of FIG. The test pattern generator (TPG) 101 includes a seed value change timing generator 102 and a pseudo-random number generator 105.
　シード値変更タイミング生成器１０２は、カウンタ回路１０３と、シード値格納部１０４で構成されている。シード値格納部１０４のシード値変更カウント値（Ｃ０）～（Ｃｎ）、書き換えシード値（Ｘ：Ｘ０～Ｘｎ）～（Ｙ：Ｙ０～Ｙｎ）の決定方法の一例については、図３を用いて説明する。 The seed value change timing generator 102 includes a counter circuit 103 and a seed value storage unit 104. For an example of a method for determining the seed value change count value (C 0 ) to (C n ) and the rewrite seed value (X: X 0 to X n ) to (Y: Y 0 to Y n ) of the seed value storage unit 104. , FIG. 3 will be described.
　カウンタ回路１０３のカウント値は、シード値格納部１０４に入力され、そのカウント値に従って、疑似乱数生成器１０５のシード値の書き換えを行う。 The count value of the counter circuit 103 is input to the seed value storage unit 104, and the seed value of the pseudo-random number generator 105 is rewritten according to the count value.
　疑似乱数生成器１０５は、シード値に従ってテストパターンを生成し、テスト対象論理１０６に入力される。 The pseudo-random number generator 105 generates a test pattern according to the seed value and inputs it to the test target logic 106.
　テスト対象論理１０６の出力信号は、テスト判定回路１０７に入力され、そこでテストがＦａｉｌした際は、エラーフラグをシード値変更タイミング生成器１０２に出力する。シード値変更タイミング生成器１０２が、エラーフラグを検知した際は、その時のカウント値を含んだエラー情報を通知する。 The output signal of the test target logic 106 is input to the test determination circuit 107, and when the test fails there, an error flag is output to the seed value change timing generator 102. When the seed value change timing generator 102 detects an error flag, it notifies the error information including the count value at that time.
　図３は、図１のステップＳ１０２におけるＴＰＧ設計例を示す図である。ステップＳ１０２では、シード値格納部１０４に格納するシード値変更カウント値と、書き換えシード値を決定する。従来のＴＰＧで生成される疑似乱数を用いて、ランダムテストを実行した場合、テスト実行中にテストカバレッジが増加しない不要なテストパターンが生成されるため、その分テスト時間が増加する。 FIG. 3 is a diagram showing a TPG design example in step S102 of FIG. In step S102, the seed value change count value to be stored in the seed value storage unit 104 and the rewrite seed value are determined. When a random test is executed using a pseudo-random number generated by a conventional TPG, an unnecessary test pattern that does not increase the test coverage during the test execution is generated, so that the test time increases accordingly.
　そこで、本実施例では、テストステップ数をカウンタ回路１０３でカウントし、不要なテストパターンが生成されるカウント値（Ｃ０）～（Ｃｎ）の際に、疑似乱数生成器１０５のシード値を有効なテストパターンが生成されるシード値（Ｘ：Ｘ０～Ｘｎ）～（Ｙ：Ｙ０～Ｙｎ）に書き換える。すると、不要なテストパターンが削減され、テスト時間が短縮される。 Therefore, in this embodiment, the number of test steps is counted by the counter circuit 103, and the seed value of the pseudo-random number generator 105 is effective when the count values (C 0 ) to (Cn) generate unnecessary test patterns. Rewrite with seed values (X: X 0 to Xn) to (Y: Y 0 to Yn) that generate various test patterns. Then, unnecessary test patterns are reduced and the test time is shortened.
　そのため、シード値格納部１０４のシード値変更カウント値、書き換えシード値には、カウント値（Ｃ０）～（Ｃｎ）、シード値（Ｘ：Ｘ０～Ｘｎ）～（Ｙ：Ｙ０～Ｙｎ）を格納する。 Therefore, the seed value change count value and the rewrite seed value of the seed value storage unit 104 include count values (C 0 ) to (C n ) and seed values (X: X 0 to X n ) to (Y: Y 0 to). Y n ) is stored.
　シード値格納部１０４には、例えば、不要なテストパターンが生成されるテストステップ数をカウンタ回路１０３のカウント値として格納する機能、テストに有効なテストパターンに書き換え可能なシード値を格納する機能、テストカバレッジが増加するテストパターンに書き換え可能なシード値を格納する機能、テスト対象論理のテストカバレッジ増加率が０になるテストステップ数をカウンタ回路１０３のカウント値として格納する機能などを持たせる。 In the seed value storage unit 104, for example, a function of storing the number of test steps in which an unnecessary test pattern is generated as a count value of the counter circuit 103, a function of storing a seed value rewritable into a test pattern effective for the test, a function of storing the seed value. It is provided with a function of storing a rewritable seed value in a test pattern that increases test coverage, a function of storing the number of test steps at which the test coverage increase rate of the test target logic becomes 0, and the like as a count value of the counter circuit 103.
　図４は、本発明を適用したＦＰＧＡのテストフローを示す図である。図４を用いて、図２のＴＰＧ１０１の動作について説明する。 FIG. 4 is a diagram showing a test flow of FPGA to which the present invention is applied. The operation of the TPG 101 of FIG. 2 will be described with reference to FIG.
　テスト開始後、初めにステップＳ２０１では、シード値変更タイミング生成器１０２のカウンタ回路１０３のカウント値をインクリメントし、ステップＳ２０２に進む。 After the start of the test, first in step S201, the count value of the counter circuit 103 of the seed value change timing generator 102 is incremented, and the process proceeds to step S202.
　ステップＳ２０２では、カウント値がシード値格納部１０４に格納されているシード値変更カウント値（Ｃ０）～（Ｃｎ）と一致するか確認を行う。一致する場合はステップＳ２０３に進み、疑似乱数生成器１０５のシード値を、書き換えシード値に書き換えることで、テストパターンを書き換え、ステップＳ２０５に進む。一方、異なる場合はステップＳ２０４に進み、シード値の書き換えを行わずにそのままのシード値条件でテストパターンを生成し、ステップＳ２０５に進む。 In step S202, it is confirmed whether the count value matches the seed value change count values (C 0 ) to (C n ) stored in the seed value storage unit 104. If they match, the process proceeds to step S203, the seed value of the pseudo-random number generator 105 is rewritten to the rewritten seed value, the test pattern is rewritten, and the process proceeds to step S205. On the other hand, if they are different, the process proceeds to step S204, a test pattern is generated under the same seed value condition without rewriting the seed value, and the process proceeds to step S205.
　ステップＳ２０５では、テストがＦａｉｌした際に出力されるエラーフラグをシード値変更タイミング生成器１０２が検知しなかった場合は、ステップＳ２０１に戻る。一方、シード値変更タイミング生成器１０２が、エラーフラグを検知した場合は、ステップＳ２０６に進み、ＴＰＧ１０１の動作を停止し、その際のカウント値を含んだエラー情報を通知する。 In step S205, if the seed value change timing generator 102 does not detect the error flag output when the test fails, the process returns to step S201. On the other hand, when the seed value change timing generator 102 detects the error flag, the process proceeds to step S206, the operation of the TPG 101 is stopped, and the error information including the count value at that time is notified.
　図１，図４及び図５から図８を参照して、本発明の実施例２に係る電子制御装置とそれを用いた車載装置の診断方法について説明する。 A diagnostic method of an electronic control device according to a second embodiment of the present invention and an in-vehicle device using the electronic control device will be described with reference to FIGS. 1, 4 and 5 to 8.
　図５から図８は、図１のステップＳ１０２において、本発明の設計についての一例を説明するための図である。図５は、テスト対象論理の一例を示す図であり、信号Ａ,Ｂ,Ｃ,Ｄを入力として、ノードｗ，ｘ，ｙ，ｚの”0””1”反転をテスト項目とする。テスト内容の詳細については、図６，図７を用いて説明する。 5 to 8 are diagrams for explaining an example of the design of the present invention in step S102 of FIG. FIG. 5 is a diagram showing an example of the logic to be tested, and the signals A, B, C, and D are input, and the “0” and “1” inversions of the nodes w, x, y, and z are set as test items. The details of the test contents will be described with reference to FIGS. 6 and 7.
　図６は、図５の論理において、本発明適用前の従来のランダムテストのタイミングチャートの一例を示す図である。テストステップ１～６において、ノードｗ，ｘ，ｙのテストは完了しているが、ノードｚのテストを実施するには、テストステップ１５まで待つ必要がある。つまり、テストステップ７～１４は、テストカバレッジが増加しない不要なテストパターンである。そのため、不要なテストパターン分、テスト時間が増大し、テスト完了するまでに１６のテストステップを要する。 FIG. 6 is a diagram showing an example of a timing chart of a conventional random test before the application of the present invention in the logic of FIG. Although the tests of the nodes w, x, and y have been completed in the test steps 1 to 6, it is necessary to wait until the test step 15 in order to carry out the test of the node z. That is, test steps 7 to 14 are unnecessary test patterns that do not increase the test coverage. Therefore, the test time increases by the amount of unnecessary test patterns, and 16 test steps are required to complete the test.
　図７は、図５の論理において、本発明を適用した時のランダムテストのタイミングチャートである。テストステップ数７において、Ａ～Ｄのテストパターンを“１１１０”に書き換えることで、ノードｚの“０”→“1”の反転テストが実施可能である。そのため、不要なテストパターンが削減され、テストステップ８でテストが完了する。図６と図７のテスト完了時間を比較すると、本発明適用前後でテスト時間が５０％短縮される。 FIG. 7 is a timing chart of a random test when the present invention is applied in the logic of FIG. By rewriting the test patterns of A to D to "1110" in the number of test steps 7, the inversion test of "0" → "1" of the node z can be performed. Therefore, unnecessary test patterns are reduced, and the test is completed in test step 8. Comparing the test completion times of FIGS. 6 and 7, the test time is shortened by 50% before and after the application of the present invention.
　図８は、図１のステップＳ１０２において設計された本発明を含むテスト論理図であり、図７のランダムテストを実行する場合の例を示している。 FIG. 8 is a test logic diagram including the present invention designed in step S102 of FIG. 1, and shows an example of executing the random test of FIG. 7.
　ＴＰＧ２０１は、シード値変更タイミング生成器２０２と疑似乱数生成器２０５で構成されており、図２のシード値変更タイミング生成器１０２、疑似乱数生成器１０５と同様の機能を有する。 The TPG 201 is composed of a seed value change timing generator 202 and a pseudo-random number generator 205, and has the same functions as the seed value change timing generator 102 and the pseudo-random number generator 105 in FIG.
　シード値変更タイミング生成器２０２は、カウンタ回路２０３とシード値格納部２０４で構成されている。シード値格納部２０４は、シード値変更カウント値に“７”を、書き換えシード値に“１１１０”を格納している。 The seed value change timing generator 202 is composed of a counter circuit 203 and a seed value storage unit 204. The seed value storage unit 204 stores "7" in the seed value change count value and "1110" in the rewrite seed value.
　テスト対象論理２０６は、図５に示す論理である。テスト判定回路２０７は、図２のテスト判定回路１０７と同様の機能を有する。図４のテストフローでランダムテストを実行した際に、図４のステップＳ２０５においてカウント値が7の時にエラーフラグを検知した場合は、ＴＰＧ２０１は動作を停止して、カウント値7を含んだエラー情報を通知する。カウント値７がエラー情報に含まれていることから、ノードｚが“０”→“１”の反転でエラーが生じていることが判別可能である。 The test target logic 206 is the logic shown in FIG. The test determination circuit 207 has the same function as the test determination circuit 107 of FIG. When a random test is executed in the test flow of FIG. 4, if an error flag is detected when the count value is 7 in step S205 of FIG. 4, the TPG 201 stops operating and error information including the count value 7. Notify. Since the count value 7 is included in the error information, it is possible to determine that an error has occurred when the node z is inverted from “0” to “1”.
　以上のことから、本発明は、テスト対象論理のエラーが生じた箇所の特定に有効である。 From the above, the present invention is effective in identifying the location where an error occurs in the logic to be tested.
　図９を参照して、本発明の実施例３に係る車両について説明する。図９は、本発明を適用した電子制御装置を車両に搭載した時の一例を示す図である。 The vehicle according to the third embodiment of the present invention will be described with reference to FIG. FIG. 9 is a diagram showing an example when an electronic control device to which the present invention is applied is mounted on a vehicle.
　図９に示すように、本実施例では、車両３０１に図２と同様の構成である本発明を含むテスト論理３０２、車載表示装置３０３を搭載する。車載表示装置３０３は、制御部３０４とインストルメントパネル等の表示パネル３０５で構成されている。 As shown in FIG. 9, in the present embodiment, the vehicle 301 is equipped with a test logic 302 and an in-vehicle display device 303 including the present invention having the same configuration as that of FIG. The in-vehicle display device 303 includes a control unit 304 and a display panel 305 such as an instrument panel.
　本発明を車両に搭載することによって、車両走行前後等の車載診断（車載装置の診断）が短時間で実施可能になる。例えば、テスト時間が大きく、車載診断への適用が困難な場合は、本発明を適用することで、テスト時間が短縮され、車載診断への適用が可能になる。 By mounting the present invention on a vehicle, in-vehicle diagnosis (diagnosis of in-vehicle device) such as before and after traveling of the vehicle can be performed in a short time. For example, when the test time is long and it is difficult to apply it to in-vehicle diagnosis, by applying the present invention, the test time can be shortened and it can be applied to in-vehicle diagnosis.
　また、車載診断時にエラーが生じた場合は、テスト論理３０２は、エラーが生じたときのカウント値を含んだエラー情報を車載表示装置３０３の制御部３０４に通知する。制御部３０４は、テスト論理３０２からのエラー情報を受信し、そこに含まれているカウント値に従った制御信号（車載診断結果）を表示パネル３０５に出力する。その結果、表示パネルにエラー内容を表示させることが可能である。 Further, when an error occurs during the vehicle-mounted diagnosis, the test logic 302 notifies the control unit 304 of the vehicle-mounted display device 303 of the error information including the count value when the error occurs. The control unit 304 receives the error information from the test logic 302, and outputs a control signal (vehicle-mounted diagnosis result) according to the count value included therein to the display panel 305. As a result, it is possible to display the error content on the display panel.
　以上説明したように、本発明のテストパターン生成器（ＴＰＧ）１０１，２０１を備えた電子制御装置によれば、不要なテストパターンが発生するテストステップ数（カウント値）で、疑似乱数生成器１０５，２０５のシード値を書き換えることで、不要なテストパターンが削減され、テスト時間の短縮が可能である。 As described above, according to the electronic control device provided with the test pattern generators (TPGs) 101 and 201 of the present invention, the pseudo-random number generator 105 is the number of test steps (count values) in which unnecessary test patterns are generated. By rewriting the seed value of, 205, unnecessary test patterns can be reduced and the test time can be shortened.
　また、テストがＦａｉｌし、テスト判定回路１０７，２０７からエラーフラグを検知した場合、その時のカウンタ回路のカウント値を含んだエラー情報を通知する事で、テストがＦａｉｌしたテストパターンが判別されるため、エラー箇所の特定が可能である。 Further, when the test fails and an error flag is detected from the test judgment circuits 107 and 207, the test pattern in which the test fails is determined by notifying the error information including the count value of the counter circuit at that time. , It is possible to identify the error location.
　さらに、本発明を適用した電子制御装置を搭載することで、出荷前試験、車両走行前後等の診断が短時間で実施可能となる。診断を実行し、問題が生じた場合は、エラー情報に含まれているカウント値がエラーコードとなり、インストルメントパネル等にエラー内容を表示させることが可能である。 Furthermore, by installing an electronic control device to which the present invention is applied, pre-shipment tests, diagnosis before and after vehicle running, etc. can be performed in a short time. When the diagnosis is executed and a problem occurs, the count value included in the error information becomes an error code, and the error content can be displayed on the instrument panel or the like.
　なお、本発明は上記した実施例に限定されるものではなく、様々な変形例が含まれる。例えば、上記の実施例は本発明に対する理解を助けるために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施例の構成の一部を他の実施例の構成に置き換えることが可能であり、また、ある実施例の構成に他の実施例の構成を加えることも可能である。また、各実施例の構成の一部について、他の構成の追加・削除・置換をすることが可能である。 The present invention is not limited to the above-described embodiment, but includes various modifications. For example, the above embodiments have been described in detail to aid in understanding of the present invention and are not necessarily limited to those comprising all of the described configurations. Further, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, it is possible to add / delete / replace a part of the configuration of each embodiment with another configuration.
　１０１…テストパターン生成器（ＴＰＧ）、１０２…シード値変更タイミング生成器、１０３…カウンタ回路、１０４…シード値格納部、１０５…疑似乱数生成器、１０６…テスト対象論理、１０７…テスト判定回路、２０１…ＴＰＧ、２０２…シード値変更タイミング生成器、２０３…カウンタ回路、２０４…シード値格納部、２０５…疑似乱数生成器、２０６…テスト対象論理、２０７…テスト判定回路、３０１…車両、３０２…（本発明を適用した）テスト論理、３０３…車載表示装置、３０４…（車載表示装置における）制御部、３０５…表示パネル。 101 ... Test pattern generator (TPG), 102 ... Seed value change timing generator, 103 ... Counter circuit, 104 ... Seed value storage unit, 105 ... Pseudo-random number generator, 106 ... Test target logic, 107 ... Test judgment circuit, 201 ... TPG, 202 ... Seed value change timing generator, 203 ... Counter circuit, 204 ... Seed value storage unit, 205 ... Pseudo-random number generator, 206 ... Test target logic, 207 ... Test judgment circuit, 301 ... Vehicle, 302 ... Test logic (to which the present invention is applied), 303 ... vehicle-mounted display device, 304 ... control unit (in the vehicle-mounted display device), 305 ... display panel.

Claims (13)

  1. 　疑似乱数生成器と、
    　シード値変更タイミング生成器と、を備え、
    　前記シード値変更タイミング生成器は、テストステップ数をカウントするカウンタ回路と、
    　前記カウンタ回路のカウント値と前記疑似乱数生成器の書き換えを行うシード値を格納したシード値格納部と、を有する電子制御装置。     Pseudo-random number generator and
    With a seed value change timing generator,
    The seed value change timing generator includes a counter circuit that counts the number of test steps and a counter circuit.
    An electronic control device including a seed value storage unit that stores a count value of the counter circuit and a seed value for rewriting the pseudo-random number generator.
  2. 　請求項１に記載の電子制御装置であって、
    　前記シード値変更タイミング生成器は、前記カウンタ回路のカウント値に応じて、前記疑似乱数生成器のシード値を、前記シード値格納部に格納したシード値に書き換える機能を有する電子制御装置。     The electronic control device according to claim 1.
    The seed value change timing generator is an electronic control device having a function of rewriting the seed value of the pseudo-random number generator to the seed value stored in the seed value storage unit according to the count value of the counter circuit.
  3. 　請求項２に記載の電子制御装置であって、
    　前記疑似乱数生成器で生成されたテストパターンが入力されたテスト対象論理の出力信号を判定するテスト判定回路を備え、
    　前記シード値変更タイミング生成器は、前記テスト判定回路からエラーフラグを検知した際に、前記カウンタ回路のカウント値を含んだエラー情報を通知する機能を有する電子制御装置。     The electronic control device according to claim 2.
    It is equipped with a test judgment circuit that judges the output signal of the test target logic to which the test pattern generated by the pseudo-random number generator is input.
    The seed value change timing generator is an electronic control device having a function of notifying error information including a count value of the counter circuit when an error flag is detected from the test determination circuit.
  4. 　請求項３に記載の電子制御装置であって、
    　前記シード値格納部は、不要なテストパターンが生成されるテストステップ数を前記カウンタ回路のカウント値として格納する機能を有する電子制御装置。     The electronic control device according to claim 3.
    The seed value storage unit is an electronic control device having a function of storing the number of test steps in which an unnecessary test pattern is generated as a count value of the counter circuit.
  5. 　請求項４に記載の電子制御装置であって、
    　前記シード値格納部は、テストに有効なテストパターンに書き換え可能なシード値を格納する機能を有する電子制御装置。     The electronic control device according to claim 4.
    The seed value storage unit is an electronic control device having a function of storing rewritable seed values in a test pattern effective for testing.
  6. 　請求項５に記載の電子制御装置であって、
    　前記シード値格納部は、テストカバレッジが増加するテストパターンに書き換え可能なシード値を格納する機能を有する電子制御装置。     The electronic control device according to claim 5.
    The seed value storage unit is an electronic control device having a function of storing rewritable seed values in a test pattern that increases test coverage.
  7. 　請求項６に記載の電子制御装置であって、
    　前記シード値格納部は、テスト対象論理のテストカバレッジ増加率が０になるテストステップ数を前記カウンタ回路のカウント値として格納する機能を有する電子制御装置。     The electronic control device according to claim 6.
    The seed value storage unit is an electronic control device having a function of storing the number of test steps at which the test coverage increase rate of the test target logic becomes 0 as the count value of the counter circuit.
  8. 　請求項３に記載の電子制御装置であって、
    　前記電子制御装置は、車両に搭載された車載電子制御装置であり、
    　前記エラー情報を車載表示装置に通知し、
    　前記車載表示装置の制御部は、前記エラー情報に含まれているカウント値に従い、前記車載表示装置の表示パネルに制御信号を出力する電子制御装置。     The electronic control device according to claim 3.
    The electronic control device is an in-vehicle electronic control device mounted on a vehicle.
    Notify the in-vehicle display device of the error information and
    The control unit of the vehicle-mounted display device is an electronic control device that outputs a control signal to the display panel of the vehicle-mounted display device according to a count value included in the error information.
  9. 　以下のステップを含む車載装置の診断方法；
    　（ａ）テストステップ数をカウントするステップ、
    　（ｂ）前記（ａ）ステップにおいてカウントしたカウント値と、予め格納されたシード値変更カウント値を比較するステップ。     Diagnosis method of in-vehicle device including the following steps;
    (A) Steps for counting the number of test steps,
    (B) A step of comparing the count value counted in the step (a) with the seed value change count value stored in advance.
  10. 　請求項９に記載の車載装置の診断方法であって、
    　前記（ｂ）ステップにおいて、前記カウント値と前記シード値変更カウント値が一致した場合、疑似乱数生成器のシード値を前記シード値変更カウント値に対応する書き換えシード値に書き換えて、前記疑似乱数生成器の生成するテストパターンを書き換える車載装置の診断方法。     The method for diagnosing an in-vehicle device according to claim 9.
    When the count value and the seed value change count value match in the step (b), the seed value of the pseudo-random number generator is rewritten to the rewritten seed value corresponding to the seed value change count value to generate the pseudo-random number. A diagnostic method for in-vehicle devices that rewrites the test patterns generated by the device.
  11. 　請求項９に記載の車載装置の診断方法であって、
    　前記（ｂ）ステップにおいて、前記カウント値と前記シード値変更カウント値が異なる場合、疑似乱数生成器のシード値の書き換えを行わずに、そのままのシード値条件で前記疑似乱数生成器がテストパターンを生成する車載装置の診断方法。     The method for diagnosing an in-vehicle device according to claim 9.
    In the step (b), when the count value and the seed value change count value are different, the pseudo-random number generator sets a test pattern under the same seed value condition without rewriting the seed value of the pseudo-random number generator. Diagnosis method of the in-vehicle device to be generated.
  12. 　請求項１０または１１に記載の車載装置の診断方法であって、
    　前記書き換えたテストパターンまたは前記生成したテストパターンによりテスト対象論理のテストを実行し、
    　当該テストがＦａｉｌした際、その時のカウント値を含んだエラー情報を通知する車載装置の診断方法。     The method for diagnosing an in-vehicle device according to claim 10 or 11.
    The test of the logic to be tested is executed by the rewritten test pattern or the generated test pattern, and the test is executed.
    A diagnostic method for an in-vehicle device that notifies error information including a count value at that time when the test fails.
  13. 　請求項１２に記載の車載装置の診断方法であって、
    　前記エラー情報を車載表示装置に通知し、
    　前記エラー情報に含まれているカウント値に基づき、前記車載表示装置の表示パネルに車載診断結果を表示する車載装置の診断方法。     The method for diagnosing an in-vehicle device according to claim 12.
    Notify the in-vehicle display device of the error information and
    A diagnostic method for an in-vehicle device that displays an in-vehicle diagnosis result on a display panel of the in-vehicle display device based on a count value included in the error information.
PCT/JP2021/033337 2020-12-28 2021-09-10 Electronic control device and method for diagnosing vehicle-mounted device WO2022145092A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2022572910A JPWO2022145092A1 (en) 2020-12-28 2021-09-10

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020-218806 2020-12-28
JP2020218806 2020-12-28

Publications (1)

Publication Number Publication Date
WO2022145092A1 true WO2022145092A1 (en) 2022-07-07

Family

ID=82259183

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2021/033337 WO2022145092A1 (en) 2020-12-28 2021-09-10 Electronic control device and method for diagnosing vehicle-mounted device

Country Status (2)

Country Link
JP (1) JPWO2022145092A1 (en)
WO (1) WO2022145092A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10312311A (en) * 1997-05-13 1998-11-24 Mitsubishi Electric Corp Logical simulation method and computer-readable recording medium record with program for implementing logical simulation method
JPH1139181A (en) * 1997-07-18 1999-02-12 Fujitsu Ltd Method for testing computer
JP2013212048A (en) * 2013-05-07 2013-10-10 Honda Motor Co Ltd Charging system of electric vehicle
JP2020205047A (en) * 2019-06-17 2020-12-24 バイドゥ ユーエスエイ エルエルシーＢａｉｄｕ ＵＳＡ ＬＬＣ Vulnerability driven hybrid test system for application programs

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10312311A (en) * 1997-05-13 1998-11-24 Mitsubishi Electric Corp Logical simulation method and computer-readable recording medium record with program for implementing logical simulation method
JPH1139181A (en) * 1997-07-18 1999-02-12 Fujitsu Ltd Method for testing computer
JP2013212048A (en) * 2013-05-07 2013-10-10 Honda Motor Co Ltd Charging system of electric vehicle
JP2020205047A (en) * 2019-06-17 2020-12-24 バイドゥ ユーエスエイ エルエルシーＢａｉｄｕ ＵＳＡ ＬＬＣ Vulnerability driven hybrid test system for application programs

Also Published As

Publication number Publication date
JPWO2022145092A1 (en) 2022-07-07

Similar Documents

Publication Publication Date Title
US6453437B1 (en) Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation
KR100233627B1 (en) Test pattern generation method and test pattern generating system
JP3804733B2 (en) Integrated circuit having a function of testing a memory using a voltage for stress
KR20200007133A (en) Method and apparatus for dinamically injecting fault for vehicle ecu software test
US7673210B2 (en) Methods and apparatus for diagnosing a degree of interference between a plurality of faults in a system under test
JPH08320808A (en) Emulation system
WO2014119143A1 (en) Inertial force detection device
JP3871384B2 (en) Defect analysis memory for semiconductor memory test equipment
WO2022145092A1 (en) Electronic control device and method for diagnosing vehicle-mounted device
US6934656B2 (en) Auto-linking of function logic state with testcase regression list
US20150046138A1 (en) Vehicular simulation test generation
US20120054564A1 (en) Method and apparatus to test memory using a regeneration mechanism
US6754864B2 (en) System and method to predetermine a bitmap of a self-tested embedded array
US20050108596A1 (en) Method of verifying circuitry used for testing a new logic component prior to the first release of the component
US5504862A (en) Logic verification method
US7277840B2 (en) Method for detecting bus contention from RTL description
JPH0664125B2 (en) In-circuit inspection method with automatic suppression of spurious signals
Braun et al. Simulation-based verification of the MOST netinterface specification revision 3.0
US20080040638A1 (en) Evaluation Circuit and Method for Detecting and/or Locating Faulty Data Words in a Data Stream Tn
JPH05119122A (en) Formation of test pattern of scanning circuit
US20030188273A1 (en) Simulation-based technique for contention avoidance in automatic test pattern generation
JPH07198782A (en) Diagnosis circuit
JP2011504579A (en) How to test an address bus in a logic module
JPH0798365A (en) Fault detection factor calculating method for test pattern and device thereof
CN111859845A (en) Detection system for connecting line from top layer inside chip to top layer outside chip and application

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21914953

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022572910

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21914953

Country of ref document: EP

Kind code of ref document: A1