WO2022143587A1 - Finfet basic structure and manufacturing method therefor - Google Patents

Finfet basic structure and manufacturing method therefor Download PDF

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Publication number
WO2022143587A1
WO2022143587A1 PCT/CN2021/141852 CN2021141852W WO2022143587A1 WO 2022143587 A1 WO2022143587 A1 WO 2022143587A1 CN 2021141852 W CN2021141852 W CN 2021141852W WO 2022143587 A1 WO2022143587 A1 WO 2022143587A1
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layer
finfet
sti
manufacturing
basic structure
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PCT/CN2021/141852
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French (fr)
Chinese (zh)
Inventor
张峰溢
苏廷锜
黄崇哲
苏韦菘
林盈志
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广州集成电路技术研究院有限公司
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Publication of WO2022143587A1 publication Critical patent/WO2022143587A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present invention relates to the technical field of semiconductors, and in particular, to a FinFET basic structure and a manufacturing method thereof.
  • FIG. 1 shows a schematic diagram of the flow state of the interlayer dielectric planarization step of an existing FinFET basic structure manufacturing method
  • FIG. 2 shows the interlayer dielectric planarization shown in FIG. 1.
  • Fig. 3 shows a schematic diagram of the flow state of the trenching step of the manufacturing method of the existing FinFET basic structure shown in Fig. 1;
  • Fig. 4 shows the trenching shown in Fig. 3 A schematic cross-sectional view of the state of the step B-B;
  • FIG. 5 shows a schematic diagram of the flow state of the step of filling SiN by ALD technology in the manufacturing method of the existing FinFET basic structure shown in FIG. 1;
  • FIG. 6 shows the process shown in FIG.
  • FIG. 7 shows a schematic flow state schematic diagram of the step of removing the polysilicon layer of the manufacturing method of the existing FinFET basic structure shown in FIG. 1 ;
  • FIG. 8 shows the 7 is a schematic cross-sectional view of the state in the step of removing the polysilicon layer shown in the D-D direction;
  • FIG. 9 shows a schematic diagram of the flow state of the step of removing the dummy layer in the manufacturing method of the existing FinFET basic structure shown in FIG. 1;
  • FIG. 10 shows A schematic cross-sectional view of the E-E direction in the state of the step of removing the dummy layer shown in FIG. 9 is shown;
  • FIG. 11 shows a schematic diagram of the flow state of the oxide film growth step of the manufacturing method of the existing FinFET basic structure shown in FIG. 1;
  • FIG. 12 shows a schematic cross-sectional view in the direction F-F of the state of the oxide film growth step shown in FIG. 11;
  • FIG. 13 shows the high dielectric constant material/TiN deposition step of the manufacturing method of the existing FinFET base structure shown in FIG.
  • FIG. 14 shows a schematic G-G cross-section of the state of the high dielectric constant material/TiN deposition step shown in Figure 13;
  • Figure 15 shows the fabrication of the existing FinFET base structure shown in Figure 1
  • Figure 16 shows a schematic cross-sectional view in the H-H direction of the state of the formation step of the cap layer shown in Figure 15;
  • Figure 17 shows the existing FinFET foundation shown in Figure 1.
  • FIG. 18 shows a schematic cross-sectional view along the I-I direction of the state of the removal step of the cap layer shown in FIG. 17 ;
  • FIG. 18 shows a schematic cross-sectional view along the I-I direction of the state of the removal step of the cap layer shown in FIG. 17 ;
  • step 1 preparing a substrate, the substrate comprising an STI layer 1, a plurality of fins 2 interposed in the STI layer 1, a dummy layer 3 attached to the fins 2, and a layer covering the STI polysilicon layer 4 on layer 1 and dummy layer 3; then, the polysilicon layer 4 is planarized; step 2, a groove 5 is opened on the substrate, and the groove 5 runs through the polysilicon layer 4 and ends inside the STI layer 1 ; Step 3, fill SiN in the groove 5 by ALD technology, thereby forming a filling member 6; Step 4, remove Polysilicon layer 4; Step 5, remove the dummy layer 3; Step 6, form an oxide film 7 on the outer wall of the fin 2; Step 7, successively form a high dielectric constant material layer 8 and a first TiN layer 9 by deposition technology ; Step
  • the purpose of the present invention is to provide a FinFET basic structure and a manufacturing method thereof in view of the above technical problems.
  • the present invention provides a method for manufacturing a FinFET basic structure, comprising the following steps:
  • Step S providing a substrate, and then opening grooves on the substrate by etching technology
  • Step S oxidizing a part of the inner wall of the groove close to the opening to form a first oxide layer, so that the groove bottom is protruded to form a convex groove;
  • Step S filling the grooves and the convex grooves with a filling material to form a filling member; wherein, the filling material filled in the convex grooves forms a convex portion of the filling member;
  • Step S by removing a part of the base body, so that the convex part of the filler is exposed;
  • Step S forming a cap layer so that the cap layer covers the convex portion of the filler; then annealing to remove the cap layer; and then arranging a metal layer at the position of the removed cap layer to form a metal gate.
  • the substrate in step S, includes an STI layer, a plurality of fins inserted on the STI layer, a dummy layer, and a polysilicon layer covering the STI layer and the dummy layer,
  • the dummy layer is covered and disposed on the outer wall of the fin above the top surface of the STI layer; the groove penetrates the polysilicon layer and extends into the interior of the STI layer.
  • the step S further includes: removing the polysilicon layer; and then removing the dummy layer and the first oxide layer, so that the convex portion of the filler is exposed.
  • step S further includes: forming a second oxide layer on the outer wall of the fin above the top surface of the STI layer; A TiN layer; wherein, the high dielectric constant material layer covers the outer wall of the second oxide layer, the top surface of the STI layer and the outer wall of the filler located above the top surface of the STI layer respectively; the first TiN layer covers the high dielectric constant material. layer; after that, a cap layer is formed on the first TiN layer.
  • both the STI layer and the dummy layer use SiO; the thickness of the first oxide layer is smaller than that of the dummy layer;
  • the filling material is SiN, SiON, SiOC, SiOCN, SiCN, SiC or metal oxide, wherein the metal oxide is AlO, TiO, hafnium oxide or zirconium oxide;
  • the high dielectric constant material layer adopts HfO, TiO, HfZrO, HfSiNO, TaO, ZrO, ZrSiO or AlO;
  • the metal layer adopts W.
  • step S exposing the protruding portion of the filler includes the step of making at least one contour inflection point or contour inflection line of the protruding portion located above the top surface of the STI layer.
  • step S after removing the cap layer, the method further includes forming a TaN layer and a second TiN layer by a deposition method, and then arranging a metal layer on the second TiN layer. to form a metal gate.
  • the present invention also provides a FinFET basic structure, which includes a base body, and the base body includes an STI layer; the FinFET basic structure further includes a filler inserted on the STI layer; a protrusion is formed on the sidewall of the bottom of the filler; the raised portion protrudes from the top surface of the STI layer;
  • the FinFET infrastructure also includes a metal gate overlying the STI layer and portions of the filler sidewalls above the STI layer.
  • At least one contour inflection point or contour inflection line of the raised portion is located above the top surface of the STI layer.
  • the protruding portion is disposed around the filler to form a bottom frustum contour structure with a diameter gradually decreasing from bottom to top.
  • the FinFET base structure of the present invention and its fabrication method avoids the problem of residual Si upon removal of the cap layer by employing the raised portion.
  • the filling space of the filling member is greatly reduced, thereby increasing the filling and removing space of the silicon material in the subsequent capping annealing process, and avoiding the problem of silicon residues.
  • the FinFET basic structure and the manufacturing method thereof of the present invention have novel design and strong practicability.
  • FIG. 1 shows a schematic flow state diagram of an interlayer dielectric planarization step of a conventional method for manufacturing a FinFET basic structure
  • FIG. 2 shows a schematic cross-sectional view along the A-A direction of the state of the interlayer dielectric planarization step shown in FIG. 1;
  • FIG. 3 shows a schematic flow state diagram of a trenching step of the prior art FinFET basic structure manufacturing method shown in FIG. 1;
  • FIG. 4 shows a schematic cross-sectional view along the B-B direction of the state of the grooving step shown in FIG. 3;
  • FIG. 5 shows a schematic flow state diagram of a step of filling SiN by ALD technology of the existing manufacturing method of the FinFET basic structure shown in FIG. 1;
  • FIG. 6 shows a schematic cross-sectional view in the C-C direction of the state of filling the SiN step by the ALD technology shown in FIG. 5;
  • FIG. 7 shows a schematic flow state diagram of the step of removing the polysilicon layer of the conventional method for manufacturing the FinFET basic structure shown in FIG. 1;
  • FIG. 8 shows a schematic cross-sectional view in the D-D direction of the state in the step of removing the polysilicon layer shown in FIG. 7;
  • FIG. 9 shows a schematic flow state diagram of a step of removing a dummy layer in the manufacturing method of the existing FinFET basic structure shown in FIG. 1;
  • FIG. 10 shows a schematic cross-sectional view along the E-E direction in the state of the step of removing the dummy layer shown in FIG. 9;
  • FIG. 11 shows a schematic flow state diagram of the oxide film growth step of the prior art FinFET basic structure manufacturing method shown in FIG. 1;
  • FIG. 12 shows a schematic cross-sectional view in the direction of F-F in the state of the oxide film growth step shown in FIG. 11;
  • FIG. 13 shows a schematic flow state diagram of the high dielectric constant material/TiN deposition step of the conventional method for manufacturing the FinFET basic structure shown in FIG. 1;
  • Figure 14 shows a schematic cross-sectional view in the G-G direction of the state of the high dielectric constant material/TiN deposition step shown in Figure 13;
  • FIG. 15 shows a schematic flow state diagram of the forming step of the cap layer of the conventional method for manufacturing the FinFET basic structure shown in FIG. 1;
  • FIG. 16 shows a schematic cross-sectional view in the H-H direction of the state of the capping layer forming step shown in FIG. 15;
  • FIG. 17 shows a flow state schematic diagram of the removing step of the cap layer of the conventional method for manufacturing the FinFET basic structure shown in FIG. 1;
  • FIG. 18 shows a schematic cross-sectional view along the I-I direction of the state of the removal step of the cap layer shown in FIG. 17;
  • FIG. 19 shows a schematic flow state diagram of a metal gate formation step of the prior art FinFET basic structure manufacturing method shown in FIG. 1;
  • FIG. 20 shows a schematic cross-sectional view of the metal gate shown in FIG. 19 in the J-J direction in the state of the forming step
  • FIG. 21 shows a schematic diagram of the first step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention.
  • FIG. 22 is a schematic diagram showing the second step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention.
  • FIG. 23 shows a schematic diagram of the third step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention.
  • FIG. 24 shows a schematic diagram of the fourth step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention.
  • FIG. 25 shows a schematic diagram of the fifth step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention.
  • FIG. 26 shows a schematic diagram of the sixth step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention.
  • FIG. 27 shows a schematic diagram of the seventh step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention.
  • FIG. 28 shows a schematic diagram of the eighth step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention.
  • FIG. 29 shows a state schematic diagram of the ninth step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention.
  • FIG. 30 shows a state schematic diagram of the tenth step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention.
  • FIG. 21 shows a schematic diagram of the first step of the manufacturing method of the FinFET base structure of the preferred embodiment of the present invention
  • FIG. 22 shows the first step of the manufacturing method of the FinFET base structure of the preferred embodiment of the present invention.
  • Two-step state schematic diagram FIG. 23 shows the third step state schematic diagram of the manufacturing method of the FinFET base structure of the preferred embodiment of the present invention
  • FIG. 24 shows the fourth step of the manufacturing method of the FinFET base structure of the preferred embodiment of the present invention.
  • FIG. 25 shows a schematic state diagram of the fifth step of the manufacturing method of the FinFET base structure of the preferred embodiment of the present invention
  • FIG. 26 shows the state schematic diagram of the sixth step of the manufacturing method of the FinFET base structure of the preferred embodiment of the present invention
  • 27 shows a schematic diagram of the seventh step of the manufacturing method of the FinFET basic structure of the preferred embodiment of the present invention
  • FIG. 28 shows the schematic diagram of the eighth step of the manufacturing method of the FinFET basic structure of the preferred embodiment of the present invention
  • 29 shows a state schematic diagram of the ninth step of the manufacturing method of the FinFET basic structure of the preferred embodiment of the present invention
  • FIG. 30 shows a state schematic diagram of the tenth step of the manufacturing method of the FinFET basic structure of the preferred embodiment of the present invention.
  • the manufacturing method of the FinFET base structure includes the following steps:
  • Step 1 Provide a base, which includes the STI layer 100, a plurality of fins 200 inserted on the STI layer 100, a dummy layer 300, and a polysilicon layer 400 covering the STI layer 100 and the dummy layer 300, as shown in FIG. 21 .
  • the dummy layer 300 is covered and arranged on the outer wall of the fin 200 above the top surface of the STI layer 100;
  • both the STI layer 100 and the dummy layer 300 are made of SiO 2 .
  • Step 2 opening a groove 500 on the substrate by etching technology; the groove 500 penetrates the polysilicon layer 400 and extends to the interior of the STI layer 100, as shown in FIG. 22;
  • Step 3 oxidizing a part of the inner wall of the groove 500 close to the opening to form a first oxide layer 510, so that the bottom of the groove 500 is protruded to form a convex groove 530, as shown in FIG. 23;
  • the thickness of the first oxide layer 510 is smaller than the thickness of the dummy layer 300, so that the first oxide layer is removed together and the complete removal of the first oxide layer is ensured during the subsequent removal of the dummy layer.
  • the first oxide layer 510 can be formed on the inner wall of the groove 500 by oxidizing the polysilicon layer 400 with an oxidant under heating conditions, and at the same time, the groove bottom of the groove 500 can be protruded to form a convex groove 530.
  • Step 4 Filling the groove 500 and the convex groove 530 with a filling material to form the filling member 520; wherein, the filling material filled in the convex groove 530 forms the convex portion 521 of the filling member 520, as shown in FIG. 24 ;
  • the filling material is SiN, SiON, SiOC, SiOCN, SiCN, SiC or metal oxide, wherein the metal oxide is Al 2 O 3 , TiO 2 , hafnium oxide or zirconium oxide.
  • the protruding portion 521 is disposed around the filler 520 to form a bottom frustoconical profile structure with a diameter gradually decreasing from bottom to top.
  • the filler is used to isolate adjacent gates.
  • Step 5 Remove the polysilicon layer 400, as shown in FIG. 25; then remove the dummy layer 300 and the first oxide layer 510, so that the protrusions 521 of the filler 520 are exposed, as shown in FIG. 26; A second oxide layer 540 is formed on the outer wall of 200 above the top surface of the STI layer 100; then a high dielectric constant material layer 600 and a first TiN layer 700 are successively formed by deposition techniques; wherein, the high dielectric constant material layer 600 respectively covers On the outer wall of the second oxide layer 540, the top surface of the STI layer 100, and the outer wall of the filler 520 above the top surface of the STI layer 100; the first TiN layer 700 covers the high dielectric constant material layer 600, as shown in FIG. 27 ;
  • the high dielectric constant material layer 600 refers to a material whose dielectric constant is higher than that of SiO 2 .
  • exposing the protruding portion 521 of the filler 520 includes: making at least one contour inflection point or contour inflection line of the protruding portion 521 located above the top surface of the STI layer 100 .
  • the high dielectric constant material layer 600 can be made of HfO 2 , TiO 2 , HfZrO, HfSiNO, Ta 2 O 5 , ZrO 2 , ZrSiO 2 or Al 2 O 3 .
  • Step 6 forming a cap layer 800 on the first TiN layer 700, and capping annealing, as shown in FIG. 28; then removing the cap layer 800, as shown in FIG. A metal layer 910 is positioned to form a metal gate, as shown in FIG. 30 .
  • the cap layer 800 is made of Si.
  • the steps further include forming a TaN layer 920 and a second TiN layer 930 by a deposition method, and then arranging a metal layer 910 on the second TiN layer 930 to A metal gate is formed.
  • the metal layer 910 adopts W.
  • the filling groove includes an upper part located in the polysilicon layer and a groove bottom deep in the STI layer, and the inner wall of the polysilicon layer in the groove is oxidized to form a first oxide by using inconsistent materials of the polysilicon layer and the STI layer. layer, and the silicon oxide material of the STI layer is not affected by it, so that the groove bottom of the groove protrudes to form a convex groove.
  • the first oxide layer is completely removed while removing the dummy layer, without adding an additional removal step; above the surface of the STI layer, leaving it exposed.
  • the present invention also provides a FinFET basic structure, including a base body; the base body includes an STI layer 100 and a plurality of fins 200 interposed on the STI layer 100 ;
  • the FinFET basic structure further includes a filler 520 inserted on the STI layer 100; a protrusion 521 is formed protruding from the sidewall of the bottom of the filler 520; the protrusion 521 protrudes from the top surface of the STI layer 100;
  • the FinFET basic structure further includes a high dielectric constant material layer 600 covering the base and the portion of the sidewall of the filler 520 above the STI layer 100; the high dielectric constant material layer 600 is covered with a first TiN layer 700; A TiN layer 700 is covered with a TaN layer 920 , the TaN layer 920 is covered with a second TiN layer 930 , and the second TiN layer 930 is covered with a metal layer 910 .
  • At least one contour inflection point or contour inflection line of the raised portion 521 is located above the top surface of the STI layer 100 ; in this embodiment, the raised portion 521 is arranged around the filler 520 to form a gradual taper from bottom to top Diameter bottom frustum contour structure.
  • the STI layer 100 is made of SiO 2 .
  • the filler 520 is made of SiN, SiON, SiOC, SiOCN, SiCN, SiC or metal oxide, wherein the metal oxide is made of Al 2 O 3 , TiO 2 , hafnium oxide or zirconium oxide.

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Abstract

The present invention provides a FinFET basic structure and a manufacturing method therefor. The FinFET basic structure comprises a substrate, and further comprises a filling member (520) inserted on the substrate; the side wall of the bottom of the filling member (520) protrudes to form a protruding portion (521); the protruding portion (521) protrudes from the top surface of the substrate; the FinFET basic structure further comprises a metal gate covering the substrate and the portion of the side wall of the filling member (520) located above the substrate. The FinFET basic structure and the manufacturing method therefor of the present invention have a novel design and high practicability.

Description

一种FinFET基础结构及其制造方法A kind of FinFET basic structure and its manufacturing method 技术领域technical field
本发明涉及半导体技术领域，尤其涉及一种FinFET基础结构及其制造方法。The present invention relates to the technical field of semiconductors, and in particular, to a FinFET basic structure and a manufacturing method thereof.
背景技术Background technique
如图1-图20所示，图1示出了一种现有FinFET基础结构的制造方法的层间介质平坦化步骤的流程状态示意图；图2示出了图1所示的层间介质平坦化步骤的状态的A-A向的剖面示意图；图3示出了图1所示的现有FinFET基础结构的制造方法的开槽步骤的流程状态示意图；图4示出了图3所示的开槽步骤的状态的B-B向的剖面示意图；图5示出了图1所示的现有FinFET基础结构的制造方法的通过ALD技术填充SiN步骤的流程状态示意图；图6示出了图5所示的通过ALD技术填充SiN步骤的状态的C-C向的剖面示意图；图7示出了图1所示的现有FinFET基础结构的制造方法的移除多晶硅层步骤的流程状态示意图；图8示出了图7所示的移除多晶硅层步骤的状态的D-D向的剖面示意图；图9示出了图1所示的现有FinFET基础结构的制造方法的移除虚设层步骤的流程状态示意图；图10示出了图9所示的移除虚设层步骤的状态的E-E向的剖面示意图；图11示出了图1所示的现有FinFET基础结构的制造方法的氧化膜生长步骤的流程状态示意图；图12示出了图11所示的氧化膜生长步骤的状态的F-F向的剖面示意图；图13示出了图1所示的现有FinFET基础结构的制造方法的高介电常数材料/TiN沉积步骤的流程状态示意图；图14示出了图13所示的高介电常数材料/TiN沉积步骤的状态的G-G向的剖面示意图；图15示出了图1所示的现有FinFET基础结构的制造方法的帽层的形成步骤的流程状态示意图；图16示出了图15所示的帽层的形成步骤的状态的H-H向的剖面示意图；图17示出了图1所示的现有FinFET基础结构的制造方法的帽层的移除步骤的流程状态示意图；图18示出了图17所示的帽层的移除步骤的状态的I-I向的剖面示意图；图19示出了图1所示的现有FinFET基础结构的制造方法的金属栅极的形成步骤的流程状态示意图；图20示出了图19所示的金属栅极的形成步骤的状态的J-J向的剖面示意图；该FinFET基础结构的制造方法包括以下步骤：步骤1、准备衬底，该衬底包括STI层1、插设在STI层1中的多个鳍片2、附着在鳍片2上的虚设层3以及覆盖在STI层1和虚设层3上的多晶硅层4；然后，对多晶硅层4进行平坦化；步骤2、在衬底上开设有凹槽5，该凹槽5贯穿多晶硅层4并止于STI层1内部；步骤3、通过ALD技术在凹槽5中填充SiN，从而形成填充件6；步骤4、移除多晶硅层4；步骤5、移除虚设（Dummy）层3；步骤6、在鳍片2外壁形成氧化膜7；步骤7、先后通过沉积技术形成高介电常数材料层8和第一TiN层9；步骤8、在第一TiN层9上形成帽层10，封帽退火（Post capping anneal，PCA）；步骤9、移除帽层10；步骤10、先后通过沉积方法形成TaN层12、第二TiN层13，然后再在第二TiN层13上布置金属层14以形成金属栅极。As shown in FIG. 1-FIG. 20, FIG. 1 shows a schematic diagram of the flow state of the interlayer dielectric planarization step of an existing FinFET basic structure manufacturing method; FIG. 2 shows the interlayer dielectric planarization shown in FIG. 1. Fig. 3 shows a schematic diagram of the flow state of the trenching step of the manufacturing method of the existing FinFET basic structure shown in Fig. 1; Fig. 4 shows the trenching shown in Fig. 3 A schematic cross-sectional view of the state of the step B-B; FIG. 5 shows a schematic diagram of the flow state of the step of filling SiN by ALD technology in the manufacturing method of the existing FinFET basic structure shown in FIG. 1; FIG. 6 shows the process shown in FIG. A schematic cross-sectional view in the C-C direction of the state of the SiN filling step by ALD technology; FIG. 7 shows a schematic flow state schematic diagram of the step of removing the polysilicon layer of the manufacturing method of the existing FinFET basic structure shown in FIG. 1 ; FIG. 8 shows the 7 is a schematic cross-sectional view of the state in the step of removing the polysilicon layer shown in the D-D direction; FIG. 9 shows a schematic diagram of the flow state of the step of removing the dummy layer in the manufacturing method of the existing FinFET basic structure shown in FIG. 1; FIG. 10 shows A schematic cross-sectional view of the E-E direction in the state of the step of removing the dummy layer shown in FIG. 9 is shown; FIG. 11 shows a schematic diagram of the flow state of the oxide film growth step of the manufacturing method of the existing FinFET basic structure shown in FIG. 1; FIG. 12 shows a schematic cross-sectional view in the direction F-F of the state of the oxide film growth step shown in FIG. 11; FIG. 13 shows the high dielectric constant material/TiN deposition step of the manufacturing method of the existing FinFET base structure shown in FIG. 1 Figure 14 shows a schematic G-G cross-section of the state of the high dielectric constant material/TiN deposition step shown in Figure 13; Figure 15 shows the fabrication of the existing FinFET base structure shown in Figure 1 Figure 16 shows a schematic cross-sectional view in the H-H direction of the state of the formation step of the cap layer shown in Figure 15; Figure 17 shows the existing FinFET foundation shown in Figure 1. Schematic diagram of the flow state of the removal step of the cap layer of the manufacturing method of the structure; FIG. 18 shows a schematic cross-sectional view along the I-I direction of the state of the removal step of the cap layer shown in FIG. 17 ; FIG. 19 shows the 20 shows a schematic cross-sectional view of the J-J direction of the state of the formation step of the metal gate shown in FIG. 19; the FinFET basic structure The manufacturing method includes the following steps: step 1, preparing a substrate, the substrate comprising an STI layer 1, a plurality of fins 2 interposed in the STI layer 1, a dummy layer 3 attached to the fins 2, and a layer covering the STI polysilicon layer 4 on layer 1 and dummy layer 3; then, the polysilicon layer 4 is planarized; step 2, a groove 5 is opened on the substrate, and the groove 5 runs through the polysilicon layer 4 and ends inside the STI layer 1 ; Step 3, fill SiN in the groove 5 by ALD technology, thereby forming a filling member 6; Step 4, remove Polysilicon layer 4; Step 5, remove the dummy layer 3; Step 6, form an oxide film 7 on the outer wall of the fin 2; Step 7, successively form a high dielectric constant material layer 8 and a first TiN layer 9 by deposition technology ; Step 8, forming a cap layer 10 on the first TiN layer 9, capping annealing (Post capping anneal, PCA); Step 9, removing the cap layer 10; Step 10, successively forming a TaN layer 12 by a deposition method, the second TiN layer 13, and then a metal layer 14 is disposed on the second TiN layer 13 to form a metal gate.
技术问题technical problem
在这种FinFET基础结构的制造方法中，帽层的移除时，由于鳍片2与填充件6之间高深宽比的沟槽，会有Si残余11，这会导致FinFET基础结构电性能不良。In this method of manufacturing the FinFET base structure, when the cap layer is removed, due to the high aspect ratio trench between the fin 2 and the filler 6, there will be Si residues 11, which may lead to poor electrical performance of the FinFET base structure. .
技术解决方案technical solutions
本发明的目的是针对上述技术问题，提出一种FinFET基础结构及其制造方法。The purpose of the present invention is to provide a FinFET basic structure and a manufacturing method thereof in view of the above technical problems.
本发明解决其技术问题的技术方案是：The technical scheme that the present invention solves its technical problem is:
本发明提出了一种FinFET基础结构的制造方法，包括以下步骤：The present invention provides a method for manufacturing a FinFET basic structure, comprising the following steps:
步骤S、提供基体，然后通过刻蚀技术在基体上开设凹槽；Step S, providing a substrate, and then opening grooves on the substrate by etching technology;
步骤S、在凹槽内壁的靠近其开口的一部分氧化形成第一氧化层，使凹槽槽底凸出形成凸槽；Step S, oxidizing a part of the inner wall of the groove close to the opening to form a first oxide layer, so that the groove bottom is protruded to form a convex groove;
步骤S、在凹槽和凸槽中填充填充材料，从而形成填充件；其中，填充在凸槽内的填充材料形成填充件的凸起部；Step S, filling the grooves and the convex grooves with a filling material to form a filling member; wherein, the filling material filled in the convex grooves forms a convex portion of the filling member;
步骤S、通过移除基体的一部分，从而使得填充件的凸起部暴露出来；Step S, by removing a part of the base body, so that the convex part of the filler is exposed;
步骤S、形成帽层，以使帽层覆盖填充件的凸起部；然后退火移除帽层；再在已被移除的帽层的位置布置金属层以形成金属栅极。Step S, forming a cap layer so that the cap layer covers the convex portion of the filler; then annealing to remove the cap layer; and then arranging a metal layer at the position of the removed cap layer to form a metal gate.
本发明上述的FinFET基础结构的制造方法中，在步骤S中，该基体包括STI层、插设在STI层上的多个鳍片、虚设层以及覆盖在STI层和虚设层上的多晶硅层，虚设层覆盖设置在鳍片的处于STI层顶面上方的外壁上；凹槽贯穿多晶硅层，并延伸至STI层内部。In the above-mentioned manufacturing method of the FinFET basic structure of the present invention, in step S, the substrate includes an STI layer, a plurality of fins inserted on the STI layer, a dummy layer, and a polysilicon layer covering the STI layer and the dummy layer, The dummy layer is covered and disposed on the outer wall of the fin above the top surface of the STI layer; the groove penetrates the polysilicon layer and extends into the interior of the STI layer.
本发明上述的FinFET基础结构的制造方法中，步骤S还包括：移除多晶硅层；再移除虚设层和第一氧化层，使得填充件的凸起部暴露出来。In the above-mentioned manufacturing method of the FinFET basic structure of the present invention, the step S further includes: removing the polysilicon layer; and then removing the dummy layer and the first oxide layer, so that the convex portion of the filler is exposed.
本发明上述的FinFET基础结构的制造方法中，步骤S还包括：在鳍片的处于STI层顶面上方的外壁上形成第二氧化层；然后先后通过沉积技术形成高介电常数材料层和第一TiN层；其中，高介电常数材料层分别覆盖在第二氧化层外壁、STI层顶面以及填充件的位于STI层顶面上方的外壁上；第一TiN层覆盖在高介电常数材料层上；之后，在第一TiN层上形成帽层。In the above-mentioned manufacturing method of the FinFET basic structure of the present invention, step S further includes: forming a second oxide layer on the outer wall of the fin above the top surface of the STI layer; A TiN layer; wherein, the high dielectric constant material layer covers the outer wall of the second oxide layer, the top surface of the STI layer and the outer wall of the filler located above the top surface of the STI layer respectively; the first TiN layer covers the high dielectric constant material. layer; after that, a cap layer is formed on the first TiN layer.
本发明上述的FinFET基础结构的制造方法中，STI层和虚设层均采用SiO；第一氧化层的厚度要小于虚设层的厚度；In the above-mentioned manufacturing method of the FinFET basic structure of the present invention, both the STI layer and the dummy layer use SiO; the thickness of the first oxide layer is smaller than that of the dummy layer;
填充材料采用SiN、SiON、SiOC、SiOCN、SiCN、SiC或者金属氧化物，其中，金属氧化物采用AlO、TiO、铪的氧化物或者锆的氧化物；The filling material is SiN, SiON, SiOC, SiOCN, SiCN, SiC or metal oxide, wherein the metal oxide is AlO, TiO, hafnium oxide or zirconium oxide;
高介电常数材料层采用 HfO、TiO、HfZrO、HfSiNO、TaO、ZrO、ZrSiO或者AlO；The high dielectric constant material layer adopts HfO, TiO, HfZrO, HfSiNO, TaO, ZrO, ZrSiO or AlO;
金属层采用W。The metal layer adopts W.
本发明上述的FinFET基础结构的制造方法中，在步骤S中，使得填充件的凸起部暴露出来包括：使凸起部的至少一个轮廓转折点或轮廓转折线位于STI层顶面上方的步骤。In the above-mentioned manufacturing method of the FinFET basic structure of the present invention, in step S, exposing the protruding portion of the filler includes the step of making at least one contour inflection point or contour inflection line of the protruding portion located above the top surface of the STI layer.
本发明上述的FinFET基础结构的制造方法中，在步骤S中，在移除帽层后，还包括先后通过沉积方法形成TaN层、第二TiN层，然后再在第二TiN层上布置金属层以形成金属栅极的步骤。In the above-mentioned manufacturing method of the FinFET basic structure of the present invention, in step S, after removing the cap layer, the method further includes forming a TaN layer and a second TiN layer by a deposition method, and then arranging a metal layer on the second TiN layer. to form a metal gate.
本发明还提出了一种FinFET基础结构，包括基体，该基体包括STI层；FinFET基础结构还包括插设在STI层上的填充件；填充件底部的侧壁上凸出形成有凸起部；该凸起部突出于STI层顶面上；The present invention also provides a FinFET basic structure, which includes a base body, and the base body includes an STI layer; the FinFET basic structure further includes a filler inserted on the STI layer; a protrusion is formed on the sidewall of the bottom of the filler; the raised portion protrudes from the top surface of the STI layer;
FinFET基础结构还包括覆盖在STI层以及填充件侧壁的位于STI层上方的部分上的金属栅极。The FinFET infrastructure also includes a metal gate overlying the STI layer and portions of the filler sidewalls above the STI layer.
本发明上述的FinFET基础结构中，凸起部的至少一个轮廓转折点或轮廓转折线位于STI层顶面上方。In the above-mentioned FinFET basic structure of the present invention, at least one contour inflection point or contour inflection line of the raised portion is located above the top surface of the STI layer.
本发明上述的FinFET基础结构中，凸起部环绕填充件设置，形成从下往上逐渐缩径的底部锥台轮廓结构。In the above-mentioned FinFET basic structure of the present invention, the protruding portion is disposed around the filler to form a bottom frustum contour structure with a diameter gradually decreasing from bottom to top.
有益效果beneficial effect
本发明的FinFET基础结构及其制造方法通过采用凸起部避免了在帽层的移除时残余Si的问题。特别地，通过形成填充件外壁的第一氧化层，大大缩小填充件的填充空间，从而使后续封帽退火过程中硅材料的填充和去除空间增加，避免硅残留问题。本发明的FinFET基础结构及其制造方法设计新颖，实用性强。The FinFET base structure of the present invention and its fabrication method avoids the problem of residual Si upon removal of the cap layer by employing the raised portion. In particular, by forming the first oxide layer on the outer wall of the filling member, the filling space of the filling member is greatly reduced, thereby increasing the filling and removing space of the silicon material in the subsequent capping annealing process, and avoiding the problem of silicon residues. The FinFET basic structure and the manufacturing method thereof of the present invention have novel design and strong practicability.
附图说明Description of drawings
下面将结合附图及实施例对本发明作进一步说明，附图中：The present invention will be further described below in conjunction with the accompanying drawings and embodiments, in which:
图1示出了一种现有FinFET基础结构的制造方法的层间介质平坦化步骤的流程状态示意图；FIG. 1 shows a schematic flow state diagram of an interlayer dielectric planarization step of a conventional method for manufacturing a FinFET basic structure;
图2示出了图1所示的层间介质平坦化步骤的状态的A-A向的剖面示意图；FIG. 2 shows a schematic cross-sectional view along the A-A direction of the state of the interlayer dielectric planarization step shown in FIG. 1;
图3示出了图1所示的现有FinFET基础结构的制造方法的开槽步骤的流程状态示意图；FIG. 3 shows a schematic flow state diagram of a trenching step of the prior art FinFET basic structure manufacturing method shown in FIG. 1;
图4示出了图3所示的开槽步骤的状态的B-B向的剖面示意图；FIG. 4 shows a schematic cross-sectional view along the B-B direction of the state of the grooving step shown in FIG. 3;
图5示出了图1所示的现有FinFET基础结构的制造方法的通过ALD技术填充SiN步骤的流程状态示意图；FIG. 5 shows a schematic flow state diagram of a step of filling SiN by ALD technology of the existing manufacturing method of the FinFET basic structure shown in FIG. 1;
图6示出了图5所示的通过ALD技术填充SiN步骤的状态的C-C向的剖面示意图；FIG. 6 shows a schematic cross-sectional view in the C-C direction of the state of filling the SiN step by the ALD technology shown in FIG. 5;
图7示出了图1所示的现有FinFET基础结构的制造方法的移除多晶硅层步骤的流程状态示意图；FIG. 7 shows a schematic flow state diagram of the step of removing the polysilicon layer of the conventional method for manufacturing the FinFET basic structure shown in FIG. 1;
图8示出了图7所示的移除多晶硅层步骤的状态的D-D向的剖面示意图；FIG. 8 shows a schematic cross-sectional view in the D-D direction of the state in the step of removing the polysilicon layer shown in FIG. 7;
图9示出了图1所示的现有FinFET基础结构的制造方法的移除虚设层步骤的流程状态示意图；FIG. 9 shows a schematic flow state diagram of a step of removing a dummy layer in the manufacturing method of the existing FinFET basic structure shown in FIG. 1;
图10示出了图9所示的移除虚设层步骤的状态的E-E向的剖面示意图；FIG. 10 shows a schematic cross-sectional view along the E-E direction in the state of the step of removing the dummy layer shown in FIG. 9;
图11示出了图1所示的现有FinFET基础结构的制造方法的氧化膜生长步骤的流程状态示意图；FIG. 11 shows a schematic flow state diagram of the oxide film growth step of the prior art FinFET basic structure manufacturing method shown in FIG. 1;
图12示出了图11所示的氧化膜生长步骤的状态的F-F向的剖面示意图；FIG. 12 shows a schematic cross-sectional view in the direction of F-F in the state of the oxide film growth step shown in FIG. 11;
图13示出了图1所示的现有FinFET基础结构的制造方法的高介电常数材料/TiN沉积步骤的流程状态示意图；FIG. 13 shows a schematic flow state diagram of the high dielectric constant material/TiN deposition step of the conventional method for manufacturing the FinFET basic structure shown in FIG. 1;
图14示出了图13所示的高介电常数材料/TiN沉积步骤的状态的G-G向的剖面示意图；Figure 14 shows a schematic cross-sectional view in the G-G direction of the state of the high dielectric constant material/TiN deposition step shown in Figure 13;
图15示出了图1所示的现有FinFET基础结构的制造方法的帽层的形成步骤的流程状态示意图；FIG. 15 shows a schematic flow state diagram of the forming step of the cap layer of the conventional method for manufacturing the FinFET basic structure shown in FIG. 1;
图16示出了图15所示的帽层的形成步骤的状态的H-H向的剖面示意图；FIG. 16 shows a schematic cross-sectional view in the H-H direction of the state of the capping layer forming step shown in FIG. 15;
图17示出了图1所示的现有FinFET基础结构的制造方法的帽层的移除步骤的流程状态示意图；FIG. 17 shows a flow state schematic diagram of the removing step of the cap layer of the conventional method for manufacturing the FinFET basic structure shown in FIG. 1;
图18示出了图17所示的帽层的移除步骤的状态的I-I向的剖面示意图；FIG. 18 shows a schematic cross-sectional view along the I-I direction of the state of the removal step of the cap layer shown in FIG. 17;
图19示出了图1所示的现有FinFET基础结构的制造方法的金属栅极的形成步骤的流程状态示意图；FIG. 19 shows a schematic flow state diagram of a metal gate formation step of the prior art FinFET basic structure manufacturing method shown in FIG. 1;
图20示出了图19所示的金属栅极的形成步骤的状态的J-J向的剖面示意图；FIG. 20 shows a schematic cross-sectional view of the metal gate shown in FIG. 19 in the J-J direction in the state of the forming step;
图21示出了本发明优选实施例的FinFET基础结构的制造方法的第一步骤状态示意图；FIG. 21 shows a schematic diagram of the first step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention;
图22示出了本发明优选实施例的FinFET基础结构的制造方法的第二步骤状态示意图；FIG. 22 is a schematic diagram showing the second step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention;
图23示出了本发明优选实施例的FinFET基础结构的制造方法的第三步骤状态示意图；FIG. 23 shows a schematic diagram of the third step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention;
图24示出了本发明优选实施例的FinFET基础结构的制造方法的第四步骤状态示意图；FIG. 24 shows a schematic diagram of the fourth step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention;
图25示出了本发明优选实施例的FinFET基础结构的制造方法的第五步骤状态示意图；FIG. 25 shows a schematic diagram of the fifth step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention;
图26示出了本发明优选实施例的FinFET基础结构的制造方法的第六步骤状态示意图；FIG. 26 shows a schematic diagram of the sixth step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention;
图27示出了本发明优选实施例的FinFET基础结构的制造方法的第七步骤状态示意图；FIG. 27 shows a schematic diagram of the seventh step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention;
图28示出了本发明优选实施例的FinFET基础结构的制造方法的第八步骤状态示意图；FIG. 28 shows a schematic diagram of the eighth step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention;
图29示出了本发明优选实施例的FinFET基础结构的制造方法的第九步骤状态示意图；FIG. 29 shows a state schematic diagram of the ninth step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention;
图30示出了本发明优选实施例的FinFET基础结构的制造方法的第十步骤状态示意图。FIG. 30 shows a state schematic diagram of the tenth step of the manufacturing method of the FinFET basic structure according to the preferred embodiment of the present invention.
具体实施方式Detailed ways
为了使本发明的技术目的、技术方案以及技术效果更为清楚，以便于本领域技术人员理解和实施本发明，下面将结合附图及具体实施例对本发明做进一步详细的说明。In order to make the technical purpose, technical solutions and technical effects of the present invention clearer, and to facilitate those skilled in the art to understand and implement the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
参照图21-图30，图21示出了本发明优选实施例的FinFET基础结构的制造方法的第一步骤状态示意图；图22示出了本发明优选实施例的FinFET基础结构的制造方法的第二步骤状态示意图；图23示出了本发明优选实施例的FinFET基础结构的制造方法的第三步骤状态示意图；图24示出了本发明优选实施例的FinFET基础结构的制造方法的第四步骤状态示意图；图25示出了本发明优选实施例的FinFET基础结构的制造方法的第五步骤状态示意图；图26示出了本发明优选实施例的FinFET基础结构的制造方法的第六步骤状态示意图；图27示出了本发明优选实施例的FinFET基础结构的制造方法的第七步骤状态示意图；图28示出了本发明优选实施例的FinFET基础结构的制造方法的第八步骤状态示意图；图29示出了本发明优选实施例的FinFET基础结构的制造方法的第九步骤状态示意图；图30示出了本发明优选实施例的FinFET基础结构的制造方法的第十步骤状态示意图。具体地，FinFET基础结构的制造方法包括以下步骤：21-30, FIG. 21 shows a schematic diagram of the first step of the manufacturing method of the FinFET base structure of the preferred embodiment of the present invention; FIG. 22 shows the first step of the manufacturing method of the FinFET base structure of the preferred embodiment of the present invention. Two-step state schematic diagram; FIG. 23 shows the third step state schematic diagram of the manufacturing method of the FinFET base structure of the preferred embodiment of the present invention; FIG. 24 shows the fourth step of the manufacturing method of the FinFET base structure of the preferred embodiment of the present invention. Schematic diagram of the state; FIG. 25 shows a schematic state diagram of the fifth step of the manufacturing method of the FinFET base structure of the preferred embodiment of the present invention; FIG. 26 shows the state schematic diagram of the sixth step of the manufacturing method of the FinFET base structure of the preferred embodiment of the present invention 27 shows a schematic diagram of the seventh step of the manufacturing method of the FinFET basic structure of the preferred embodiment of the present invention; FIG. 28 shows the schematic diagram of the eighth step of the manufacturing method of the FinFET basic structure of the preferred embodiment of the present invention; 29 shows a state schematic diagram of the ninth step of the manufacturing method of the FinFET basic structure of the preferred embodiment of the present invention; FIG. 30 shows a state schematic diagram of the tenth step of the manufacturing method of the FinFET basic structure of the preferred embodiment of the present invention. Specifically, the manufacturing method of the FinFET base structure includes the following steps:
步骤1、提供基体，该基体包括STI层100、插设在STI层100上的多个鳍片200、虚设层300以及覆盖在STI层100和虚设层300上的多晶硅层400，如图21所示；虚设层300覆盖设置在鳍片200的处于STI层100顶面上方的外壁上；Step 1. Provide a base, which includes the STI layer 100, a plurality of fins 200 inserted on the STI layer 100, a dummy layer 300, and a polysilicon layer 400 covering the STI layer 100 and the dummy layer 300, as shown in FIG. 21 . The dummy layer 300 is covered and arranged on the outer wall of the fin 200 above the top surface of the STI layer 100;
在本步骤中，STI层100和虚设层300均采用SiO 2。 In this step, both the STI layer 100 and the dummy layer 300 are made of SiO 2 .
步骤2、通过刻蚀技术在基体上开设凹槽500；该凹槽500贯穿多晶硅层400，延伸至STI层100的内部，如图22所示；Step 2, opening a groove 500 on the substrate by etching technology; the groove 500 penetrates the polysilicon layer 400 and extends to the interior of the STI layer 100, as shown in FIG. 22;
步骤3、在凹槽500的内壁的靠近其开口的一部分氧化形成第一氧化层510，使凹槽500的槽底凸出形成凸槽530，如图23所示；Step 3, oxidizing a part of the inner wall of the groove 500 close to the opening to form a first oxide layer 510, so that the bottom of the groove 500 is protruded to form a convex groove 530, as shown in FIG. 23;
在本步骤中，通过控制工艺条件，使得第一氧化层510的厚度小于虚设层300的厚度，以便后续去除虚设层的过程中，一并去除第一氧化层且确保第一氧化层的完全去除。In this step, by controlling the process conditions, the thickness of the first oxide layer 510 is smaller than the thickness of the dummy layer 300, so that the first oxide layer is removed together and the complete removal of the first oxide layer is ensured during the subsequent removal of the dummy layer. .
在本步骤中，在加热条件下通过氧化剂氧化多晶硅层400的方法，可以在凹槽500的内壁上生成第一氧化层510，同时，也可以实现使凹槽500的槽底凸出形成凸槽530。In this step, the first oxide layer 510 can be formed on the inner wall of the groove 500 by oxidizing the polysilicon layer 400 with an oxidant under heating conditions, and at the same time, the groove bottom of the groove 500 can be protruded to form a convex groove 530.
步骤4、在凹槽500和凸槽530中填充填充材料，从而形成填充件520；其中，填充在凸槽530内的填充材料形成填充件520的凸起部521，如图24所示；Step 4. Filling the groove 500 and the convex groove 530 with a filling material to form the filling member 520; wherein, the filling material filled in the convex groove 530 forms the convex portion 521 of the filling member 520, as shown in FIG. 24 ;
在本步骤中，填充材料采用SiN、SiON、SiOC、SiOCN、SiCN、SiC或者金属氧化物，其中，金属氧化物采用Al 2O 3、TiO 2、铪的氧化物或者锆的氧化物。 In this step, the filling material is SiN, SiON, SiOC, SiOCN, SiCN, SiC or metal oxide, wherein the metal oxide is Al 2 O 3 , TiO 2 , hafnium oxide or zirconium oxide.
在本实施例中，凸起部521环绕填充件520设置，形成从下往上逐渐缩径的底部锥台轮廓结构。In this embodiment, the protruding portion 521 is disposed around the filler 520 to form a bottom frustoconical profile structure with a diameter gradually decreasing from bottom to top.
进一步地，所述填充件是用于隔离相邻的栅极。Further, the filler is used to isolate adjacent gates.
步骤5、移除多晶硅层400，如图25所示；再移除虚设层300和第一氧化层510，使得填充件520的凸起部521暴露出来，如图26所示；然后在鳍片200的处于STI层100顶面上方的外壁上形成第二氧化层540；然后先后通过沉积技术形成高介电常数材料层600和第一TiN层700；其中，高介电常数材料层600分别覆盖在第二氧化层540外壁、STI层100顶面以及填充件520的位于STI层100顶面上方的外壁上；第一TiN层700覆盖在高介电常数材料层600上，如图27所示；Step 5. Remove the polysilicon layer 400, as shown in FIG. 25; then remove the dummy layer 300 and the first oxide layer 510, so that the protrusions 521 of the filler 520 are exposed, as shown in FIG. 26; A second oxide layer 540 is formed on the outer wall of 200 above the top surface of the STI layer 100; then a high dielectric constant material layer 600 and a first TiN layer 700 are successively formed by deposition techniques; wherein, the high dielectric constant material layer 600 respectively covers On the outer wall of the second oxide layer 540, the top surface of the STI layer 100, and the outer wall of the filler 520 above the top surface of the STI layer 100; the first TiN layer 700 covers the high dielectric constant material layer 600, as shown in FIG. 27 ;
高介电常数材料层600是指介电常数高于SiO2的材料。The high dielectric constant material layer 600 refers to a material whose dielectric constant is higher than that of SiO 2 .
在本步骤中，使得填充件520的凸起部521暴露出来包括：使凸起部521的至少一个轮廓转折点或轮廓转折线位于STI层100顶面上方的步骤。In this step, exposing the protruding portion 521 of the filler 520 includes: making at least one contour inflection point or contour inflection line of the protruding portion 521 located above the top surface of the STI layer 100 .
优选地，在本步骤中，高介电常数材料层600可采用 HfO 2、TiO 2、HfZrO、HfSiNO、Ta 2O 5、ZrO 2、ZrSiO 2或者Al 2O 3。 Preferably, in this step, the high dielectric constant material layer 600 can be made of HfO 2 , TiO 2 , HfZrO, HfSiNO, Ta 2 O 5 , ZrO 2 , ZrSiO 2 or Al 2 O 3 .
步骤6、在第一TiN层700上形成帽层800，并封帽退火，如图28所示；然后移除帽层800，如图29所示，再在已被移除的帽层800的位置布置金属层910以形成金属栅极，如图30所示。帽层800为Si制成。Step 6, forming a cap layer 800 on the first TiN layer 700, and capping annealing, as shown in FIG. 28; then removing the cap layer 800, as shown in FIG. A metal layer 910 is positioned to form a metal gate, as shown in FIG. 30 . The cap layer 800 is made of Si.
在本步骤中，如图30所示，在移除帽层800后，还包括先后通过沉积方法形成TaN层920、第二TiN层930，然后再在第二TiN层930上布置金属层910以形成金属栅极。优选地，金属层910采用W。In this step, as shown in FIG. 30 , after removing the cap layer 800 , the steps further include forming a TaN layer 920 and a second TiN layer 930 by a deposition method, and then arranging a metal layer 910 on the second TiN layer 930 to A metal gate is formed. Preferably, the metal layer 910 adopts W.
通过上述FinFET基础结构的制造方法，通过采用凸起部避免了在帽层的移除时残余Si的问题。With the above-described manufacturing method of the FinFET base structure, the problem of residual Si upon removal of the cap layer is avoided by employing the raised portion.
具体地，本发明中填充凹槽包括位于多晶硅层中的上部分和深入STI层中的槽底，利用多晶硅层和STI层两种材料不一致，在凹槽中多晶硅层的内壁氧化形成第一氧化层，而STI层的氧化硅材质不受其影响，以使凹槽的槽底凸出形成凸槽。Specifically, in the present invention, the filling groove includes an upper part located in the polysilicon layer and a groove bottom deep in the STI layer, and the inner wall of the polysilicon layer in the groove is oxidized to form a first oxide by using inconsistent materials of the polysilicon layer and the STI layer. layer, and the silicon oxide material of the STI layer is not affected by it, so that the groove bottom of the groove protrudes to form a convex groove.
其后，在虚设层去除并重新沉积第二氧化层的过程中，一是去除虚设层的同时完整去除第一氧化层，无需增加额外的去除步骤；二是通过去除虚设层，确保凸起部高于STI层的表面，使其暴露。After that, in the process of removing the dummy layer and redepositing the second oxide layer, firstly, the first oxide layer is completely removed while removing the dummy layer, without adding an additional removal step; above the surface of the STI layer, leaving it exposed.
进一步地，如图30所示，本发明还提出了一种FinFET基础结构，包括基体；该基体包括STI层100、插设在STI层100上的多个鳍片200；Further, as shown in FIG. 30 , the present invention also provides a FinFET basic structure, including a base body; the base body includes an STI layer 100 and a plurality of fins 200 interposed on the STI layer 100 ;
FinFET基础结构还包括插设在STI层100上的填充件520；填充件520底部的侧壁上凸出形成有凸起部521；该凸起部521突出于STI层100顶面上；The FinFET basic structure further includes a filler 520 inserted on the STI layer 100; a protrusion 521 is formed protruding from the sidewall of the bottom of the filler 520; the protrusion 521 protrudes from the top surface of the STI layer 100;
FinFET基础结构还包括覆盖在基体以及填充件520侧壁的位于STI层100上方的部分上的高介电常数材料层600；高介电常数材料层600上覆盖设置有第一TiN层700；第一TiN层700上覆盖设置有TaN层920，该TaN层920上覆盖设置有第二TiN层930，第二TiN层930上覆盖设置有金属层910。The FinFET basic structure further includes a high dielectric constant material layer 600 covering the base and the portion of the sidewall of the filler 520 above the STI layer 100; the high dielectric constant material layer 600 is covered with a first TiN layer 700; A TiN layer 700 is covered with a TaN layer 920 , the TaN layer 920 is covered with a second TiN layer 930 , and the second TiN layer 930 is covered with a metal layer 910 .
在上述技术方案中，凸起部521的至少一个轮廓转折点或轮廓转折线位于STI层100顶面上方；在本实施例中，凸起部521环绕填充件520设置，形成从下往上逐渐缩径的底部锥台轮廓结构。In the above technical solution, at least one contour inflection point or contour inflection line of the raised portion 521 is located above the top surface of the STI layer 100 ; in this embodiment, the raised portion 521 is arranged around the filler 520 to form a gradual taper from bottom to top Diameter bottom frustum contour structure.
在上述技术方案中，STI层100采用SiO 2。 In the above technical solution, the STI layer 100 is made of SiO 2 .
填充件520采用SiN、SiON、SiOC、SiOCN、SiCN、SiC或者金属氧化物，其中，金属氧化物采用Al 2O 3、TiO 2、铪的氧化物或者锆的氧化物。 The filler 520 is made of SiN, SiON, SiOC, SiOCN, SiCN, SiC or metal oxide, wherein the metal oxide is made of Al 2 O 3 , TiO 2 , hafnium oxide or zirconium oxide.
应当理解的是，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，而所有这些改进和变换都应属于本发明所附权利要求的保护范围。It should be understood that, for those skilled in the art, improvements or changes can be made according to the above description, and all these improvements and changes should fall within the protection scope of the appended claims of the present invention.

Claims (10)

  1. 一种FinFET基础结构的制造方法，其特征在于，包括以下步骤： A method for manufacturing a FinFET base structure, comprising the following steps:
    步骤S1、提供基体，然后通过刻蚀技术在基体上开设凹槽（500）；Step S1, providing a substrate, and then opening a groove (500) on the substrate by etching technology;
    步骤S2、在凹槽（500）内壁的靠近其开口的一部分氧化形成第一氧化层（510），使凹槽（500）槽底凸出形成凸槽（530）；Step S2, forming a first oxide layer (510) by oxidizing a part of the inner wall of the groove (500) close to its opening, so that the bottom of the groove (500) is protruded to form a convex groove (530);
    步骤S3、在凹槽（500）和凸槽（530）中填充填充材料，从而形成填充件（520）；其中，填充在凸槽（530）内的填充材料形成填充件（520）的凸起部（521）；Step S3 , filling the groove ( 500 ) and the convex groove ( 530 ) with a filling material to form a filling piece ( 520 ); wherein, the filling material filled in the convex groove ( 530 ) forms the protrusion of the filling piece ( 520 ) Ministry(521);
    步骤S4、通过移除基体的一部分，从而使得填充件（520）的凸起部（521）暴露出来；Step S4, by removing a part of the base body, so that the convex part (521) of the filler (520) is exposed;
    步骤S5、形成帽层（800），以使帽层（800）覆盖填充件（520）的凸起部（521）；然后退火移除帽层（800）；再在已被移除的帽层（800）的位置布置金属层（910）以形成金属栅极。Step S5, forming a cap layer (800) so that the cap layer (800) covers the convex portion (521) of the filler (520); then annealing to remove the cap layer (800); A metal layer (910) is disposed at the location of (800) to form a metal gate.
  2. 根据权利要求1所述的FinFET基础结构的制造方法，其特征在于， The method of manufacturing a FinFET base structure according to claim 1, wherein:
    在步骤S1中，该基体包括STI层（100）、插设在STI层（100）上的多个鳍片（200）、虚设层（300）以及覆盖在STI层（100）和虚设层（300）上的多晶硅层（400），虚设层（300）覆盖设置在鳍片（200）的处于STI层（100）顶面上方的外壁上；凹槽（500）贯穿多晶硅层（400），并延伸至STI层（100）内部。In step S1, the base body includes an STI layer (100), a plurality of fins (200) interposed on the STI layer (100), a dummy layer (300), and covering the STI layer (100) and the dummy layer (300) ) on the polysilicon layer (400), the dummy layer (300) is covered and disposed on the outer wall of the fin (200) above the top surface of the STI layer (100); the groove (500) penetrates the polysilicon layer (400) and extends to the inside of the STI layer (100).
  3. 根据权利要求2所述的FinFET基础结构的制造方法，其特征在于，步骤S4还包括：移除多晶硅层（400）；再移除虚设层（300）和第一氧化层（510），使得填充件（520）的凸起部（521）暴露出来。 The method for manufacturing a FinFET basic structure according to claim 2, wherein step S4 further comprises: removing the polysilicon layer (400); and then removing the dummy layer (300) and the first oxide layer (510) so as to fill the The raised portion (521) of the piece (520) is exposed.
  4. 根据权利要求3所述的FinFET基础结构的制造方法，其特征在于，步骤S5还包括：在鳍片（200）的处于STI层（100）顶面上方的外壁上形成第二氧化层（540）；然后先后通过沉积技术形成高介电常数材料层（600）和第一TiN层（700）；其中，高介电常数材料层（600）分别覆盖在第二氧化层（540）外壁、STI层（100）顶面以及填充件（520）的位于STI层（100）顶面上方的外壁上；第一TiN层（700）覆盖在高介电常数材料层（600）上；之后，在第一TiN层（700）上形成帽层（800）。The method for manufacturing a FinFET basic structure according to claim 3, wherein step S5 further comprises: forming a second oxide layer (540) on the outer wall of the fin (200) above the top surface of the STI layer (100) and then successively form a high dielectric constant material layer (600) and a first TiN layer (700) through deposition techniques; wherein, the high dielectric constant material layer (600) covers the outer wall of the second oxide layer (540) and the STI layer respectively (100) the top surface and the outer wall of the filler (520) above the top surface of the STI layer (100); the first TiN layer (700) overlies the high dielectric constant material layer (600); A cap layer (800) is formed on the TiN layer (700).
  5. 根据权利要求4所述的FinFET基础结构的制造方法，其特征在于， STI层（100）和虚设层（300）均采用SiO 2；第一氧化层（510）的厚度要小于虚设层（300）的厚度； The method for manufacturing a FinFET basic structure according to claim 4, characterized in that, both the STI layer (100) and the dummy layer (300) are made of SiO 2 ; and the thickness of the first oxide layer (510) is smaller than that of the dummy layer (300) thickness of;
    填充材料采用SiN、SiON、SiOC、SiOCN、SiCN、SiC或者金属氧化物，其中，金属氧化物采用Al 2O 3、TiO 2、铪的氧化物或者锆的氧化物； The filling material is SiN, SiON, SiOC, SiOCN, SiCN, SiC or metal oxide, wherein the metal oxide is Al 2 O 3 , TiO 2 , hafnium oxide or zirconium oxide;
    高介电常数材料层（600）采用 HfO 2、TiO 2、HfZrO、HfSiNO、Ta 2O 5、ZrO 2、ZrSiO 2或者Al 2O 3； The high dielectric constant material layer (600) adopts HfO 2 , TiO 2 , HfZrO, HfSiNO, Ta 2 O 5 , ZrO 2 , ZrSiO 2 or Al 2 O 3 ;
    金属层（910）采用W。The metal layer (910) uses W.
  6. 根据权利要求1所述的FinFET基础结构的制造方法，其特征在于，在步骤S4中，使得填充件（520）的凸起部（521）暴露出来包括：使凸起部（521）的至少一个轮廓转折点或轮廓转折线位于STI层（100）顶面上方的步骤。 The method for manufacturing a FinFET base structure according to claim 1, characterized in that, in step S4, exposing the protruding portion (521) of the filler (520) comprises: exposing at least one of the protruding portions (521). A step in which the contour turning point or contour turning line is above the top surface of the STI layer (100).
  7. 根据权利要求1所述的FinFET基础结构的制造方法，其特征在于，在步骤S5中，在移除帽层（800）后，还包括先后通过沉积方法形成TaN层（920）、第二TiN层（930），然后再在第二TiN层（930）上布置金属层（910）以形成金属栅极的步骤。 The method for manufacturing a FinFET basic structure according to claim 1, characterized in that, in step S5, after removing the cap layer (800), it further comprises forming a TaN layer (920) and a second TiN layer by a deposition method successively (930), and then disposing a metal layer (910) on the second TiN layer (930) to form a metal gate.
  8. 一种FinFET基础结构，其特征在于，包括基体，该基体包括STI层（100）；FinFET基础结构还包括插设在STI层（100）上的填充件（520）；填充件（520）底部的侧壁上凸出形成有凸起部（521）；该凸起部（521）突出于STI层（100）顶面上； A FinFET basic structure, characterized in that it includes a base body, and the base body includes an STI layer (100); the FinFET basic structure further includes a filling member (520) interposed on the STI layer (100); A raised portion (521) is formed protruding from the side wall; the raised portion (521) protrudes from the top surface of the STI layer (100);
    FinFET基础结构还包括覆盖在STI层（100）以及填充件（520）侧壁的位于STI层（100）上方的部分上的金属栅极。The FinFET infrastructure also includes a metal gate overlying the STI layer (100) and the portion of the sidewall of the filler (520) that is above the STI layer (100).
  9. 根据权利要求8所述的FinFET基础结构，其特征在于， 凸起部（521）的至少一个轮廓转折点或轮廓转折线位于STI层（100）顶面上方。 The FinFET infrastructure of claim 8, wherein: At least one contour inflection point or contour inflection line of the raised portion (521) is located above the top surface of the STI layer (100).
  10. 根据权利要求8所述的FinFET基础结构，其特征在于，凸起部（521）环绕填充件（520）设置，形成从下往上逐渐缩径的底部锥台轮廓结构。 The FinFET basic structure according to claim 8, characterized in that the protruding part (521) is arranged around the filler (520) to form a bottom frustum contour structure with a diameter gradually decreasing from bottom to top.
PCT/CN2021/141852 2020-12-29 2021-12-28 Finfet basic structure and manufacturing method therefor WO2022143587A1 (en)

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CN108493156A (en) * 2017-02-13 2018-09-04 格芯公司 Grid notch is integrated and relevant apparatus
US20190131428A1 (en) * 2017-10-30 2019-05-02 Globalfoundries Inc. Methods of forming replacement gate structures on transistor devices
CN110416160A (en) * 2018-04-27 2019-11-05 台湾积体电路制造股份有限公司 The manufacturing method of semiconductor device
US20190371912A1 (en) * 2018-05-29 2019-12-05 International Business Machines Corporation Gate cut in rmg

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108493156A (en) * 2017-02-13 2018-09-04 格芯公司 Grid notch is integrated and relevant apparatus
US20190131428A1 (en) * 2017-10-30 2019-05-02 Globalfoundries Inc. Methods of forming replacement gate structures on transistor devices
CN110416160A (en) * 2018-04-27 2019-11-05 台湾积体电路制造股份有限公司 The manufacturing method of semiconductor device
US20190371912A1 (en) * 2018-05-29 2019-12-05 International Business Machines Corporation Gate cut in rmg

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