WO2022143084A1

WO2022143084A1 - Slice preparation method for ultra-thin silicon wafer, ultra-thin silicon wafer and solar cell

Info

Publication number: WO2022143084A1
Application number: PCT/CN2021/136808
Authority: WO
Inventors: 吴兆; 徐琛; 李子峰; 靳金玲; 解俊杰
Original assignee: 隆基绿能科技股份有限公司
Priority date: 2020-12-29
Filing date: 2021-12-09
Publication date: 2022-07-07

Abstract

The present disclosure provides an ultra-thin silicon wafer slicing method, an ultra-thin silicon wafer, and a solar cell, and relates to the technical field of solar photovoltaic. A defect layer is provided below a surface layer of a silicon block body, and in this case, the surface layer can be heated, such that the surface layer on one side of the defect layer obtains a thermal expansion stress, and the silicon block body on the other side of the defect layer generates a stress gradient, and when the thermal expansion stress is not applied, the surface layer and the silicon block body are more easily separated from the position of the defect layer, thereby reducing the requirements for defect density of the defect layer, improving the setting rate of the defect layer and the crystalline quality of the surface layer. Due to the thermal expansion stress applied to the surface layer, the requirements of applying stress on the edge of the surface layer can be reduced in the process of peeling the surface layer, such that damage to the ultra-thin silicon wafer is avoided, and the quality of the ultra-thin silicon wafer obtained by slicing is improved. Therefore, the ultra-thin silicon wafer provided by embodiments of the present disclosure has the advantages of high production rate, good repeatability and high product yield, and can obtain the ultra-thin silicon wafer with high quality.

Description

A kind of slice preparation method of ultra-thin silicon wafer, ultra-thin silicon wafer and solar cell

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of the Chinese patent application with the application number 202011603101.X and titled "A method for preparing an ultra-thin silicon wafer, an ultra-thin silicon wafer and a solar cell" filed with the China Patent Office on December 29, 2020 , and filed with the Chinese Patent Office on December 29, 2020, with the application number 202011603161.X, titled "A Slicing Method for Ultra-thin Silicon Wafers, Ultra-thin Silicon Wafers, and Solar Cells", the entire contents of which are incorporated herein by reference Applying.

technical field

The present disclosure relates to the technical field of solar photovoltaics, and in particular, to a method for preparing ultrathin silicon wafer slices, an ultrathin silicon wafer and a solar cell.

Background technique

In the preparation of crystalline silicon solar cells, while ensuring high conversion efficiency, reducing the thickness of the silicon wafer can effectively reduce the photovoltaic production cost, component cost and levelized cost of energy (LCOE).

Ultra-thin silicon wafers refer to silicon wafers with a thickness of less than 100 μm, which are mainly cut by diamond wire slicing. Due to the limitation of the diameter of the diamond wire and the process method, it is difficult to obtain silicon wafers with a thickness of less than 100 μm, and the thickness is 50 μm. The following silicon wafers are more difficult to prepare; alternatively, a defect layer can also be provided below the surface of the silicon block, such as hydrogen ion implantation, laser nonlinear absorption, etc. below the surface of the silicon block, and then the defect layer above the surface of the silicon block. The surface layer is partially peeled off, and the separated surface layer is used as an ultra-thin silicon wafer.

However, in order to facilitate peeling, the sacrificial layer needs a higher defect density, and the higher defect density may lead to a lower quality of the ultra-thin silicon wafer produced by epitaxy; Surface stress, however, the current method for applying surface stress is difficult to ensure the complete peeling of the ultra-thin silicon wafer while effectively reducing the damage to the ultra-thin silicon wafer.

However, this method has a high demand for the defect density of the defect layer, so that the setting rate of the defect layer is slow and the diffusion distance is long, which affects the quality of the surface layer, and it is difficult to effectively peel off the surface layer; The layer can provide large thermal stress to the surface of the silicon block, thereby peeling off the surface layer of the silicon block, but the material of the stress layer is required to be high, and a large stress needs to be provided to peel off the surface layer, which may lead to ultra-thin stripping. The silicon wafer is curled, and there are many internal stress and defects, resulting in low quality of the ultra-thin silicon wafer.

Overview

The present disclosure provides a method for slicing ultra-thin silicon wafers, an ultra-thin silicon wafer and a solar cell, aiming to improve the slicing production rate, process repeatability, and product yield of ultra-thin silicon wafers, and obtain high-quality ultra-thin silicon wafers .

In a first aspect, an embodiment of the present disclosure provides a method for slicing an ultra-thin silicon wafer, the method comprising:

A defect layer is arranged under the surface layer of the silicon block;

Electromagnetic induction heating is performed on the surface layer, the penetration depth δ of the electromagnetic induction heating does not exceed the depth of the defect layer, and the silicon block and the epitaxial layer are formed at the edge at the same time or after the electromagnetic induction heating. initial separation interface;

Starting from the initial separation interface, the surface layer is gradually peeled off from the silicon bulk to obtain an ultra-thin silicon wafer.

Optionally, the step of performing electromagnetic induction heating on the surface layer includes:

Electromagnetic induction heating is performed on the surface layer by electromagnetic waves of a preset frequency, and the preset frequency is a single frequency or an adjustable frequency; more preferably, the penetration depth δ of the electromagnetic induction heating does not exceed the depth of the defect layer ;

In the present disclosure, the skin depth (electromagnetic wave penetration depth) can be controlled by adjusting the frequency of the electromagnetic wave, and the skin depth is the penetration depth δ of the electromagnetic wave in the surface layer, wherein the formula for controlling the skin depth is as follows:

In the above formula (1), μ0 is the magnetic permeability, σ is the electrical conductivity, and ω is the frequency of the electromagnetic wave. When the doping concentration of the silicon material is fixed, the magnetic permeability and the electrical conductivity are fixed. At this time, the frequency of the electromagnetic wave can be adjusted accurately. skin depth, which controls the depth of heat applied to the surface layer.

Optionally, the single frequency is more than 100MHz;

Optionally, the adjustable frequency is set in the following manner:

Use electromagnetic waves above 100GHz to heat from room temperature to preset temperature;

From a preset temperature, electromagnetic waves of 1 Hz to 100 GHz are used for heating, and the preset temperature range is 100° C. to 300° C.

Optionally, the single frequency is above 1 GHz.

Optionally, after the defect layer is disposed under the surface layer of the silicon block, the method further includes:

A support structure is provided on the surface of the skin.

Optionally, the material of the support structure includes at least one of organic material, glass, transparent alumina crystal, and metal material.

Optionally, the organic material includes at least one of polyimide, epoxy resin, polymethyl methacrylate, ethylene-ethyl acetate copolymer and polyvinyl butyral;

Optionally, the metal material includes at least one of a metal grid, a metal film, a metal wire, a metal sheet and a metal plate.

Optionally, the thickness of the surface layer is 1 μm˜100 μm.

Optionally, the thickness of the defect layer is less than or equal to 30% of the thickness of the surface layer.

Optionally, the method for gradually peeling off the surface layer from the silicon block starting from the initial separation interface includes at least one of the following:

External forces pull, curl, and elevate the surface layer.

In a second aspect, an embodiment of the present disclosure provides an ultra-thin silicon wafer, and the ultra-thin silicon wafer is prepared by the method for slicing an ultra-thin silicon wafer described in the first aspect.

In a third aspect, embodiments of the present disclosure provide a solar cell including the ultra-thin silicon wafer described in the second aspect.

In the embodiment of the present disclosure, a defect layer is arranged under the surface layer of the silicon block. At this time, the surface layer can be heated, so that the surface layer on one side of the defect layer obtains thermal expansion stress, and the silicon block on the other side of the defect layer generates a stress gradient, Compared with when no thermal expansion stress is applied, the surface layer and the silicon bulk are easier to separate from the position of the defect layer, thereby reducing the requirement for the defect density of the defect layer, improving the setting rate of the defect layer and the crystal quality of the surface layer; The thermal expansion stress exerted by the surface layer can also reduce the requirement of applying stress to the edge of the surface layer during the process of peeling off the surface layer, thereby avoiding damage to the ultra-thin silicon wafer and improving the quality of the ultra-thin silicon wafer obtained by slicing. Therefore, the present disclosure implements The slicing method for ultra-thin silicon wafers provided in the example has high production rate, good repeatability, and high product yield, and can obtain high-quality ultra-thin silicon wafers.

In a fourth aspect, an embodiment of the present disclosure further provides a method for preparing an ultra-thin silicon wafer, the method comprising:

forming a defect layer and an epitaxial layer on the surface of the silicon substrate, and the defect layer is located between the silicon substrate and the epitaxial layer;

heating the silicon substrate to generate thermal stress at the interface of the silicon substrate and the epitaxial layer, and forming the silicon substrate and the epitaxial layer at the edges while or after the heating of the silicon substrate The initial separation interface;

Starting from the initial separation interface, the epitaxial layer is gradually stripped from the silicon substrate.

Optionally, the step of forming the defect layer and the epitaxial layer on the surface of the silicon substrate includes sequentially:

forming the defect layer on the surface of the silicon substrate;

The epitaxial layer is prepared on the defect layer.

preparing the epitaxial layer on the surface of the silicon substrate;

The defect layer is formed at the contact interface between the epitaxial layer and the silicon substrate.

Optionally, in the step of heating the silicon substrate, the temperature gradient at the defect layer is at least 10K/mm.

Optionally, the method for forming the initial separation interface of the silicon substrate and the epitaxial layer at the edge includes at least one of the following:

Mechanical peeling of the epitaxial layer at the edge;

The edge of the contact interface between the silicon substrate and the epitaxial layer is scanned with a laser.

Optionally, after the step of forming the defect layer and the epitaxial layer on the surface of the silicon substrate, the method further includes:

A support structure is provided on the surface of the epitaxial layer.

Optionally, the thickness of the defect layer is less than or equal to 2 μm.

Optionally, the method for gradually peeling off the epitaxial layer from the silicon substrate starting from the initial separation interface includes at least one of the following:

An external force pulls, curls or lifts the epitaxial layer or support structure.

In a fifth aspect, an embodiment of the present disclosure further provides an ultra-thin silicon wafer prepared by the method for preparing an ultra-thin silicon wafer described in the first aspect.

In a sixth aspect, embodiments of the present disclosure provide a solar cell including the ultra-thin silicon wafer described in the second aspect.

In the embodiment of the present disclosure, a defect layer and an epitaxial layer may be formed on a silicon substrate, and the defect layer is between the silicon substrate and the epitaxial layer, and the silicon substrate and the epitaxial layer are heated by heating the silicon substrate. The thermal expansion stress is formed at the interface, and the thermal expansion stress has good stress uniformity, which is convenient for the peeling of the epitaxial layer. Since the thermal expansion stress applied to the silicon substrate reduces the difficulty of peeling off the epitaxial layer, it also reduces the defect density in the defect layer. The lower defect density in the defect layer can effectively improve the quality of the epitaxial layer on the defect layer; at the same time, the thermal expansion stress applied to the silicon substrate also reduces the stress applied when the epitaxial layer is peeled off, avoiding high stress. The destruction of the epitaxial layer improves the yield and efficiency of ultra-thin silicon wafer preparation, and the process repeatability is good.

Brief Description of Drawings

In order to illustrate the technical solutions of the embodiments of the present disclosure more clearly, the following briefly introduces the drawings that are used in the description of the embodiments of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. , for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative labor.

FIG. 1 shows a flow of steps of a method for slicing an ultra-thin silicon wafer provided by an embodiment of the present disclosure;

FIG. 2 shows a flowchart of steps of another method for slicing an ultra-thin silicon wafer provided by an embodiment of the present disclosure;

FIG. 3 shows a schematic cross-sectional view of a support structure provided by an embodiment of the present disclosure;

FIG. 4 shows a flow chart of a slicing process of an ultra-thin silicon wafer provided by an embodiment of the present disclosure;

FIG. 5 shows a flow chart of a slicing process of an ultra-thin silicon wafer provided by an embodiment of the present disclosure;

FIG. 6 shows a flow chart of steps of a method for preparing an ultra-thin silicon wafer provided by an embodiment of the present disclosure;

FIG. 7 shows a flow chart of steps of another method for preparing an ultra-thin silicon wafer provided by an embodiment of the present disclosure;

FIG. 8 shows a flow chart of steps of another method for preparing an ultra-thin silicon wafer provided by an embodiment of the present disclosure;

FIG. 9 shows a schematic diagram of stress distribution during heating of a silicon substrate provided by an embodiment of the present disclosure;

FIG. 10 shows a process flow diagram of a method for preparing an ultra-thin silicon wafer provided by an embodiment of the present disclosure; and

FIG. 11 shows a process flow diagram of another method for preparing an ultra-thin silicon wafer provided by an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, but not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

FIG. 1 shows a flowchart of steps of a method for slicing an ultra-thin silicon wafer provided by an embodiment of the present disclosure. Referring to FIG. 1 , the method may include:

Step 101 , a defect layer is provided under the surface layer of the silicon block.

In the embodiment of the present disclosure, the silicon block may be a single crystal or polycrystalline silicon block obtained by a process such as Czochralski or ingot casting, wherein the size of the silicon block is not particularly limited. Optionally, prior to forming the defect layer, the silicon block may be subjected to processes such as cleaning, polishing, etc., to avoid the influence of impurities attached to the silicon block on subsequent processes. After the silicon bulk is prepared, a defect layer may be provided below the surface layer of the silicon bulk.

In the embodiment of the present disclosure, the surface layer is a silicon layer to be peeled off below the surface of the silicon block. The thickness of the surface layer can be the thickness required for ultra-thin silicon wafers. The surface layer includes a defect layer and a layer structure between the surfaces of the silicon block. Therefore, the surface layer The thickness and shape of the silicon block are related to the setting depth and angle of the defect layer. Those skilled in the art can determine the thickness of the surface layer of the silicon block according to the actual needs of the ultra-thin silicon wafer, and set the defect layer below the surface layer, so as to facilitate the surface layer. stripping.

In the embodiment of the present disclosure, the defect layer has a relatively high density of defect structures. Optionally, the defect structures may include dislocations, line defects, and bulk defects. Therefore, the density of defect structures in the defect layer may be lower than the density of defect structures in the defect layer in the prior art. Optionally, the defect layer can be formed by ion implantation, laser deep etching, chemical etching or any other process. Within the surface of the block, there are at least two discontinuous spacer layers corresponding to parallel planes on the surface, and the formation process and shape of the defect layer are not specifically limited in the embodiments of the present disclosure.

Step 102: Perform electromagnetic induction heating on the surface layer, the penetration depth δ of the electromagnetic induction heating does not exceed the depth of the defect layer, and the silicon block and the silicon block are formed at the edge at the same time or after the electromagnetic induction heating. The initial separation interface of the epitaxial layer.

In the embodiment of the present disclosure, electromagnetic induction heating can be performed on the surface layer, wherein the penetration depth δ of the electromagnetic induction heating does not exceed the depth of the defect layer, so that thermal stress is generated at the interface between the surface layer and the silicon block, which is easy to destroy the defect layer. The surface layer is peeled off.

In the embodiment of the present disclosure, after heating the surface layer or during the heating process, an initial separation interface may be formed between the surface layer and the silicon block, optionally, the surface layer at the edge may be peeled off mechanically, or The edge of the interface between the silicon bulk and the surface layer is scanned with a laser. Since the surface layer has thermal expansion stress due to the heating of the surface layer, the defect layer is easily destroyed under the action of thermal expansion stress, so that the surface layer can form an initial separation interface under the condition that the stress exerted by the edge is small, so that the surface layer and the silicon block are gradually peeled off .

Step 103: Starting from the initial separation interface, gradually peel off the surface layer from the silicon block to obtain an ultra-thin silicon wafer.

In the embodiment of the present disclosure, the silicon block can be peeled off from the initial separation interface, so that the defect layer is further damaged, and the initial separation interface is gradually diffused. The diffusion rate of the separation interface and the control of the diffusion direction can improve the fabrication efficiency of ultra-thin silicon wafers. Alternatively, an auxiliary object can be placed between the surface layer and the silicon block, inserted into the initial separation interface between the silicon block and the surface layer, moved in a direction parallel to the surface layer of the silicon block, or the surface layer and the silicon block can be scanned with a laser. between the blocks, wherein the auxiliary objects may be wedge-shaped structures.

In the embodiment of the present disclosure, the diffusion rate of the initial separation interface can be controlled by controlling the separation rate between the silicon bulk and the surface layer. Optionally, the separation rate should be less than or equal to the lateral conduction of the initial separation interface generated by the defect layer under the action of stress. rate. When the initial separation interface is controlled to gradually diffuse to the entire surface of the silicon block, it can be determined that the silicon block and the surface layer are completely separated, and at this time, the separated surface layer is an ultra-thin silicon wafer.

FIG. 2 shows a flowchart of steps of another ultra-thin silicon wafer slicing method provided by an embodiment of the present disclosure. As shown in FIG. 2 , the method may include:

Step 201 , a defect layer is provided under the surface layer of the silicon block.

In this embodiment of the present disclosure, step 201 can be referred to the relevant description of the foregoing step 101, which is not repeated here in order to avoid repetition.

Optionally, the thickness of the surface layer is 1 μm˜100 μm.

In the embodiment of the present disclosure, the thickness of the surface layer can be any arc between 1 μm and 100 μm, such as 1 μm, 5 μm, 10 μm, 20 μm, 50 μm, 100 μm, etc., according to process conditions, application requirements, etc., so as to meet the thickness requirements of ultra-thin silicon wafers, And avoid the problem of high peeling difficulty when the depth of the defect layer is too shallow.

In the embodiment of the present disclosure, the thickness of the surface layer may correspond to the depth of the defect layer, and the thickness of the defect layer is less than or equal to 30% of the depth of the defect layer inside the surface of the silicon block, so as to achieve efficient separation of the surface layer while avoiding defects Material waste caused by excessively thick layer thickness improves process repeatability and process efficiency. For example, when the thickness of the surface layer is 100 μm, the thickness of the defect layer is less than or equal to 30 μm, and when the thickness of the surface layer is 50 μm, the thickness of the defect layer is less than or equal to 15 μm, The embodiments of the present disclosure do not specifically limit this.

Step 202 , providing a support structure on the surface of the surface layer.

In the embodiment of the present disclosure, a support structure may be provided on the surface of the surface layer to facilitate subsequent peeling operations, wherein the support structure may play a supporting role on the surface layer to ensure the integrity and continuity of the surface layer in subsequent operations, and avoid external stress. The probability of surface cracks and fragments increases the efficiency of stripping ultra-thin silicon wafers and the quality of the obtained ultra-thin silicon wafers. Optionally, the support structure may be a single-layer structure or a composite-layer structure; the support structure may be connected to the surface of the surface layer through adhesion, or may be connected to the surface of the surface layer through an interfacial reaction, which is not specifically limited in this embodiment of the present disclosure .

Optionally, the organic material includes at least one of polyimide, epoxy resin, polymethyl methacrylate, ethylene-ethyl acetate copolymer and polyvinyl butyral.

In the embodiment of the present disclosure, the support structure may be composed of a high temperature-resistant and corrosion-resistant organic material, wherein the organic material may include polyimide, epoxy resin, polymethyl methacrylate, EVA (Ethylene-Vinyl Acetate copolymer, ethylene-ethyl acetate copolymer), polyvinyl butyral, etc.; the supporting structure can also be composed of glass, tempered glass, transparent alumina crystal, etc.; the supporting structure can also be composed of metal materials, wherein the metal materials include metal Grids, metal films, metal wires, metal sheets, metal plates, etc.; or, the support structure may also be composed of two or more composite materials among the above-mentioned materials, which are not specifically limited in the embodiments of the present disclosure.

In the embodiment of the present disclosure, the supporting structure may adopt a comprehensive metal thin layer, a metal plate, and be bonded to the surface layer, or adopt a hollow structure such as a metal grid and a metal wire, and be disposed on the surface layer. Optionally, the supporting structure may be It is obtained by bonding the metal grid to the surface layer with polyimide, or laying the metal grid first and then depositing the dielectric layer, and burying the metal grid in the dielectric layer. The dielectric layer has no electromagnetic heating effect and can play a role in adhesion bonding, or laying a high-temperature metal film or grid on the surface layer for cooling, and connecting the metal and the surface layer by means of heat treatment, which is not specifically limited in the embodiment of the present disclosure.

In the embodiment of the present disclosure, on the basis of the foregoing layer structures, in the case where the support structure includes metal materials, the metal materials can be used as ultra-thin silicon wafers when applied to the preparation of solar cells, and the components of the solar cell structure, such as The metal structure can be an electrode, grid line, etc. on the surface of the solar cell. In this case, the support structure can also have at least one surface layer structure of the solar cell, such as a surface passivation layer, an aperture passivation layer, a transmission layer, and a field effect layer. And metal electrodes, etc., the material is a combination of materials commonly used in the surface layer structure of solar cells, thereby simplifying the preparation process of solar cells and improving the efficiency of the overall process.

FIG. 3 shows a schematic cross-sectional view of a support structure provided by an embodiment of the present disclosure. As shown in FIG. 3 , it includes a silicon block 301 , a defect layer 302 , a surface layer 303 , and a support structure 304 , wherein the support structure 304 includes passivation Structure 3041 and metal structure 3042.

As shown in FIG. 3 , the passivation structure 3041 serves to passivate the surface of the ultra-thin silicon wafer, and at the same time, the area of the metal-silicon contact interface can be reduced, thereby reducing the interface recombination. Optionally, the passivation structure 3041 can be a dielectric A thin film, such as a single layer or a composite layer composed of two or more materials, such as silicon oxide, silicon nitride, aluminum oxide, etc.

Among them, the metal structure 3042 covers the surface of the ultra-thin silicon wafer, and is in contact with the surface of the ultra-thin silicon wafer through the hollow part in the passivation structure 3041, and can be connected with the surface of the ultra-thin silicon wafer through sintering or interface reaction; The area where the structure 3042 is in contact with the ultra-thin silicon wafer may have a localized heavily doped structure; the metal structure 3042 may play a supporting role, and at the same time, through the connection with the ultra-thin silicon wafer, it may be used as an electrode in a solar cell.

In the embodiment of the present disclosure, for the needs of subsequent heating, the support structure can choose a battery surface structure that can withstand temperatures above 250°C, such as PERC (Passivated Emitter and Rear Cell, passivated emitter and back cell), POLO ( The surface structure of POLy-Si on passivating interfacial Oxides, polysilicon oxide selective passivation contact) cell, TOPCon (Tunnel Oxide Passivating Contacts, tunnel oxide passivating contact) cell, etc., can not choose amorphous silicon structure.

In step 203, electromagnetic induction heating is performed on the surface layer by electromagnetic waves of a preset frequency, the preset frequency is a single frequency or an adjustable frequency, and the penetration depth δ of the electromagnetic induction heating does not exceed the depth of the defect layer, In order to form a temperature gradient on both sides of the defect layer, the initial separation interface of the silicon bulk and the epitaxial layer is formed at the edge while or after electromagnetic induction heating.

In the embodiment of the present disclosure, step 203 can be referred to the relevant description of the aforementioned step 102. In order to avoid repetition, it will not be repeated here. The electromagnetic induction heating of the surface layer by electromagnetic waves with a preset frequency can efficiently start hot and accurately control the heating temperature. , thereby improving the heating efficiency of the surface layer and ensuring the uniformity of the surface layer heating, thereby ensuring the uniformity of thermal expansion stress.

In the embodiment of the present disclosure, the preset frequency of the electromagnetic wave may be a single frequency or an adjustable frequency, wherein the single frequency means that the same frequency is used for heating during the adding process, and the adjustable frequency means that the frequency of the electromagnetic wave in the heating process is based on The needs are adjusted within the scope.

Optionally, the single frequency is above 100MHz

In the embodiment of the present disclosure, the single frequency may be above 100 MHz, that is, the frequency of the electromagnetic wave may be 100 MHz, 150 MHz, 200 MHz, 500 MHz, etc., which is not specifically limited in the embodiment of the present disclosure.

Optionally, the single frequency is above 1 GHz.

In the embodiment of the present disclosure, electromagnetic induction heating of the surface layer may be performed directly by electromagnetic waves with a single frequency above 1 GHz, so as to improve the heating efficiency.

Optionally, the adjustable frequency is set in the following manner:

From the preset temperature, the electromagnetic wave of 100MHz～100GHz is used for heating, and the preset temperature range is 100℃～300℃

In the embodiment of the present disclosure, in order to ensure the formation of the temperature gradient on both sides of the defect layer and improve the heating efficiency, the electromagnetic wave with gradient power can be used to heat the surface layer, and the electromagnetic wave above 100 GHz is used to preheat the surface layer. After the temperature of the surface layer reaches the preset temperature, the electromagnetic wave is reduced to 1 Hz to 100 GHz and further heated, so that the penetration depth δ can be more accurately controlled by adjusting the frequency of the electromagnetic wave, and the thermal stress in the heating process can be avoided to cause damage to the surface layer. The present disclosure The embodiment does not specifically limit this.

In the embodiment of the present disclosure, in the case where the support structure formed in step 202 includes a metal material, or the support structure is a metal structure, since the metal is easily heated by AC electromagnetic waves, the connected surface layers can be heated in the form of heat conduction, Therefore, the support structure can also assist the electromagnetic wave heating process in step 203. If the support structure is composed of a composite material of metal mesh and polyimide, or the support structure is a metal film, it can assist the heating of the surface layer and widen the electromagnetic wave during heating. The frequency range is increased, the heating rate is increased, and the temperature uniformity is improved.

In the embodiment of the present disclosure, the temperature gradient on both sides of the defect layer can be formed by controlling the penetration depth δ of the electromagnetic induction heating. Since the thermal expansion stress is different at different temperatures, the defect layer forms a stress gradient relative to the two interface directions, so that the defect layer is It is easier to form the initial separation interface, which is convenient for surface layer peeling, and the process repeatability is good, and high-quality ultra-thin silicon wafers can be obtained with high efficiency. Optionally, the temperature gradient on both sides of the defect layer may be greater than or equal to 50K·mm ⁻¹ , for example, the temperature gradient may be 50K·mm ⁻¹ , 70K·mm ⁻¹ , 100K·mm ⁻¹ , etc., an embodiment of the present disclosure There is no specific restriction on this.

Step 204 , starting from the initial separation interface, gradually peel off the surface layer from the silicon block to obtain an ultra-thin silicon wafer.

In this embodiment of the present disclosure, step 204 may refer to the relevant description of the foregoing step 103, which is not repeated here in order to avoid repetition.

Optionally, implement at least one of the following methods in step 204:

External forces pull, curl, and elevate the surface layer.

In the embodiment of the present disclosure, when a support structure is provided on the surface layer, on the basis of the initial separation interface, operations such as pulling, curling, etc. may be performed on the surface layer or the corresponding position of the initial separation interface on the support structure to apply stress, to lift it from the silicon bulk, wherein the lifting may be to apply stress to the surface layer or at least one location of the support structure against the silicon bulk to lift the peeling to separate the skin from the silicon bulk, such as by ceramic suction cup adsorption or other physical adsorption Absorb the surface layer or the support structure and apply stress to lift the surface layer; the curling can be rolling and peeling the surface layer or the side of the surface layer provided with the support structure, etc., or it can also be lifted and curled at the same time. specific restrictions.

In the embodiment of the present disclosure, a defect layer is arranged under the surface layer of the silicon block. At this time, the surface layer can be heated, so that the surface layer on one side of the defect layer obtains thermal expansion stress, and the silicon block on the other side of the defect layer generates a stress gradient, Compared with when no thermal expansion stress is applied, the surface layer and the silicon bulk are easier to separate from the position of the defect layer, thereby reducing the requirement for the defect density of the defect layer, improving the setting rate of the defect layer and the crystal quality of the surface layer; The thermal expansion stress exerted by the surface layer can also reduce the requirement of applying stress to the edge of the surface layer during the process of peeling off the surface layer, thereby avoiding damage to the ultra-thin silicon wafer and improving the quality of the ultra-thin silicon wafer obtained by slicing. Therefore, the present disclosure implements The slicing method for ultra-thin silicon wafers provided in the example has high production rate, good repeatability, and high product yield, and can obtain high-quality ultra-thin silicon wafers. An embodiment of the present disclosure also provides an ultra-thin silicon wafer, which is prepared by the slicing method of the ultra-thin silicon wafer shown in FIGS. 1 to 3 .

Embodiments of the present disclosure also provide a solar cell, which includes the above-mentioned ultra-thin silicon wafer.

Example 1

FIG. 4 shows a flow chart of a slicing process of an ultra-thin silicon wafer provided by an embodiment of the present disclosure. As shown in FIG. 4 , the process may include:

(1) The silicon block 401 obtained by post-cutting the Czochralski single crystal, the silicon block 401 is cleaned and pre-polished, and then the surface 4011 of the silicon block 401 is polished and cleaned, wherein the surface 4011 is preferably (111) crystal plane;

(2) According to the thickness of the surface layer 403, the setting depth of the defect layer 402 is determined to be 50 μm, and at a depth position of 50 μm below the surface 4011, the defect layer 402 parallel to the surface is set by scanning a focused laser beam, wherein the laser can be a wavelength greater than 1500 nm. Long-wavelength laser, the focusing of the laser can be single-beam focusing or multi-beam focusing, the focal spot diameter of the laser is less than or equal to 3μm, and the focus energy density is greater than or equal to 8×10 ¹² W/m ² to generate nonlinear absorption at the focus position , so as to generate thermomechanical stress to form the defect layer 402, and form the surface layer 403 between the defect layer 402 and the surface 4011;

(3) Lay the support structure 404 of the polyimide film on the surface layer 403 to facilitate the subsequent peeling and transfer operations of the surface layer 403 to provide mechanical support, wherein the polyimide film can withstand a high temperature of 500° C. in a short time. , the surface layer 403 can be stably supported in the subsequent heating;

(4) Use 26GHz radio frequency to heat the surface layer 403, use gradient power for heating, 350W power preheat to the surface layer 403 temperature of 180 ° C, increase to 1kW power for heating, in order to increase the heating rate, and in the preheating process, from silicon The side of the block 401 corresponds to the depth of the defect layer 402, and the pre-stripping point on the side is set by laser scanning. During the heating process after increasing the power, when the surface temperature rises to 450 °C, the side corresponding to the pre-stripping point is upward Pulling the support structure 404 to separate the surface layer 403 from the silicon bulk 401 at the position of the defect layer 402 to form an initial separation interface 4031 that gradually diffuses;

(5) Pull the support structure 404 to the initial separation interface 4031 and gradually diffuse to completely separate the surface layer 403 and the silicon block 401;

(6) The surface layer 403 obtained by peeling is obtained as an ultra-thin silicon wafer, and a support structure 404 is also included on the ultra-thin silicon wafer.

Example 2

FIG. 5 shows a flow chart of a slicing process of an ultra-thin silicon wafer provided by an embodiment of the present disclosure. As shown in FIG. 5 , the process may include:

(1) The silicon block 501 obtained by post-cutting the Czochralski single crystal, the silicon block 501 is cleaned and pre-polished, and then the surface 5011 of the silicon block 501 is polished and cleaned, wherein the surface 5011 is preferably (111) crystal plane;

(2) According to the thickness of the surface layer 503, the setting depth of the defect layer 502 is determined to be 50 μm, and at a depth position of 50 μm below the surface 5011, the defect layer 502 parallel to the surface is set by scanning a focused laser beam, wherein the laser can be a wavelength greater than 1500 nm. Long-wavelength laser, the focusing of the laser can be single-beam focusing or multi-beam focusing, the focal spot diameter of the laser is less than or equal to 3μm, and the focus energy density is greater than or equal to 8×1012W/m2 to generate nonlinear absorption at the focal position, resulting in thermomechanical stress to form the defect layer 502, and to form a surface layer 503 between the defect layer 502 and the surface 5011;

(3) Using 26GHz radio frequency to heat the surface layer 503, using gradient power for heating, 350W power preheating to the surface layer 503 temperature reaching 180 ℃, then increasing to 1kW power for heating to increase the heating rate, and in the preheating process, from silicon The side of the block 501 corresponds to the depth of the defect layer 502, and the pre-stripping point on the side is set by means of laser scanning. The ceramic suction cup is used for adsorption on the side, and the ceramic suction cup is pulled upward to separate the surface layer 503 and the silicon block 501 at the position of the defect layer 502, forming an initial separation interface 5031 that gradually diffuses;

(4) Pull the ceramic suction cup to the initial separation interface 5031 and gradually diffuse to completely separate the surface layer 503 and the silicon block 501;

(5) The surface layer 503 obtained by peeling is obtained as an ultra-thin silicon wafer.

FIG. 6 shows a flowchart of steps of a method for preparing an ultra-thin silicon wafer provided by an embodiment of the present disclosure. As shown in FIG. 6 , the method may include:

Step 601 , forming a defect layer and an epitaxial layer on the surface of a silicon substrate, where the defect layer is located between the silicon substrate and the epitaxial layer.

In the embodiments of the present disclosure, the silicon substrate may be a monocrystalline or polycrystalline silicon bulk obtained by a process such as Czochralski, ingot casting, etc., wherein the size of the silicon substrate is not particularly limited. Optionally, the silicon substrate may be cleaned and polished before forming the defect layer and the epitaxial layer, so as to avoid the influence of the impurities attached on the silicon substrate on the subsequent process. After the silicon substrate is prepared, a defect layer and an epitaxial layer can be formed on the surface of the silicon substrate, wherein any surface of the silicon substrate can be selected according to application requirements.

In the embodiment of the present disclosure, the defect layer has a relatively high density of defect structures. Optionally, the defect structures may include dislocations, line defects, and bulk defects. However, in the subsequent process, the silicon substrate may be heated to assist Therefore, the density of defect structures in the defect layer is lower than the density of defect structures in the defect layer in the prior art. Optionally, the defect layer may be formed by ion implantation, laser deep etching, chemical etching or any other process, and the defect layer may cover the entire surface of the silicon substrate, or may cover at least two spaces on the surface of the silicon substrate. In this region, the formation process and shape of the defect layer are not specifically limited in the embodiments of the present disclosure.

In the embodiment of the present disclosure, the epitaxial layer is an ultra-thin silicon wafer to be peeled off, and the thickness of the epitaxial layer can be set according to the application requirements of the ultra-thin silicon wafer, which is not specifically limited in the embodiment of the present disclosure.

Step 602: Heating the silicon substrate to generate thermal stress at the interface between the silicon substrate and the epitaxial layer, and forming the silicon substrate and the edge at the edge while or after heating the silicon substrate. The initial separation interface of the epitaxial layer.

In the embodiment of the present disclosure, the silicon substrate can be heated to generate thermal stress at the interface between the silicon substrate and the epitaxial layer, wherein the heating depth of the heating can be controlled not to exceed the depth of the interface between the silicon substrate and the epitaxial layer, Therefore, thermal stress is generated at the interface between the silicon substrate and the epitaxial layer. Since there is a defect layer between the silicon substrate and the epitaxial layer, the thermal stress generated at the interface between the silicon substrate and the epitaxial layer can act on the defect layer. The epitaxial layer on the defect layer is easier to be peeled off. Optionally, the heating method for the silicon substrate may be electromagnetic wave heating, infrared heating, etc., which is not specifically limited in this embodiment of the present disclosure.

In the embodiment of the present disclosure, after the silicon substrate is heated, or during the heating process, an initial separation interface between the silicon substrate and the epitaxial layer may be formed at the edge, and the initial separation interface is a defect between the epitaxial layer and the silicon substrate. The separation interface formed after the layer is destroyed, due to the heating of the silicon substrate, the interface between the silicon substrate and the epitaxial layer has thermal expansion stress. The process forms an initial separation interface that gradually diffuses, which reduces the difficulty of the process and improves the efficiency of production and preparation.

Step 603: Starting from the initial separation interface, gradually peel off the epitaxial layer from the silicon substrate.

In the embodiment of the present disclosure, the epitaxial layer may be further peeled off on the basis of the initial separation interface, so that the initial separation interface is gradually diffused, thereby gradually separating the epitaxial layer and the silicon substrate, and the peeled epitaxial layer is the prepared epitaxial layer. Ultra-thin silicon wafers. Optionally, in the process of peeling off the epitaxial layer, other auxiliary methods can be used to improve the diffusion rate of the initial separation interface and control the diffusion direction of the initial separation interface, so as to improve the preparation efficiency of ultra-thin silicon wafers. The separation interface is inserted between the epitaxial layer and the silicon substrate and moves in a direction parallel to the surface layer of the silicon substrate, or a laser can be used to scan the initial separation interface between the epitaxial layer and the silicon substrate, wherein the auxiliary object can be a wedge-shaped structure.

In the embodiment of the present disclosure, the diffusion rate of the initial separation interface can be controlled by controlling the separation rate between the silicon substrate and the epitaxial layer. Optionally, the separation rate should be less than or equal to the damage of the defect layer under the action of stress to generate the initial separation Transverse conduction velocity at the interface. When the initial separation interface is controlled to completely diffuse to the entire defect layer, it can be determined that the silicon substrate and the epitaxial layer are completely separated, and at this time, the separated epitaxial layer is an ultra-thin silicon wafer.

FIG. 7 shows a flowchart of steps of another method for preparing an ultra-thin silicon wafer provided by an embodiment of the present disclosure. As shown in FIG. 7 , the method may include:

Step 701 , forming a defect layer and an epitaxial layer on the surface of a silicon substrate, where the defect layer is located between the silicon substrate and the epitaxial layer.

In this embodiment of the present disclosure, step 701 may correspond to the relevant description of step 601, which is not repeated here in order to avoid repetition.

Optionally, the thickness of the silicon substrate is less than or equal to 20 cm.

In the embodiment of the present disclosure, the thickness of the silicon substrate may be less than or equal to 20 cm, and alternatively, the thickness of the silicon substrate may be 500 μm, 1 mm, 5 mm, 1 cm, 5 cm, 10 cm, 20 cm, etc., to avoid the size of the silicon substrate If the size of the silicon substrate is too large, it is difficult to operate, or the size of the silicon substrate is too small and the process cannot be repeated many times, resulting in low production efficiency, which is not specifically limited in this embodiment of the present disclosure.

Optionally, the thickness of the defect layer may be less than or equal to 2 μm.

in the embodiments of the present disclosure. The thickness of the defect layer can be less than or equal to 2 μm, so as to avoid that the defect layer is too thick and inconvenient to peel off in the subsequent process, which affects the preparation efficiency of ultra-thin silicon wafers.

In the embodiment of the present disclosure, the defect layer is located between the silicon substrate and the epitaxial layer. Optionally, the defect layer may be formed on the surface of the silicon substrate first, and then the epitaxial layer may be formed on the defect layer, or the An epitaxial layer is formed on the surface of the silicon substrate, and then a defect layer is formed between the silicon substrate and the epitaxial layer. The formation process of the defect layer can be more flexibly selected by forming the defect layer first, and the formation of the epitaxial layer first can avoid growth on the defect layer. The high-density defect structure in the epitaxial layer causes the problem of low quality of the epitaxial layer. Those skilled in the art can select the formation method of forming the defect layer and the epitaxial layer according to requirements, which are not specifically limited in the embodiments of the present disclosure.

Optionally, the step 701 includes:

Step S11, forming the defect layer on the surface of the silicon substrate;

Step S12, preparing the epitaxial layer on the defect layer.

In the embodiments of the present disclosure, a defect layer can be formed on the surface of the substrate. For example, high-density ion implantation, laser etching, chemical etching, ion etching, etc. can be performed on the surface of the silicon substrate. Epitaxial growth may be performed on the defect layer to form an epitaxial layer, wherein the ion implantation may be hydrogen implantation.

Optionally, the step 701 includes:

Step S21, preparing the epitaxial layer on the surface of the silicon substrate;

Step S21 , forming the defect layer at the contact interface between the epitaxial layer and the silicon substrate.

In the embodiment of the present disclosure, the epitaxial layer can also be prepared on the surface of the silicon substrate first. Since the surface defects of the silicon substrate are few, the epitaxial layer obtained by epitaxial growth is of higher quality, so that the quality of the prepared ultra-thin silicon wafer can be improved. , after the epitaxial layer is prepared, a defect layer is formed at the contact interface between the epitaxial layer and the silicon substrate. etc., thereby forming a corresponding defect layer at the contact interface.

Step 702 , heating the silicon substrate by electromagnetic waves of a preset frequency to form a temperature gradient at the defect layer, so as to generate thermal stress at the interface between the silicon substrate and the epitaxial layer, and heating the silicon substrate At the same time or after the initial separation interface of the silicon substrate and the epitaxial layer is formed at the edge.

Optionally, in the step 702, the temperature gradient at the defect layer is at least 10K/mm.

In the embodiments of the present disclosure, those skilled in the art can choose different ways of heating the silicon substrate according to process conditions, application requirements, etc., for example, electromagnetic wave heating, infrared heating and the like can be selected. Optionally, taking electromagnetic wave heating as an example, the silicon substrate can be heated by electromagnetic waves with a preset frequency, and the electromagnetic wave heating can efficiently heat up and precisely control the heating temperature, thereby improving the heating efficiency of the silicon substrate and ensuring that the silicon substrate is heated. The uniformity of the heating of the substrate, so as to ensure the uniformity of thermal expansion stress, optionally, the preset frequency can be greater than or equal to 0.3MHz; at this time, the silicon substrate and the epitaxy can be formed by forming a temperature gradient at the defect layer. Thermal stress is generated at the interface of the layer. Due to the different thermal expansion stress of different temperatures, the defect layer forms a stress gradient relative to the two interface directions. Therefore, the defect layer is more likely to form an initial separation interface, which is convenient for epitaxial layer peeling. The process has good repeatability, and Heating the silicon substrate can also avoid the influence on the minority carrier lifetime of crystalline silicon caused by the current heating of the epitaxial layer, and obtain ultra-thin silicon wafers of higher quality with high efficiency. Optionally, the temperature gradient at the defect layer may be greater than or equal to 10K·mm ⁻¹ , for example, the temperature gradient may be 10K·mm ⁻¹ , 30K·mm ⁻¹ , 50K·mm ⁻¹ , 70K·mm ⁻¹ , 100K·mm ⁻¹ , etc., which are not specifically limited in the embodiments of the present disclosure.

In the embodiment of the present disclosure, a metal structure can be arranged on the heating part of the silicon substrate. Based on the good thermal conductivity of the metal structure, the heating structure can be simplified. For example, the optional frequency range of electromagnetic wave heating can be wider, so as to obtain better heating For uniformity, optionally, the metal structure may adopt a metal thin layer or a metal plate that is fully covered, or a hollow structure such as a metal grid or a metal wire, which is not specifically limited in this embodiment of the present disclosure.

In the embodiment of the present disclosure, the skin depth (electromagnetic wave penetration depth) can be controlled by adjusting the frequency of the electromagnetic wave, so as to adjust the heating depth of the electromagnetic wave heating, wherein the formula for controlling the skin depth is as follows:

In the above formula (1), δ is the skin depth, μ0 is the magnetic permeability, σ is the electrical conductivity, and ω is the frequency of the electromagnetic wave. When the doping concentration of the silicon material is fixed, the magnetic permeability and the electrical conductivity are fixed. At this time, it can be adjusted by adjusting The frequency of the electromagnetic wave can precisely control the skin depth, thereby controlling the heating depth of the heating.

Optionally, the step 702 includes:

Step S31 , preheating the silicon substrate through electromagnetic waves of a first preset power, and controlling the temperature of the silicon substrate to be a first preset temperature.

Step S32 , heating the silicon substrate by electromagnetic waves of a second preset power, and controlling the temperature of the silicon substrate to be a second preset temperature, and the second preset power is greater than the first preset power , the second preset temperature is greater than the first preset temperature.

In the embodiment of the present disclosure, in order to ensure the temperature gradient where the defect layer is formed, electromagnetic waves with gradient power may be used to heat the silicon substrate. After the temperature of the silicon substrate reaches the first preset temperature, the power is increased to the second preset power to increase the heating rate for heating, which is not specifically limited in this embodiment of the present disclosure.

Optionally, the method for implementing the step 702 further includes at least one of the following:

Step S41, mechanically peeling off the epitaxial layer at the edge;

Step S42, scanning the edge of the contact interface between the silicon substrate and the epitaxial layer with a laser.

In the embodiment of the present disclosure, in order to assist the peeling and improve the peeling efficiency of the epitaxial layer, the above-mentioned heating may be performed at any stage, such as during the pre-heating process, after the pre-heating, during the heating process with the second preset power, and after the heating with the second preset power. etc., the initial separation interface is formed at any position on the edge of the defect layer. Optionally, the initial separation interface can be formed by laser scanning at the corresponding position between the silicon substrate and the epitaxial layer at the side edge, or mechanical The initial separation interface is formed by peeling off the epitaxial layer at the edge, and the setting of the initial separation interface can make the defect layer more likely to be damaged under stress, and further improve the peeling efficiency of the epitaxial layer.

Step 703: Starting from the initial separation interface, gradually peel off the epitaxial layer from the silicon substrate.

In this embodiment of the present disclosure, step 703 may correspond to the relevant description of step 603, which is not repeated here in order to avoid repetition.

In the embodiment of the present disclosure, when the initial separation interface is formed at the edge, the epitaxial layer may be peeled off at a position corresponding to the initial separation interface of the epitaxial layer. Alternatively, the corresponding position of the initial separation interface of the epitaxial layer may be on the epitaxial layer. The side surface corresponding to the initial separation interface may also be at least one point position on the edge of the epitaxial layer whose distance from the initial separation interface is less than a preset distance, which is not specifically limited in this embodiment of the present disclosure.

Optionally, the method for implementing the step 703 includes at least one of the following:

The epitaxial layer is pulled, curled or lifted by an external force.

In the embodiment of the present disclosure, on the basis of the initial separation interface, the epitaxial layer may be pulled, curled or lifted at the corresponding position of the initial separation interface of the epitaxial layer, so as to apply stress to the epitaxial layer to make it peel off from the silicon substrate, Wherein, the lifting can be at least one position of the epitaxial layer and the silicon substrate by applying stress in the opposite direction to lift off to separate the epitaxial layer and the silicon substrate; the curling can be rolling and peeling one side of the epitaxial layer, etc., or it can also be used simultaneously. Lifting and curling the peeling epitaxial layer, which is not specifically limited in the embodiment of the present disclosure.

FIG. 8 shows a flow chart of steps of another method for preparing an ultra-thin silicon wafer provided by an embodiment of the present disclosure. As shown in FIG. 8 , the method may include:

Step 801 , forming a defect layer and an epitaxial layer on the surface of a silicon substrate, where the defect layer is located between the silicon substrate and the epitaxial layer.

In this embodiment of the present disclosure, step 801 can be referred to the relevant description of the foregoing step 601, which is not repeated here in order to avoid repetition.

Step 802 , providing a support structure on the surface of the epitaxial layer.

In the embodiment of the present disclosure, a support structure may be provided on the surface of the epitaxial layer to facilitate subsequent peeling operations, wherein the support structure may play a supporting role in the epitaxial layer, so as to ensure the integrity and connection of the epitaxial layer in the subsequent operation, and avoid the The applied stress results in the probability of epitaxial layer cracks and fragments, improving the efficiency of stripping ultra-thin silicon wafers and the quality of the resulting ultra-thin silicon wafers. Optionally, the support structure may be a single-layer structure or a composite-layer structure; the support structure may be connected to the surface of the epitaxial layer through adhesion, or may be connected to the surface of the epitaxial layer through an interface reaction, which is not made in the embodiments of the present disclosure. specific restrictions.

In the embodiment of the present disclosure, the support structure may be composed of high-temperature and corrosion-resistant organic substances, wherein the organic substances may include polyimide, epoxy resin, polymethyl methacrylate, EVA (Ethylene-Vinyl Acetate copolymer, ethylene-vinyl acetate) Ethyl acetate copolymer), polyvinyl butyral, etc.; the supporting structure can also be composed of glass, tempered glass, transparent alumina crystal, etc.; the supporting structure can also be metal grids, metal films, metal wires, metal sheets , metal plate, etc.; or, the support structure may also be composed of two or more composite materials among the above materials, which is not specifically limited in the embodiment of the present disclosure.

Step 803 , heating the silicon substrate, generating thermal stress at the interface between the silicon substrate and the epitaxial layer, and forming the silicon substrate and the edge at the edge while or after heating the silicon substrate. The initial separation interface of the epitaxial layer.

In this embodiment of the present disclosure, step 803 may refer to the relevant description of the foregoing step 602, which is not repeated here in order to avoid repetition.

In the embodiment of the present disclosure, a corresponding thermal expansion stress is applied to the silicon substrate in the process of heating the silicon substrate. At this time, since the support structure has the function of supporting the epitaxial layer, a shrinkage stress that resists the thermal expansion stress will be generated , so that the epitaxial layer and the silicon substrate are respectively subjected to stress in opposite directions. On this basis, the epitaxial layer is easier to peel off from the silicon substrate, so that the support structure supports the epitaxial layer and improves the ultra-thin silicon substrate. sheet peeling efficiency.

FIG. 9 shows a schematic diagram of stress distribution during heating of a silicon substrate provided by an embodiment of the present disclosure. As shown in FIG. 9 , it includes a silicon substrate 901 , a defect layer 902 , an epitaxial layer 903 and a support structure 904 . The lower surface 9011 of the bottom 901 is heated to apply thermal expansion stress to the silicon substrate 901. At this time, under the support of the epitaxial layer 903 by the support structure 904, a shrinkage stress against the thermal expansion stress is generated, thereby facilitating the peeling of the epitaxial layer 903.

Step 804, starting from the initial separation interface, gradually peel off the epitaxial layer from the silicon substrate.

In this embodiment of the present disclosure, step 804 may refer to the relevant description of the foregoing step 603, which is not repeated here in order to avoid repetition.

In the embodiment of the present disclosure, the support structure on the epitaxial layer can be pulled, rolled or lifted by external force, so that the defect layer is fractured to form an initial separation interface, and the initial separation interface diffuses into the interior of the defect layer in a direction parallel to the surface of the silicon substrate , so that the epitaxial layer and the silicon substrate are gradually separated from the position of the defect layer.

In the embodiment of the present disclosure, the separated ultra-thin silicon wafer may have a support structure. Optionally, the support structure may be removed, or the ultra-thin silicon wafer required in the solar cell fabrication process may be selected when forming the support structure. Film material, such as the need to form a metal film on an ultra-thin silicon wafer in the preparation process of solar cells, the support structure can choose a metal film to directly obtain an ultra-thin silicon wafer with a metal film, which can simplify the preparation of solar cells process, thereby further improving the efficiency of subsequent processes.

Example 3

FIG. 10 shows a process flow diagram of a method for preparing an ultra-thin silicon wafer provided by an embodiment of the present disclosure. As shown in FIG. 10 , the method may include:

(1) obtaining a silicon substrate 501 with a thickness of 2 mm by rear-cutting a Czochralski single crystal, and cleaning and polishing the silicon substrate 501';

(2) A defect layer 1002 of 1 μm is formed on the silicon substrate 1001 by scanning a focused laser beam, wherein the laser wavelength is greater than or equal to 1500 nm, which can be single-beam focusing or multi-beam focusing, the diameter of the focus spot is less than or equal to 1 μm, and the focus The energy density is greater than or equal to 8×10 ¹² W/m ² to generate nonlinear absorption at the focal position of the laser beam, thereby generating thermo-mechanical stress to form the defect layer 1002;

(3) Epitaxial growth of 15 μm on the defect layer 1002 by chemical vapor deposition method;

(4) Use 3GHz radio frequency electromagnetic waves to heat the bottom 10011 of the silicon substrate 1001, first use 500W power to heat to 250°C, and then use 1000W power to heat to 700°C, and during the heating process, the peeling position 10031 of the epitaxial layer 1003 Lift up to separate the epitaxial layer 1003 from the silicon substrate 1001 at the position of the defect layer 1002 to form an initial separation interface 10032;

(5) The initial separation interface 5032 gradually diffuses to completely separate the epitaxial layer 1003;

(6) The epitaxial layer 1003 obtained by peeling is obtained as an ultra-thin silicon wafer.

Example 4

FIG. 11 shows a process flow diagram of another method for preparing an ultra-thin silicon wafer provided by an embodiment of the present disclosure. As shown in FIG. 11 , the method may include:

(1) Obtain a silicon substrate 1101 with a thickness of 2 mm by rear-cutting a Czochralski single crystal, and clean and polish the silicon substrate 1101;

(2) An epitaxial layer 1102 with a thickness of 15 μm is epitaxially grown on the silicon substrate 1101 by chemical vapor deposition, and a polyimide film is laid on the epitaxial layer as a support structure 1103 .

(3) A defect layer 1104 of 1 μm is formed at the contact interface between the epitaxial layer 1102 and the silicon substrate 1101 by scanning a focused laser beam, wherein the laser wavelength is greater than or equal to 1600 nm, which can be single-beam focusing or multi-beam focusing. The diameter is less than or equal to 1 μm, and the focal energy density is greater than or equal to 8×10 ¹² W/m ² , so as to generate nonlinear absorption at the focal position of the laser beam, thereby generating thermo-mechanical stress to form the defect layer 604;

(4) Use 3GHz radio frequency electromagnetic waves to heat the bottom 11011 of the silicon substrate 1101, first use 600W power to heat to 250°C, and then use 1000W power to heat to 700°C, and during the heating process, the peeling position 11031 of the support structure 1103 is heated. Lift up to separate the epitaxial layer 1102 from the silicon substrate 1101 at the position of the defect layer 1104 to form an initial separation interface 11021;

(5) The initial separation interface 11021 gradually diffuses to completely separate the epitaxial layer 1102;

(6) The epitaxial layer 1102 obtained by peeling is obtained as an ultra-thin silicon wafer, and the ultra-thin silicon wafer also includes a support structure 1103 .

It should be noted that, for the purpose of simple description, the method embodiments are expressed as a series of action combinations, but those skilled in the art should know that the embodiments of the present disclosure are not limited by the described action sequences, because According to embodiments of the present disclosure, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily all necessary for the embodiments of the present disclosure.

It should be noted that, herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, It also includes other elements not expressly listed or inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

The embodiments of the present disclosure have been described above in conjunction with the accompanying drawings, but the present disclosure is not limited to the above-mentioned specific embodiments, which are merely illustrative rather than restrictive. Under the inspiration of the present disclosure, many forms can be made without departing from the scope of the present disclosure and the protection scope of the claims, which all fall within the protection of the present disclosure.

Claims

A method for slicing ultra-thin silicon wafers, characterized in that the method comprises:

A defect layer is arranged under the surface layer of the silicon block;

Electromagnetic induction heating is performed on the surface layer and the penetration depth δ of the heating is controlled not to exceed the depth of the defect layer, and the initial separation interface of the silicon bulk and the epitaxial layer is formed at the edge at the same time or after the electromagnetic induction heating. ;

Starting from the initial separation interface, the surface layer is gradually peeled off from the silicon bulk to obtain an ultra-thin silicon wafer.
The method according to claim 1, wherein the step of performing electromagnetic induction heating on the surface layer comprises:

Electromagnetic induction heating is performed on the surface layer by electromagnetic waves of a preset frequency, and the preset frequency is a single frequency or an adjustable frequency;

The single frequency is above 100MHz;

The adjustable frequency is set in the following manner:

Use electromagnetic waves above 100GHz to heat from room temperature to preset temperature;

From a preset temperature, electromagnetic waves of 100MHz to 100GHz are used for heating, and the preset temperature range is 100°C to 300°C.
The method according to claim 2, wherein the single frequency is above 1 GHz.
The method according to claim 1, wherein after the defect layer is arranged under the surface layer of the silicon block, the method further comprises:

A support structure is provided on the surface of the skin.
The method according to claim 4, wherein the material of the support structure comprises at least one of organic material, glass, transparent alumina crystal, and metal material.
The method according to claim 5, wherein the organic material comprises polyimide, epoxy resin, polymethyl methacrylate, ethylene-ethyl acetate copolymer and polyvinyl butyral at least one of;

The metal material includes at least one of metal grids, metal films, metal wires, metal sheets and metal plates.
The method according to claim 1, wherein the thickness of the surface layer is 1 μm˜100 μm.
The method of claim 1, wherein the thickness of the defect layer is less than or equal to 30% of the thickness of the surface layer.
The method according to claim 1, wherein the method of gradually peeling off the surface layer from the silicon block starting from the initial separation interface comprises at least one of the following:

External forces pull, curl, and elevate the surface layer.
A method for preparing an ultra-thin silicon wafer, wherein the method comprises:

forming a defect layer and an epitaxial layer on the surface of the silicon substrate, and the defect layer is located between the silicon substrate and the epitaxial layer;

heating the silicon substrate to generate thermal stress at the interface of the silicon substrate and the epitaxial layer, and forming the silicon substrate and the epitaxial layer at the edges while or after the heating of the silicon substrate the initial separation interface of the layers;

Starting from the initial separation interface, the epitaxial layer is gradually stripped from the silicon substrate.
The method according to claim 10, wherein the step of forming the defect layer and the epitaxial layer on the surface of the silicon substrate comprises the steps of:

forming the defect layer on the surface of the silicon substrate;

The epitaxial layer is prepared on the defect layer.
The method according to claim 10, wherein the step of forming the defect layer and the epitaxial layer on the surface of the silicon substrate comprises the steps of:

preparing the epitaxial layer on the surface of the silicon substrate;

The defect layer is formed at the contact interface between the epitaxial layer and the silicon substrate.
The method of claim 10, wherein in the step of heating the silicon substrate, the temperature gradient at the defect layer is at least 10K/mm.
The method of claim 10, wherein the method of forming an initial separation interface between the silicon substrate and the epitaxial layer at the edge comprises at least one of the following:

Mechanical peeling of the epitaxial layer at the edge;

or,

The edge of the contact interface between the silicon substrate and the epitaxial layer is scanned with a laser.
The method according to claim 10, wherein after the step of forming a defect layer and an epitaxial layer on the surface of the silicon substrate, further comprising:

A support structure is provided on the surface of the epitaxial layer.
The method according to claim 10, wherein the thickness of the defect layer is less than or equal to 2 μm.
The method according to any one of claims 10-16, wherein the method of gradually peeling off the epitaxial layer from the silicon substrate starting from the initial separation interface comprises at least one of the following :

An external force pulls, curls or lifts the epitaxial layer or support structure.
An ultra-thin silicon wafer, characterized in that, the ultra-thin silicon wafer is prepared by the method of any one of claims 1-17.
A solar cell, characterized in that the solar cell uses the ultra-thin silicon wafer of claim 18 .