CN113541626A - Composite single crystal piezoelectric substrate and preparation method thereof - Google Patents

Composite single crystal piezoelectric substrate and preparation method thereof Download PDF

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Publication number
CN113541626A
CN113541626A CN202010315140.3A CN202010315140A CN113541626A CN 113541626 A CN113541626 A CN 113541626A CN 202010315140 A CN202010315140 A CN 202010315140A CN 113541626 A CN113541626 A CN 113541626A
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layer
single crystal
crystal piezoelectric
silicon dioxide
silicon
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李真宇
朱厚彬
张秀全
王金翠
张涛
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Jinan Jingzheng Electronics Co Ltd
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Jinan Jingzheng Electronics Co Ltd
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Priority to CN202010315140.3A priority Critical patent/CN113541626A/en
Priority to KR1020217040777A priority patent/KR20220007691A/en
Priority to PCT/CN2021/088510 priority patent/WO2021213410A1/en
Publication of CN113541626A publication Critical patent/CN113541626A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/64—Filters using surface acoustic waves
    • H03H9/6489—Compensation of undesirable effects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/071—Mounting of piezoelectric or electrostrictive parts together with semiconductor elements, or other circuit elements, on a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials

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  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

The application discloses a composite single crystal piezoelectric substrate and a preparation method thereof, the composite single crystal piezoelectric substrate comprises a silicon substrate layer (1), a silicon dioxide layer (2) and a single crystal piezoelectric layer (3), wherein the surface of the silicon substrate layer (1) is damaged to form a damaged layer (4), the damaged layer (4) is in contact with the silicon dioxide layer (2), the method provided by the application arranges high-temperature process steps before the damaged layer (4) is formed, and the damaged layer (4) is prepared through the silicon dioxide layer (2) in a remote spacing way, so that the thickness uniformity of the silicon dioxide layer (2) is good, the defect density for capturing carriers in the damaged layer (4) is large, the structure of the composite single crystal piezoelectric substrate is stable, and the carriers generated due to unavoidable defects on the interface of the silicon substrate layer (1) and the silicon dioxide layer (2) can be effectively captured, thereby improving the performance of a device manufactured on the basis of the composite single crystal piezoelectric substrate.

Description

Composite single crystal piezoelectric substrate and preparation method thereof
Technical Field
The application belongs to the field of preparation of functional semiconductor materials, and particularly relates to a composite single crystal piezoelectric substrate and a preparation method thereof.
Background
The composite single crystal piezoelectric substrate can show better performance in the surface acoustic wave filter, and comprises a single crystal piezoelectric layer, a low acoustic resistance layer and a high acoustic resistance substrate layer which are sequentially stacked. The low acoustic resistance layer is mainly used for forming acoustic resistance difference with the high acoustic resistance layer, so that the energy of the acoustic wave is mainly concentrated in the single crystal piezoelectric layer and the low acoustic resistance layer, and the energy is limited to leak downwards. Silicon dioxide is the most commonly used material for the low-acoustic-resistance layer, and in contrast to a common piezoelectric material, the silicon dioxide layer has a positive acoustic temperature coefficient and has a compensation effect on the frequency temperature coefficient of the piezoelectric material, so that the frequency temperature drift coefficient of a final device is reduced, and the compensation effect is related to the thickness of the silicon dioxide layer. Therefore, the composite single crystal piezoelectric substrate has two requirements for the low acoustic resistance layer: firstly, the acoustic transmission loss is low; secondly, the thickness uniformity. Meanwhile, silicon and silicon carbide materials become the first choice of high-acoustic-resistance materials due to the mature preparation and processing industrialization degree of the silicon and silicon carbide materials.
In the prior art, SiO is grown by thermal oxidation2The performance is most excellent in the above two requirements. In addition, the composite single crystal piezoelectric substrate generally requires that the roughness of each layer interface is less than 0.5nm, so that the energy loss caused by scattering of sound waves at each interface is reduced, and the pattern distortion caused by diffuse reflection of laser at the interface during subsequent photoetching is avoided. However, the composite single crystal piezoelectric substrate actually produced has many charges at the interface between the silicon dioxide layer and the silicon substrate layer, and these charges can attract carriers in the silicon substrate layerThe conductive layer can interact with an electromagnetic field generated by the surface acoustic wave filter device in the using process to cause signal loss.
In the prior art, a polysilicon layer is introduced between a silicon dioxide layer and a silicon substrate layer, and carriers are captured by utilizing naturally existing lattice defects in the polysilicon layer, so that the interference of a conductive layer on signals is reduced. However, the introduction of polysilicon makes it very difficult to obtain a good silicon dioxide layer and brings with it other problems: firstly, the polysilicon is generally prepared by a deposition process, the used raw materials are generally gas or liquid containing Si element, and the raw materials are not environment-friendly; secondly, at the thermal oxidation temperature for preparing silicon dioxide, polysilicon re-crystallizes, resulting in a reduction in the effect of trapping carriers by the polysilicon layer, and thus high quality silicon dioxide cannot be prepared by thermal oxidation after preparing polysilicon.
Disclosure of Invention
In order to solve the problems existing in the process of preparing a composite monocrystalline piezoelectric substrate with a polycrystalline silicon layer in the prior art, the application provides a composite monocrystalline piezoelectric substrate, which comprises a silicon substrate layer, a silicon dioxide layer and a monocrystalline piezoelectric layer, wherein a damaged layer is introduced into the interface of the silicon substrate layer and the silicon dioxide layer, and the damaged layer has lattice defects which can be used for capturing carriers, so that the signal loss is weakened, and the application also provides a method for preparing the composite monocrystalline piezoelectric substrate. The performance of capturing carriers by the damaged layer is improved; in addition, the silicon dioxide layer prepared by the thermal oxidation process has good compactness and uniformity, and further, the performance of a device prepared at the downstream is good.
An object of the application is to provide a compound single crystal piezoelectric substrate, compound single crystal piezoelectric substrate includes silicon substrate layer 1, silica layer 2 and single crystal piezoelectric layer 3 in proper order, wherein, silicon substrate layer 1 is damaged from its interface with the silica layer to its inside region that has the predetermined depth and forms damage layer 4, damage layer 4 with silica layer 2 meets.
The damage layer of thickness is predetermine in this application setting on the interface that silicon substrate layer and silica layer meet, the damage layer can catch the current carrier that gathers in the two interface to weaken the conducting layer, reduce the signal loss of surface acoustic wave filter device in the use.
In a practical manner, the defect density of the damaged layer 4 is at least 1011atoms/cm2E.g. 1011To 1014atoms/cm2Therefore, the damaged layer 4 can meet the requirement of capturing carriers, and the process difficulty and complexity can be reduced to the greatest extent.
Optionally, the thickness of the damaged layer 4 is 300nm to 3 μm, so that the thickness is minimum under the condition that the damaged layer can provide sufficient carrier capturing capability, and the process complexity is reduced.
Further, the damaged layer 4 is formed in an ion implantation or laser etching manner, and the ion implantation layer or the laser etching layer is used as the damaged layer by using the structural characteristics of the ion implantation layer or the laser etching layer, so that the damaged layer is integrally prepared based on the silicon substrate layer and the silicon dioxide layer, the preparation complexity is reduced, and the overall stability of the prepared composite single crystal piezoelectric substrate can be improved.
In an achievable mode, the silicon dioxide layer 2 is prepared by a thermal oxidation method, so that the silicon dioxide layer is compact and uniform, and compared with a thermal deposition mode and the like, raw materials required by a thermal oxidation process are only oxygen and water, so that the method is environment-friendly.
In an achievable manner, the silicon dioxide layer 2 has a thickness uniformity of less than 2% to meet composite single crystal piezoelectric substrate performance requirements.
In one implementable manner, the composite single crystal piezoelectric substrate is prepared by a method comprising:
performing thermal oxidation treatment on the upper surface of the silicon substrate layer to generate a silicon dioxide layer;
penetrating through the silicon dioxide layer to damage the surface of the silicon substrate layer connected with the silicon dioxide layer to form a damaged layer;
and preparing a single crystal piezoelectric layer, and superposing the single crystal piezoelectric layer, the silicon dioxide layer, the damage layer and the silicon substrate layer to form the composite single crystal piezoelectric substrate.
In the application, the composite single crystal piezoelectric substrate sequentially comprises a silicon substrate layer 1, a silicon dioxide layer 2 and a single crystal piezoelectric layer 3 from bottom to top, and the direction of the upper part in the upper surface is the same as the direction of the upper part in the upper surface.
Another object of the present application is to provide a method of manufacturing the composite single crystal piezoelectric substrate of the first aspect, the method including:
carrying out thermal oxidation treatment on the upper surface of the silicon substrate layer 1 to generate a silicon dioxide layer 2;
penetrating through the silicon dioxide layer 2 to damage the surface of the silicon substrate layer 1 connected with the silicon dioxide layer to form a damaged layer 4;
and preparing a single crystal piezoelectric layer, and superposing the single crystal piezoelectric layer, the silicon dioxide layer, the damage layer and the silicon substrate layer to form the composite single crystal piezoelectric substrate.
This application prepares the silica layer through the thermal oxidation mode on the silicon substrate layer surface, can make compactly, even silica layer, the gained silica layer has lower sound wave transmission loss and good thickness homogeneity, and it combines stably with the silicon substrate layer, thereby pass the silica layer again and carry out ion implantation to the interface of silica layer and silicon substrate layer and prepare the damage layer, thereby the mode of rethread bonding at last will prepare in advance the single crystal piezoelectric layer shift to the silica layer upper surface, thereby avoid the destruction that the damage layer caused to compound single crystal piezoelectric substrate can be followed to the high temperature that utilizes at preparation single crystal piezoelectric layer in-process. According to the method, the silicon dioxide layer is prepared by thermal oxidation firstly, and then the process sequence of preparing the damaged layer in an ion implantation mode is adopted, so that the stable structure of the damaged layer can be ensured, the stronger carrier capturing capability is realized, and the higher quality of the silicon dioxide layer can be ensured, and the problem of recovery of amorphous silicon or polycrystalline silicon defects caused by high temperature in the process of sequentially preparing the amorphous silicon or polycrystalline silicon layer and the silicon dioxide layer on the silicon substrate in the traditional scheme is effectively solved.
In a realizable manner, the uniformity of the produced silicon dioxide layer 2 is less than 2% to meet the performance requirements of the composite single crystal piezoelectric substrate.
In an implementation manner, the damage to the surface of the silicon substrate layer 1 through the silicon dioxide layer 2 includes an ion implantation method and a laser etching method, which on one hand ensures that the properties of the silicon dioxide layer 2, such as acoustic wave transmission loss rate and thickness uniformity, do not change, and on the other hand can obtain a damaged layer with excellent carrier capture capability at a target position.
In a practical mode, the damaged layer is prepared by ion implantation, and the ion implantation method is used for implanting ions with the concentration of at least 1011atoms/cm2E.g. 1011To 1014atoms/cm2Therefore, the defect density of the damaged layer is realized, the damaged layer can meet the requirement of capturing carriers, and the process difficulty and the complexity are reduced to the greatest extent.
Optionally, based on the surface of the silicon substrate layer connected to the silicon dioxide layer, for each different product, the specific depth range of ion implantation may be specifically set according to the thickness of the damaged layer, so that the position of the damaged layer is exactly in the silicon substrate layer close to the silicon dioxide layer, so as to ensure that the defect formed by ion implantation can play a role in inhibiting conduction near the interface of the silicon substrate layer, thereby reducing the attenuation of the conductive layer to signals.
In another realizable mode, preparing the damage layer by adopting a laser damage method, wherein the wavelength of the laser is 200 nm-1064 nm; the energy density of the laser is 1J/cm2～100J/cm2。
In one implementable form, the preparing a single crystal piezoelectric layer comprises:
carrying out ion implantation on the single crystal piezoelectric wafer bonded on the substrate material to form a thin film layer, an implanted layer and a residual material layer;
bonding a substrate with the thin film layer of the single crystal piezoelectric wafer;
and peeling the residual material layer from the thin film layer along the injection layer.
The method can prepare the single crystal piezoelectric layers such as lithium niobate and lithium tantalate in advance by adopting an ion implantation mode so as to transfer the piezoelectric single crystal layer to the silicon dioxide layer.
This application accomplishes the recovery to single crystal piezoelectric layer crystal lattice at prefabricated single crystal piezoelectric layer in-process for the single crystal piezoelectric layer only need bond with the silica layer, need not high temperature treatment once more after the bonding, thereby will the single crystal piezoelectric layer shifts to it is not right again to need on the silica layer the single crystal piezoelectric layer carries out thermal treatment, guarantees to damage a layer stable in structure, and the single crystal piezoelectric layer has good crystal lattice form.
In one implementable form, transferring the single crystal piezoelectric layer to the silicon dioxide layer upper surface can comprise:
respectively carrying out surface activation on the upper surface of the silicon dioxide layer and the surface of the single crystal piezoelectric layer;
bonding the silicon dioxide layer after surface activation and the single crystal piezoelectric layer;
and removing the substrate material on the single crystal piezoelectric layer.
The bonding mode that this application adopted can be for need not to use the bonding mode of high temperature treatment among the prior art to get rid of the substrate material who bears the weight of single crystal piezoelectric layer after the bonding, avoid handling the rest in the compound single crystal piezoelectric base plate, thereby guarantee the performance and the structural stability of compound single crystal piezoelectric base plate.
Compared with the prior art, the composite single crystal piezoelectric substrate has a compact and uniform silicon dioxide layer, and a damage layer with preset defect density is arranged at a preset position of a silicon substrate layer and has sufficient carrier capture capacity, so that a conductive layer in the composite single crystal piezoelectric substrate is weakened, and signal loss caused by the conductive layer is reduced; the preparation that this application provided compound single crystal piezoelectric substrate's method is at first through the thermal oxidation method preparation silica layer on the silicon substrate layer, penetrating modes such as rethread ion implantation or laser irradiation form the damage layer at silicon substrate layer and silica interface, and the normal atmospheric temperature bonding mode of recycling bonds the single crystal piezoelectric layer on the silica layer at last, and this method sets up high temperature technology before ion implantation/laser etching, can enough make the silica layer compact even, can guarantee again that damage layer structure and stable performance make the compound single crystal piezoelectric substrate performance that finally obtains good.
Drawings
FIG. 1 illustrates a schematic cross-sectional structure of a composite single crystal piezoelectric substrate provided herein;
fig. 2 is a schematic view showing a flow of preparing the composite single crystal piezoelectric substrate of this example.
1-silicon substrate layer, 2-silicon dioxide layer, 3-single crystal piezoelectric layer, 003-lithium tantalate wafer, 031-film layer, 032-injection layer, 033-residual material layer, 4-damage layer, 5-single crystal piezoelectric layer and 51-silicon substrate.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of methods consistent with certain aspects of the invention, as detailed in the appended claims.
The piezoelectric composite substrate and the method for manufacturing the same provided by the present application are described in detail below with specific examples.
Fig. 1 shows a schematic cross-sectional structure diagram of a composite single crystal piezoelectric substrate provided by the present application, and as shown in fig. 1, the composite single crystal piezoelectric substrate sequentially includes a silicon substrate layer 1, a silicon dioxide layer 2, and a single crystal piezoelectric layer 3.
In this example, the material for preparing the single crystal piezoelectric layer 3 includes a piezoelectric material such as lithium niobate or lithium tantalate, and the single crystal piezoelectric layer 3 may be any one of the single crystal piezoelectric layers 3 used in the composite single crystal piezoelectric substrate in the prior art.
In the present example, the single crystal piezoelectric layer 3 can be prepared on the composite single crystal piezoelectric substrate by means of film transfer.
In this example, the method for preparing the silicon dioxide layer is a thermal oxidation method, so that the silicon dioxide layer is dense and uniform, and compared with a thermal deposition method and the like, the thermal oxidation method requires only oxygen and water as raw materials, which is more environment-friendly.
In this example, the thickness uniformity of the silicon dioxide layer 2 is less than 2% to meet the performance requirements of the composite single crystal piezoelectric substrate.
As mentioned above, due to the limitation of the process, when silicon dioxide is prepared on a silicon substrate, there are many unsaturated oxidized silicon and structural defects at the silicon dioxide/silicon interface, and these defects can emit carriers into the silicon substrate, enhancing the conductivity of silicon; in addition, these defects can also result in charge near the interface, which can attract carriers to concentrate in the silicon near the interface, enhancing conductivity. Because the composite substrate is originally in an electromagnetic field environment in a use state, carriers concentrated at the interface of the silicon substrate layer 1 and the silicon dioxide layer 2 interact with the electromagnetic field, so that signal loss is generated; on the other hand, the extra loss also causes the whole device to heat up; the two aspects result in large loss and short service life of electronic devices using the traditional composite substrate.
In the present embodiment, the thickness of the silicon dioxide layer may be 100nm to 2 μm, and the applicant finds that the silicon dioxide layer with the above thickness can not only satisfy the function of the silicon dioxide layer as a low acoustic resistance layer, but also ensure that the total volume of the prepared composite single crystal piezoelectric substrate is small, thereby facilitating the subsequent use.
The damaged layer 4 with the carrier capturing capability provided in the present example can capture carriers formed on the surface of the silicon substrate layer 1, thereby eliminating a series of problems caused by interface defects between the silicon substrate layer 1 and the silicon dioxide layer 2.
Because the current carriers often exist near the interface of the silicon substrate layer 1 and the silicon dioxide layer 2, a layer of polysilicon is prepared on the silicon substrate for capturing the current carriers in the conventional scheme, the preparation sequence is silicon substrate-polysilicon-silicon dioxide layer, the process for preparing the silicon dioxide layer comprises a deposition method and a thermal oxidation method, however, if the silicon dioxide layer is prepared by adopting the deposition method, the surface uniformity of the obtained silicon dioxide layer is poor, the surface of the silicon dioxide layer needs to be polished, the process complexity is increased, and the uniformity of the silicon dioxide is easily reduced; since the oxidation rate has an orientation to the silicon crystal orientation, if the thermal oxidation method is used to prepare the silicon dioxide layer, the polysilicon has grains of different sizes, so that the final SiO2The roughness of the oxidation interface of the polysilicon is too large, and even reaches the level of dozens of nanometers, so that the performance of the silicon dioxide layer is influenced. Therefore, the performance of the silicon dioxide layer is difficult to guarantee by the prior art process.
Referring to fig. 1, in this example, the damaged layer 4 is prepared in the order of silicon substrate layer-silicon dioxide layer-damaged layer, wherein the damaged layer 4 is formed by damaging the surface of the silicon substrate layer 1 contacting the silicon dioxide layer 2, that is, the damaged layer 4 extends from the surface of the silicon substrate layer 1 contacting the silicon dioxide layer 2 to the inside of the silicon substrate layer 1, so that the damaged layer 4 is located at the interface of the silicon substrate layer 1 and the silicon dioxide layer 2.
In the embodiment, by adjusting the preparation sequence of the silicon substrate layer 1, the damaged layer 4 and the silicon dioxide layer 2, on one hand, the performance of the silicon dioxide layer 2 is remarkably improved, and on the other hand, the interface roughness of the silicon dioxide layer 2 and the damaged layer 4 is kept at a lower level, so that the performance of the silicon dioxide layer 2 is ensured, and further, the damaged layer 4 can be ensured to keep higher defect density and has stronger carrier capturing capability.
In this example, the surface of the damaged layer 4 and its internal structure may have defects or may have no significant defects from a macroscopic point of view, but from a microscopic point of view, the lattice structure in the damaged layer 4 is broken to form holes that can be used to trap carriers.
The applicant has found that the charge density in the silicon dioxide layer 2, i.e. the carrier density, is generally 1010～1013atoms/cm2If a good carrier trapping effect is achieved, the defect density of the damaged layer 4 needs to be much higher than the charge density in the silicon dioxide layer, which may be 10, for example11To 1014atoms/cm2The method can meet the requirement of capturing carriers and reduce the process difficulty and complexity to the maximum extent. It will be appreciated that the damaged layer 4 may also be damaged to amorphous silicon, even in porous form.
Optionally, the thickness of the damaged layer 4 is 300nm to 3 μm, so that the thickness of the damaged layer can be the minimum under the condition that the damaged layer can provide sufficient carrier capturing effect.
In a practical manner, the defect density of the damaged layer 4 from its interface with the silicon dioxide layer 2 to its interior decreases gradually, i.e. the defect density is greatest at the interface of the damaged layer 4 with the silicon dioxide layer 2, since the carriers are mainly concentrated at the interface of the silicon dioxide layer 2 with the silicon substrate layer 1 and move within said interface, the greatest defect density at the interface of the silicon dioxide layer 2 with the silicon substrate layer 1 enables the carriers to be captured to the greatest extent by the damaged layer 4.
Further, the rate of decrease of the defect density in the damaged layer 4 can be specifically set according to specific needs. For example, if the silicon substrate layer 1 is thick, a thick damage layer 4 may be provided, if the silicon substrate layer 1 is thin, a thin damage layer 4 may be provided, and the like.
In this example, the forming manner of the damaged layer 4 may include ion implantation or laser etching, and may also include other methods that can form the damaged layer 4 by directly damaging the surface of the silicon substrate layer 1 on the surface of the silicon substrate layer 1 through the silicon dioxide layer 2.
In an example, the damaged layer 4 is formed by ion implantation, and the damaged layer 4 is an ion implanted layer, the applicant finds that ions implanted by the ion implantation can break lattices in the silicon substrate layer 1, so that the ion implanted layer generates a lot of lattice defects, carriers on the surface of the silicon substrate layer 1 can be captured by using the lattice defects of the ion implanted layer, and further the silicon substrate layer 1 is prevented from conducting electricity, and the ion implantation can accurately control indexes such as the position of the damaged layer 4, the defect density of the damaged layer, the thickness of the damaged layer and the like by accurately controlling the energy and the dose of the ion implantation.
The applicant has found that since the silicon dioxide layer itself is amorphous, even if the aforementioned concentration of implanted ions (such as hydrogen ions, helium ions, etc.) passes through the silicon dioxide layer 2 during ion implantation, there is almost no effect on the performance of the silicon dioxide layer 2 and there is no problem of damage, and in addition, taking the implanted ions as hydrogen ions as an example, the implanted hydrogen can form Si — H bonds with silicon atoms in the silicon dioxide, the bonds are chemical bonds that are stable and immovable and do not cause secondary current, and moreover, the low-temperature annealing process can diffuse H out of the silicon dioxide after ion implantation is completed, thereby weakening the effect of ion implantation on the performance of the silicon dioxide layer 2.
Specifically, in the present example, the ion implantation concentration, that is, the dose of ion implantation may be 1010～1015ions/cm2Thereby forming sufficient defects.
In this example, since the thickness of the damaged layer is formed by stacking a plurality of ion implantation sublayers with different depths (positions), and the depth of the ion implantation sublayer is determined by the energy of the ion implantation, the energy range of the ion implantation can be set according to the total thickness of the silicon dioxide layer and the damaged layer. The applicant has found that the above-mentioned ion implantation amount is a relatively low ion implantation concentration, while the thickness of silicon dioxide is generally several hundred nanometers to one or two micrometers, and the ion energy required for penetrating the silicon dioxide layer with the thickness to reach the silicon layer is only several tens to several hundreds of kev, which is easy to be realized by the equipment commonly used in the field. For example, for a damaged layer with a thickness of 300nm and a silicon dioxide layer with a thickness of 100nm, the ion implantation depth is 100nm to 400nm and the required ion energy is 6 to 40keV, while for a damaged layer with a thickness of 3 μm and a silicon dioxide layer with a thickness of 2 μm, the ion implantation depth is 2 μm to 5 μm and the required ion energy is 200 to 450 keV.
Further, in this example, since the carriers between the interface of the silicon substrate layer and the silicon dioxide layer mainly move near the interface, that is, the current caused by the carriers mainly causes the lateral conduction near the interface, in this example, the ion implantation layer is attached to the silicon dioxide layer, and the ion implantation dose at the interface of the silicon dioxide layer and the silicon substrate layer is the largest, so that the damaged layer 4 has the strongest carrier trapping capability.
In another realisable way, the damage layer 4 is formed by means of laser ablation, the applicant has found that, because the light transmittance and damage threshold of the silicon dioxide and the silicon to the laser with different wavelengths are different, the laser with specific wavelength and specific energy density can penetrate through the silicon dioxide layer 2 to irradiate on the silicon substrate layer 1, the silicon substrate layer 1 absorbs the laser energy and is heated, and chemical bonds among atoms are fused, thereby generating lattice defects to form a laser etching layer, and carriers on the surface of the silicon substrate layer 1 can be captured by the lattice defects of the laser etching layer, and further, the silicon substrate layer 1 is prevented from conducting electricity, and the laser damage mode can accurately control parameters such as the position of the damaged layer 4, the defect density of the damaged layer, the thickness of the damaged layer and the like by accurately controlling parameters such as the wavelength, the energy density, the irradiation time, the incident focal depth and the like of laser.
The applicant finds that by using the structural characteristics of an ion implantation layer or a laser etching layer as the damage layer 4, the damage layer 4 can be integrally prepared on the basis of a bonding body formed by the silicon substrate layer 1 and the silicon dioxide layer 2, so that the surface of the silicon substrate layer 1 combined with the damage layer 4 has no obvious defects in macroscopic view, but has a carrier capture capacity, the process for preparing the damage layer 4 is low in complexity, the repair and elimination of lattice defects in the process of preparing the silicon dioxide layer 2 are avoided, and the overall stability of the prepared composite single crystal piezoelectric substrate can be improved.
Fig. 2 shows a schematic flow chart of the present example for preparing the composite single crystal piezoelectric substrate, which can be prepared according to a method including the following steps 1 to 4, as shown in fig. 2:
the following describes a process for preparing the composite single crystal piezoelectric substrate provided by the present application, taking the single crystal piezoelectric layer as a lithium tantalate thin film as an example.
The general idea of preparing the composite single crystal piezoelectric substrate in this example is to prepare a silicon dioxide layer on the surface of a silicon substrate on the basis of the silicon substrate, then damage the silicon substrate through the silicon dioxide layer to form a damaged layer, control the depth of damage to be just the interface between the silicon substrate and the silicon dioxide, namely, the end face of the formed damaged layer is just located at the interface between the silicon substrate and the silicon dioxide layer, the other face of the damaged layer is located inside the silicon substrate, and then transfer a lithium tantalate film to the upper surface of the silicon dioxide layer. However, if the silicon dioxide is prepared by using a thermal oxidation process on the basis of the polycrystalline silicon, a regular lattice structure is formed inside the polycrystalline silicon in the thermal oxidation process, even the monocrystalline silicon is formed, so that the polycrystalline silicon attracts charges, and the capability of capturing carriers is reduced.
Step 1, performing thermal oxidation treatment on the upper surface of a silicon substrate layer 1 to generate a silicon dioxide layer 2.
In this example, the silicon dioxide layer may be prepared on the upper surface of the single crystal silicon layer by means of thermal oxidation. The applicant has found that the performance of a silicon dioxide layer prepared by thermal oxidation shows great superiority in terms of compactness, uniformity, surface roughness, etc. compared to a silicon dioxide layer prepared by deposition means, such as Plasma Enhanced Chemical Vapor Deposition (PECVD) or Low Pressure Chemical Vapor Deposition (LPCVD), and in particular, the silicon dioxide layer prepared by thermal oxidation can directly meet the requirement of being bondable to a single-crystal piezoelectric thin film, and the thermal oxidation is low in preparation cost and simple in process.
In this example, the parameters used in the thermal oxidation method may be specifically set according to the specification size of the silicon dioxide layer and the like.
And 2, damaging the surface of the silicon substrate layer 1 connected with the silicon dioxide layer through the silicon dioxide layer 2 to form a damaged layer.
In this example, as described above, the damaged layer may be formed by ion implantation or laser ablation, and further, an ion beam or laser for forming the damaged layer may penetrate the silicon dioxide layer to a target position, and a damaged layer having a high defect density may be formed since the ion beam or laser passes through a lattice structure that may damage single crystal silicon. The silicon dioxide layer is in an amorphous state, the problem that crystal lattices are damaged is not involved, further, the thickness of the silicon dioxide layer is generally far smaller than that of the silicon substrate layer, so that ions can penetrate through the silicon dioxide layer to reach the monocrystalline silicon substrate layer, further, the preparation of the damaged layer 4 can be completed under the condition of low ion implantation energy or laser emission intensity, and the process difficulty is reduced.
In this example, the implanted ions or laser light act on the interface of the silicon substrate layer 1 and the silicon dioxide layer 2 and form a damaged layer 4 inside the silicon substrate layer 1.
In one embodiment, as shown in FIG. 2, the damaged layer is formed by ion implantation at a concentration of at least 1011atoms/cm2For example, the concentration of ion implantation is 1011To 1015atoms/cm2The applicant finds that the damage layer formed by the ion implantation mode can meet the requirement of carrier capture, and the process difficulty and the complexity are reduced to the greatest extent.
Furthermore, the thickness of the formed ion injection layer is 300 nm-3 μm, and the thickness is minimum under the condition that the damage layer can provide sufficient carrier capturing effect.
In another embodiment, the damage is formed by laser ablationA layer (not shown in FIG. 2) using a laser having a wavelength of 200nm to 1064 nm; the energy density of the laser is 1J/cm2～100J/cm2So that the laser can penetrate through the silicon dioxide layer to reach the surface of the monocrystalline silicon to damage the silicon.
And 3, preparing a single crystal piezoelectric layer 3 of the single crystal piezoelectric layer, and superposing the single crystal piezoelectric layer, the silicon dioxide layer, the damage layer and the silicon substrate layer to form the composite single crystal piezoelectric substrate.
In this example, the single crystal piezoelectric layer may be prefabricated on another substrate, and then transferred onto the silicon dioxide layer by a film transfer method, so as to obtain a composite single crystal piezoelectric substrate with a stable structure, and avoid repairing lattice defects in a damaged layer or peeling the silicon dioxide layer from the silicon substrate layer along the damaged layer in the process of performing a lattice recovery process on the single crystal piezoelectric layer, thereby improving the yield.
In this example, the method of producing the single crystal piezoelectric layer 3 is not particularly limited, and the single crystal piezoelectric layer 3 can be produced by any method of producing a single crystal piezoelectric film on a substrate in the prior art. For example, the single crystal piezoelectric layer 3 can be prepared by means of ion implantation.
In this example, the single crystal piezoelectric layer may be a lithium tantalate thin film on a silicon oxide substrate, a lithium niobate single crystal thin film on a silicon oxide substrate, or may have other structures, for example, a lithium tantalate thin film on a silicon substrate, a lithium niobate single crystal thin film on a silicon substrate, or the like.
The method for preparing the single crystal piezoelectric layer is described below by taking a silicon substrate-lithium tantalate thin film as an example, and specifically, the single crystal piezoelectric layer can be prepared by a method including the following steps S31 to S33:
s31, performing ion implantation on the lithium tantalate wafer 003 to form a thin film layer 031, an implanted layer 032, and a remainder layer 033;
s32, bonding the silicon substrate 51 and the thin film layer 031 of the lithium tantalate wafer;
s33, peeling the remainder layer 033 from the thin film layer 031 along the injection layer 032, wherein the thin film layer 031 is the single crystal piezoelectric layer 3 to be transferred subsequently.
In this example, each parameter for producing the single crystal piezoelectric layer is not particularly limited and can be specifically set according to specific needs.
Further, after the residual material layer is stripped, lattice recovery processing is carried out on the single crystal piezoelectric layer, so that lattice damage possibly caused by the single crystal piezoelectric layer in the ion implantation process is recovered to a single crystal state. The method of the lattice recovery process is not particularly limited in this example, and for example, the lattice of the single crystal piezoelectric layer may be recovered by an annealing method.
The process parameters for preparing the single crystal piezoelectric layer by the ion implantation method are not particularly limited in this example, and those skilled in the art can specifically select specific parameters according to specific needs.
The embodiment completes the restoration of the crystal lattice of the single crystal piezoelectric layer in the process of preparing the single crystal piezoelectric layer, so that the single crystal piezoelectric layer only needs to be bonded with the silicon dioxide layer, and high-temperature treatment is not needed again after bonding, thereby ensuring the stable structure of the damaged layer.
And 4, transferring the single crystal piezoelectric layer 3 to the upper surface of the silicon dioxide layer 2.
In this example, the single crystal piezoelectric layer 3 and the silicon dioxide layer 2 in the semi-finished product obtained in step 2 are respectively subjected to surface activation and then bonded, the single crystal piezoelectric layer 3 is transferred onto the silicon dioxide layer 2, and then the substrate in the single crystal piezoelectric layer 3 is removed, so as to finally obtain the composite single crystal piezoelectric substrate.
In particular, transferring the single crystal piezoelectric layer 3 to the upper surface of the silicon dioxide layer 2 may comprise:
respectively carrying out surface activation on the upper surface of the silicon dioxide layer 2 and the surface of the single crystal piezoelectric film in the single crystal piezoelectric layer 3;
bonding the silicon dioxide layer 2 after surface activation and the single crystal piezoelectric layer 3;
the substrate on the single crystal piezoelectric layer 3 is removed.
The bonding mode adopted by the embodiment can be a bonding mode without high-temperature treatment in the prior art, and the substrate material for bearing the single crystal piezoelectric layer is removed after bonding, so that the performance and the structural stability of the composite single crystal piezoelectric substrate are ensured.
The method for removing the substrate in the single crystal piezoelectric layer is not particularly limited in this example, and a method for removing the substrate in the prior art may be used, and for example, the substrate may be removed by a chemical solution etching, a reactive ion etching, a grinding process, or the like, or a combination thereof.
The silicon dioxide layer in the composite single crystal piezoelectric substrate is prepared on the silicon substrate layer in a thermal oxidation mode, the damaged layer penetrates through the silicon dioxide layer and is prepared on the surface layer of the single crystal silicon layer, the thickness uniformity of the silicon dioxide layer in the composite single crystal piezoelectric substrate is good, the defect density for capturing carriers in the damaged layer is large, the structure of the composite single crystal piezoelectric substrate is stable, the carriers generated due to inevitable defects on the interface of the silicon substrate layer and the silicon dioxide layer can be effectively captured, and therefore the performance of a device prepared based on the composite single crystal piezoelectric substrate is improved.
Furthermore, the composite single crystal piezoelectric substrate provided by the application has a compact and uniform silicon dioxide layer, and can provide sufficient carrier capture capacity, so that a conductive thin layer in the composite single crystal piezoelectric substrate is weakened, and signal loss caused by the conductive thin layer is reduced; according to the method for preparing the composite single crystal piezoelectric substrate, the silicon dioxide layer is prepared on the silicon substrate layer through a thermal oxidation method, ion implantation is performed on the interface of the silicon substrate layer and the silicon dioxide layer to form the damaged layer, the silicon dioxide layer is compact and uniform, the high-temperature process is arranged before the ion implantation, the structure and the performance stability of the damaged layer are guaranteed, the single crystal piezoelectric layer is bonded on the silicon dioxide layer through a normal-temperature bonding mode, the structure and the performance stability of the damaged layer are further guaranteed, and the composite single crystal piezoelectric film with excellent performance is finally obtained.
According to the preparation method, the silicon dioxide layer is prepared on the upper surface of the silicon substrate layer through a thermal oxidation mode, the compact and uniform silicon dioxide layer can be prepared at a lower temperature, the silicon dioxide layer has good performance and is stably combined with the silicon substrate layer, ion implantation is carried out on the surface layer of the monocrystalline silicon substrate layer through the silicon dioxide layer, so that a damage layer is prepared on the surface layer of the silicon substrate layer, and finally the monocrystalline piezoelectric layer prepared in advance is transferred to the upper surface of the silicon dioxide layer through a bonding mode, so that the damage to the composite monocrystalline piezoelectric substrate along the ion implantation layer due to high temperature in the process of preparing the monocrystalline piezoelectric layer is avoided.
The embodiment makes full use of the structural characteristics and the preparation process characteristics of the damaged layer and the silicon dioxide layer, skillfully sets the sequence of the process steps, sets the high-temperature process step before the damaged layer is formed, and the damaged layer is prepared through the silica layer in a remote space way, the requirements of poor thermal stability of the damaged layer and high-temperature process for preparing the silica layer are considered, the damaged layer is prevented from being in a high-temperature environment, therefore, the composite single crystal piezoelectric substrate with stable structure and excellent performance can be prepared through simpler process steps, the stable structure of the damaged layer is ensured, the defects of the amorphous silicon or polycrystalline silicon layer in the process of sequentially preparing the amorphous silicon or polycrystalline silicon layer and the silicon dioxide layer on the silicon substrate in the traditional scheme can be effectively recovered, the problems that the damaged layer is damaged by high-temperature process steps and the like are solved, and the carrier capture capacity of the damaged layer is ensured.
Examples
Example 1
Step 1, taking 4-inch monocrystalline silicon, and performing thermal oxidation treatment on the upper surface of the monocrystalline silicon, wherein the thermal oxidation treatment parameter is dry oxygen oxidation at 1000 ℃ to generate a 300nm silicon dioxide layer, and the thickness uniformity of the silicon dioxide layer is 1.5%;
step 2, ion implantation is carried out on the surface of the monocrystalline silicon layer through the silicon dioxide layer, and the implanted ions are H+Ion implantation concentration of 1011atoms/cm2The thickness of the formed damage layer (4) is 300 nm;
step 3, taking a 4-inch lithium tantalate wafer, and performing ion implantation on the lithium tantalate wafer to form a thin film layer, an implanted layer and a residual material layer on the lithium tantalate wafer, wherein the thickness of the thin film layer is 600 nm; bonding the lithium tantalate wafer after ion implantation on a silicon substrate, wherein the thin film layer is bonded with the silicon substrate; carrying out heat treatment on the bonding body to enable the lithium tantalate residual material layer to be stripped along the injection layer, forming a lithium tantalate film on the silicon substrate, and then carrying out annealing treatment on the lithium tantalate film to recover the lattice form of the lithium tantalate film;
and 4, transferring the lithium tantalate film to the upper surface of the silicon dioxide, and removing the silicon substrate on the lithium tantalate film to obtain the composite single crystal piezoelectric substrate.
In the composite single crystal piezoelectric substrate obtained in step 4 of this example, the thickness uniformity of the silicon dioxide layer is better than 2%, and the defect density of the damaged layer is 1011atoms/cm2In a use state, the resistivity of the silicon substrate layer is greater than 5000 Ω · cm.
Example 2
Step 1, taking 6-inch monocrystalline silicon, and carrying out thermal oxidation treatment on the upper surface of the monocrystalline silicon, wherein the thermal oxidation treatment parameter is 1200 ℃ wet-oxygen oxidation to generate a 700nm silicon dioxide layer, and the thickness uniformity of the silicon dioxide layer is 1%;
step 2, laser etching is carried out on the surface of the monocrystalline silicon layer through the silicon dioxide layer, and the intensity of the laser is 20J/cm2The thickness of the formed damage layer (4) is 500 nm;
step 3, taking a 6-inch lithium tantalate wafer, and performing ion implantation on the lithium tantalate wafer to form a thin film layer, an implanted layer and a residual material layer on the lithium tantalate wafer, wherein the thickness of the thin film layer is 900 nm; bonding the lithium tantalate wafer after ion implantation on a silicon substrate, wherein the thin film layer is bonded with the silicon substrate; carrying out heat treatment on the bonding body to enable the lithium tantalate residual material layer to be stripped along the injection layer, forming a lithium tantalate film on the silicon substrate, and then carrying out annealing treatment on the lithium tantalate film to recover the lattice form of the lithium tantalate film;
and 4, transferring the lithium tantalate film to the upper surface of the silicon dioxide, and removing the silicon substrate on the lithium tantalate film to obtain the composite single crystal piezoelectric substrate.
In the composite single crystal piezoelectric substrate obtained in step 4 of this example, the thickness uniformity of the silicon dioxide layer is better than 2%, and the defect density of the damaged layer is 1014atoms/cm2In the use state, the electric of the silicon substrate layerThe resistivity is more than 10000 omega cm.
Comparative example
Comparative example 1
Step 1, taking a 4-inch monocrystalline silicon substrate, and depositing 1um polycrystalline silicon by using an LPCVD (low pressure chemical vapor deposition) scheme;
step 2, depositing a 600 nm-thick silicon dioxide layer on the polysilicon by utilizing PECVD, wherein the thickness uniformity of the silicon dioxide layer is 3%;
step 3, performing chemical mechanical polishing on the silicon dioxide to obtain a smooth surface which can be used for bonding, wherein the silicon dioxide is polished to 300nm, and the uniformity of the silicon dioxide after polishing is 6%;
and 4, step 4: and (3) manufacturing a lithium tantalate single crystal thin film on the silicon dioxide layer obtained in the step (3) by using an ion implantation and bonding mode, wherein the thickness of the thin film layer is 900 nm.
The composite piezoelectric substrate obtained in the present comparative example had a thickness uniformity of the silica layer of less than 6%, and in the used state, the temperature coefficient of frequency and the center frequency uniformity of the final device were deteriorated because the thickness uniformity of the silica layer was poor.
The present application has been described in detail with reference to specific embodiments and illustrative examples, but the description is not intended to limit the application. Those skilled in the art will appreciate that various equivalent substitutions, modifications or improvements may be made to the presently disclosed embodiments and implementations thereof without departing from the spirit and scope of the present disclosure, and these fall within the scope of the present disclosure. The protection scope of this application is subject to the appended claims.

Claims (10)

1. The composite single crystal piezoelectric substrate is characterized by sequentially comprising a silicon substrate layer (1), a silicon dioxide layer (2) and a single crystal piezoelectric layer (3) from bottom to top, wherein the silicon substrate layer (1) is damaged from an interface between the silicon substrate layer and the silicon dioxide layer to an area with a preset depth inside the silicon substrate layer to form a damaged layer (4), and the damaged layer (4) is connected with the silicon dioxide layer (2).
2. The composite single-crystal piezoelectric substrate according to claim 1,
the defect density of the damage layer (4) is at least 1011atoms/cm2(ii) a And/or
The thickness of the damage layer (4) is 300 nm-3 mu m.
3. The composite single crystal piezoelectric substrate according to claim 1 or 2, wherein the damaged layer (4) is formed by means of ion implantation or laser ablation.
4. The composite single-crystal piezoelectric substrate according to any one of claims 1 to 3,
the silicon dioxide layer (2) is prepared by a thermal oxidation method; and/or
The thickness uniformity of the silicon dioxide layer (2) is less than 2%.
5. The composite single-crystal piezoelectric substrate according to any one of claims 1 to 4, wherein the composite single-crystal piezoelectric substrate is produced by a method comprising:
performing thermal oxidation treatment on the upper surface of the silicon substrate layer to generate a silicon dioxide layer;
penetrating through the silicon dioxide layer to damage the surface of the silicon substrate layer connected with the silicon dioxide layer to form a damaged layer;
and preparing a single crystal piezoelectric layer, and superposing the single crystal piezoelectric layer, the silicon dioxide layer, the damage layer and the silicon substrate layer to form the composite single crystal piezoelectric substrate.
6. A method of producing the composite single-crystal piezoelectric substrate according to any one of claims 1 to 5, comprising:
performing thermal oxidation treatment on the upper surface of the silicon substrate layer to generate a silicon dioxide layer;
damaging the surface of the silicon substrate layer through the silicon dioxide layer to form a damaged layer;
and preparing a single crystal piezoelectric layer, and superposing the single crystal piezoelectric layer, the silicon dioxide layer, the damage layer and the silicon substrate layer to form the composite single crystal piezoelectric substrate.
7. The method of claim 6, wherein damaging the surface of the silicon substrate layer through the silicon dioxide layer comprises ion implantation and laser ablation.
8. The method of claim 7,
in the ion implantation method, the concentration of ion implantation is at least 1011atoms/cm2(ii) a And/or
In the laser ablation method, the wavelength of the laser is 200 nm-1064 nm, and the energy density is 1J/cm2～100J/cm2。
9. The method of any of claims 6 to 8, wherein the preparing the single crystal piezoelectric layer comprises:
carrying out ion implantation on the single crystal piezoelectric wafer bonded on the substrate material to form a thin film layer, an implanted layer and a residual material layer;
bonding a substrate with the thin film layer of the single crystal piezoelectric wafer;
and peeling the residual material layer from the thin film layer along the injection layer.
10. The method of any of claims 6 to 9, wherein transferring the single crystal piezoelectric layer to the low acoustic resistance layer upper surface comprises:
respectively carrying out surface activation on the upper surface of the silicon dioxide layer and the surface of the single crystal piezoelectric layer;
bonding the low-acoustic-resistance layer with the single crystal piezoelectric layer after surface activation;
and removing the substrate material on the single crystal piezoelectric layer.
CN202010315140.3A 2020-04-21 2020-04-21 Composite single crystal piezoelectric substrate and preparation method thereof Pending CN113541626A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115867106A (en) * 2023-02-27 2023-03-28 青禾晶元(天津)半导体材料有限公司 Composite piezoelectric substrate and preparation method and application thereof
CN116887658A (en) * 2023-08-24 2023-10-13 北京超材信息科技有限公司 Composite substrate, manufacturing method and application

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115867106A (en) * 2023-02-27 2023-03-28 青禾晶元(天津)半导体材料有限公司 Composite piezoelectric substrate and preparation method and application thereof
CN115867106B (en) * 2023-02-27 2023-12-08 青禾晶元(天津)半导体材料有限公司 Composite piezoelectric substrate and preparation method and application thereof
CN116887658A (en) * 2023-08-24 2023-10-13 北京超材信息科技有限公司 Composite substrate, manufacturing method and application

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