WO2022142205A1 - 信号处理电路和装置 - Google Patents

信号处理电路和装置 Download PDF

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Publication number
WO2022142205A1
WO2022142205A1 PCT/CN2021/102851 CN2021102851W WO2022142205A1 WO 2022142205 A1 WO2022142205 A1 WO 2022142205A1 CN 2021102851 W CN2021102851 W CN 2021102851W WO 2022142205 A1 WO2022142205 A1 WO 2022142205A1
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Prior art keywords
signal
circuit
pass filter
frequency
processing circuit
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PCT/CN2021/102851
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English (en)
French (fr)
Inventor
周鑫
苏雷
张宇翔
黎美琪
廖风云
齐心
Original Assignee
深圳市韶音科技有限公司
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Application filed by 深圳市韶音科技有限公司 filed Critical 深圳市韶音科技有限公司
Priority to EP21912961.6A priority Critical patent/EP4203345A4/en
Priority to CN202180070831.4A priority patent/CN116964963A/zh
Priority to KR1020237013272A priority patent/KR20230070281A/ko
Priority to JP2023524766A priority patent/JP2023547159A/ja
Publication of WO2022142205A1 publication Critical patent/WO2022142205A1/zh
Priority to US18/181,575 priority patent/US20230216486A1/en

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    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/30—Input circuits therefor
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/30—Input circuits therefor
    • A61B5/304—Switching circuits
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/68—Arrangements of detecting, measuring or recording means, e.g. sensors, in relation to patient
    • A61B5/6801—Arrangements of detecting, measuring or recording means, e.g. sensors, in relation to patient specially adapted to be attached to or worn on the body surface
    • A61B5/6802—Sensor mounted on worn items
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/30—Input circuits therefor
    • A61B5/305—Common mode rejection
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/30—Input circuits therefor
    • A61B5/307—Input circuits therefor specially adapted for particular uses
    • A61B5/313—Input circuits therefor specially adapted for particular uses for electromyography [EMG]
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/68—Arrangements of detecting, measuring or recording means, e.g. sensors, in relation to patient
    • A61B5/6801—Arrangements of detecting, measuring or recording means, e.g. sensors, in relation to patient specially adapted to be attached to or worn on the body surface
    • A61B5/6802—Sensor mounted on worn items
    • A61B5/6804—Garments; Clothes
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/72—Signal processing specially adapted for physiological signals or for diagnostic purposes
    • A61B5/7203—Signal processing specially adapted for physiological signals or for diagnostic purposes for noise prevention, reduction or removal
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/72—Signal processing specially adapted for physiological signals or for diagnostic purposes
    • A61B5/7225—Details of analog processing, e.g. isolation amplifier, gain or sensitivity adjustment, filtering, baseline or drift compensation
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/72—Signal processing specially adapted for physiological signals or for diagnostic purposes
    • A61B5/7235—Details of waveform analysis
    • A61B5/725—Details of waveform analysis using specific filters therefor, e.g. Kalman or adaptive filters
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B13/00—Transmission systems characterised by the medium used for transmission, not provided for in groups H04B3/00 - H04B11/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H2011/0488—Notch or bandstop filters

Definitions

  • the present application generally relates to the field of circuit design, and more particularly, to a circuit and apparatus for processing physiological signals.
  • physiological signal monitoring devices As people pay more and more attention to scientific sports and physiological health, the demand for physiological signal monitoring devices is also increasing.
  • the strength of some physiological signals (for example, the EMG signal when the user is exercising) is weak, and in the presence of noise, it is difficult for general signal processing circuits to retain effective physiological signals after removing the noise. Therefore, it is desirable to provide a signal processing circuit suitable for a physiological signal monitoring device, which can process specific physiological signals in a targeted manner.
  • Embodiments of the present application provide a signal processing circuit.
  • the signal processing circuitry may include analog circuitry.
  • An analog circuit can be used to process the original signal it receives.
  • the initial signal may include a target signal and a noise signal.
  • the analog circuit may include a first processing circuit and a second processing circuit connected to the first processing circuit.
  • the first processing circuit may be configured to improve the signal-to-noise ratio of the initial signal to output a first processed signal.
  • the second processing circuit may be configured to amplify the first processing signal, and the gain multiple of the first processing signal by the second processing circuit varies with the frequency of the first processing signal.
  • the first processing circuit may include a common mode signal rejection circuit, a low pass filter circuit and a high pass filter circuit.
  • the common mode signal suppression circuit may be used to suppress the common mode signal in the initial signal.
  • the common mode signal rejection circuit may include a differential amplifier.
  • the low-pass filter circuit may include a bridge circuit structure formed at the input of the differential amplifier.
  • the input impedance of the differential amplifier is greater than 10 M ⁇ .
  • the cut-off frequency point of the low-pass filter circuit may be within a frequency range of 100Hz-1000Hz.
  • the cut-off frequency point of the high-pass filter circuit is within the frequency range of 5Hz-200Hz.
  • the first processing circuit may include a trap circuit for suppressing the power frequency signal.
  • the trap circuit may include a cascade trap circuit, and the cascade trap circuit is further configured to suppress harmonics of the power frequency signal.
  • the trap circuit may comprise a dual-T active trap circuit.
  • the first processing circuit may further include a voltage-controlled low-pass filter circuit for providing gain around its target frequency in combination with the low-pass filter circuit to compensate for the attenuation of the low-pass filter circuit.
  • the first processing circuit may include performing amplification processing on the target signal by a first amplification factor, and performing amplification processing on the target signal.
  • the noise signal is attenuated.
  • the second processing circuit may include an amplification circuit, a feedback circuit and a follower.
  • the amplifying circuit may be configured to perform amplifying processing on the first processing signal by a second amplification factor, where the second amplification factor is greater than the first amplification factor.
  • the follower can be used to isolate the influence of the output terminal of the signal processing circuit.
  • the gain response of the second processing circuit to the first processed signal in a first frequency range is greater than the gain response outside the first frequency range.
  • the first frequency range may include 20Hz-140Hz.
  • the initial signal may comprise an electromyographic signal.
  • the signal processing circuit may further include a control circuit, a switch circuit, and at least two signal acquisition circuits.
  • the at least two signal acquisition circuits may be used to acquire at least two channels of initial signals.
  • the switch circuit can be used to control the conduction between the at least two signal acquisition circuits and the analog circuit, so that only part of the initial signals acquired by the signal acquisition circuits of the at least two signal acquisition circuits are transmitted to the analog circuit at the same time. the analog circuit.
  • the control circuit may be configured to receive the target signal processed by the analog circuit, and sample the processed target signal.
  • the switch circuit may include a plurality of input channels, each of the at least two signal acquisition circuits is independently connected to an input channel, and at the same time, the switch circuit is based on the control circuit The control signal selects an input channel to turn on.
  • the signal processing device includes a signal processing circuit.
  • the signal processing circuitry may include analog circuitry.
  • An analog circuit can be used to process the original signal it receives.
  • the initial signal may include a target signal and a noise signal.
  • the analog circuit may include a first processing circuit and a second processing circuit connected to the first processing circuit.
  • the first processing circuit may be configured to improve the signal-to-noise ratio of the initial signal to output a first processed signal.
  • the second processing circuit may be configured to amplify the first processing signal, and the gain multiple of the first processing signal by the second processing circuit varies with the frequency of the first processing signal.
  • the first processing circuit may include a common mode signal rejection circuit, a low pass filter circuit and a high pass filter circuit.
  • the common mode signal suppression circuit may be used to suppress the common mode signal in the initial signal.
  • FIG. 1 is a schematic diagram of an exemplary circuit of a signal acquisition device according to some embodiments of the present application
  • FIG. 2 is an exemplary flowchart of a signal processing method according to some embodiments of the present application.
  • 3A is a schematic block diagram of an exemplary signal processing circuit according to some embodiments of the present application.
  • 3B is a frequency response curve diagram of various cascaded trap circuits according to some embodiments of the present application.
  • 4A-4C are schematic structural diagrams of exemplary low-pass filter circuits according to some embodiments of the present application.
  • 4D is a frequency response curve diagram of the low-pass filter circuit in FIGS. 4A, 4B and 4C;
  • 5A-5B are schematic structural diagrams of low-pass filter circuits according to some embodiments of the present application.
  • 5C is a frequency response curve diagram of the low-pass filter circuit in FIGS. 5A and 5B;
  • 6A is a schematic structural diagram of a RC low-pass filter circuit according to some embodiments of the present application.
  • 6B is a frequency response curve diagram of the second-order distributed low-pass filter circuit and the resistance-capacitance low-pass filter circuit in FIG. 6A;
  • FIG. 7A is a schematic structural diagram of a voltage-controlled low-pass filter circuit according to some embodiments of the present application.
  • FIG. 7B is a frequency response curve diagram of the second-order low-pass filter circuit and the voltage-controlled low-pass filter circuit in FIG. 7A;
  • FIG. 8A is a schematic structural diagram of an exemplary low-pass filter circuit according to some embodiments of the present application.
  • FIG. 8B is a frequency response curve diagram of the low-pass filter circuit in FIG. 8A;
  • 9A-9B are schematic structural diagrams of exemplary high-pass filter circuits according to some embodiments of the present application.
  • Figure 9C is a frequency response graph of the high-pass filter circuit in Figures 9A-9B;
  • 10A is a schematic diagram of a circuit architecture of an exemplary signal processing circuit according to some embodiments of the present application.
  • Fig. 10B is the frequency response curve of the signal processing circuit in Fig. 10A;
  • FIG. 11 is a schematic diagram of a circuit architecture of an exemplary signal processing circuit according to some embodiments of the present application.
  • FIG. 12A is a schematic diagram of a circuit architecture of an exemplary signal processing circuit according to some embodiments of the present application.
  • FIG. 12B is a frequency response curve when the frequency response peak of the signal processing circuit in FIG. 12A is 80 Hz;
  • 12C is a schematic diagram of the circuit architecture of an exemplary signal processing circuit according to some embodiments of the present application.
  • Fig. 12D is a frequency response curve when the frequency response peak of the signal processing circuit in Fig. 12C is 80 Hz;
  • FIG. 13 is a comparison diagram of a frequency response curve of a signal processing circuit measured at different times and a simulated frequency response curve according to some embodiments of the present application.
  • FIG. 14 is an electromyographic signal collected when a bicep curl experiment is performed using a signal processing circuit according to some embodiments of the present application.
  • the mechanical connection between the two elements may comprise a welded connection, a keyed connection, a pinned connection, an interference fit connection, etc., or any combination thereof.
  • Other words used to describe the relationship between the elements should be interpreted in a like fashion (eg, "between”, “between”, “adjacent” versus “directly adjacent”, etc.).
  • the signal processing circuit and method described in the embodiments of the present application can be applied to a signal monitoring device that needs to collect one or more signal sources, especially a monitoring device for physiological signals, such as a smart wearable device.
  • a monitoring device for physiological signals such as a smart wearable device.
  • the smart wearable devices eg, clothing, wristbands, shoulder straps, etc.
  • the human body e.g, calves, thighs, waist, back, chest, shoulders, neck, etc.
  • the collected signals can be further processed subsequently.
  • the physiological signal is a signal that can be detected and can reflect a physical state, for example, may include a breathing signal, an electrocardiographic signal (ECG), an electromyographic signal, a blood pressure signal, a temperature signal, and other signals.
  • ECG electrocardiographic signal
  • the frequency range of the physiological signal may include 0.05 Hz to 2 kHz, wherein the frequency range of the electrocardiographic signal may include 0.05 Hz to 100 Hz, and the range of the electromyographic signal may include 5 Hz to 2 kHz.
  • noise reduction processing may be performed on the acquired signal in advance to prevent Subsequent noise is amplified to saturation and the target signal is lost.
  • performing noise reduction and then amplifying processing on the collected signal can also leave more processing margin for the target signal.
  • Embodiments of the present application provide a signal processing circuit.
  • the signal processing circuitry may include analog circuitry.
  • An analog circuit can be used to process the original signal it receives.
  • the initial signal may include a target signal and a noise signal.
  • the analog circuit may include a first processing circuit and a second processing circuit connected to the first processing circuit.
  • the first processing circuit may be configured to improve the signal-to-noise ratio of the initial signal to output a first processed signal.
  • the second processing circuit may be configured to amplify the first processing signal, and the gain multiple of the first processing signal by the second processing circuit varies with the frequency of the first processing signal.
  • the first processing circuit may include a common mode signal rejection circuit, a low pass filter circuit and/or a high pass filter circuit.
  • the common mode signal suppression circuit can be used to suppress the common mode signal in the input signal.
  • the noise signal in the acquired signal may annihilate the valid physiological signal during signal processing (eg, amplification). If, for example, amplification is performed on the collected signal before the noise signal is removed, the circuit may be saturated and the physiological signal cannot be effectively extracted. For example, power frequency signals (noise) may be introduced in the process of collecting EMG signals.
  • the first processing circuit performs noise reduction processing on the physiological signal, and then the second processing circuit performs amplification processing on the noise reduction physiological signal, which can prevent the physiological signal acquisition process from being Anomalies occur that cause circuit saturation during processing, resulting in accurate, high-quality physiological signals.
  • FIG. 1 is a schematic diagram of an exemplary circuit 100 of a signal acquisition apparatus according to some embodiments of the present application.
  • the circuit 100 of the signal acquisition device can realize the acquisition and processing of multiple channels of physiological signals.
  • the circuit 100 adopts the time-division multiplexing scheme, which can save space and economic cost, save hardware resources such as ADC, and prevent crosstalk while ensuring the acquisition and processing of multiple signal sources.
  • the circuit 100 may include at least two signal acquisition circuits (eg, signal acquisition circuits 112 , 114 , 116 and 118 ), a switch circuit 120 , an analog circuit 130 and a control circuit 140 .
  • the switch circuit 120 can be disposed between the multiplexed signal acquisition circuits and the analog circuit 130 , and can be used to control the conduction state of each of the signal acquisition circuits and the analog circuit 130 . For example, at a certain point in time, the switch circuit 120 may turn on one signal acquisition circuit and the analog circuit 130 . Within a certain time range, the switch circuit 120 may cycle through each signal acquisition circuit and the analog circuit 130 in a periodic manner. When the switch circuit 120 turns on a certain signal acquisition circuit and the analog circuit 130, the signal collected by the signal acquisition circuit (for example, the EMG signal) can be transmitted to the analog circuit 130 for processing (for example, noise reduction, amplification, etc. ), and the processed signal will be transmitted to the control circuit 140 for signal analysis.
  • the signal collected by the signal acquisition circuit for example, the EMG signal
  • processing for example, noise reduction, amplification, etc.
  • the switch circuit 120 can process the signals collected by different signal acquisition circuits at different time points, which can effectively reduce the use of The complexity and cost of multiple analog circuits also reduces the number of channels for signaling between subsequent analog circuits and control circuits.
  • the switch circuit 120 and the analog circuit 130 shown in FIG. 1 are only for the purpose of illustration. In actual use, more than one switch circuit or Analog circuits, these switching circuits or analog circuits can still implement a process similar to that described above.
  • the at least two signal acquisition circuits may be used to acquire at least two target signals.
  • the target signal may be a physiological signal capable of reflecting the user's physical state, such as one or more of a breathing signal, an electrocardiogram (ECG) signal, an electromyography signal, a blood pressure signal, a temperature signal, and the like.
  • ECG electrocardiogram
  • different signal acquisition circuits may respectively include one or more electrodes in contact with the user's body, and the electromyographic signals on the surface of the user's body may be collected through the electrodes.
  • Different signal acquisition circuits can be arranged at different positions of the user's body to acquire physiological signals of the same or different types of users.
  • the signal acquisition circuits respectively arranged on different sides of the user's thighs may all be used to acquire the EMG signals at the thighs.
  • the signal acquisition circuit arranged at the user's forearm can be used to collect the EMG signal at the forearm
  • the signal acquisition circuit arranged at the user's heart can be used to collect the user's ECG signal.
  • the circuit 100 or similar circuits can be used to collect and process the above physiological signals of the same kind or different kinds, which is not limited in this application.
  • the at least two signal acquisition circuits may include only two signal acquisition circuits, or may include three signal acquisition circuits, four signal acquisition circuits, or more signal acquisition circuits.
  • the frequency range of the physiological signal may include 0.05 Hz to 2 kHz, wherein the frequency range of the electrocardiographic signal may include 0.05 Hz to 100 Hz, and the range of the electromyographic signal may include 5 Hz to 2 kHz.
  • the control circuit 140 samples the signal processed by the analog circuit 130 .
  • the sampling frequency of the control circuit 140 is related to the number of signal acquisition circuits, the control strategy for the switch circuit 120 and the target frequency.
  • the sampling frequency of each signal by the control circuit 140 is not lower than twice its target frequency.
  • the control circuit 140 can use the sampling frequency of 2000 Hz to sample the EMG signal.
  • the control circuit 140 needs to provide a total sampling frequency of 8000 Hz, so as to ensure that the sampling rate of each EMG signal reaches 2000 Hz.
  • control circuit 140 may employ a fully reconfigurable strategy and an intensity characterization strategy to control the switching of the switch circuit 120 .
  • the sampling frequency is related to the number of signal acquisition circuits, the rising edge and falling edge time of a single channel, etc., wherein the rising edge and falling edge time of a single channel are related to the output voltage amplitude of the analog circuit 130 (which is related to the magnification and input voltage amplitude) and the slew rate of the circuit elements.
  • the switch circuit 120 may be used to control the conduction between the at least two signal acquisition circuits and the analog circuit 130, so that only part of the signals in the at least two signal acquisition circuits are at the same time.
  • the target signal collected by the collection circuit is transmitted to the analog circuit 130 .
  • the input end of the switch circuit 120 may be connected to the at least two signal acquisition circuits, and the output end of the switch circuit 120 may be connected to the analog circuit 130 .
  • the switch circuit 120 may include multiple input channels, and each signal acquisition circuit in the at least two signal acquisition circuits may be independently connected to an input channel. At the same time, the switch circuit 120 may be based on The control signal of the control circuit 140 selects one input channel to be turned on.
  • the switch circuit 120 may select a switch chip with multiple channels and dual outputs, for example, a switch chip with a model of TMUX1209.
  • the switch circuit 120 can realize time-division multiplexing of 4 channels through 3 control pins, of which 1 pin EN is marked as enable function, and the other two pins A1 and A0 are marked as selection. aisle.
  • the four input channels of the switch circuit 120 are respectively used to connect to the signal acquisition circuit to acquire the target signal, and the output port of the switch circuit 120 is connected to the analog circuit 130 .
  • the gating of the switch chip can be controlled by the values of the control pins (EN, A1, A0).
  • the control circuit 140 when (1, 0, 0) is input, it means strobe channel A, when (1, 0, 1) is input, it means strobe channel B, and when (1, 1, 0) is input, it means strobe channel Channel C, when (1, 1, 1) is input, indicates strobe channel D.
  • the control circuit 140 selects the channel A of the switch circuit 120 , the target signal corresponding to the channel A will be connected to the analog circuit 130 and finally sampled by the control circuit 140 . After this sampling is successful, the control circuit 140 will give a new control command, for example, the command (1, 0, 1) can be given for gating channel B, then the target signal of channel B will be connected to the analog circuit 130 And finally sampled by the control circuit 140, and so on.
  • control circuit 140 can control the switch circuit 120 to cyclically switch among multiple signal acquisition circuits, so as to achieve the effect of time-division multiplexing, that is, one analog circuit 130 can process multiple signal sources in time-division, thereby saving space cost and reduce hardware requirements.
  • the control circuit 140 may control the switching of the switch circuit 120 based on different strategies. For example, in order to enable the subsequent sampling data to completely retain the information of each target signal (ie, the control circuit 140 can reconstruct each target signal based on the sampled data), the control circuit 140 can use a fully reconstructed strategy to control the switching circuit 120. switch. Under the fully reconfigurable strategy, the control circuit 140 can switch the input channels of the switch circuit 120 according to the total sampling frequency it provides. For example, the frequency at which the switching circuit 120 switches the input channels may be equal to the sampling frequency provided by the control circuit 140. In this case, each time the switch circuit 120 switches the input channel, that is, each time one signal acquisition circuit is turned on, the control circuit 140 will sample the target signal acquired by the signal acquisition circuit once.
  • the fully reconstructed strategy can ensure that each target signal has at least two sampling points in each cycle. More details about the fully reproducible control strategy can be found in the detailed description of Figure 2.
  • the control circuit 140 may use an intensity-characterized strategy to control the switching of the switch circuit 120.
  • the control circuit 140 may switch the input channel of the switch circuit 120 based on a preset frequency.
  • the preset frequency may be related to a period during which the user performs a certain action.
  • the preset frequency may be a certain multiple of the frequency at which the user performs a specific action (for example, bench press), so that when the user performs one of the specific actions
  • the switch circuit 120 can turn on each signal acquisition circuit for multiple times, so that the control circuit 140 can separately sample each target signal for multiple times.
  • the control circuit 140 may acquire intensity information of each target signal based on the sampling result. More details about the intensity-represented strategy can be found in the detailed description of Figure 2.
  • the analog circuit 130 is used for processing the received target signal.
  • the analog circuit 130 since the amplitude of the original target signal directly collected by the signal collection circuit is very small and has a large amount of noise, the analog circuit 130 needs to be used to filter, differentially amplify, amplify, and negatively feedback the original target signal. Noise cancellation, etc.
  • the analog circuit 130 may also be referred to as a signal processing circuit.
  • the analog circuit 130 may include a differential amplifier for suppressing common-mode signals and amplifying the received target signal.
  • the analog circuit 130 may include a multi-stage amplification circuit for performing multi-stage amplification processing on the received target signal.
  • the analog circuit 130 may include a filter circuit for filtering the received target signal.
  • Exemplary filtering processes include high-pass filtering, low-pass filtering, band-pass filtering, or filtering to remove specific frequency components, and the like. The filtering process may occur before all amplification processes, or between the multi-stage amplification processes.
  • the analog circuit 130 may include a right leg drive circuit, which is used to extract the common mode signal in the target signal received by the analog circuit 130, and feedback it back to the signal source after inverse amplification, which can mainly suppress the common mode signal in the signal source. power frequency.
  • the analog circuit 130 may include a differential amplifier, a multi-stage amplifier, a filter circuit and a right leg drive circuit at the same time, or only one or more of them. More descriptions of signal processing circuits can be found elsewhere in this application (eg, FIGS. 3A-12C and their descriptions).
  • control circuit 140 may be configured to receive the target signal processed by the analog circuit 130 and sample the processed target signal.
  • the control circuit 140 may include a plurality of analog-to-digital conversion channels (ie, ADC channels), each ADC channel may be used to convert the received target signal processed by the analog circuit 130 into a digital signal Read and process.
  • the control circuit 140 may also be connected to a display device, so as to display the read digital signal, so as to visually reflect the condition of the physiological signal.
  • the control circuit 140 may read, store, process and analyze the target signal, and optionally, the control circuit 140 may also issue corresponding instructions according to the sampled data.
  • the sampling of each processed target signal by the control circuit 140 occurs a period of time after the control circuit 140 starts to receive the processed each target signal. That is to say, after the switch circuit 120 switches the conduction channel, the control circuit 140 will not immediately sample the newly turned-on target signal, or even if the control circuit 140 samples the newly turned-on target signal, it will not immediately sample the newly turned-on target signal. Take the sampled result as part of the target signal.
  • the switching of the switching channels will cause the signals received by the control circuit 140 to have certain rising and falling edges.
  • the rising edge corresponds to the time it takes for a signal change at the input to cause the signal at the output to rise until it reaches a steady state.
  • the falling edge corresponds to the time it takes for a signal change at the input to cause the signal at the output to drop until it stabilizes.
  • the rising edge and the falling edge may be jointly affected by multiple factors, including the response and stabilization speed of the switching circuit 120 , the voltage swing of the chip in the circuit, and the charging and discharging of devices such as capacitors in the circuit. Therefore, in order to ensure that the target signal read by the control circuit 140 is truly valid, the sampling of the target signal will be performed after the signal is stable, that is, after the switch circuit 120 switches the conduction channel, the control circuit 140 does not respond to the signal during the rising edge time. to sample.
  • the value finally read by the control circuit 140 will be an intermediate transition value. It can be understood that if the rising edge time is fixed, even if the waiting time is insufficient, the final obtained transition value is proportional to the real value, which can be used for subsequent processing and analysis. However, when the rising edge time is related to the magnitude of the voltage change, if the reading is not stabilized, the ratio of the value read each time by the control circuit 140 to the actual value is not fixed and cannot be used for subsequent processing. In addition, it can be understood that if the relationship between the transition value and the stable value is clearly considered, or the error between the transition value and the stable value can be accepted, then even if the waiting time is insufficient, it can be used for subsequent processing and analysis.
  • the strength of the target signal and the gain of the circuit should be considered to obtain the maximum rising edge time as a reference for the waiting time of the control circuit 140.
  • a reference time that is not less than the maximum rising edge time can be set. The sampling of each target signal by the control circuit 140 occurs after the reference time when the control circuit 140 starts to receive the target signal, or the control circuit 140 controls The sampling of the target signal by the circuit 140 occurs after the reference time each time the switching circuit switches the conducting channel.
  • FIG. 2 is an exemplary flowchart of a signal processing method according to some embodiments of the present application.
  • process 200 may be implemented by circuit 100 .
  • Step 210 Collect at least two target signals through at least two signal collecting circuits.
  • step 210 may be implemented by at least two signal acquisition circuits in circuit 100 (eg, signal acquisition circuits 112, 114, 116, and 118).
  • the at least two signal acquisition circuits may be used to acquire at least two target signals.
  • the target signal may be a physiological signal capable of reflecting the user's physical state, such as one or more of a breathing signal, an electrocardiogram (ECG) signal, an electromyography signal, a blood pressure signal, a temperature signal, and the like.
  • ECG electrocardiogram
  • different signal acquisition circuits may respectively include one or more electrodes in contact with the user's body, and the electromyographic signals on the surface of the user's body may be collected through the electrodes.
  • Different signal acquisition circuits can be arranged at different positions of the user's body to acquire physiological signals of the same or different types of users.
  • the signal acquisition circuits respectively arranged on different sides of the user's thighs may all be used to acquire the EMG signals at the thighs.
  • the signal acquisition circuit arranged at the user's forearm can be used to collect the EMG signal at the forearm
  • the preference acquisition circuit arranged at the user's heart can be used to collect the user's ECG signal.
  • the circuit 100 or similar circuits can be used to collect and process the above physiological signals of the same kind or different kinds, which is not limited in this application.
  • the at least two signal acquisition circuits may include only two signal acquisition circuits, or may include three signal acquisition circuits, four signal acquisition circuits, or more signal acquisition circuits.
  • the frequency range of the physiological signal may include 0.05 Hz to 2 kHz, wherein the frequency range of the electrocardiographic signal may include 0.05 Hz to 100 Hz, and the range of the electromyographic signal may include 5 Hz to 2 kHz.
  • Step 220 Control the conduction between the at least two signal acquisition circuits and the analog circuit through the switch circuit, so that only part of the target signals collected by the signal acquisition circuits in the at least two signal acquisition circuits are transmitted to the analog circuit at the same time.
  • step 220 may be implemented by switch circuit 120 in circuit 100 .
  • the input terminal of the switch circuit may be connected to the at least two signal acquisition circuits, and the output terminal of the switch circuit may be connected to an analog circuit (eg, the analog circuit 130 ).
  • the switch circuit may include a plurality of input channels, each signal acquisition circuit of the at least two signal acquisition circuits is individually connected to an input channel, and at the same time, the switch circuit may be based on a control circuit (eg, The control signal of the control circuit 140) selects one input channel to be turned on.
  • the switch circuit may implement the conduction between the signal acquisition circuit and the analog circuit based on a control instruction of the control circuit.
  • a control instruction of the control circuit For example, an instruction can be given for gating channel B, then the target signal of channel B will be connected to the analog circuit 130 and finally sampled by the control circuit, And so on.
  • control circuit 140 can control the switch circuit 120 to cyclically switch among multiple signal acquisition circuits, so as to achieve the effect of time-division multiplexing, that is, one analog circuit 130 can process multiple signal sources in time-division, thereby saving space cost and reduce hardware requirements.
  • step 230 the received target signal is processed by an analog circuit.
  • step 230 may be implemented by analog circuit 130 in circuit 100 .
  • the analog circuit 130 since the amplitude of the original target signal directly collected by the signal collection circuit is very small and has a large amount of noise, the analog circuit 130 needs to be used to filter, differentially amplify, amplify, and negatively feedback the original target signal. Noise cancellation, etc.
  • the analog circuit 130 may include a differential amplifier for suppressing common-mode signals and amplifying the received target signal.
  • the analog circuit 130 may include a multi-stage amplifying circuit for amplifying the received target signal.
  • the analog circuit 130 may include a filter circuit for filtering the received target signal.
  • the analog circuit 130 may include a right leg drive circuit, which is used to extract the common mode signal in the target signal received by the analog circuit 130, and feedback it back to the signal source after inverse amplification, which can mainly suppress the common mode signal in the signal source. power frequency.
  • the analog circuit 130 may include a differential amplifier, a multi-stage amplifier, a filter circuit and a right leg drive circuit at the same time, or only one or more of them.
  • the gain of the analog circuit to the target signal ie, reduce the amplification factor in the analog circuit
  • it is possible to reduce the gain of the analog circuit to the target signal ie, reduce the amplification factor in the analog circuit
  • select a control chip with a high-precision ADC channel and/or choose to use a resistor to adjust the reference potential to solve the problem of baseline drift, and/or choose to add high-pass filtering in the analog circuit 130 to filter out the baseline drift.
  • Step 240 Receive the target signal processed by the analog circuit through the control circuit, and sample the processed target signal.
  • step 240 may be implemented by control circuit 140 in circuit 100 .
  • control circuit 140 includes a plurality of ADC channels, and each ADC channel can be used to convert the received target signal processed by the analog circuit 130 into a digital signal for reading and processing.
  • control circuit 140 may also be connected to a display device, so as to display the read digital signal, so as to visually reflect the condition of the physiological signal.
  • control circuit 140 may read, store, process and analyze the target signal, and optionally, the control circuit 140 may also issue corresponding instructions according to the sampled data.
  • the sampling of each processed target signal by the control circuit 140 occurs a period of time after the control circuit 140 starts to receive the processed each target signal. That is to say, after the switch circuit 120 switches the conduction channel, the control circuit 140 will not immediately sample the newly turned-on target signal, or even if the control circuit 140 samples the newly turned-on target signal, it will not immediately sample the newly turned-on target signal. Take the sampled result as part of the target signal.
  • the sampling frequency of the control circuit 140 is related to the number of signal acquisition circuits, the type of target signal, and the target frequency.
  • the sampling frequency of each signal by the control circuit 140 is not lower than twice its target frequency.
  • the control circuit can use the adopted frequency of 2000 Hz to sample the EMG signal.
  • the control circuit 140 needs to provide a total sampling frequency of 8000 Hz, so as to ensure that the sampling rate of each EMG signal reaches 2000 Hz.
  • control circuit 140 may control the switching of the switch circuit 120 based on different strategies.
  • the control circuit 140 can use a complete reconstruction strategy to control Switching of the switch circuit 120 .
  • the control circuit 140 can switch the input channels of the switch circuit 120 according to the total sampling frequency it provides. For example, the frequency at which the switching circuit 120 switches the input channels may be equal to the sampling frequency provided by the control circuit 140 .
  • the control circuit 140 will sample the target signal acquired by the signal acquisition circuit once.
  • the sampling frequency of each target signal by the control circuit 140 is more than twice the target frequency, the fully reconstructed strategy can ensure that each target signal has at least two sampling points in each cycle.
  • the control circuit provides a sampling frequency of 2kHz for each EMG signal.
  • a total sampling frequency of 8 kHz is provided.
  • the switch circuit also switches between the four signal acquisition circuits at a frequency of 8kHz, which switches every 125 microseconds. Between every two adjacent switches of the switch circuit, the control circuit samples the received EMG signal once. .
  • control circuit can completely reproduce the corresponding multi-channel target signal based on the obtained sampling data. For example, the control circuit can reconstruct each target signal, and further analyze the frequency, phase, intensity (amplitude) and other information in each target signal.
  • control circuit may send the obtained sampling data or the reconstructed target signal to an external processing circuit for analysis in a wired or wireless manner.
  • the frequency at which the switching circuit 120 switches the input channel may also be equal to half the sampling frequency or other fractional value provided by the control circuit 140 .
  • the control circuit 140 may sample the target signal acquired by the signal acquisition circuit twice.
  • the control circuit provides a sampling frequency of 2kHz for each EMG signal.
  • a total sampling frequency of 8 kHz is provided. The switch circuit only needs to switch between the 4 signal acquisition circuits at a frequency of 4kHz, which switches every 250 microseconds.
  • the control circuit performs the received EMG signal. Sample twice. Compared with the case where the target signal collected in this way is only sampled once between every two adjacent switches of the switching circuit, since the sampling time point of each signal is not uniform enough, each target signal reconstructed based on the sampled data may be There are certain deviations.
  • the number of channels that the control circuit can process by adopting the time-division multiplexing method will be affected by the time of the rising and falling edges of the target signal.
  • the control circuit needs to provide a sampling frequency greater than 1kHz for a single channel.
  • the switching speed of the switch needs to reach 4kHz when realizing 4-channel time-division multiplexing.
  • the dwell time of the switch circuit is only 250 microseconds, and the switching speed of the switch needs to reach 8 kHz when realizing 8-channel time-division multiplexing, and the dwell time of the switch circuit in a single channel is only 125 microseconds.
  • the dwell time of the switch circuit in each channel should not be too small. For example, if both the rising edge and the falling edge are 50 microseconds, in this case, time-division multiplexing of up to 16 channels can be realized. Therefore, the rising edge and falling edge time, the number of channels and the frequency range of the target signal are usually considered comprehensively, so as to select the appropriate number of channels and the corresponding channel switching time.
  • the control circuit 140 can use an intensity-based strategy to control the switching of the switch circuit 120 .
  • the control circuit 140 may switch the input channel of the switch circuit 120 based on a preset frequency.
  • the preset frequency may be related to a period during which the user performs a certain action.
  • the preset frequency may be a certain multiple of the frequency at which the user performs a specific action (for example, bench press), so that when the user performs one of the specific actions
  • the switch circuit 120 can turn on each signal acquisition circuit for multiple times, so that the control circuit 140 can separately sample each target signal for multiple times.
  • the control circuit waits for the signal to stabilize first, and then performs continuous sampling until the 25ms time of the signal is over.
  • the switching speed of the switching circuit is independent of the total sampling frequency of the control circuit.
  • the control circuit can use a higher total sampling frequency to achieve the effect of collecting high-frequency signals in the target signal.
  • the control circuit may acquire intensity information of the target signal based on the obtained sampling data. For example, under the intensity characterization strategy, the control circuit continuously samples the target signal generated by a single signal acquisition circuit over a period of time. The control circuit may calculate the intensity of the target signal collected by the signal collecting circuit during this period of time based on the continuously sampled data, for example, calculate the average value of the continuously sampled data, and the like. Of course, the control circuit can also calculate the intensity of the target signal based on all the sampled data corresponding to the signal acquisition circuit.
  • control circuit when the control circuit calculates the intensity of the target signal corresponding to the same signal acquisition circuit in multiple discrete time periods, the control circuit can generate the signal intensity of the target and the corresponding time based on the signal intensity and the corresponding time.
  • the time-varying relationship is used to extract the specific frequency information of the target signal.
  • the intensity characterization strategy may collect partial frequency information at the same time as the intensity information is collected. Under this strategy, since the signals of all time periods are not completely collected, part of the signal information will be lost, so part of the frequency information will be lost.
  • the switching circuit is controlled with a total frequency of 40Hz. In the case of 4 signal acquisition circuits, the acquisition time length of each input channel is 25ms. At this time, the acquisition of low-frequency signals with a signal frequency less than 40Hz will be There is a certain loss.
  • each segment of the acquired signal that is, the signal that is sampled multiple times after a single channel switching
  • a representative value for example, an average value is extracted from the signal collected every 25ms
  • the ability of time-division multiplexing under the intensity characterization strategy is related to the frequency of user actions and the monitoring accuracy requirements for user actions. Due to the long acquisition duration of a single channel, it is more affected by rising and falling edges. weak. In some embodiments, if the frequency of the target signal is too low under this strategy, the number of channels for time-division multiplexing will be limited, so it is also related to the frequency of the target signal. Due to the need to extract the frequency and intensity information of the target signal, it is difficult to collect low-frequency signals, such as signals with frequencies below 40 Hz. In this case, the number of channels of time-division multiplexing can be reduced, that is, the number of channels of signal acquisition circuits can be reduced. .
  • the control circuit 140 can adjust the specific switch control strategy according to the actual situation. For example, the control circuit 140 may switch between a fully reconfigurable strategy and an intensity-characterized strategy. The selection or switching between the fully reconfigurable strategy and the strength characterization strategy can be based on the circuit's delay time (eg, rising edge time and falling edge time) and the circuit's signal-to-noise ratio requirements. For example, when the delay time of the circuit is long and the target signal frequency, the number of signal acquisition circuits, and the amplification factor of the analog circuit cannot be changed, the control circuit 140 may select an intensity characterization strategy.
  • the delay time of the circuit is long and the target signal frequency, the number of signal acquisition circuits, and the amplification factor of the analog circuit cannot be changed.
  • the control circuit 140 may select an intensity characterization strategy considering that the filter circuit will cause a longer delay time. Conversely, when the delay time of the circuit is short or the demand for the signal-to-noise ratio is not high, the control circuit 140 may select a fully reconfigurable strategy. In some embodiments, the control circuit 140 may adjust the switch control strategy based on environmental factors or user instructions. For example, assuming that different switch control strategies correspond to different power consumption rates, the control circuit 140 may implement adjustments to the switch control strategies according to the power status of the power supply (eg, battery), and select a lower power consumption rate when the power supply is low. switch control strategy. For another example, the control circuit 140 may adjust the switch control strategy according to the user's input instruction to meet the different needs of the user.
  • the power status of the power supply eg, battery
  • the signal processing circuit 300 may include a first processing circuit 310 and a second processing circuit 320 connected to the first processing circuit 310 .
  • the signal processing circuit 300 may be used to process the initial signal it receives.
  • the initial signal may be the signal collected by the aforementioned signal collection circuit.
  • the initial signal may include a target signal and a noise signal.
  • first processing circuit 310 and second processing circuit 320 may be collectively referred to as analog circuits (eg, analog circuit 130).
  • the first processing circuit 310 may be used to improve the signal-to-noise ratio of the original signal and output the first processed signal.
  • the first processing circuit 310 may perform first amplification processing on the target signal in the initial signal and attenuation processing on the noise signal in the initial signal.
  • the first processing circuit 310 can perform amplification processing on the target signal and the noise signal at the same time, wherein the amplification factor of the target signal is greater than the amplification factor of the noise signal, thereby improving the signal-to-noise ratio of the signal.
  • the target signal in the initial signal may be a physiological signal that can reflect the physical state of the user, such as one or more of a breathing signal, an electrocardiogram (ECG) signal, an electromyography signal, a blood pressure signal, a temperature signal, and the like.
  • ECG electrocardiogram
  • electromyographic signal will be used as an example of the physiological signal in this application. It should be understood that the data described below for the characteristics of myoelectric signals does not limit the scope of the present application.
  • the target signal is an ECG signal
  • its corresponding intensity (amplitude) range and/or frequency range may correspond to data values of the ECG signal.
  • the amplitude range of the ECG signal may be within the range of 10 ⁇ V-4mV; the frequency range may be within the range of 0.05Hz to 100Hz.
  • various corrections and changes can be made to the signal processing circuit 300 under the guidance of the present application to adapt to the processing of the ECG signal.
  • the magnitude and/or frequency of the EMG signal may vary from muscle to muscle (eg, pectoralis major, biceps, etc.), from individual to individual (eg, adult, child, etc.).
  • the biceps and traps can easily reach the millivolt level, while the latissimus dorsi and abs generally only reach the 100 microvolt level.
  • the frequency distributions of the electromyographic signals obtained for explosive force and continuous force may be different.
  • the amplitude and frequency of the EMG signal are also affected by the degree of muscle fatigue. The amplitude of the EMG signal obtained after muscle fatigue will become larger, and the frequency distribution will be red-shifted.
  • the magnitude of the EMG signal may be in the range of 5 ⁇ V-100 mV.
  • the frequency of the myoelectric signal may be in the range of 10 Hz-1000 Hz. In some embodiments, the frequency of the myoelectric signal may be in the range of 10 Hz-700 Hz. In some embodiments, the frequency of the myoelectric signal may be in the range of 10Hz-500Hz. In some embodiments, the frequency of the myoelectric signal may be in the range of 20Hz-500Hz. In some embodiments, the frequency of the myoelectric signal may be in the range of 20Hz-140Hz.
  • the obtained electromyography signal in order to accurately analyze the movement of the muscle, the obtained electromyography signal needs to have the characteristics of high signal-to-noise ratio and good stability.
  • the complex noise signal in the EMG signal due to the complex noise signal in the EMG signal, the EMG signal of different individuals and different muscles is different, it is very difficult to obtain a complete EMG signal (for example, the EMG signal of 10Hz-1000Hz).
  • the main frequency components of different EMG signals for example, 80%, 90% of the total frequency components, etc.
  • the analysis result of the EMG signal analysis can also reflect the accurate muscle movement.
  • the EMG signal in the main frequency component also called the target frequency band
  • the target frequency band For the convenience of description, 20 Hz to 140 Hz will be used as an example of the target frequency band in this application, which does not limit the scope of this application. It should be noted that when the target frequency band changes, one or more parameters of the signal processing circuit in the present application can also be changed accordingly, so that the signal processing circuit can be adapted to the changed target frequency band.
  • the noise signal may include motion artifact noise (Motion Artifacts, MA), power frequency signals, power frequency harmonic signals (ie, harmonic signals of power frequency signals), aliasing noise, white noise, etc. one or more.
  • the initial signal is a signal collected by a signal collection circuit (eg, the signal collection circuit 112 )
  • the signal collection circuit eg, an electrode
  • the signal collection circuit may also simultaneously collect power frequency signals, power frequency harmonics Signal, MA, etc.
  • the power frequency signal and/or the power frequency harmonic signal may saturate the output of the signal processing circuit, which, if not processed, may result in the loss of the target signal.
  • the first processing circuit 310 may first perform noise attenuation processing on the noise signal (for example, MA, power frequency signal and power frequency harmonic signal) in the initial signal, and simultaneously perform noise attenuation processing on the target signal therein.
  • the second processing circuit 320 performs the second amplification process on the signal subjected to the noise attenuation process, so as to suppress the interference of the noise signal to the target signal.
  • the signal processing circuit 300 may be connected with a digital circuit to convert the signal processed by the second processing circuit 320 into a digital signal for reading and processing. It should be noted that further amplifying the processed signal by the second processing circuit 320 can have the following advantages: (1) when the digital circuit has noise, the second processing circuit 320 can improve the overall signal-to-noise ratio; ( 2) By setting the second processing circuit 320, the ADC precision requirement on the digital circuit can be reduced.
  • the power frequency signal is generated from the power supply system.
  • the frequency of the power frequency signal may be 50 Hz, 60 Hz, or the like.
  • the power frequency noise of 50 Hz will be used as an example for description.
  • the power supply system may also generate power frequency harmonic signals.
  • the strength of the power frequency harmonic signal may be weaker than that of the power frequency signal.
  • the power frequency harmonic signals may include power frequency odd harmonic signals and power frequency even harmonic signals. That is, the frequency of the power frequency harmonic signal may include 100 Hz, 150 Hz, 200 Hz, 250 Hz, 300 Hz, 350 Hz, 400 Hz, and the like.
  • the appearance of a non-sinusoidal periodic signal will generate a power frequency harmonic signal .
  • Odd harmonics can dominate the power frequency harmonic signal generated in this case. That is, the frequency of the power frequency harmonic signal may mainly include 150 Hz, 250 Hz, 350 Hz, 450 Hz, and the like.
  • the frequency of the power frequency signal is 50Hz, this frequency is within the target frequency band of the EMG signal (for example, 20Hz-140Hz), and the strength of the power frequency signal can reach the volt level. Therefore, the existence of the power frequency signal will affect the EMG signal. Signals (signal strength in the millivolt range) have serious effects.
  • the power frequency signal is very strong and the EMG signal is very weak, even if the power frequency harmonic signal is weaker than the power frequency signal, the power frequency harmonic signal may still have a huge impact on the EMG signal. Therefore, in order to suppress the influence of the power frequency signal and the power frequency harmonic signal on the EMG signal, it is necessary to process the power frequency signal and the power frequency harmonic signal.
  • the high-pass filter cannot be relied on alone, because the high-pass filter to filter out the 50Hz frequency will sacrifice More EMG signals (eg, EMG signals with frequencies in the range of 20 to 40 Hz).
  • EMG signals with frequencies in the range of 20 to 40 Hz.
  • a high-pass filter with an extremely narrow transition band needs to be used, but a high-pass filter with an extremely narrow transition band needs more stages, which has a great impact on the resource consumption. Higher cost.
  • the common mode signal suppression circuit 312 in the first processing circuit 310 may be used to process the power frequency signal.
  • the common mode signal suppression circuit 312 may be used to suppress the common mode signal in the original signal.
  • a common mode signal may refer to a signal with the same phase and amplitude. Since the power frequency signal comes from the power supply system and the human body can be regarded as a good conductor, the phase and amplitude of the power frequency signal are the same, that is, the power frequency signal is a common mode signal. Therefore, the power frequency signal can be suppressed by the common mode signal suppression circuit 312 .
  • the common mode signal rejection circuit 312 may include a differential amplifier, an instrumentation amplifier, etc., or any combination thereof.
  • the common mode signal rejection circuit 312 may be a long tail differential amplifier.
  • the differential amplifier or instrumentation amplifier can use the common-mode properties of the initial signals at its two input ends to cancel the signals at the two input ends to suppress the common-mode signal.
  • the differential amplifier as an example (such as the differential amplifier U1 in FIG. 10A )
  • the contact between the electrodes and the human body changes for example, one electrode in the signal acquisition circuit is in good contact, and one electrode falls off or half falls off
  • the input signal at the input end of the differential amplifier is equivalent to changing from a common mode signal to a differential mode signal.
  • the differential amplifier cannot effectively suppress the power frequency signal.
  • the contact between it and the human body is unstable.
  • each link can divide the voltage. Therefore, when the contact between the electrodes and the skin changes, the input at both ends of the differential amplifier will be inconsistent.
  • the large input impedance has the advantages of circuit voltage division and the ability to resist input signal fluctuations, so that when the input signal of the differential amplifier changes, it will not cause large signal fluctuations in its output signal.
  • the voltage division advantage may refer to the fact that when the contact impedance becomes larger (for example, the electrode falls off), the circuit can still divide the voltage to obtain an EMG signal of sufficient strength.
  • the ability to resist input signal fluctuations can refer to the large input impedance that can reduce the impact of input signal fluctuations when the contact impedance fluctuates. Therefore, in order to suppress the power frequency signal as much as possible and obtain a strong EMG signal, the input impedance of the differential amplifier can be as large as possible to reduce the noise caused by the unbalanced differential input terminals.
  • the input impedance of the differential amplifier may be greater than or equal to 10 M ⁇ .
  • the input impedance of the differential amplifier may be 50M ⁇ , 100M ⁇ , 500M ⁇ , 1G ⁇ , 1.5G ⁇ , 2G ⁇ , 2.5G ⁇ , 3G ⁇ , 5G ⁇ , 10G ⁇ , etc.
  • the first processing circuit 310 may further include a trap circuit.
  • a trap circuit can be used to suppress signals of specific frequencies, such as power frequency signals.
  • the notch frequency of the notch circuit can be set to 50Hz.
  • the trap point frequency of the trap circuit may refer to the resonance frequency of the trap circuit.
  • the trap circuit in order to make the trap circuit have a high quality factor (ie, Q value) as much as possible, the trap circuit may include a dual-T active trap circuit with a higher Q value (as in FIG. 12A ). trap circuit 1214).
  • positive feedback can be introduced and/or the parameter values of the notch circuit can be adjusted, so that the FWHM of the notch of the notch circuit is smaller than the FWHM threshold, so as to obtain a higher quality factor Q and improve the notch The Q value and notch capability of the circuit.
  • the value and/or precision of the resistance, capacitance, etc. in the notch circuit can be adjusted so that the FWHM of the notch valley is within the FWHM threshold.
  • the FWHM threshold may be 5 Hz, 4 Hz, 3 Hz, 1 Hz, 0.5 Hz, or the like.
  • the trap circuit may include cascaded trap circuits.
  • FIG. 3B is a frequency response graph of various cascaded trap circuits according to some embodiments of the present application.
  • the curve l1 represents the frequency response curve of the double-T active trap circuit.
  • Curve l2 represents the frequency response curve of the dislocation double trap circuit.
  • Curve l3 represents the frequency response curve of the co-located double trap circuit.
  • Curve l4 represents the frequency response curve of the double-same-double-displacement trap circuit.
  • the dislocation double trap circuit may refer to two double T active trap circuits connected in series, wherein the trap point frequency of one double T active trap circuit may be set to the first frequency (for example, 48.5 Hz), the notch frequency of the other double-T active notch circuit can be set to a second frequency (eg, 50 Hz) different from the first frequency.
  • the first frequency and the second frequency may be located near a specific frequency, and the frequency difference between the two may be within 4 Hz, 3 Hz, 2 Hz, or 1 Hz.
  • the co-located double trap circuit may refer to a circuit in which two active double T traps are connected in series with both trap points at a specific frequency (for example, 50 Hz).
  • the double-same-double-displacement trap circuit may refer to a circuit in which four double-T active trap circuits are connected in series, and the trap point frequencies may be respectively set to, for example, 48.5Hz, 50Hz, 50Hz, and 51.5Hz.
  • the frequency response of the double-same-double-displacement trap circuit ie, curve l4
  • an appropriate cascaded notch circuit can be selected according to the frequency value of the signal to be filtered and its intensity distribution.
  • any series of co-location and/or dislocation traps can be freely cascaded according to actual needs. wave circuit to achieve the goal.
  • the first processed signal also includes more power frequency harmonic signals.
  • the initial signal is the EMG signal collected when the human body wears the EMG suit and performs actions such as shrugging the shoulders, raising the hand high, etc.
  • the trap circuit may further include a multi-cascade trap circuit.
  • the multi-cascade trap circuit may include at least two cascade trap sub-circuits.
  • At least two cascaded trap subcircuits can be connected in series. There may be different notch point frequencies among the cascaded notch sub-circuits.
  • the notch frequency of each cascaded notch sub-circuit can be set to 50Hz, 100Hz, 150Hz, 200Hz, 250Hz, etc. respectively. It should be pointed out that the multi-cascade trap circuit can suppress the power frequency signal and the power frequency harmonic signal, but each power frequency harmonic signal needs at least one trap circuit.
  • the low-pass filter circuit 314 may be set in the signal processing circuit 300 according to the commonality of the EMG signals (that is, the EMG signal with the target frequency band of 20Hz-140Hz can meet the analysis requirements). Power frequency harmonic signals in higher frequency bands are directly filtered out.
  • the signal processing circuit 300 may include one or more low-pass filter circuits 314 .
  • the low pass filter circuit 314 can attenuate signals above its upper cutoff frequency.
  • the upper limit cutoff frequency of the low-pass filter circuit may refer to the frequency corresponding to the position where the gain of the low-pass filter circuit decreases by the first special intensity value relative to the low-frequency passband.
  • the first characteristic intensity value may be greater than or equal to 10 dB, for example, may be 15 dB, 20 dB, 30 dB, 40 dB, or the like.
  • the upper cutoff frequency may be within the frequency range of 100Hz-1000Hz. In some embodiments, the upper cutoff frequency may be within the frequency range of 100Hz-800Hz. In some embodiments, the upper cutoff frequency may be within the frequency range of 100Hz-600Hz. In some embodiments, the upper cutoff frequency may be within the frequency range of 100Hz-400Hz. In some embodiments, the upper cutoff frequency may be within the frequency range of 120Hz-400Hz. In some embodiments, the upper cutoff frequency may be within the frequency range of 140Hz-400Hz.
  • the upper limit cutoff frequency may be 900 Hz, 700 Hz, 500 Hz, 300 Hz, 250 Hz, 200 Hz, 150 Hz, 140 Hz, 130 Hz, 120 Hz, 110 Hz, and so on.
  • the upper limit cutoff frequency may be higher than the high frequency point of the target frequency band, for example, may be 140Hz, 150Hz, and so on.
  • aliasing noise is a mixture of other noise signals (eg, power-frequency harmonic signals and white noise), which are mainly located in high frequency bands (eg, above 500 Hz)
  • the low-pass filter circuit 314 When the upper cutoff frequency is set to be low (for example, 140 Hz), the low-pass filter circuit 314 can also filter out aliasing noise while filtering out the high-order power frequency harmonic signal. Since the intensity of white noise is positively related to the signal bandwidth, at this time, the white noise can also be relatively reduced.
  • the low-pass filtering circuit 314 may be set at any position in the signal processing circuit 300, which is not limited here, as long as it can perform low-pass filtering on the signal.
  • a low-pass filter circuit 314 may be provided in the first processing circuit 310 .
  • the low-pass filter circuit 314 may be provided at the input end of the differential amplifier.
  • a low-pass filter composed of a resistor R1 and a capacitor C1 and a low-pass filter composed of a resistor R2 and a capacitor C3 can be set at the input end of the differential amplifier U1.
  • the low-pass filter circuit 314 may also be provided in the second processing circuit 320 .
  • the low-pass filter circuit 314 may be provided at the input end of the amplifying circuit in the second processing circuit 320 .
  • the second processing circuit 1220 may further include a resistance-capacitance low-pass filter amplifying circuit 1224 including a low-pass filter.
  • the low-pass filter circuit 314 may include a first-order low-pass filter circuit, a second-order low-pass filter circuit, a high-order filter circuit (a filter circuit higher than the second-order, such as a third-order low-pass filter circuit), etc., or any combination thereof. More descriptions of low-pass filter circuits can be found elsewhere in this application (eg, FIGS. 4A-4C and their descriptions).
  • the low-pass filter circuit 314 may include a bridge circuit configured Structured low-pass filter (also known as bridge low-pass filter circuit).
  • a bridge circuit configured Structured low-pass filter (also known as bridge low-pass filter circuit).
  • FIG. 12A only a capacitor C2 needs to be added between the two input terminals of the differential amplifier U1, and the low-pass filter circuit can be designed as a bridge circuit structure (the circuit in the dotted box 1212). It should be known that when there is a radio frequency signal in the initial signal, the radio frequency signal can reach the two input ends of the differential amplifier U1 through the capacitor C2 and be suppressed by it.
  • the bridge low-pass filter circuit can further suppress the radio frequency signal.
  • resistor R1, resistor R2 and capacitor C2 can also form a first-stage low-pass filter, which helps to narrow the transition band of the filter.
  • the bridge-type low-pass filter and the differential amplifier may be collectively referred to as a bridge-type low-pass filter amplifying circuit.
  • the signal processing circuit 300 may also not include a bridge low-pass filter circuit. More descriptions of bridge-type low-pass filter amplifier circuits can be found elsewhere in this application (eg, FIGS. 5A-5C and their descriptions).
  • Motion artifact noise may refer to noise caused by motion. Movement of different objects (eg, pectoralis major, biceps, etc.) can cause different MAs.
  • the MA may include baseline drift, glitches, and the like. For example, baseline drift may be caused when motion causes fluctuations in the stratum corneum potential across the acquired signal.
  • the frequency of the MA may be in the lower frequency range, eg, in the range of 0Hz-20Hz.
  • the strength of the MA can be in the range of 0mV-40mV.
  • the MA since the frequency band in which the MA is located is outside the target frequency band, the MA can be processed by constructing a high-pass filter circuit 316 .
  • the baseline drift has a limit value
  • the second processing circuit 320 will amplify the target signal.
  • the amplification factor of the target signal by the second processing circuit 320 can be appropriately reduced. So that the amplified signal is not distorted.
  • the reference potential when the baseline drift causes the signal to approach the upper limit of the saturation voltage, the reference potential can be programmed to decrease; on the contrary, when the baseline drift causes the signal to approach the lower voltage limit, the reference point can be programmed to increase.
  • the frequency range of the MA may be wide, eg, there may be glitches in the range of 0-1000 Hz. In this case, processing can be done with the aid of signal amplitude and frequency.
  • the signal processing circuit 300 may include one or more high-pass filter circuits 316 .
  • the high pass filter circuit 316 can attenuate signals below its lower cutoff frequency.
  • the lower limit cutoff frequency of the high-pass filter circuit may refer to the frequency corresponding to the position where the gain of the high-pass filter circuit decreases by the second special intensity value relative to the high-frequency passband.
  • the second special intensity value may be greater than or equal to 10 dB, eg, may be 15 dB, 20 dB, 30 dB, 40 dB, or the like.
  • the second special intensity value and the first special intensity value may be the same or different.
  • the lower cutoff frequency may be within the frequency range of 5Hz-200Hz. In some embodiments, the lower cutoff frequency may be within the frequency range of 7 Hz-180 Hz. In some embodiments, the lower cutoff frequency may be within the frequency range of 10 Hz-160 Hz. In some embodiments, the lower cutoff frequency may be within the frequency range of 10 Hz-100 Hz. In some embodiments, the lower cutoff frequency may be within the frequency range of 10 Hz-80 Hz. In some embodiments, the lower cutoff frequency may be within the frequency range of 10 Hz-60 Hz. In some embodiments, the lower cutoff frequency may be within a frequency range of 10 Hz-40 Hz.
  • the lower cutoff frequency may be within a frequency range of 10 Hz-20 Hz. Specifically, the lower limit cutoff frequency may be 190 Hz, 150 Hz, 100 Hz, 70 Hz, 50 Hz, 30 Hz, 20 Hz, 17 Hz, 15 Hz, 13 Hz, 12 Hz, 10 Hz, 5 Hz, and the like.
  • the lower limit cutoff frequency may be different according to whether there is a trap circuit for the power frequency signal in the signal processing circuit 300 .
  • the lower limit cutoff frequency of the high-pass filter circuit 316 can be lower than the lower limit when the notch circuit does not exist.
  • the cutoff frequency is low.
  • the lower limit cutoff frequency may be within a frequency range of 10 Hz-40 Hz.
  • the lower limit cutoff frequency may be 35 Hz, 30 Hz, 25 Hz, 20 Hz, 10 Hz, or the like.
  • the lower limit cutoff frequency may be within a frequency range of 10 Hz-160 Hz.
  • the lower limit cutoff frequency may be 80 Hz, 60 Hz, 50 Hz, 20 Hz, or the like.
  • the lower cutoff frequency of the high-pass filter circuit 316 may be set according to the target frequency band. For example, if the target frequency band is 20Hz-140Hz, the lower cutoff frequency can be set to 20Hz. If the target frequency band is 5Hz-200Hz, the lower limit cutoff frequency can be set to 5Hz.
  • the high-pass filter circuit 316 can be set at any position in the signal processing circuit 300, which is not limited here, as long as it can perform high-pass filter on the signal.
  • a high pass filter circuit 316 may be provided in the first processing circuit 310 .
  • a high-pass filter 1014 may be provided at the output end of the differential amplifier U1 in the first processing circuit 1010 .
  • the high-pass filter circuit 316 may also be provided in the second processing circuit 320 .
  • the second processing circuit 1220 may be provided with a RC high-pass filter amplifying circuit 1222 including a high-pass filter.
  • the high-pass filter circuit 316 may include a first-order high-pass filter circuit, a second-order high-pass filter circuit, a third-order high-pass filter circuit, etc., or any combination thereof. More descriptions of high-pass filter circuits can be found elsewhere in this application (eg, FIGS. 9A-9C and their descriptions).
  • the signal processing circuit 300 may further include a voltage control low pass filter circuit.
  • the voltage-controlled low-pass filter circuit may include a voltage-controlled peak (eg, peak 712 of curve d2 in FIG. 7B).
  • the voltage-controlled low-pass filter circuit can be used to provide gain near the target frequency and combined with the low-pass filter circuit 314 to compensate for the attenuation of the low-pass filter circuit 314, thereby obtaining a flatter frequency response passband.
  • the vicinity of the target frequency may refer to a distance within a certain range (eg, 10 Hz, 20 Hz, etc.) of a certain frequency in the target frequency band.
  • the frequency response passband can also be made to have a higher peak at a specific frequency point (that is, to provide a higher peak value at a specific frequency position). large gain).
  • the drop rate of the voltage-controlled peak of the voltage-controlled low-pass filter circuit can be adjusted by adjusting the resistance and capacitance parameters in the voltage-controlled low-pass filter circuit, so that the signal processing circuit 300 can
  • the frequency response passband has the highest intensity at, for example, 80 Hz.
  • the drop rate of the voltage controlled low pass filter circuit may be greater than 20 dB/decade. In some embodiments, the drop rate of the voltage controlled low pass filter circuit may be greater than 30 dB/decade. In some embodiments, the drop rate of the voltage controlled low pass filter circuit may be greater than 40dB/decade. In some embodiments, the drop rate of the voltage controlled low pass filter circuit may be greater than 60 dB/decade.
  • the drop rate of the voltage controlled low pass filter circuit may be greater than 80 dB/decade.
  • the falling speed of the voltage-controlled low-pass filter circuit can be 25dB/decade, 35dB/decade, 45dB/decade, 55dB/decade, 65dB/decade, 75dB/decade, etc. .
  • the voltage-controlled low-pass filter circuit can be set at any position in the signal processing circuit 300, which is not limited here, as long as it can regulate the signal.
  • a voltage-controlled low-pass filter circuit may be provided in the first processing circuit 310 .
  • the voltage-controlled low-pass filter circuit 1226 may be disposed after the trap circuit 1214 in the first processing circuit 1210 .
  • the voltage-controlled low-pass filter circuit may also be provided in the second processing circuit 320 .
  • the voltage-controlled low-pass filter circuit 1226 may be arranged before the follower 1229 in the second processing circuit 1220 . More descriptions of voltage-controlled low-pass filter circuits can be found elsewhere in this application (eg, FIGS. 7A-7B and their descriptions).
  • the second processing circuit 320 may be used to amplify the first processed signal.
  • the second processing circuit 320 may include an amplification circuit (eg, an amplifier).
  • the resistance of the feedback network in the amplifying circuit can be replaced by a resistor and a capacitor connected in parallel, so that the formed circuit can be called a resistance-capacitance amplifying circuit, and the feedback network thereof can be called a resistance-capacitance feedback network.
  • the resistor R12 and capacitor C7 in the amplifier U2B and its feedback network can be composed of a resistor-capacitor amplifying circuit, and the parallel resistor R12 and capacitor C7 can be called a resistor-capacitor feedback network.
  • the gain of the RC amplifier circuit can also change with the frequency of the signal. Therefore, the gain multiple of the first processing signal by the second processing circuit 320 may vary with the frequency of the first processing signal.
  • the feedback network 620 of the amplifier U2B in FIG. 6A (which may also be referred to as a RC feedback network) as an example, since there is a capacitor C7 on the feedback network 620 of the amplifier U2B. According to the property that the impedance of the capacitor changes with the frequency of the AC signal, the greater the signal frequency, the more the current signal will flow directly from the shunt of the capacitor C7 to the output end of the amplifier U2B.
  • the resistance-capacitance amplifier circuit has the effect of a low-pass filter circuit. Therefore, in the present application, a resistance-capacitance feedback network can be constructed in the amplifier circuit, and a better high-frequency and low-frequency suppression effect can be achieved by using as few amplifiers as possible, and the manufacturing cost of the circuit can be reduced.
  • the RC amplifier circuit may also be referred to as a RC low-pass filter circuit. More descriptions of RC low-pass filter circuits can be found elsewhere in this application (eg, Figures 6A-6B and their descriptions).
  • the combined circuit thereof when the RC amplifier circuit is connected to a high-pass filter circuit or a low-pass filter circuit, the combined circuit thereof may also be referred to as a RC high-pass filter circuit or a RC low-pass filter circuit.
  • the gain of the amplifying circuit (or the second processing circuit 320 ) to the target frequency band signal can be adjusted by adjusting the values of the resistance and capacitance of the feedback network in the amplifying circuit.
  • the second processing circuit 320 may have a larger gain for signals within the first frequency range and a smaller gain for signals outside the first frequency range.
  • the processing of the first processing signal by the second processing circuit 320 can achieve a band-pass effect.
  • the second processing circuit 320 may have a gain of more than 100 times for signals within the target frequency band (eg, 20Hz-140Hz), and a gain of less than 100 times for signals outside the target frequency band, wherein the farther away from the target frequency band, the The corresponding gain is smaller.
  • the second processing circuit 320 may be configured to perform amplification processing on the first processing signal by a second amplification factor.
  • the second magnification of the second processing circuit 320 may also refer to the total magnification of each amplifier in the second processing circuit 320 to amplify the signal.
  • the second magnification may be 15 times, 20 times, 50 times, 100 times, 200 times, 300 times, 500 times, and the like.
  • the amplifying circuit in order to make a signal in a specific frequency band (eg, a band-pass frequency band) to have greater gain, the amplifying circuit may include a multi-stage amplifying circuit.
  • the second magnification may be related to a noise signal in the first processed signal, the ADC accuracy of the digital circuit, or the like. For example, when there is a baseline drift in the first processed signal, the second magnification can be appropriately reduced and/or a control circuit of a higher-precision ADC can be selected to control the baseline drift not to exceed the output capability of the signal processing circuit 300, so as not to occur Distortion case.
  • the first amplification factor of the first processing circuit 310 may refer to the amplification of the signal by each amplifier in the first processing circuit 310 total magnification.
  • the first amplification factor of the first processing circuit 310 may be set to be less than 20 times.
  • the first magnification may be 20 times, 15 times, 10 times, 9 times, 7 times, 5 times, and the like.
  • the second magnification of the second processing circuit 320 may be greater than, less than or equal to the first magnification of the first processing circuit 310 .
  • the first magnification may be 20 times and the second magnification may be 200 times.
  • the first magnification may be 20 times, and the second magnification may be 15 times.
  • both the first magnification and the second magnification may be 20 times.
  • the frequency response peak of the signal processing circuit 300 may be set to In the position as far as possible from the frequency of the power frequency signal 50Hz.
  • the frequency response peak of the signal processing circuit 300 may be set to 80 Hz, 90 Hz, 100 Hz, 110 Hz, 120 Hz, and so on.
  • the signal processing circuit 300 can have the maximum gain for the signal at 120 Hz, while the gain for the signal far from 120 Hz is smaller, which is equivalent to a further increase in the power frequency signal. suppress. At this time, the gain of the signal processing circuit 300 is still strong at 80Hz-100Hz, which meets the analysis requirements of the EMG signal.
  • the noise attenuation target can be achieved by adjusting the peak position of the frequency response gain of the signal processing circuit 300 to keep it away from the frequency of the noise to be suppressed.
  • the frequency response peak of the signal processing circuit 300 may be set away from 150 Hz (eg, 80 Hz).
  • the second processing circuit 320 may also include a follower.
  • the follower can be used to isolate the mutual influence between the output end of the signal processing circuit 300 and the back-end circuit.
  • the signal processing circuit 300 may also include a negative feedback circuit.
  • a negative feedback circuit can be used to adjust the second amplification factor of the amplification circuit.
  • the signal processing circuit 300 may also include a feedback circuit. The feedback circuit can be used to improve or control the performance index of the signal processing circuit 300, for example, to suppress interference and noise. More descriptions of signal processing circuits can be found elsewhere in this application (eg, Figures 10, 11, 12A, and 12C and their descriptions).
  • the above description of the signal processing circuit 300 is only for example and illustration, and does not limit the scope of application of the present application.
  • various modifications and changes can be made to the signal processing circuit 300 under the guidance of the present application.
  • the algorithmic noise reduction process may include filtering algorithms, spectral subtraction algorithms, adaptive algorithms, minimum mean square error estimation algorithms, etc., or any combination thereof.
  • FIGS. 4A , 4B and 4C are schematic structural diagrams of exemplary low-pass filter circuits according to some embodiments of the present application.
  • FIG. 4D is a frequency response graph of the low-pass filter circuit in FIGS. 4A , 4B and 4C.
  • the low-pass filter circuit 400A may include a first low-pass filter composed of a resistor R9 and a capacitor C1 and an amplifier U2B.
  • a first low pass filter can be connected to the input of amplifier U2B.
  • the low-pass filter circuit 400A may also be referred to as a first-order active low-pass filter circuit.
  • the low-pass filter circuit 400B may further include a second low-pass filter composed of a resistor R1 and a capacitor C2 .
  • the first low-pass filter may be directly connected to the second low-pass filter.
  • a second-order low-pass filter circuit formed by directly connecting two-stage low-pass filters as shown in the low-pass filter circuit 400B may also be referred to as a second-stage cascaded low-pass filter circuit.
  • the low-pass filter circuit 400C may further include a third low-pass filter composed of a resistor R3 and a capacitor C2, an amplifier U1B, a resistor R1 and a resistor R2.
  • a third low pass filter may be connected to the output of amplifier U2B and to the input of amplifier U1B.
  • a second-order low-pass filter circuit formed by directly connecting two first-order active low-pass filter circuits as shown in the low-pass filter circuit 400C may also be referred to as a second-order distributed low-pass filter circuit.
  • a1 represents the frequency response curve of the first-order active low-pass filter circuit (ie, the low-pass filter circuit 400A).
  • Curve a2 represents the frequency response curve of the second cascaded low-pass filter circuit (ie, the low-pass filter circuit 400B).
  • Curve a3 represents the frequency response curve of the second-order distributed low-pass filter circuit (ie, the low-pass filter circuit 400C). It can be seen from FIG. 4D that low-pass filter circuits with different structures may have different frequency responses.
  • the first-order active low-pass filter circuit 400A (corresponding to curve a1) can reach an attenuation speed of 15dB/decade (100Hz to 1kHz), and the second-order cascaded low-pass filter circuit 400B (corresponding to curve a2) can reach 30dB/decade
  • the attenuation speed (100Hz to 1KHz) of the second-order distributed low-pass filter circuit 400C (corresponding to the curve a3) can reach the attenuation speed of 34dB/decade (100Hz to 1KHz).
  • higher order filter circuits may be preferred in order to preserve more low frequency signals (eg, signals within 120 Hz) when the same suppression effect is achieved at 1 KHz.
  • the reason for the difference between the second-order cascaded low-pass filter circuit and the second-order distributed low-pass filter circuit can be understood as the influence of the second stage of the second-order cascaded low-pass filter circuit on the first stage.
  • the current flows through the resistance of the first stage, from the point of view of the next node, it is the parallel connection of the capacitor in the first stage and the circuit of the second stage, which actually increases the total capacitance value, resulting in the frequency of the low-pass filter circuit in the second stage.
  • the louder cutoff becomes smaller, filtering out more low-frequency signals.
  • FIGS. 5A and 5B are schematic structural diagrams of low-pass filter circuits according to some embodiments of the present application.
  • FIG. 5C is a frequency response graph of the low-pass filter circuit in FIGS. 5A and 5B .
  • both the low-pass filter circuit 500A and the low-pass filter circuit 500B may include two low-pass filters (eg, a low-pass filter formed by a resistor R1 and a capacitor C8 , a low-pass filter formed by a resistor R2 and a capacitor Low-pass filter composed of C12) and differential amplifier U1.
  • the difference between the low-pass filter circuit 500A and the low-pass filter circuit 500B is that the input end of the differential amplifier U1 in the low-pass filter circuit 500B forms a bridge circuit structure (resistor R1 and capacitor C8) by adding a capacitor C11 (dotted line circle).
  • the low-pass filter circuit 500A may also be referred to as a first-order active low-pass filter circuit.
  • the low-pass filter circuit 500B may also be referred to as a bridge-type low-pass filter circuit.
  • resistor R1, resistor R2 and capacitor C11 can also form a first-stage low-pass filter, which helps to narrow the transition band of the filter.
  • the curve b1 represents the frequency response curve of the first-order active low-pass filter circuit (ie, the low-pass filter circuit 500A).
  • Curve b2 represents the frequency response curve of the bridge-type low-pass filter circuit (ie, the low-pass filter circuit 500B).
  • the suppression effect of the low-pass filter circuit on high frequencies can be enhanced. For example, at 1 KHz, the frequency response strength of the low-pass filter circuit 500A is 6 dB stronger than that of the low-pass filter circuit 500B.
  • the principle of the bridge circuit structure can be understood as, through the additional capacitor (ie, capacitor C11), the AC signal of certain frequencies can pass through the capacitor from one input channel to another input channel, and finally reach the differential The amplifier U1, after being suppressed by the common mode, achieves the effect of attenuation. Adjusting the size of the capacitor can control the frequency of the AC signal that can pass through the capacitor.
  • FIG. 6A is a schematic structural diagram of a RC low-pass filter circuit according to some embodiments of the present application.
  • FIG. 6B is a frequency response curve diagram of the second-order distributed low-pass filter circuit and the RC low-pass filter circuit in FIG. 6A .
  • the RC low-pass filter circuit 600 may include a second-order distributed RC low-pass filter circuit, which is connected with the second-order distributed low-pass filter circuit (eg, the second-order distributed low-pass filter circuit 400C). The difference is: the capacitor in the low-pass filter in the second-order distributed low-pass filter circuit is removed; in addition, the resistor in the feedback network in the second-order distributed low-pass filter circuit is replaced by a parallel connection of a resistor and a capacitor, that is Build a RC feedback network.
  • the second-order distributed RC low-pass filter circuit may also be referred to as a second-order distributed RC amplifier circuit.
  • the gain of the second-order distributed RC low-pass filter circuit can also change with the frequency of the signal.
  • the RC feedback network 620 of the amplifier U2B in FIG. 6A since there is a capacitor C7 on the RC feedback network 620 of the amplifier U2B.
  • the impedance of the capacitor changes with the frequency of the AC signal, with the increase of the signal frequency, the current signal that flows directly from the shunt of the capacitor C7 to the output end of the amplifier U2B gradually increases. When the signal frequency is large enough, the effect of the resistor R12 will be weakened.
  • the current signal mainly flows directly from the capacitor C7 to the output end of the amplifier U2B, which eventually leads to the attenuation of the circuit gain or even no gain. Therefore, the gain of the amplifier U2B to the target frequency band signal can be adjusted by adjusting the values of the resistor R12 and the capacitor C7. Similarly, it can be known that the value of the setting resistor R7 and the capacitor C3 can be adjusted to adjust the gain of the amplifier U2A to the target frequency band signal.
  • the curve c1 represents the frequency response curve of the second-order distributed low-pass filter circuit (eg, the low-pass filter circuit 400C).
  • Curve c2 represents the frequency response curve of the second-order distributed RC low-pass filter circuit (ie, the low-pass filter circuit 600 ).
  • the second-order distributed resistance-capacitance low-pass filter circuit (corresponding to the curve c2 ) and the second-order distributed low-pass filter circuit (corresponding to the curve c1 ) have the same frequency response.
  • the second-order distributed resistance-capacitance low-pass filter circuit is compatible with the second-order distributed low-pass filter circuit.
  • a second-order distributed resistance-capacitance low-pass filter circuit can be selected.
  • FIG. 7A is a schematic structural diagram of a voltage-controlled low-pass filter circuit according to some embodiments of the present application.
  • FIG. 7B is a frequency response curve diagram of the second-order low-pass filter circuit and the voltage-controlled low-pass filter circuit in FIG. 7A .
  • the voltage-controlled low-pass filter circuit 700 may have a similar structure to the second-stage cascaded low-pass filter circuit 400B. The difference between the two is that in the voltage-controlled low-pass filter circuit 700 , the capacitor of the first-stage low-pass filter (ie, the capacitor C14 ) is directly connected to the output terminal of the amplifier to form a feedback loop of the output voltage.
  • the voltage-controlled low-pass filter circuit 700 may also be referred to as a voltage-controlled voltage source second-order low-pass filter circuit.
  • the response of a certain frequency can reach a larger value, so that the frequency response curve of the voltage-controlled low-pass filter circuit 700 can include a convex peak.
  • the curve d1 represents the frequency response curve of the two-stage cascaded low-pass filter circuit.
  • the frequency response curve of the voltage-controlled voltage source second-order low-pass filter circuit (ie, the voltage-controlled low-pass filter circuit 700 ) represented by curve d2 .
  • the capacitors C13 and C14 in FIG. 7A are equivalent to an open circuit, and the capacitor C14 does not play a feedback role.
  • the feedback effect of the capacitor C14 can gradually take effect.
  • the capacitor C13 will introduce a large amount of the input signal and the feedback signal into the virtual ground, which will reduce the output. Therefore, different values of capacitors C13 and C14 can be controlled to design feedback and retain higher frequency signals.
  • the quantitative calculation of specific values of capacitances C13 and C14 depends on the transfer function.
  • the gain A or the open-loop gain Aop is a formula for s.
  • Aop(s) in the circuit diagram 7A is a ratio of resistors, a transimpedance bandpass can be designed by using a capacitor, so that the circuit can be Further frequency response design.
  • FIG. 8A is a schematic structural diagram of an exemplary low-pass filter circuit according to some embodiments of the present application.
  • FIG. 8B is a frequency response graph of the low-pass filter circuit in FIG. 8A .
  • the low-pass filter circuit 800 may include a voltage-controlled low-pass filter circuit 810 , a bridge-type low-pass filter circuit 820 and a fourth-order low-pass filter circuit 830 .
  • the low-pass filter circuit 800 may also be referred to as a thresholded low-pass filter circuit.
  • the fourth-order low-pass filter circuit 830 may be implemented with two stages of amplifiers (eg, amplifiers U2A and U2B). Specifically, the fourth-order low-pass filter circuit 830 may be implemented by a second-order distributed low-pass filter circuit and a second-order resistance-capacitance low-pass filter circuit.
  • the curve e1 represents the frequency response curve of the voltage-controlled low-pass filter circuit 810 .
  • the curve e2 represents the frequency response curve of the circuit in which the bridge-type low-pass filter circuit 820 and the fourth-order low-pass filter circuit 830 are connected in series.
  • Curve e3 represents the frequency response curve of the low-pass filter circuit 800 .
  • a curve such as curve e1 can be obtained, which can include the frequency response peak 812 .
  • a threshold low-pass filter circuit (corresponding to the curve e3) that fully retains the low-frequency signal is obtained. As can be seen from FIG.
  • the circuit in which the bridge-type low-pass filter circuit 820 and the fourth-order low-pass filter circuit 830 are connected in series has a suppression capability of 20dB at 200Hz relative to 100Hz, while the threshold-type low-pass filter
  • the suppression capability of the filter circuit 800 (corresponding to the curve e3 ) at 200 Hz relative to 100 Hz is about 50 dB, which is equivalent to an improvement of the suppression capability by 31.6 times.
  • FIGS. 9A-9B are schematic structural diagrams of exemplary high-pass filter circuits according to some embodiments of the present application.
  • Fig. 9C is a frequency response graph of the high pass filter circuit of Figs. 9A-9B.
  • the high-pass filter circuit 900A may include a high-pass filter 910 composed of a resistor R4 and a capacitor C1 and an amplifier U2B.
  • a first high pass filter 910 may be connected to the input of amplifier U2A.
  • the first high pass filter 910 may be located on the signal path.
  • the high-pass filter circuit 900A including a high-pass filter and located on the signal path may also be referred to as a first-order main-path high-pass filter circuit.
  • the structure of the high-pass filter circuit 900B may be similar to that of the high-pass filter circuit 900A. The difference between the two is that the high-pass filter 920 in the high-pass filter circuit 900B is not located on the signal path.
  • a high-pass filter circuit 900B that includes a high-pass filter that is not on the signal path may also be referred to as a first-order bypass high-pass filter circuit.
  • the high-pass filter circuit in this specification can also include a second-order, third-order high-pass filter circuit or a higher-order high-pass filter circuit, for example, a second-order cascaded main-path high-pass filter circuit or Second-order distributed bypass high-pass filter circuit.
  • the high-order high-pass filter circuit may include at least one first-order main path high-pass filter circuit or at least one bypass high-pass filter circuit.
  • including at least one first-order main high-pass filter circuit and at least one bypass high-pass filter circuit may also be referred to as a high-order hybrid high-pass filter circuit.
  • the curve f1 represents the frequency response curve of the first and second-order distributed main path high-pass filter circuit.
  • the curve f2 represents the frequency response curve of the first second-order distributed bypass high-pass filter circuit.
  • the curve f3 represents the frequency response curve of the second second-order distributed bypass high-pass filter circuit, wherein the parameters of the second second-order distributed bypass high-pass filter circuit are different from the parameters of the first second-order distributed bypass high-pass filter circuit.
  • Curve f4 represents the frequency response curve of the second-order distributed hybrid high-pass filter circuit.
  • Curve f5 represents the frequency response curve of the second second-order distributed main path high-pass filter circuit, wherein the parameters of the second second-order distributed main path high-pass filter circuit are different from those of the first second-order distributed main path high-pass filter circuit. It can be seen from FIG. 9C that high-pass filter circuits with different structures and/or parameters may have different frequency responses.
  • the first and second-order distributed main path high-pass filter circuit (corresponding to curve f1) has a strong inhibitory effect on very low-frequency signals (for example, signals within 1Hz), but it inhibits low-frequency signals (for example, signals higher than 1Hz). limited effect.
  • the first second-order distributed bypass high-pass filter circuit (corresponding to the curve f2) and the second second-order distributed bypass high-pass filter circuit (corresponding to the curve f3) have limited suppressing effects on low-frequency signals.
  • the second-order distributed hybrid high-pass filter circuit (corresponding to the curve f4) has a great suppression of very low frequency signals.
  • the second-order distributed hybrid high-pass filter circuit suppresses the signal within 1Hz stronger than the first second-order distributed bypass high-pass filter circuit (corresponding to the curve f2) and the second second-order distributed bypass high-pass filter circuit (corresponding to the curve f3) ).
  • the second-order distributed hybrid high-pass filter circuit (corresponding to curve f4) also has a greater ability to suppress signals within 5Hz (stronger than the first second-order distributed main path high-pass filter circuit (corresponding to curve f1) and the second second-order distribution.
  • Main circuit high-pass filter circuit (corresponding to curve f5)).
  • each circuit since each exemplary circuit further includes an amplifier, in addition to performing corresponding processing on the signal, each of the above exemplary circuits can also perform amplification processing on the signal.
  • the low-pass filter circuit 400A can amplify the filtered signal in addition to the low-pass filter processing on the signal. Therefore, the low-pass filter circuit 400A can also be referred to as a low-pass filter amplifying circuit.
  • the low-pass filter amplifying circuit can also be called a resistance-capacitance low-pass filter amplifying circuit.
  • the high-pass filter circuit 900A can also amplify the filtered signal. Therefore, the high-pass filter circuit 900A can also be referred to as a low-pass filter amplifying circuit.
  • the amplifier in the high-pass filter amplifying circuit includes a resistance-capacitance feedback network
  • the high-pass filter amplifying circuit can also be called a resistance-capacitance low-high filter amplifying circuit.
  • the amplification factor of each amplifier may be the same or different.
  • the magnification of the signal by the amplifier can be 2 times, 4 times, 10 times, 20 times, 100 times, 300 times, 500 times, 1000 times, and so on.
  • FIG. 10A is a schematic diagram of a circuit architecture of an exemplary signal processing circuit according to some embodiments of the present application.
  • FIG. 10B is a frequency response curve of the signal processing circuit in FIG. 10A .
  • the signal processing circuit 1000 may include a first processing circuit 1010 and a second processing circuit 1020 .
  • the second processing circuit 1020 may be directly connected to the first processing circuit 1010 .
  • the first processing circuit 1010 may include a bridge low-pass filter circuit 1012 , a differential amplifier U1 and a high-pass filter 1014 .
  • bridge low-pass filter circuit 1012 may be connected to the input of differential amplifier U1.
  • a high pass filter 1014 may be connected to the output of the differential amplifier U1.
  • the first processing circuit 1010 can attenuate the noise signal in the initial signal (for example, the initial signal collected by the electrodes) and amplify the target signal in the initial signal, and output the first processed signal.
  • the bridge-type low-pass filtering circuit 1012 can perform low-pass filtering processing on the initial signal.
  • the upper cutoff frequency of the bridge low-pass filter circuit 1012 may be in the frequency range of 100Hz-1000Hz.
  • the upper limit cutoff frequency of the bridge-type low-pass filter circuit 1012 may be 140 Hz.
  • the signal processed by bridge low-pass filter circuit 1012 may be further processed by differential amplifier U1.
  • differential amplifier U1 may reject common-mode signals (eg, power frequency signals) in the filtered signal.
  • the differential amplifier U1 can amplify the filtered signal.
  • the amplification factor of the signal by the differential amplifier U1 may not be greater than 10 times.
  • the amplification factor of the differential amplifier U1 to the signal may not be greater than 7 times.
  • the amplification factor of the signal by the differential amplifier U1 may not be greater than 5 times.
  • the amplification factor of the signal by the differential amplifier U1 may not be greater than 4 times.
  • the amplification factor of the signal by the differential amplifier U1 may not be greater than 3 times.
  • the amplification factor of the differential amplifier U1 to the signal may not be greater than 2 times.
  • the first processing circuit 1010 since the first processing circuit 1010 includes only one amplifier (ie, the differential amplifier U1 ), the amplification factor of the differential amplifier U1 is referred to as the first amplification factor of the first processing circuit 1010 .
  • the high-pass filter 1014 can perform high-pass filtering processing on the signal processed by the differential amplifier U1.
  • the lower cutoff frequency of the high pass filter 1014 may be in the frequency range of 5Hz-200Hz.
  • the upper cutoff frequency of the high-pass filter 1014 may be 20 Hz.
  • the signal processed by the high-pass filter 1014 is the first processed signal.
  • the second processing circuit 1020 may be used to amplify the first processed signal.
  • the second processing circuit 1020 may include an amplification circuit 1022 , a negative feedback circuit 1024 and a follower 1026 .
  • the amplifier circuit 1022 may include a resistance-capacitance feedback network (as shown in FIG. 6A , which is composed of a resistor R7 and a capacitor C3 ) (that is, the amplifier circuit 1022 may also be referred to as a resistance-capacitance amplifier circuit), and the second processing circuit 1020 can The gain multiple of the first processed signal may vary with the frequency of the first processed signal.
  • the second processing circuit 1020 may perform amplifying processing on the first processing signal by a second multiple.
  • the second processing circuit 1020 includes a plurality of amplifiers, and the second amplification factor may be a total amplification factor of the plurality of amplifiers.
  • the second magnification may be greater than the first magnification.
  • the second magnification may be greater than 30 times, 50 times, 100 times, 200 times, 500 times, and the like.
  • Negative feedback circuit 1024 can be used to achieve a wide range of gain (ie, magnification) tunability using sliding rheostat R5. For example, a gain change from 0-A, where A is the gain of amplifier 1022, can be achieved.
  • sliding varistor R5 may also be referred to as a voltage divider resistor.
  • the follower 1026 can be used to isolate the influence of the output terminal on the signal processing circuit 1000 .
  • the frequency response (ie, bandpass effect) of the signal processing circuit 1000 can be optimized by adjusting the resistance and capacitance values in the RC feedback network in the amplifier circuit 1022 .
  • the resistors in the RC feedback network can be enlarged by a factor of 2 and the capacitors can be reduced in value by a factor of 2.
  • the values of the resistors and capacitors in the high-pass filter 1014 may be adjusted non-proportionally to amplify the effect of the capacitors (eg, only increase the value of the capacitors). value), but at this time, the signal of the non-target frequency band is also boosted.
  • a higher-order signal processing circuit can be designed on the basis of the signal processing circuit 1000 .
  • FIG. 11 is a schematic diagram of a circuit architecture of an exemplary signal processing circuit according to some embodiments of the present application.
  • the signal processing circuit 1100 may include the same first processing circuit 1010 as the signal processing circuit 1000 .
  • the signal processing circuit 1100 may also include a second processing circuit 1120 .
  • the second processing circuit 1120 may include an amplifier circuit 1122 , a resistance-capacitance high-pass filter amplifier circuit 1124 , a negative feedback circuit 1126 and a follower 1128 .
  • the second processing circuit 1120 in the signal processing circuit 1100 may further include a resistance-capacitance high-pass filter amplifying circuit 1124, which may acts as a high-pass filter.
  • the RC high-pass filter amplifying circuit 1124 may further include a RC feedback network which is provided in parallel between the input terminal and the output terminal of the amplifier by a capacitor and a resistor.
  • the signal processing circuit 1100 may also be referred to as a second-order filter EMG processing circuit. Further, compared with the second processing circuit 1020, in the second processing circuit 1120, the sliding varistor R5 in the second processing circuit 1020 is replaced with resistors R5 and R6.
  • the parameters of the amplification circuit 1122 can be adjusted to change the second processing The gain of the circuit 1120 to the signal. For example, resistor R7 and capacitor C8 can be reduced in the same proportion.
  • FIG. 12A is a schematic diagram of a circuit architecture of an exemplary signal processing circuit according to some embodiments of the present application.
  • FIG. 12B is a frequency response curve when the frequency response peak of the signal processing circuit in FIG. 12A is 80 Hz.
  • the signal processing circuit 1200 may include a first processing circuit 1210 and a second processing circuit 1220 .
  • the second processing circuit 1220 may be directly connected to the first processing circuit 1210 .
  • the first processing circuit 1210 may include a bridge low-pass filter circuit 1212 , a differential amplifier U1 and a trap circuit 1214 .
  • the bridge low-pass filter circuit 1212 and the differential amplifier U1 may have the same structure as the bridge low-pass filter circuit 1012 and the differential amplifier U1 in the signal processing circuit 1000 .
  • the trap circuit 1214 may comprise a dual-T active type trap circuit.
  • the notch frequency of the notch circuit 1214 may be set to the frequency of the power frequency signal (eg, 50 Hz).
  • the trap circuit 1214 may also include cascaded trap circuits. Further, the trap circuit 1214 may include multiple cascaded trap circuits. The frequency of the notch points of each cascaded notch circuit in the multi-cascade notch circuit can be set to 50Hz, 100Hz, 150Hz, 250Hz, etc. respectively.
  • the second processing circuit 1220 may include a RC high-pass filter amplifying circuit 1222 , a RC low-pass filter amplifying circuit 1224 , a voltage-controlled low-pass filter circuit 1226 , a negative feedback circuit 1128 and a follower 1229 .
  • the RC high-pass filter amplifying circuit 1222 , the RC low-pass filter amplifying circuit 1224 , the voltage-controlled low-pass filter circuit 1226 , and the follower 1229 may be connected in series in sequence.
  • the RC high-pass filtering and amplifying circuit 1222 can perform high-pass filtering and amplifying processing on the signal.
  • the RC low-pass filtering and amplifying circuit 1224 can perform low-pass filtering and amplifying processing on the signal.
  • the amplifiers in the RC high-pass filter amplifying circuit 1222 and the amplifiers in the RC low-pass filter amplifying circuit 1224 may have the same or different amplifying capabilities for signals.
  • the amplification of the signal by the amplifier may be greater than 10 times. In some embodiments, the amplification of the signal by the amplifier may be greater than 30 times. In some embodiments, the amplification of the signal by the amplifier may be greater than 100 times. In some embodiments, the amplification of the signal by the amplifier may be greater than 500 times.
  • the voltage controlled low pass filter circuit 1226 may be combined with the bridge low pass filter pass 1212 and/or the RC low pass filter amplifier circuit 1224 to compensate for the bridge low pass filter pass 1212 and/or the RC low pass filter amplifier circuit 1224. Attenuation near its upper cutoff frequency makes the passband flatter.
  • the resistor R5 and the resistor R6 may also be referred to as voltage divider resistors.
  • the frequency response of the signal processing circuit 1200A can be adjusted by adjusting the resistance value of the voltage dividing resistor. For example, the resistance of the voltage dividing resistor can be increased to prevent the loss of the target signal caused by signal saturation (especially noise signal saturation).
  • the curve g0 represents the frequency response curve of the conventional signal processing product.
  • the curve g1 represents the frequency response curve of the signal processing circuit 1200 when the voltage dividing resistor is the first resistance value
  • the curve g2 represents the frequency response curve of the signal processing circuit 1200 when the voltage dividing resistor is the second resistance value, wherein the second resistance value is greater than the first resistance value.
  • a resistance value It can be seen from FIG. 12B that due to the existence of the trap circuit 1214 for the power frequency signal (50 Hz), the curve g1 and the curve g2 have a dip at 50 Hz, that is, the power frequency signal is greatly suppressed.
  • the frequency response peak of the signal processing circuit 1200 is set to 80 Hz, compared with conventional signal processing products, the signal processing circuit 1200 contains less noise signals, and the signals in the high frequency range are effectively suppressed.
  • the signal processing circuit 1200A can be adjusted based on the principle of prioritizing the processing of power frequency signals, power frequency harmonic signals, and MA, and then performing larger gains, as shown in FIG. 12C .
  • FIG. 12C is a schematic diagram of a circuit architecture of an exemplary signal processing circuit according to some embodiments of the present application.
  • FIG. 12D is a frequency response curve when the frequency response peak of the signal processing circuit in FIG. 12C is 80 Hz.
  • the voltage-controlled low-pass filter circuit 1226 in the second processing circuit 1220 can be connected before the RC high-pass filter amplifier circuit 1222 , and the RC low-pass filter amplifier circuit 1224 can be directly connected with the negative feedback circuit 1228 .
  • the voltage-controlled low-pass filter circuit 1226 when the voltage-controlled low-pass filter circuit 1226 is disposed immediately after the trap circuit 1214, the voltage-controlled low-pass filter circuit 1226 may also be considered to be disposed in the first processing circuit.
  • FIG. 13 is a comparison diagram of a frequency response curve of a signal processing circuit measured at different times and a simulated frequency response curve according to some embodiments of the present application.
  • one electrode in the acquisition circuit may be lifted by half (that is, the electrode is half detached) or fully lifted (that is, the electrode is completely detached).
  • the time 1 curve and the time 2 curve were measured at different times and under different conditions of electrode detachment.
  • the signal acquisition electrode can be lifted by half, and in the process of obtaining the time 2 curve, the electrode can be not lifted.
  • the frequency response curves of the signal processing circuit measured at different times (for example, time 1 and time 2) and under different conditions (electrode half-off and not off) The consistency is high, and the difference with the simulated signal is small, and there is no signal saturation problem. Therefore, the signal processing circuit in the embodiment of the present application has strong stability and high accuracy, and can cope with the problem of electrode falling off to a large extent during the test process.
  • FIG. 14 is an electromyographic signal collected when a bicep curl experiment is performed using a signal processing circuit according to some embodiments of the present application.
  • Figure 14 shows the signal data collected for the biceps, trapezius, and pectoralis major muscles from top to bottom.
  • the subjects' movements can be followed by two normal bicep curling movements, two shoulder shrug movements and two chest clipping movements.
  • the signal-to-noise ratio of the signal processed by the signal processing circuit is high (the signal-to-noise ratio can reach 500), the power frequency and its harmonics are greatly suppressed, and the EMG signal components are simplified (mainly including the target frequency band). signal of). Therefore, the signal processing circuit in the embodiment of the present application can successfully complete the high-quality acquisition of the EMG signal in the bicep curl exercise.
  • the possible beneficial effects of the embodiments of the present application include but are not limited to: (1) By adopting the time-division multiplexing method, under the condition of ensuring the collection and processing of multiple signal sources, it is possible to save space costs and reduce hardware requirements. Purpose; (2) When multiple input channels have signals at the same time, the crosstalk between each input channel can be reduced; (3) The fully reconstructed strategy can completely reproduce the corresponding multi-channel target signals based on the obtained sampling data; (4) Under the intensity characterization strategy, the intensity information and part of the frequency information of the target signal can be obtained based on the obtained sampling data; (5) The possible baselines can be solved by means of small-gain high-precision ADCs, programmable baselines and adding high-pass filter circuits (6) By first processing power frequency signals and power frequency harmonic signals and other high-intensity noise signals, and then performing a larger gain, it can prevent the signal from being over-saturated and causing the loss of the target signal; (7) By switching the circuit The frequency response peak is set at a position far
  • aspects of this application may be illustrated and described in terms of several patentable classes or situations, including any new and useful process, machine, product or combination of matter or combinations of them. Any new and useful improvements. Accordingly, various aspects of the present application may be performed entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or by a combination of hardware and software.
  • the above hardware or software may be referred to as a "data block”, “module”, “engine”, “unit”, “component” or “system”.
  • aspects of the present application may be embodied as a computer product comprising computer readable program code embodied in one or more computer readable media.

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Abstract

本申请实施例公开了一种信号处理电路。该信号处理电路包括模拟电路。所述模拟电路用于对其接收的初始信号进行处理，所述初始信号包括目标信号和噪声信号。所述模拟电路包括第一处理电路和与所述第一处理电路相连接的第二处理电路。第一处理电路用于提高所述目标信号与所述噪声信号之间的比值，输出第一处理信号。第二处理电路用于对所述第一处理信号进行放大处理，所述第二处理电路对所述第一处理信号的增益倍数随所述第一处理信号的频率变化而变化。所述第一处理电路包括共模信号抑制电路、低通滤波电路和高通滤波电路。所述共模信号抑制电路用于抑制所述初始信号中的共模信号。

Description

信号处理电路和装置
交叉引用
本申请要求2020年12月31日提交的申请号为PCT/CN2020/142529的国际专利申请的优先权，其全部内容通过引用并入本文。
技术领域
本申请一般涉及电路设计领域，尤其涉及一种用于处理生理信号的电路和装置。
背景技术
随着人们对科学运动和生理健康的关注与日俱增，对生理信号监测装置的需求也越来越多。有些生理信号(例如，用户运动时的肌电信号)的强度较弱，在存在噪声的情况下，一般的信号处理电路很难在剔除噪声后保留有效的生理信号。因此，期望提供一种适用于生理信号监测装置的信号处理电路，可以针对性地对特定的生理信号进行处理。
发明内容
本申请实施例提供了一种信号处理电路。该信号处理电路可以包括模拟电路。模拟电路可以用于对其接收的初始信号进行处理。所述初始信号可以包括目标信号和噪声信号。所述模拟电路可以包括第一处理电路和与所述第一处理电路相连接的第二处理电路。所述第一处理电路可以用于提高所述初始信号的信噪比，以输出第一处理信号。所述第二处理电路可以用于对所述第一处理信号进行放大处理，所述第二处理电路对所述第一处理信号的增益倍数随所述第一处理信号的频率变化而变化。所述第一处理电路可以包括共模信号抑制电路、低通滤波电路和高通滤波电路。所述共模信号抑制电路可以用于抑制所述初始信号中的共模信号。
在一些实施例中，所述共模信号抑制电路可以包括差分放大器。
在一些实施例中，所述低通滤波电路可以包括在所述差分放大器的输入端形成的桥式电路结构。
在一些实施例中，所述差分放大器的输入阻抗大于10MΩ。
在一些实施例中，所述低通滤波电路的截止频率点可以在100Hz-1000Hz的频率范围之内。
在一些实施例中，所述高通滤波电路的截止频率点在5Hz-200Hz的频率范围之内。
在一些实施例中，所述第一处理电路可以包括陷波电路，所述陷波电路用于抑制工频信号。
在一些实施例中，所述陷波电路可以包括级联陷波电路，所述级联陷波电路还用于抑制工频信号的谐波。
在一些实施例中，所述陷波电路可以包括双T有源型陷波电路。
在一些实施例中，所述第一处理电路还可以包括压控低通滤波电路，所述压控低通滤波电路用于在其目标频率附近提供增益，并与所述低通滤波电路相结合以补偿所述低通滤波电路的衰减。
在一些实施例中，所述第一处理电路在提高所述目标信号与所述噪声信号之间的比值的过程中，可以包括对所述目标信号进行第一放大倍数的放大处理，以及对所述噪声信号进行衰减处理。
在一些实施例中，所述第二处理电路可以包括放大电路、反馈电路和跟随器。所述放大电路可以用于对所述第一处理信号进行第二放大倍数的放大处理，所述第二放大倍数大于所述第一放大倍数。所述跟随器可以用于隔绝所述信号处理电路输出端的影响。
在一些实施例中，所述第二处理电路对所述第一处理信号在第一频率范围的增益响应大于在所述第一频率范围之外的增益响应。
在一些实施例中，所述第一频率范围可以包括20Hz-140Hz。
在一些实施例中，所述初始信号可以包括肌电信号。
在一些实施例中，所述的信号处理电路还可以包括控制电路、开关电路以及至少两个信号采集电路。所述至少两个信号采集电路可以用于采集至少两路初始信号。所述开关电路可以用于控制所述至少两个信号采集电路与所述模拟电路的导通，使得在同一时间所述至少两个信号采集电路中仅有部分信号采集电路采集的初始信号传输至所述模拟电路。所述控制电路可以用于接收经模拟电路处理后的目标信号，并对所述经过处理的目标信号进行采样。
在一些实施例中，所述开关电路可以包括多个输入通道，所述至少两个信号采集电路中每个信号采集电路单独连接一个输入通道，在同一时间，所述开关电路基于所述控制电路的控制信号选择一个输入通道导通。
本申请实施例提供了一种信号处理装置。该信号处理装置包括信号处理电路。该信号处理电路可以包括模拟电路。模拟电路可以用于对其接收的初始信号进行处理。所述初始信号可以包括目标信号和噪声信号。所述模拟电路可以包括第一处理电路和与所述第一处理电路相连接的第二处理电路。所述第一处理电路可以用于提高所述初始信号的信噪比，以输出第一处理信号。所述第二处理电路可以用于对所述第一处理信号进行放大处理，所述第二处理电路对所述第一处理信号的增益倍数随所述第一处理信号的频率变化而变化。所述第一处理电路可以包括共模信号抑制电路、低通滤波电路和高通滤波电路。所述共模信号抑制电路可以用于抑制所述初始信号中的共模信号。
附加的特征将在下面的描述中部分地阐述，并且对于本领域技术人员来说，通过查阅以下内容和附图将变得显而易见，或者可以通过实例的产生或操作来了解。本发明的特征可以通过实践或使用以下详细实例中阐述的方法、工具和组合的各个方面来实现和获得。
附图说明
根据示例性实施例可以进一步描述本申请。参考附图可以详细描述所述示例性实施例。所述实施例并非限制性的示例性实施例，其中相同的附图标记代表附图的几个视图中相似的结构，并且其中：
图1是根据本申请的一些实施例所示的信号采集装置的示例性电路的示意图；
图2是根据本申请的一些实施例所示的信号处理方法的示例性流程图；
图3A是根据本申请的一些实施例所示的示例性信号处理电路的示意框图；
图3B是根据本申请一些实施例所示的多种级联陷波电路的频响曲线图；
图4A-4C是根据本申请的一些实施例所示的示例性低通滤波电路的结构示意图；
图4D是图4A、图4B和图4C中的低通滤波电路的频响曲线图；
图5A-5B是根据本申请的一些实施例所示的低通滤波电路的结构示意图；
图5C是图5A和图5B中的低通滤波电路的频响曲线图；
图6A是根据本申请的一些实施例所示的阻容低通滤波电路的结构示意图；
图6B是二阶分布式低通滤波电路和图6A中的阻容低通滤波电路的频响曲线图；
图7A是根据本申请的一些实施例所示的压控低通滤波电路的结构示意图；
图7B是二阶低通滤波电路和图7A中的压控低通滤波电路的频响曲线图；
图8A是根据本申请的一些实施例所示的示例性低通滤波电路的结构示意图；
图8B是图8A中的低通滤波电路的频响曲线图；
图9A-9B是根据本申请的一些实施例所示的示例性高通滤波电路的结构示意图；
图9C是图9A-9B中的高通滤波电路的频响曲线图；
图10A是根据本申请的一些实施例所示的示例性信号处理电路的电路架构示意图；
图10B是图10A中信号处理电路的频响曲线；
图11是根据本申请的一些实施例所示的示例性信号处理电路的电路架构示意图；
图12A是根据本申请的一些实施例所示的示例性信号处理电路的电路架构示意图；
图12B是图12A中信号处理电路的频响峰为80Hz时的频响曲线；
图12C是根据本申请的一些实施例所示的示例性信号处理电路的电路架构示意图；
图12D是图12C中信号处理电路的频响峰为80Hz时的频响曲线；
图13是根据本申请的一些实施例所示的不同时间测量得到的信号处理电路的频响曲线与仿真频响曲线的对比图；以及
图14是根据本申请的一些实施例所示的利用信号处理电路进行二头弯举实验时采集的肌电信号。
具体实施方式
为了更清楚地说明本申请的实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单的介绍。显而易见地，下面描述中的附图仅仅是本申请的一些示例或实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图将本申请应用于其他类似情景。图中各电子器件的相同标号可以表示不同的电子器件，其仅用于区分相同实施例中的各个器件。例如，相同的标号R1可以代表不同的阻值的电阻器。
如本申请和权利要求书中所示，除非上下文明确提示例外情形，“一”、“一个”、
“一种”和/或“该”等词并非特指单数，也可包括复数。一般说来，术语“包括”与“包含”仅提示 包括已明确标识的步骤和元素，而这些步骤和元素不构成一个排它性的罗列，方法或者设备也可能包含其他的步骤或元素。
应当理解，本文使用的术语“数据块”、“系统”、“引擎”、“单元”、“组件”、“模块”和/或“块”是用以区分不同级别的不同组件、元件、部件、部分或组件的一种方法。然而，如果其他词语可以实现相同的目的，则可通过其他表达来替换所述词语。
使用各种术语描述元素之间(例如，层之间)的空间和功能关系，包括“连接”、
“接合”、“接口”和“耦合”。除非明确描述为“直接”，否则在本申请中描述第一和第二元素之间的关系时，该关系包括在第一和第二元素之间不存在其他中间元素的直接关系，以及在第一和第二元素之间存在(空间或功能上)一个或以上中间元素的间接关系。相反，当元件被称为“直接”连接、接合、接口或耦合到另一元件时，不存在中间元件。另外，可以以各种方式实现元件之间的空间和功能关系。例如，两个元件之间的机械连接可包括焊接连接、键连接、销连接、过盈配合连接等，或其任何组合。用于描述元素之间关系的其他词语应以类似的方式解释(例如，“之间”、“与......之间”、“相邻”与“直接相邻”等)。
本申请实施例中描述的信号处理电路和方法可以应用于需要采集一路或多路信号源的信号监测装置，特别是生理信号的监测装置，例如智能穿戴设备。在一些实施例中，所述智能穿戴设备(例如，服装、护腕、肩带等)可以设置在人体各个部位(例如，小腿、大腿、腰、后背、胸部、肩部、颈部等)，用于采集用户在不同状态时其身体各个部位的生理信号，后续还可以进一步对采集的信号进行处理。在一些实施例中，所述生理信号为可以被检测的能够体现身体状态的信号，例如，可以包括呼吸信号、心电信号(ECG)、肌电信号、血压信号、温度信号等多种信号。在一些实施例中，所述生理信号的频率范围可以包括0.05Hz～2kHz，其中，所述心电信号的频率范围可以包括0.05Hz～100Hz，所述肌电信号的范围可以包括5Hz～2kHz。
在一些实施例中，为了在处理过程中有效地保留所采集的信号中的目标信号(例如，肌电信号)，可以在噪声信号达到饱和前，预先对所采集的信号进行降噪处理以防止后续噪声被放大至饱和状态而造成目标信号丢失。此外，对所采集的信号进行先降噪后放大的处理，还可以对目标信号留有更多的处理裕度。
本申请实施例提供了一种信号处理电路。该信号处理电路可以包括模拟电路。模拟电路可以用于对其接收的初始信号进行处理。初始信号可以包括目标信号和噪声信号。所 述模拟电路可以包括第一处理电路和与所述第一处理电路相连接的第二处理电路。所述第一处理电路可以用于提高所述初始信号的信噪比，以输出第一处理信号。所述第二处理电路可以用于对所述第一处理信号进行放大处理，所述第二处理电路对所述第一处理信号的增益倍数随所述第一处理信号的频率变化而变化。所述第一处理电路可以包括共模信号抑制电路、低通滤波电路和/或高通滤波电路。所述共模信号抑制电路可以用于抑制所述输入信号中的共模信号。
在一些实施例中，若在生理信号采集过程中出现异常现象，则采集的信号中的噪声信号可能会在信号处理过程中(例如，放大处理)湮没有效的生理信号。如果在剔除掉噪声信号之前对采集到的信号进行例如，放大处理，则可能造成电路饱和而无法有效地提取出生理信号。例如，在采集肌电信号的过程中可能会引入工频信号(噪声)。由于工频信号的强度远大于肌电信号的强度(前者可达十伏级别，后者只有毫伏级别)，若在采集肌电信号过程中采集电极出现异常(例如，电极脱落、电极被掀起部分等)，则可能造成最终采集的信号中肌电信号被工频信号湮没。因此，根据本申请的一些实施例，首先通过第一处理电路对生理信号进行降噪处理后，再由第二处理电路对降噪后的生理信号进行放大处理，可以防止在生理信号采集过程中出现异常现象而导致处理过程中电路饱和，从而获得准确的高质量的生理信号。
图1是根据本申请的一些实施例所示的信号采集装置的示例性电路100的示意图。信号采集装置的电路100可以实现对多路生理信号的采集和处理。相比于多通道方案，电路100采用分时复用方案，在保证多路信号源采集和处理的情况下，可以达到节约空间和经济成本，节省ADC等硬件资源，防串扰等目的。具体地，如图1所述，电路100可以包括至少两个信号采集电路(例如，信号采集电路112、114、116和118)、开关电路120、模拟电路130以及控制电路140。
开关电路120可以设置在多路信号采集电路和模拟电路130之间，其可以用来控制每路信号采集电路和模拟电路130的导通状态。例如，在某一时间点，开关电路120可以导通一路信号采集电路和模拟电路130。在一定时间范围内，开关电路120可以以周期性的方式循环导通各路信号采集电路和模拟电路130。当开关电路120导通某路信号采集电路和模拟电路130时，该路信号采集电路所采集的信号(例如，肌电信号)就可以传递给模拟电路130进行处理(例如，降噪、放大等)，且处理后的信号会传递给控制电路140进行信号 分析。可以理解的是，通过在多路信号采集电路与模拟电路130之间设置开关电路120，可以实现同一个模拟电路在不同时间点分别对不同信号采集电路采集的信号进行处理，这样可以有效降低使用多个模拟电路的复杂性和成本，同时也减少了后续模拟电路和控制电路之间的信号传递的通道数量。需要知道的是，图1中所示出的开关电路120和模拟电路130仅作为说明的目的，在实际的使用中，多路信号采集电路和控制电路140之间也可以采用不止一个开关电路或模拟电路，这些开关电路或模拟电路仍然可以实现类似上述描述的过程。
在一些实施例中，所述至少两个信号采集电路可以用于采集至少两路目标信号。所述目标信号可以是能够体现用户身体状态的生理信号，例如，呼吸信号、心电信号(ECG)、肌电信号、血压信号、温度信号等中的一种或多种。仅作为示例，不同的信号采集电路可以分别包括一个或多个与用户身体接触的电极，通过电极可以采集用户身体表面的肌电信号。不同的信号采集电路可以布置在用户身体的不同位置，用于采集同种或不同种用户的生理信号。例如，分别布置在用户大腿不同侧的信号采集电路可以都用来采集大腿处的肌电信号。再例如，布置在用户小臂处的信号采集电路可以用来采集小臂处的肌电信号，而布置在用户心脏部位的信号采集电路可以用来采集用户的心电信号。需要知道的是，在一定的场景下，电路100或与其类似的电路可以用来采集并处理上述同种或不同种生理信号，本申请对此不作限制。在一些实施例中，所述至少两个信号采集电路可以仅包括两个信号采集电路，也可以包括三个信号采集电路、四个信号采集电路或者更多个信号采集电路。在一些实施例中，所述生理信号的频率范围可以包括0.05Hz～2kHz，其中，所述心电信号的频率范围可以包括0.05Hz～100Hz，所述肌电信号的范围可以包括5Hz～2kHz。
控制电路140会对模拟电路130处理后的信号进行采样。在一些实施例中，控制电路140的采样频率与信号采集电路的数量、对开关电路120的控制策略和目标频率有关。例如，控制电路140对每路信号的采样频率不低于其目标频率的2倍。仅仅作为示例，对于肌电信号而言，假设其对应的目标频率在1000Hz以内，控制电路140则可以采用2000Hz的采样频率对该肌电信号进行采样。对于整个电路100而言，假定有4个采集肌电信号的信号采集电路，则需要控制电路140提供8000Hz的总采样频率，这样才能保证对每路肌电信号的采样率达到2000Hz。再例如，如本申请中其它地方提到的，控制电路140可以采用完全重构型策略和强度表征策略来控制开关电路120的切换。在完全重构型策略中，所述采样频率与信号采集电路的数量、单个通道的上升沿和下降沿时间等有关，其中单个通道的上升 沿和下降沿时间与模拟电路130的输出电压幅值(其与放大倍数和输入电压幅值相关)及电路元件的压摆率相关联。
在一些实施例中，所述开关电路120可以用于控制所述至少两个信号采集电路与所述模拟电路130的导通，使得在同一时间所述至少两个信号采集电路中仅有部分信号采集电路采集的目标信号传输至所述模拟电路130。所述开关电路120的输入端可以与所述至少两个信号采集电路相连接，所述开关电路120的输出端可以与所述模拟电路130相连接。在一些实施例中，所述开关电路120可以包括多个输入通道，所述至少两个信号采集电路中每个信号采集电路可以单独连接一个输入通道，在同一时间，所述开关电路120可以基于所述控制电路140的控制信号选择一个输入通道导通。
在一些实施例中，开关电路120可以选用具有多通道及双路输出的开关芯片，例如，型号为TMUX1209的开关芯片。仅作为示例，所述开关电路120可以通过3个控制引脚实现4通道的分时复用，其中1个引脚EN被标记为使能作用，另外两个引脚A1和A0被标记为选择通道。所述开关电路120的四个输入通道分别用于连接信号采集电路以采集目标信号，所述开关电路120的输出口连接模拟电路130。在一些实施例中，可以通过控制引脚(EN，A1，A0)的数值来控制开关芯片的选通。例如，当输入(1，0，0)时，表示选通通道A，当输入(1，0，1)时，表示选通通道B，当输入(1，1，0)时，表示选通通道C，当输入(1，1，1)时，表示选通通道D。仅仅作为示例，当控制电路140选通开关电路120的通道A后，通道A对应的目标信号会被连通至模拟电路130，并最终被控制电路140采样。当本次采样成功后，控制电路140会给出新的控制指令，例如可以给出指令(1，0，1)用于选通通道B，则通道B的目标信号会被连接至模拟电路130并最终被控制电路140采样，以此类推。也就是说，控制电路140可以控制开关电路120在多个信号采集电路之间循环切换，从而达到分时复用的作用，即可以通过一路模拟电路130分时处理多路信号源，从而节约空间成本，降低硬件要求。
在不同的情况下，控制电路140可以基于不同的策略控制开关电路120的切换。例如，为了使得后续采样数据能够完整保留每路目标信号的信息(即，控制电路140可以基于采样数据重构每路目标信号)，控制电路140可以采用完全重构型策略来控制开关电路120的切换。在完全重构型策略下，控制电路140可以根据其提供的总采样频率来切换开关电路120的输入通道。例如，开关电路120切换输入通道的频率可以等于控制电路140提供 的采样频率。这种情况下，开关电路120每切换一次输入通道，即每导通一个信号采集电路，控制电路140就会对该信号采集电路采集的目标信号进行一次采样。而且，由于控制电路140对每路目标信号的采样频率在目标频率的2倍以上，完全重构型策略可以保证每路目标信号在每个周期内都具有至少两个采样点。更多关于完全重现型控制策略的内容可以参见图2的详细描述。
再例如，考虑到控制电路140可能无法在开关通道快速切换的过程中获取有效的采样数据(由于下文中提到的开关通道的切换会导致控制电路140所接收到的信号存在一定的上升沿以及下降沿)，控制电路140可以采用强度表征型策略来控制开关电路120的切换。在强度表征型策略下，控制电路140可以基于预设频率来切换开关电路120的输入通道。所述预设频率可以和用户实施某个动作的周期有关。例如，为了对用户做力量训练时肌肉产生的肌电信号进行分析，所述预设频率可以是用户实施特定动作(例如，卧推)的频率的一定倍数，使得在用户实施该特定动作的一个周期内，开关电路120可以多次导通每一个信号采集电路，从而控制电路140可以分别对每一路目标信号进行多次采样。在强度表征型策略下，控制电路140可以基于采样结果获取每路目标信号的强度信息。更多关于强度表征型策略的内容可以参见图2的详细描述。
所述模拟电路130用于对其接收的目标信号进行处理。在一些实施例中，由于信号采集电路直接采集到的原始目标信号的幅值非常小，并且有大量的噪声，因此需要使用模拟电路130对该原始目标信号进行滤波、差分放大、放大、负反馈消噪等处理。在一些实施例中，模拟电路130也可以称为信号处理电路。在一些实施例中，所述模拟电路130可以包括差分放大器，用于对其接收的目标信号进行抑制共模信号和放大处理。在一些实施例中，所述模拟电路130可以包括多级放大电路，用于对其接收的目标信号进行多级放大处理。所述多级放大电路中不同级放大电路对其输入信号可以具有不同的放大增益。例如，在模拟电路130的多级放大电路中，位于前级的放大电路的放大增益可以小于位于后级的放大增益。在一些实施例中，所述模拟电路130可以包括滤波电路，用于对其接收的目标信号进行滤波处理。示例性的滤波处理包括高通滤波、低通滤波、带通滤波、或者滤除特定频率成分的滤波等。所述滤波处理可以发生在所有放大处理之前，或者所述多级放大处理之间。在一些实施例中，所述模拟电路130可以包括右腿驱动电路，用于对其接收的目标信号中的共模信号进行提取，反向放大后反馈回信号源，主要可以抑制信号源中的工频。在一些实施例中，所 述模拟电路130可以同时包括差分放大器、多级放大器、滤波电路和右腿驱动电路，或仅包括其中一种或几种。更多关于信号处理电路的描述可以参见本申请其他地方(例如，图3A-12C及其描述)。
如上所述，所述控制电路140可以用于接收经模拟电路130处理后的目标信号，并对所述经过处理的目标信号进行采样。在一些实施例中，所述控制电路140可以包括多个模数转换通道(即，ADC通道)，每个ADC通道都可以用于将接收的经模拟电路130处理后的目标信号转换为数字信号进行读取和处理。在一些实施例中，所述控制电路140还可以连接显示装置，以对读取的数字信号进行显示，从而直观的体现生理信号的情况。在一些实施例中，基于所述采样，控制电路140可以对目标信号进行读取、存储、处理分析等，可选地，所述控制电路140还可以根据采样的数据发出相应的指令。
在一些实施例中，所述控制电路140对经过处理的每路目标信号的采样发生在所述控制电路140开始接收所述经过处理的每路目标信号的一段时间之后。也就是说，在开关电路120切换导通通道后，控制电路140不会立即对新导通的目标信号进行采样，或者即使控制电路140对新导通的目标信号进行了采样，也不会立即将采样的结果作为目标信号的组成部分。当使用分时复用方式采集多路信号源的目标信号时，开关通道的切换会导致控制电路140所接收到的信号存在一定的上升沿以及下降沿。上升沿对应输入端信号变化引起输出端信号上升直到达到稳定状态所需要的时间。下降沿对应输入端从一个信号变化引起输出端的信号下降直到达到稳定所需要的时间。所述上升沿和下降沿会受到多个因素的共同影响，包含开关电路120的响应稳定速度、电路中芯片的压摆、电路中电容等器件的充放电等。因此，为了保证控制电路140读取到的目标信号真实有效，对目标信号的采样会在信号稳定之后再进行，即在开关电路120切换导通通道后，控制电路140在上升沿时间中不对信号进行采样。若是不等待足够的时间就开始采样，那么控制电路140最终读到的数值将会是一个中间的过渡值。可以理解的是，如果上升沿时间固定，那么即使等待时间不足，但最终得到的过渡值相对于真实值比例一致，也可以用于后续的处理和分析。然而，当上升沿时间与电压变化大小有关时，如果未稳定就读数，控制电路140每次读取的值与真实值的比例不固定，无法用于后续的处理。另外可以理解的是，如果考虑清楚过渡值和稳定值之间的关系，或者可以接受过渡值和稳定值之间的误差，那么即使等待时间不足，也可以用于后续的处理和分析。综上所述，应该考虑目标信号的强度和电路的增益，以此获得最大的上升沿时间，作为 控制电路140等待时间的参考。具体来说，可以设定不小于最大的上升沿时间的参考时间，所述控制电路140对每路目标信号的采样发生在所述控制电路140开始接收所述目标信号的参考时间之后，或者控制电路140对目标信号的采样发生在每次开关电路切换导通通道的参考时间之后。
图2是根据本申请的一些实施例所示的信号处理方法的示例性流程图。在一些实施例中，流程200可以由电路100实现。
步骤210，通过至少两个信号采集电路采集至少两路目标信号。在一些实施例中，步骤210可以由电路100中的至少两个信号采集电路(例如，信号采集电路112、114、116和118)实现。
在一些实施例中，所述至少两个信号采集电路可以用于采集至少两路目标信号。所述目标信号可以是能够体现用户身体状态的生理信号，例如，呼吸信号、心电信号(ECG)、肌电信号、血压信号、温度信号等中的一种或多种。仅作为示例，不同的信号采集电路可以分别包括一个或多个与用户身体接触的电极，通过电极可以采集用户身体表面的肌电信号。不同的信号采集电路可以布置在用户身体的不同位置，用于采集同种或不同种用户的生理信号。例如，分别布置在用户大腿不同侧的信号采集电路可以都用来采集大腿处的肌电信号。再例如，布置在用户小臂处的信号采集电路可以用来采集小臂处的肌电信号，而布置在用户心脏部位的喜好采集电路可以用来采集用户的心电信号。需要知道的是，在一定的场景下，电路100或与其类似的电路可以用来采集并处理上述同种或不同种生理信号，本申请对此不作限制。在一些实施例中，所述至少两个信号采集电路可以仅包括两个信号采集电路，也可以包括三个信号采集电路、四个信号采集电路或者更多个信号采集电路。在一些实施例中，所述生理信号的频率范围可以包括0.05Hz～2kHz，其中，所述心电信号的频率范围可以包括0.05Hz～100Hz，所述肌电信号的范围可以包括5Hz～2kHz。
步骤220，通过开关电路控制至少两个信号采集电路与模拟电路的导通，使得在同一时间至少两个信号采集电路中仅有部分信号采集电路采集的目标信号传输至模拟电路。在一些实施例中，步骤220可以由电路100中的开关电路120实现。
在一些实施例中，开关电路的输入端可以与所述至少两个信号采集电路相连接，开关电路的输出端可以与模拟电路(例如，模拟电路130)相连接。在一些实施例中，开关电路可以包括多个输入通道，所述至少两个信号采集电路中每个信号采集电路单独连接一个 输入通道，在同一时间，所述开关电路可以基于控制电路(例如，控制电路140)的控制信号选择一个输入通道导通。
在一些实施例中，开关电路可以基于控制电路的控制指令实施信号采集电路与模拟电路的导通。以上文中所描述的4通道的分时复用为例，当控制电路140选通开关电路120的通道A后，通道A对应的目标信号会被连通至模拟电路130，并最终被控制电路140采样。当本次采样成功后，控制电路140会给出新的控制指令，例如可以给出指令用于选通通道B，则通道B的目标信号会被连接至模拟电路130并最终被控制电路采样，以此类推。也就是说，控制电路140可以控制开关电路120在多个信号采集电路之间循环切换，从而达到分时复用的作用，即可以通过一路模拟电路130分时处理多路信号源，从而节约空间成本，降低硬件要求。
步骤230，通过模拟电路对其接收的目标信号进行处理。在一些实施例中，步骤230可以由电路100中的模拟电路130实现。
在一些实施例中，由于信号采集电路直接采集到的原始目标信号的幅值非常小，并且有大量的噪声，因此需要使用模拟电路130对该原始目标信号进行滤波、差分放大、放大、负反馈消噪等处理。在一些实施例中，所述模拟电路130可以包括差分放大器，用于对其接收的目标信号进行抑制共模信号和放大处理。在一些实施例中，所述模拟电路130可以包括多级放大电路，用于对其接收的目标信号进行放大处理。在一些实施例中，所述模拟电路130可以包括滤波电路，用于对其接收的目标信号进行滤波处理。在一些实施例中，所述模拟电路130可以包括右腿驱动电路，用于对其接收的目标信号中的共模信号进行提取，反向放大后反馈回信号源，主要可以抑制信号源中的工频。在一些实施例中，所述模拟电路130可以同时包括差分放大器、多级放大器、滤波电路和右腿驱动电路，或仅包括其中一种或几种。
在一些实施例中，考虑到可能存在基线漂移的情况，可以通过降低模拟电路对目标信号的增益(即降低模拟电路中的放大倍数)，和/或选用具有高精度ADC通道的控制芯片，和/或选择利用电阻来调整参考电位从而解决基线漂移的问题，和/或选择在模拟电路130中增加高通滤波的方法滤除基线漂移。
步骤240，通过控制电路接收经模拟电路处理后的目标信号，并对所述经过处理的目标信号进行采样。在一些实施例中，步骤240可以由电路100中的控制电路140实现。
在一些实施例中，所述控制电路140包括多个ADC通道，每个ADC通道都可以用于将接收的经模拟电路130处理后的目标信号转换为数字信号进行读取和处理。在一些实施例中，所述控制电路140还可以连接显示装置，以对读取的数字信号进行显示，从而直观的体现生理信号的情况。在一些实施例中，基于所述采样，控制电路140可以对目标信号进行读取，存储，处理分析等，可选的，所述控制电路140还可以根据采样的数据发出相应的指令。
在一些实施例中，所述控制电路140对经过处理的每路目标信号的采样发生在所述控制电路140开始接收所述经过处理的每路目标信号的一段时间之后。也就是说，在开关电路120切换导通通道后，控制电路140不会立即对新导通的目标信号进行采样，或者即使控制电路140对新导通的目标信号进行了采样，也不会立即将采样的结果作为目标信号的组成部分。
在一些实施例中，控制电路140的采样频率与信号采集电路的数量、目标信号的类型和目标频率有关。例如，控制电路140对每路信号的采样频率不低于其目标频率的2倍。仅仅作为示例，对于肌电信号而言，假设其对应的目标频率在1000Hz以内，控制电路则可以采用2000Hz的采用频率对该肌电信号进行采样。对于整个信号处理电路而言，假定有4个采集肌电信号的采集电路，则需要控制电路140提供8000Hz的总采样频率，这样才能保证对每路肌电信号的采样率达到2000Hz。
在不同的情况下，控制电路140可以基于不同的策略控制开关电路120的切换。
在一些实施例中，为了使得后续采样数据能够完整保留每路目标信号的信息(即，控制电路140可以基于采样数据重构每路目标信号)，控制电路140可以采用完全重构型策略来控制开关电路120的切换。在完全重构型策略下，控制电路140可以根据其提供的总采样频率来切换开关电路120的输入通道。例如，开关电路120切换输入通道的频率可以等于控制电路140提供的采样频率。这种情况下，开关电路120每切换一次输入通道，即每导通一个信号采集电路，控制电路140就会对该信号采集电路采集的目标信号进行一次采样。而且，由于控制电路140对每路目标信号的采样频率在目标频率的2倍以上，完全重构型策略可以保证每路目标信号在每个周期内都具有至少两个采样点。
继续以上述四个采集肌电信号的信号采集电路为例，假设每路肌电信号的目标频率为都在1kHz以内，控制电路为每路肌电信号提供2kHz的采样频率。对控制电路而言， 总共提供8kHz的采样频率。开关电路同样以8kHz的频率在4个信号采集电路之间切换，其在每125微秒切换一次，开关电路的每两次相邻切换之间，控制电路对接收到的肌电信号进行一次采样。
进一步地，在完全重构策略下，控制电路可以基于获得的采样数据完全复现对应的多路目标信号。例如，控制电路可以重构每路目标信号，并进一步分析每路目标信号中的频率、相位、强度(幅值)等信息。可选地，控制电路可以将获得的采样数据或者重构的目标信号通过有线或无线的方式发送给外部处理电路进行分析。
在一些实施例中，开关电路120切换输入通道的频率还可以等于控制电路140提供的采样频率的一半或其它分数值。这种情况下，开关电路120每切换一次输入通道，即每导通一个信号采集电路，控制电路140可以对该信号采集电路采集的目标信号进行两次采样。继续以上述四个采集肌电信号的信号采集电路为例，假设每路肌电信号的目标频率为都在1kHz以内，控制电路为每路肌电信号提供2kHz的采样频率。对控制电路而言，总共提供8kHz的采样频率。开关电路仅需要以4kHz的频率在4个信号采集电路之间切换，其在每250微秒内切换一次，开关电路的每两次相邻切换之间，控制电路对接收到的肌电信号进行两次采样。这种方式采集的目标信号相对于开关电路每两次相邻切换之间仅进行一次采样的情况而言，由于每路信号的采样时间点不够均匀，基于采样数据重构的每路目标信号可能存在一定的偏差。
需要知道的是，在上述完全重构型策略下，控制电路采用分时复用方式所能处理的通道数量会受到目标信号的上升沿和下降沿的时间的影响。仅作为示例，若目标信号的频率为500Hz，控制电路要为单通道提供大于1kHz的采样频率，此时，实现4通道的分时复用时开关的切换速度需要达到4kHz，开关电路在单个通道的停留时间只有250微秒，而实现8通道的分时复用时开关的切换速度需要达到8kHz，开关电路在单个通道的停留时间只有125微秒。考虑到上升沿与下降沿的影响，开关电路在每个通道的停留时间不能太小。例如，若上升沿和下降沿均为50微秒，那这种情况下，最多可以实现16通道的分时复用。因此，通常会综合考虑上升沿下降沿时间，通道数量和目标信号频率范围等，从而选择合适的通道数量以及对应的通道切换时间。
在另一些实施例中，考虑到控制电路140可能无法在开关通道快速切换的过程中获取有效的采样数据(即，上述信号的上升沿和下降沿导致开关电路在单个通道的停留时间 过长，控制电路无法在目标信号的周期内采集至少两次有效数据点)，控制电路140可以采用强度表征型策略来控制开关电路120的切换。在强度表征型策略下，控制电路140可以基于预设频率来切换开关电路120的输入通道。所述预设频率可以和用户实施某个动作的周期有关。例如，为了对用户做力量训练时肌肉产生的肌电信号进行分析，所述预设频率可以是用户实施特定动作(例如，卧推)的频率的一定倍数，使得在用户实施该特定动作的一个周期内，开关电路120可以多次导通每一个信号采集电路，从而控制电路140可以分别对每一路目标信号进行多次采样。
继续以四个采集肌电信号的信号采集电路为例，假设用户以1秒1次的速度执行某个动作，若保证一个动作下控制电路对每路目标信号采样10次，则开关电路的切换速度为每秒40次，每切换到一个信号采集电路，控制电路先等待信号稳定，再进行连续采样，直到该路信号的25ms时间结束。在这种情况下，所述开关电路的切换速度与控制电路的总采样频率无关。控制电路可以用较高的总采样频率，达到采集目标信号中高频信号的效果。
进一步地，在强度表征策略下，控制电路可以基于获得的采样数据获取目标信号的强度信息。例如，在强度表征策略下，控制电路在一段时间内对单个信号采集电路产生的目标信号进行连续地采样。控制电路可以基于这些连续采样的数据计算出这段时间该信号采集电路采集的目标信号的强度，例如，计算这些连续采样的数据的平均值等。当然，控制电路也可以基于所有与该信号采集电路对应的采样数据计算出目标信号的强度。再进一步地，当控制电路计算出同一个信号采集电路在不连续的多个时间段所分别对应的目标信号的强度，控制电路可以基于这些信号强度以及其对应的时间，生成目标的信号强度和时间的变化关系，以此提取出该目标信号的特定频率信息。
在一些实施例中，所述强度表征型策略可以在采集强度信息的同时采集部分频率信息。在该策略下，由于没有完整采集所有时间段的信号，会丢失部分信号信息，因此会损失部分频率信息。仅作为示例，以40Hz的总频率控制开关电路进行切换，在4个信号采集电路的情况下，每个输入通道的采集时间长度为25ms，此时，对于信号频率小于40Hz的低频信号的采集会有一定损失。但是，如果将每一段采集到的信号(即单次切换通道后多次采样的信号)处理为一个代表值(例如，从每25ms采集的信号中提取一个平均值)，单通道的1s时间内有10个代表值，则可以利用完全重构型策略的处理方式，重构5Hz频率以下的信号。
在一些实施例中，强度表征策略下分时复用的能力与用户动作的频率以及对用户动作的监测精度要求有关，由于单通道采集持续时间较长，其受到上升沿和下降沿的影响较弱。在一些实施例在，此种策略下目标信号频率过低会导致分时复用的路数有限制，因此与目标信号的频率也有关。由于需要对目标信号的频率和强度信息进行提取，对低频信号，例如40Hz以下频率的信号，难以进行采集在这种情况下可以降低分时复用的路数，即降低信号采集电路的路数。
在一些实施例中，控制电路140可以根据实际情况调整具体的开关控制策略。例如，控制电路140可以在完全重构型策略和强度表征型策略之间进行切换。对于完全重构型策略和强度表征型策略之间的选择或切换可以根据对电路的延迟时间(例如，上升沿时间和下降沿时间)和电路的信噪比需求进行判断。例如，当电路的延迟时间较长且无法改变目标信号频率和信号采集电路的数量、模拟电路的放大倍数时，控制电路140可以选择强度表征型策略。再例如，当模拟电路中加入合适的滤波电路以提高信噪比时，考虑到滤波电路会造成延迟时间变长，控制电路140可以选择强度表征型策略。反之，当电路的延迟时间较短或对信噪比的需求不高时，控制电路140可以选择完全重构型策略。在一些实施例中，控制电路140可以根据环境因素或者用户指示来调整开关控制策略。例如，假设不同的开关控制策略对应不同的电量消耗速度，控制电路140可以根据电源(例如，电池)的电量状况实施对开关控制策略进行调整，当电源电量较低时，选择电量消耗速度较低的开关控制策略。再例如，控制电路140可以根据用户的输入指令来调整开关控制策略，以满足用户的不同需求。
应当注意的是，上述有关流程200的描述仅仅是为了示例和说明，而不限定本申请的适用范围。对于本领域技术人员来说，在本申请的指导下可以对流程200进行各种修正和改变。然而，这些修正和改变仍在本申请的范围之内。
图3A是根据本申请的一些实施例所示的示例性信号处理电路的示意框图。如图3A所示，信号处理电路300可以包括第一处理电路310和与该第一处理电路310连接的第二处理电路320。信号处理电路300可以用于对其接收的初始信号进行处理。初始信号可以是前述信号采集电路采集的信号。在一些实施例中，初始信号可以包括目标信号和噪声信号。在一些实施例中，第一处理电路310和第二处理电路320可以统称为模拟电路(例如，模拟电路130)。
第一处理电路310可以用于提高初始信号的信噪比，并输出第一处理信号。例如，第一处理电路310可以对初始信号中的目标信号进行第一放大处理以及对初始信号中的噪声信号进行衰减处理。又例如，第一处理电路310可以同时对目标信号和噪声信号进行放大处理，其中，其对目标信号的放大倍数大于其对噪声信号的放大倍数，从而提高信号的信噪比。初始信号中的目标信号可以是能够体现用户身体状态的生理信号，例如，呼吸信号、心电信号(ECG)、肌电信号、血压信号、温度信号等中的一种或多种。为方便描述，本申请中将以肌电信号作为生理信号的示例。需要理解的是，以下针对肌电信号特性而描述的数据，并不限制本申请的范围。例如，当目标信号为心电信号时，其对应的强度(幅值)范围和/或频率范围可以与心电信号的数据值相对应。具体地，心电信号的幅值范围可以在10μV-4mV范围之内；频率范围可以在0.05Hz～100Hz范围之内。对于本领域技术人员来说，在本申请的指导下可以对信号处理电路300进行各种修正和改变，以适应心电信号的处理。
在一些实施例中，不同肌肉(例如，胸大肌、肱二头肌等)、不同个体(例如，成人、小孩等)的肌电信号的幅值和/或频率可以不同。例如，肱二头肌和斜方肌可以较为容易达到毫伏级别，而背阔肌和腹肌一般只能达到百微伏级别。又例如，对于爆发式发力和持续式发力得到的肌电信号的频率分布可以不同。再例如，肌电信号的幅值和频率还会受到肌肉疲劳程度的影响，肌肉疲劳后得到的肌电信号的幅值会变大，频率分布会红移。在一些实施例中，肌电信号的幅值可以在5μV-100mV的范围之内。在一些实施例中，肌电信号的频率可以在10Hz-1000Hz范围之内。在一些实施例中，肌电信号的频率可以在10Hz-700Hz范围之内。在一些实施例中，肌电信号的频率可以在10Hz-500Hz范围之内。在一些实施例中，肌电信号的频率可以在20Hz-500Hz范围之内。在一些实施例中，肌电信号的频率可以在20Hz-140Hz范围之内。在一些实施例中，为了对肌肉的运动进行准确分析，需要获得的肌电信号具有信噪比高、稳定性好等特点。但是由于肌电信号中的噪声信号复杂，不同个体、不同肌肉的肌电信号不同，想要获得完整的肌电信号(例如，10Hz-1000Hz的肌电信号)非常困难。由于不同的肌电信号的主要频率成分(例如，总频率成分的80％、90％等)在频域上的分布相对集中(例如，主要分布在20Hz～140Hz内)，且对主要频率成分的肌电信号进行分析的分析结果也可以反映出准确的肌肉运动情况，因此，在对采集的肌电信号进行处理时，可以只提取主要频率成分(也称为目标频段)内的肌电信号即可 获得高质量的肌电信号。为方便描述，本申请中将以20Hz～140Hz作为目标频段的示例，其并不限制本申请的范围。需要注意的是，当目标频段发生变化时，本申请中信号处理电路的一个或多个参数也可以相应改变，使得信号处理电路可以适用于变化后的目标频段。
在一些实施例中，噪声信号可以包括运动伪迹噪声(Motion Artifacts，MA)、工频信号、工频谐波信号(即工频信号的谐波信号)、混叠噪音、白噪声等中的一种或多种。例如，当初始信号是通过信号采集电路(例如，信号采集电路112)采集的信号时，除了采集肌电信号，信号采集电路(例如，电极)还可能同时采集到工频信号、工频谐波信号、MA等。需要注意的是，在众多噪声信号中，由于工频信号和/或工频谐波信号的强度远高于其他噪声信号，对目标信号的分析带来麻烦。在某些情况下，工频信号和/或工频谐波信号可能使得信号处理电路的输出达到饱和，若不对其进行处理，则可能导致目标信号丢失。在本申请的一些实施例中，初始信号可以先由第一处理电路310对其中的噪声信号(例如，MA、工频信号及工频谐波信号)进行噪声衰减处理同时对其中的目标信号进行第一放大处理，再由第二处理电路320对经噪声衰减处理的信号进行第二放大处理，以此来抑制噪声信号对目标信号的干扰。在一些实施例中，信号处理电路300可以与数字电路连接，以将经第二处理电路320处理后的信号转换为数字信号并进行读取和处理。需要知道的是，通过第二处理电路320对经处理后的信号做进一步的放大处理可以具有以下好处：(1)当数字电路有噪音时，第二处理电路320可以提高整体信噪比；(2)通过设置第二处理电路320可以降低对数字电路的ADC精度要求。
工频信号的产生来源于供电系统。在一些实施例中，工频信号的频率可以为50Hz、60Hz等。在本申请中将以工频噪声为50Hz作为示例进行说明。在一些实施例中，供电系统还可能产生工频谐波信号。工频谐波信号的强度可以弱于工频信号的强度。工频谐波信号可以包括工频奇次谐波信号和工频偶次谐波信号。也就是说，工频谐波信号的频率可以包括100Hz、150Hz、200Hz、250Hz、300Hz、350Hz、400Hz等。在一些实施例中，当发电系统的三相绕组不对称时和/或供电系统的铁心的磁化曲线处于非线性的饱和状态时，非正弦的周期性信号的出现就会产生工频谐波信号。在这种情况下产生的工频谐波信号中奇次谐波可以占主体地位。也就是说，工频谐波信号的频率可以主要包括150Hz、250Hz、350Hz、450Hz等。
由于工频信号的频率为50Hz，这个频率处在肌电信号的目标频段(例如，20Hz-140Hz)内，而且工频信号的强度可达伏级别，因此，工频信号的存在会对肌电信号(信号强度达毫伏级)产生严重影响。此外，由于工频信号极强而肌电信号很弱，因此，即便工频谐波信号的强度弱于工频信号的强度，工频谐波信号仍然可能对肌电信号产生巨大的影响。因此，为了抑制工频信号及工频谐波信号对肌电信号的影响，需要对工频信号及工频谐波信号进行处理。需要知道的是，对于肌电信号(例如，其目标频段为20Hz-140Hz)中的工频信号(频率为50Hz)，不能单独依赖高通滤波器，因为要滤除50Hz频率的高通滤波器会牺牲较多的肌电信号(如，频率在20～40Hz范围内的肌电信号)。此外，由于工频频率在目标频段的范围内，为了更好保留目标频段的信号，需要采用过渡带极窄的高通滤波器，但过渡带极窄的高通滤波器需要较多级，对资源的耗费较高。
在本申请的一些实施例中，可以利用第一处理电路310中的共模信号抑制电路312对工频信号进行处理。共模信号抑制电路312可以用于抑制初始信号中的共模信号。在本申请中，共模信号可以指相位和幅值都相同的信号。由于工频信号来源于供电系统以及人体可看作是良导体，因此工频信号的相位和幅值都相同，即，工频信号为共模信号。因此，工频信号可以利用共模信号抑制电路312对其加以抑制。在一些实施例中，共模信号抑制电路312可以包括差分放大器、仪用放大器等，或其任意组合。例如，共模信号抑制电路312可以为长尾式差分放大器。具体地，差分放大器或仪用放大器可以利用其两个输入端的初始信号的共模性质，使两个输入端的信号相互抵消达到对共模信号的抑制作用。
在一些实施例中，以差分放大器为例(如图10A中差分放大器U1)，当电极与人体的接触发生变化时(例如，信号采集电路中的一个电极接触良好，一个电极脱落或半脱落)，换句话说，当信号采集电路的输入两端不一致时，差分放大器的输入端的输入信号相当于由共模信号变成差模信号，此时，差分放大器无法有效抑制工频信号。例如，对于肌电服，由于其与人体的结合是依靠压力贴合，因此，其与人体之间的接触不稳定。人体在运动的过程中，容易引起错移、悬空(即，电极脱落)等，从而造成工频信号无法被差分放大器抑制。由于人体肌肉、皮肤、电极、信号处理电路300等连接在一些相当于串联电路，每个环节都可以分压，因此，当电极与皮肤的接触发生变化时，会导致差分放大器两端的输入不一致。而大输入阻抗具有电路分压优势和抗输入信号波动的能力，从而当差分放大器的输入信号发生变化时，不会引起其输出信号较大的信号波动。在本申请中，分压优势可以指当接 触阻抗等变大(例如，电极脱落)，电路依然可以分压得到足够强度的肌电信号。抗输入信号波动的能力可以指当接触阻抗等波动时，大输入阻抗可以减小输入信号波动的影响。因此，为了尽可能地抑制工频信号，获得强的肌电信号，差分放大器的输入阻抗可以尽可能地大以减小因为差分输入端不均衡导致的噪声。在一些实施例中，差分放大器的输入阻抗可以大于或等于10MΩ。例如，差分放大器的输入阻抗可以为50MΩ、100MΩ、500MΩ、1GΩ、1.5GΩ、2GΩ、2.5GΩ、3GΩ、5GΩ、10GΩ等。
在一些实施例中，第一处理电路310还可以包括陷波电路。陷波电路可以用于抑制特定频率的信号，例如工频信号。例如，陷波电路的陷波点频率可以设置为50Hz。在本申请中，陷波电路的陷波点频率可以指陷波电路的谐振频率。在一些实施例中，为了尽可能地使陷波电路具有高的品质因数(即，Q值)，陷波电路可以包括具有较高Q值的双T有源型陷波电路(如图12A中陷波电路1214)。在一些实施例中，可以引入正反馈和/或调节陷波电路的参数值，使陷波电路的陷波谷的半高宽小于半高宽阈值，从而得到较高的品质因数Q，提高陷波电路的Q值和陷波能力。例如，可以通过调节陷波电路中的电阻、电容等的值和/或精度，使得陷波谷的半高宽在半高宽阈值之内。在一些实施例中，半高宽阈值可以为5Hz、4Hz、3Hz、1Hz、0.5Hz等。
在一些实施例中，由于MA信号与工频信号的乘法效应可以产生例如50Hz±2Hz的干扰噪声，因此需要展宽陷波器半高宽。在这种情况下，陷波电路可以包括级联陷波电路。
图3B是根据本申请一些实施例所示的多种级联陷波电路的频响曲线图。如图3B所示，曲线l1表示双T有源型陷波电路的频响曲线。曲线l2表示错位双陷波电路的频响曲线。曲线l3表示同位双陷波电路的频响曲线。曲线l4表示双同双错位陷波电路的频响曲线。在本申请中，错位双陷波电路可以指两个双T有源型陷波电路串联连接，其中一个双T有源型陷波电路的陷波点频率可以设置为第一频率(例如，48.5Hz)，另一个双T有源型陷波电路的陷波点频率可以设置为与第一频率不同的第二频率(例如，50Hz)。在一些实施例中，第一频率和第二频率可以位于特定频率附近，且两者的频率差值可以在4Hz，3Hz，2Hz，或1Hz以内。同位双陷波电路可以指两个陷波点频率均在特定频率点(例如50Hz)的有源双T陷波器进行串联连接的电路。双同双错位陷波电路可以指将四个双T有源型陷波电路进行串联连接的电路，其陷波点频率可以分别设置为例如，48.5Hz、50Hz、 50Hz、51.5Hz。从图3B中可以看出，双同双错位陷波电路的频响(即，曲线l4)具有其独特的优势，例如，较深的陷波能力同时保证其半高宽可控且不影响非目标陷波区域信号。在实际的应用中，可以根据需要滤除的信号的频率值以及其强度分布，选择合适的级联陷波电路，例如，可以根据实际需求，自由级联任意级数的同位和/或错位陷波电路以达成目的。
在一些实施例中，当共模信号抑制电路312和/或陷波电路对初始信号进行处理后，可以发现第一处理信号还包括较多的工频谐波信号。例如，初始信号为当人体穿着肌电服做大幅度耸肩、高抬手等动作时采集的肌电信号，经共模信号抑制电路312和/或陷波电路处理后还含有工频谐波信号，尤其是工频奇次谐波信号。在本申请的一些实施例中，为了抑制工频谐波信号，陷波电路还可以包括多级联陷波电路。具体地，多级联陷波电路可以包括至少两个级联陷波子电路。至少两个级联陷波子电路可以串联连接。各个级联陷波子电路之间可以具有不同的陷波点频率。例如，各个级联陷波子电路的陷波点频率可以分别设置为50Hz、100Hz、150Hz、200Hz、250Hz等。需要指出的是，多级联陷波电路可以抑制工频信号及工频谐波信号，但是每个工频谐波信号都需要至少一级陷波电路。
在一些实施例中，为了节约成本，可以根据肌电信号的共性(即，目标频段为20Hz-140Hz的肌电信号即可满足分析需求)，在信号处理电路300中设置低通滤波电路314将较高频段的工频谐波信号直接滤除。在一些实施例中，信号处理电路300可以包括一个或以上低通滤波电路314。低通滤波电路314可以对高于其上限截止频率的信号进行衰减。在本申请中，低通滤波电路的上限截止频率可以指其增益相对于低频通带下降第一特殊强度值的位置所对应的频率。在一些实施例中，第一特征强度值可以大于或等于10dB，例如，可以为15dB、20dB、30dB、40dB等。在一些实施例中，上限截止频率可以在100Hz-1000Hz的频率范围之内。在一些实施例中，上限截止频率可以在100Hz-800Hz的频率范围之内。在一些实施例中，上限截止频率可以在100Hz-600Hz的频率范围之内。在一些实施例中，上限截止频率可以在100Hz-400Hz的频率范围之内。在一些实施例中，上限截止频率可以在120Hz-400Hz的频率范围之内。在一些实施例中，上限截止频率可以在140Hz-400Hz的频率范围之内。具体地，上限截止频率可以为900Hz、700Hz、500Hz、300Hz、250Hz、200Hz、150Hz、140Hz、130Hz、120Hz、110Hz等。在一些实施例中，当目标频段为20Hz-140Hz时，上限截止频率可以高于目标频段的高频点，例如，可以为140Hz、150Hz等。在一些实施例中，由于混叠噪音是其他噪声信号(例如，工频谐波信号和 白噪声)的混合，其主要位于高频段(例如，高于500Hz)，因此，低通滤波电路314的上限截止频率设置较低(例如，140Hz)时，低通滤波电路314在滤除高次工频谐波信号的同时还可以滤除混叠噪声。而由于白噪声的强度与信号带宽正相关，此时，白噪声也可以相对降低。
在一些实施例中，低通滤波电路314可以设置在信号处理电路300中的任意位置，在此处不做限定，只要其能对信号进行低通滤波即可。例如，低通滤波电路314可以设置在第一处理电路310中。具体地，低通滤波电路314可以设置在差分放大器的输入端。如图12C所示，在差分放大器U1的输入端可以设置由电阻R1与电容C1构成的低通滤波器和由电阻R2和电容C3构成的低通滤波器。又例如，低通滤波电路314还可以设置在第二处理电路320中。具体地，低通滤波电路314可以设置在第二处理电路320中的放大电路的输入端。如图12C所示，第二处理电路1220还可以包括含有低通滤波器的阻容低通滤波放大电路1224。在一些实施例中，低通滤波电路314可以包括一阶低通滤波电路、二阶低通滤波电路、高阶滤波电路(高于二阶的滤波电路，如三阶低通滤波电路)等，或其任意组合。更多关于低通滤波电路的描述可以参见本申请其他地方(例如，图4A-4C及其描述)。
在一些实施例中，为了充分利用资源，尽可能地少使用电子器件而更有效地抑制高频率信号(即，高于上限截止频率的信号)，低通滤波电路314可以包括设置为桥式电路结构的低通滤波器(也可以称为桥式低通滤波电路)。例如，如图12A中，只需要在差分放大器U1的两个输入端之间加入一个电容C2，则可以将低通滤波电路设计成桥式电路结构(虚线框1212中的电路)。需要知道的是，当初始信号中存在射频信号时，射频信号可以通过电容C2到达差分放大器U1的两个输入端，从而被其抑制，因此，桥式低通滤波电路还可以进一步抑制射频信号。此外，电阻R1、电阻R2和电容C2也可以构成一级低通滤波器，有助于使滤波器过渡带变窄。在一些实施例中，桥式低通滤波器设置在差分放大器的输入端时，桥式低通滤波器与差分放大器可以统称为桥式低通滤波放大电路。在一些实施例中，信号处理电路300也可以不包括桥式低通滤波电路。更多关于桥式低通滤波放大电路的描述可以参见本申请其他地方(例如，图5A-5C及其描述)。
运动伪迹噪声可以指由运动造成的噪声。不同对象(例如，胸大肌、肱二头肌等)的运动可以引起不同的MA。在一些实施例中，MA可以包括基线漂移、毛刺等。例 如，当运动造成采集信号的两端的角质层电势波动时，可能会引起基线漂移。通常情况下，MA的频率可以在较低频率范围之内，例如，0Hz-20Hz范围之内。MA的强度可以在0mV-40mV的范围之内。在本申请的一些实施例中，由于MA所处频段位于目标频段之外，可以通过构建高通滤波电路316对MA进行处理。在一些实施例中，由于基线漂移存在极限值，还可以通过降低信号处理电路300(例如，第二处理电路320)对目标信号的增益，和/或选用具有高精度ADC通道的控制芯片，和/或选择利用电阻来调整参考电位从而解决基线漂移的情况。例如，当目标信号传输至第二处理电路320时，第二处理电路320会对该目标信号进行放大处理，为解决基线漂移的问题，可以适当降低第二处理电路320对目标信号的放大倍数，使得放大后的信号不发生失真。又例如，当基线漂移使得信号接近饱和电压上限时，可以程控控制参考电位降低，反之，当基线漂移使得信号接近电压下限时，可以程控控制参考点位升高。在一些实施例中，MA的频率范围可以很宽，例如，可以在0-1000Hz范围之内存在毛刺。在这种情况下，可以借助于信号幅值和频率进行处理。
在一些实施例中，信号处理电路300可以包括一个或以上高通滤波电路316。高通滤波电路316可以对低于其下限截止频率的信号进行衰减。在本申请中，高通滤波电路的下限截止频率可以指其增益相对于高频通带下降第二特殊强度值的位置所对应的频率。在一些实施例中，第二特殊强度值可以大于或等于10dB，例如，可以为15dB、20dB、30dB、40dB等。在一些实施例中，第二特殊强度值与第一特殊强度值可以相同或不同。在一些实施例中，下限截止频率可以在5Hz-200Hz的频率范围之内。在一些实施例中，下限截止频率可以在7Hz-180Hz的频率范围之内。在一些实施例中，下限截止频率可以在10Hz-160Hz的频率范围之内。在一些实施例中，下限截止频率可以在10Hz-100Hz的频率范围之内。在一些实施例中，下限截止频率可以在10Hz-80Hz的频率范围之内。在一些实施例中，下限截止频率可以在10Hz-60Hz的频率范围之内。在一些实施例中，下限截止频率可以在10Hz-40Hz的频率范围之内。在一些实施例中，下限截止频率可以在10Hz-20Hz的频率范围之内。具体地，下限截止频率可以为190Hz、150Hz、100Hz、70Hz、50Hz、30Hz、20Hz、17Hz、15Hz、13Hz、12Hz、10Hz、5Hz等。
在一些实施例中，下限截止频率可以根据信号处理电路300中是否存在针对工频信号的陷波电路而不同。当存在陷波点为工频频率的陷波电路时，由于工频信号的干扰可以被陷波电路有效抑制，此时，高通滤波电路316的下限截止频率可以较不存在陷波电路时的 下限截止频率低。例如，当第一处理电路310包括陷波电路时，下限截止频率可以在10Hz-40Hz的频率范围之内。具体地，当第一处理电路310包括陷波电路时，下限截止频率可以为35Hz、30Hz、25Hz、20Hz、10Hz等。又例如，当第一处理电路310不包括陷波电路时，下限截止频率可以在10Hz-160Hz的频率范围之内。具体地，当第一处理电路310不包括陷波电路时，下限截止频率可以为80Hz、60Hz、50Hz、20Hz等。在一些实施例中，可以根据目标频段，设置高通滤波电路316的下限截止频率。例如，若目标频段为20Hz-140Hz，则下限截止频率可以设置为20Hz。若目标频段为5Hz-200Hz，则下限截止频率可以设置为5Hz。
在一些实施例中，高通滤波电路316可以设置在信号处理电路300中的任意位置，在此处不做限定，只要其能对信号进行高通滤波即可。例如，高通滤波电路316可以设置在第一处理电路310中。具体地，在如图10A所示的信号处理电路1000中，在第一处理电路1010中的差分放大器U1的输出端可以设置有高通滤波器1014。又例如，高通滤波电路316还可以设置在第二处理电路320中。具体地，在如图12A所示信号处理电路1200A中，在第二处理电路1220中可以设置有包括高通滤波器的阻容高通滤波器放大电路1222。在一些实施例中，高通滤波电路316可以包括一阶高通滤波电路、二阶高通滤波电路、三阶高通滤波电路等，或其任意组合。更多关于高通滤波电路的描述可以参见本申请其他地方(例如，图9A-9C及其描述)。
在一些实施例中，为了使信号处理电路300的频响通带更为平坦(即，带宽内的信号波动不超过某一数值例如，10dB、20dB等)，信号处理电路300还可以包括压控低通滤波电路。压控低通滤波电路可以包括压控峰(如图7B中曲线d2的峰712)。压控低通滤波电路可以用于在目标频率附近提供增益，并与低通滤波电路314相结合以补偿低通滤波电路314的衰减，以此来获得更为平坦的频响通带。在本说明书中，目标频率附近可以指距离在目标频段中的某一频率一定范围(例如，10Hz、20Hz等)以内。在一些实施例中，通过设置压控低通滤波电路的参数和/或其压控峰的参数，还可以使得频响通带在特定频率点具有较高峰值(即，在特定频率位置提供较大增益)。例如，可以通过调节压控低通滤波电路中的电阻、电容参数来调节压控低通滤波电路的截止频率和/或调节其压控峰的高度、宽度、位置等，使得信号处理电路300的频响通带在例如，80Hz具有最高强度。在一些实施例中，压控低通滤波电路的下降速度可以大于20dB/十倍频。在一些实施例中，压控低通滤 波电路的下降速度可以大于30dB/十倍频。在一些实施例中，压控低通滤波电路的下降速度可以大于40dB/十倍频。在一些实施例中，压控低通滤波电路的下降速度可以大于60dB/十倍频。在一些实施例中，压控低通滤波电路的下降速度可以大于80dB/十倍频。具体地，压控低通滤波电路的下降速度可以为25dB/十倍频、35dB/十倍频、45dB/十倍频、55dB/十倍频、65dB/十倍频、75dB/十倍频等。
在一些实施例中，压控低通滤波电路可以设置在信号处理电路300中的任意位置，在此处不做限定，只要其能对信号进行调控即可。例如，压控低通滤波电路可以设置在第一处理电路310中。具体地，在如图12C所示的信号处理电路1200C中，压控低通滤波电路1226可以设置在第一处理电路1210中的陷波电路1214之后。又例如，压控低通滤波电路还可以设置在第二处理电路320中。具体地，在如图12A所示的信号处理电路1200A中，压控低通滤波电路1226可以设置在第二处理电路1220中的跟随器1229之前。更多关于压控低通滤波电路的描述可以参见本申请其他地方(例如，图7A-7B及其描述)。
第二处理电路320可以用于对第一处理信号进行放大处理。第二处理电路320可以包括放大电路(例如，放大器)。在一些实施例中，可以将放大电路中反馈网络的电阻替换为电阻与电容并联连接，从而构成的电路可以称为阻容放大电路，其反馈网络可以称为阻容反馈网络。例如，在如图6A所示，由放大器U2B与其反馈网络中电阻R12和电容C7可以组成的阻容放大电路，并联的电阻R12和电容C7可以称为阻容反馈网络。需要知道的是，由于电容的阻抗随交流信号频率变化而变化，因此，阻容放大电路的增益也可以随信号的频率变化而变化。因此，第二处理电路320对第一处理信号的增益倍数可以随第一处理信号的频率变化而变化。具体地，以图6A中放大器U2B的反馈网络620(也可以称为阻容反馈网络)为例，由于放大器U2B的反馈网络620上存在电容C7。根据电容的阻抗随交流信号频率变化的性质，信号频率的越大，从电容C7分路直接流至放大器U2B的输出端的电流信号越多。当信号频率足够大时，电阻R12的作用会被削弱，此时，电流信号主要从电容C7分路直接流至放大器U2B的输出端，最终导致电路增益衰减甚至没有增益。换句话说，相对于高频信号，低频信号更易通过放大器U2B被放大。最终表现出阻容放大电路具有低通滤波电路的效果。因此，在本申请中可以通过在放大电路中构建阻容反馈网络，利用尽可能少的放大器达到更好的高频低频抑制效果，降低了电路的制作成本。在一些实施例中，阻容放大电路也可以称为阻容低通滤波电路。更多关于阻容低通滤波电路的描述可以参见本申 请其他地方(例如，图6A-6B及其描述)。在一些实施例中，当阻容放大电路连接高通滤波电路或低通滤波电路时，其组合电路也可以称为阻容高通滤波电路或阻容低通滤波电路。
在一些实施例中，可以通过调节放大电路中反馈网络的电阻和电容的值来调节放大电路(或第二处理电路320)的对目标频段信号的增益。在一些实施例中，第二处理电路320可以对第一频率范围内的信号具有较大增益，而对第一频率范围之外的信号具有较小增益。换句话说，第二处理电路320对第一处理信号的处理可以实现带通的效果。例如，第二处理电路320可以对目标频段(例如，20Hz-140Hz)内的信号具有100倍以上的增益，而对于目标频段之外的信号具有100倍以下的增益，其中，越远离目标频段，其对应的增益越小。
在一些实施例中，第二处理电路320可以用于对所述第一处理信号进行第二放大倍数的放大处理。在一些实施例中，第二处理电路320的第二放大倍数也可以指第二处理电路320中各个放大器对信号进行放大处理的总放大倍数。在一些实施例中，第二放大倍数可以为15倍、20倍、50倍、100倍、200倍、300倍、500倍等。在一些实施例中，为了使特定频段(例如，带通频段)的信号具有更大的增益，放大电路可以包括多级放大电路。在一些实施例中，第二放大倍数可以与第一处理信号中的噪声信号、数字电路的ADC精度等相关。例如，当第一处理信号中存在基线漂移时，可以适当减小第二放大倍数和/或选用更高精度ADC的控制电路，以控制基线漂移不超过信号处理电路300的输出能力，从而不发生失真的情况。
需要说明的是，由于第一处理电路310中包括一个或多个放大器(例如，差分放大器)，第一处理电路310的第一放大倍数可以指第一处理电路310中各个放大器对信号进行放大处理的总放大倍数。在一些实施例中，为了对初始信号中的噪声信号进行优先处理，可以将第一处理电路310的第一放大倍数设置为小于20倍。例如，第一放大倍数可以为20倍、15倍、10倍、9倍、7倍、5倍等。在一些实施例中，第二处理电路320的第二放大倍数可以大于、小于或等于第一处理电路310的第一放大倍数。例如，第一放大倍数可以为20倍，第二放大倍数可以为200倍。又例如，第一放大倍数可以为20倍，第二放大倍数可以为15倍。再例如，第一放大倍数和第二放大倍数都可以为20倍。
在一些实施例中，根据信号处理电路300(例如，第二处理电路320)对信号的增益随频率变化的特性，为了尽可能地抑制工频信号，可以将信号处理电路300的频响峰设置 在尽可能远离工频信号的频率50Hz的位置。例如，可以将信号处理电路300的频响峰设置为80Hz、90Hz、100Hz、110Hz、120Hz等。因为在这种情况下，即使信号处理电路300的频响峰在例如120Hz，信号处理电路300可以对120Hz的信号具有最大增益，而对远离120Hz的信号增益较小，相当于对工频信号进一步进行抑制。而此时，信号处理电路300的增益在80Hz-100Hz依然很强，满足对肌电信号的分析要求。总的来说，可以通过调整信号处理电路300的频响增益的峰值位置，使其远离待抑制噪声频率，从而达到对噪声的衰减目标。例如，为了减轻工频谐波信号中的三次谐波的影响，可以将信号处理电路300的频响峰设置为远离150Hz(例如，80Hz)。
在一些实施例中，第二处理电路320还可以包括跟随器。跟随器可以用于隔绝所述信号处理电路300输出端与后端电路的相互影响。
在一些实施例中，信号处理电路300还可以包括负反馈电路。负反馈电路可以用于调节所述放大电路的第二放大倍数。在一些实施例中，信号处理电路300还可以包括反馈电路。反馈电路可以用于改善或控制信号处理电路300的性能指标，例如，抑制干扰和噪声等。更多关于信号处理电路的描述可以参见本申请其他地方(例如，图10、图11、图12A和图12C及其描述)。
应当注意的是，上述有信号处理电路300的描述仅仅是为了示例和说明，而不限定本申请的适用范围。对于本领域技术人员来说，在本申请的指导下可以对信号处理电路300进行各种修正和改变。然而，这些修正和改变仍在本申请的范围之内。例如，经信号处理电路300处理后的信号还可以利用降噪算法进行处理。在一些实施例中，算法降噪处理可以包括滤波算法、谱减算法、自适应算法、最小均方误差估计算法等，或其任意组合。
图4A、图4B和图4C是根据本申请的一些实施例所示的示例性低通滤波电路的结构示意图。图4D是图4A、图4B和图4C中的低通滤波电路的频响曲线图。
如图4A所示，低通滤波电路400A可以包括由电阻R9和电容C1构成的第一低通滤波器和放大器U2B。第一低通滤波器可以与放大器U2B的输入端相连。在一些实施例中，低通滤波电路400A也可以称为一阶有源低通滤波电路。
如图4B所示，相对于低通滤波电路400A，低通滤波电路400B还可以包括由电阻R1和电容C2构成的第二低通滤波器。第一低通滤波器可以与第二低通滤波器直接相 连。在一些实施例中，如低通滤波电路400B所示的通过两级低通滤波器直接相连而构成的二阶低通滤波电路也可以称为二阶级联低通滤波电路。
如图4C所示，相对于低通滤波电路400A，低通滤波电路400C还可以包括由电阻R3和电容C2构成的第三低通滤波器、放大器U1B、电阻R1和电阻R2。第三低通滤波器可以与放大器U2B的输出端以及放大器U1B的输入端相连。在一些实施例中，如低通滤波电路400C所示的通过两个一阶有源低通滤波电路直接相连而构成的二阶低通滤波电路也可以称为二阶分布式低通滤波电路。
如图4D所示，a1表示一阶有源低通滤波电路(即，低通滤波电路400A)的频响曲线。曲线a2表示二阶级联低通滤波电路(即，低通滤波电路400B)的频响曲线。曲线a3表示二阶分布式低通滤波电路(即，低通滤波电路400C)的频响曲线。从图4D可以看出，不同结构的低通滤波电路可以具有不通的频率响应。一阶有源低通滤波电路400A(对应曲线a1)可以达到15dB/十倍频的衰减速度(100Hz到1kHz)，二阶级联低通滤波电路400B(对应曲线a2)可以达到30dB/十倍频的衰减速度(100Hz到1KHz)，二阶分布式低通滤波电路400C(对应曲线a3)可以达到34dB/十倍频的衰减速度(100Hz到1KHz)。
在一些实施例中，当1KHz处达到了相同的抑制效果时，为了保留更多的低频信号(例如，120Hz内的信号)，可以优选高阶(例如，二阶)滤波电路。需要注意的是，二阶级联低通滤波电路和二阶分布式低通滤波电路之间存在区别的原因，可以理解为二阶级联低通滤波电路的第二级对第一级产生了影响。当电流流过第一级的电阻后，在下个节点看来，是第一级中的电容与第二级电路的并联，实际上是增加了总电容值，导致二阶级联低通滤波电路频响截止点变小，滤除了更多的低频信号。
图5A和图5B是根据本申请的一些实施例所示的低通滤波电路的结构示意图。图5C是图5A和图5B中的低通滤波电路的频响曲线图。
如图5A和图5B所示，低通滤波电路500A和低通滤波电路500B均可以包括两个低通滤波器(例如，由电阻R1和电容C8构成的低通滤波器、由电阻R2和电容C12构成的低通滤波器)和差分放大器U1。低通滤波电路500A和低通滤波电路500B的不同之处在于低通滤波电路500B中的差分放大器U1的输入端通过加入电容C11(虚线圆圈部分)而组成桥式电路结构(电阻R1和电容C8之间为第一节点，电阻R2和电容C12之间为第 二节点，电容C11的两端分别连到第一节点和第二节点)。在一些实施例中，低通滤波电路500A也可以称为一阶有源低通滤波电路。低通滤波电路500B也可以称为桥式低通滤波电路。需要知道的是，当其输入端信号中存在射频信号时，射频信号可以通过电容C11到达差分放大器U1的两个输入端，从而被差分放大器U1的共模抑制能力抑制，因此，桥式低通滤波电路还可以进一步抑制射频信号。此外，电阻R1、电阻R2和电容C11也可以构成一级低通滤波器，有助于使滤波器过渡带变窄。
如图5C所示，曲线b1表示一阶有源低通滤波电路(即，低通滤波电路500A)的频响曲线。曲线b2表示桥式低通滤波电路(即，低通滤波电路500B)的频响曲线。从图5C可以看出，通过在差分放大器U1的输入端增加一个电容C11构建桥式电路结构，可以增强低通滤波电路对高频的抑制作用。例如，在1KHz处，低通滤波电路500A的频响强度比低通滤波电路500B的频响强度强6dB。需要理解的是，桥式电路结构的原理可以理解为，通过额外的电容(即，电容C11)可以使得某些频率的交流信号从一条输入通道穿过该电容到达另一个输入通道，最后到达差分放大器U1，被共模抑制后达到衰减的效果，调节该电容的大小可以控制能穿过这个电容的交流信号的频率。
图6A是根据本申请的一些实施例所示的阻容低通滤波电路的结构示意图。图6B是二阶分布式低通滤波电路和图6A中的阻容低通滤波电路的频响曲线图。
如图6A所示，阻容低通滤波电路600可以包括二阶分布式阻容低通滤波电路，其与二阶分布式低通滤波电路(例如，二阶分布式低通滤波电路400C)的区别在于：将二阶分布式低通滤波电路中低通滤波器中的电容移除；此外，还将二阶分布式低通滤波电路中反馈网络中的电阻替换为电阻和电容的并联，即构建阻容反馈网络。例如，在如图6A中，若在电阻R4之后接入一个与参考电位/地相接的电容且在U2A的输出端串联一个电阻，并接入一个与参考电位/地相接的电容，并将阻容反馈网络610和620中的电容移除，得到的电路则为二阶分布式低通滤波电路。在一些实施例中，二阶分布式阻容低通滤波电路也可以称为二阶分布式阻容放大电路。
需要知道的是，由于电容的阻抗随交流信号频率变化而变化，因此，二阶分布式阻容低通滤波电路的增益也可以随信号的频率变化而变化。具体地，以图6A中放大器U2B的阻容反馈网络620为例，由于放大器U2B的阻容反馈网络620上存在电容C7。根据电容的阻抗随交流信号频率变化的性质，随着信号频率的增大，从电容C7分路直接流至放大器 U2B的输出端的电流信号逐渐增多。当信号频率足够大时，电阻R12的作用会被削弱，此时，电流信号主要从电容C7分路直接流至放大器U2B的输出端，最终导致电路增益衰减甚至没有增益。因此，可以通过调节电阻R12和电容C7的值来调节放大器U2B的对目标频段信号的增益。同理可知，可以调节设置电阻R7和电容C3的值来调节放大器U2A的对目标频段信号的增益。
如图6B所示，曲线c1表示二阶分布式低通滤波电路(例如，低通滤波电路400C)的频响曲线。曲线c2表示二阶分布式阻容低通滤波电路(即，低通滤波电路600)的频响曲线。从图6B中可以看出，二阶分布式阻容低通滤波电路(对应曲线c2)与二阶分布式低通滤波电路(对应曲线c1)具有变化趋势一致的频响。二阶分布式阻容低通滤波电路与二阶分布式低通滤波电路是可以兼容的。在一些实施例中，为了不额外增加放大器个数，且对高频有强的抑制能力，优选地可以选择二阶分布式阻容低通滤波电路。
图7A是根据本申请的一些实施例所示的压控低通滤波电路的结构示意图。图7B是二阶低通滤波电路和图7A中的压控低通滤波电路的频响曲线图。
如图7A所示，压控低通滤波电路700可以具有与二阶级联低通滤波电路400B相似的结构。二者区别在于在压控低通滤波电路700中，其第一级低通滤波器的电容(即，电容C14)与放大器的输出端直接连接，形成一个输出电压的反馈循环。在一些实施例中，压控低通滤波电路700也可以称为压控电压源二阶低通滤波电路。
通过设计压控低通滤波电路700，可以使得某个频率的响应达到较大的值，从而使得压控低通滤波电路700的频响曲线可以包括一个凸峰。如图7B所示，曲线d1表示二阶级联低通滤波电路的频响曲线。曲线d2表示的压控电压源二阶低通滤波电路(即，压控低通滤波电路700)的频响曲线。
这是因为频率过低时候，图7A中电容C13和C14相当于开路，电容C14没有起反馈的作用。当频率逐渐提高可以使得电容C14的反馈作用逐渐生效。但是当频率特别高时，电容C13会把输入端信号和反馈信号都大量导入虚拟地，使得输出降低。因此，可以控制不同的电容C13和C14的值，来设计反馈以及留住较高频率信号。在一些实施例中，电容C13和C14的具体的值的定量计算依赖于传递函数。
设置图7A中R17＝R18＝R，C13＝C14＝C，输入端信号为Ui，输出信号为Uo，开环增益(即低频增益)为Aop(s)＝1+R16/R10，实际增益为A(s)＝Uo/Ui。需要知道的是，这里只是用了相同值的电容C13和C14，事实上可以使用不同的值来提供更多的设计空间。
A点的电流方程如方程(1)所示：
Figure PCTCN2021102851-appb-000001
B点的电流方程如方程(2)所示：
Figure PCTCN2021102851-appb-000002
此外，放大器U2C的负输入端有如方程(3)所示的关系：
Figure PCTCN2021102851-appb-000003
联立以上三式可得传递函数如公式(4)所示：
Figure PCTCN2021102851-appb-000004
其中，以上式子中s＝jw。设定f0＝1/(2πRC)。因此，增益A或者开环增益Aop都是关于s的式子，尽管电路图7A中的Aop(s)是一个电阻的比值，但可以通过使用电容而设计出跨阻带通，从而可以对电路进行进一步频响设计。
因为w＝2πf，当f＝f0，则s＝j/RC，当f＝f0时，增益可以如式(5)所示：
Figure PCTCN2021102851-appb-000005
增益大小与Aop(s)直接相关。例如，当开环增益Aop(s)＝2.9，那么f＝f0时，增益A＝29。当开环增益Aop(s)<2时，增益A会小于开环增益，得不到凸型频响曲线。在本申请的一些实施例中，可以设计f0＝100Hz，开环增益Aop(s)＝2.9，实现了f0处比开环增益(低频增益)大20dB的效果。在100Hz和1KHz之间达到60dB/十倍频的效果。
图8A是根据本申请的一些实施例所示的示例性低通滤波电路的结构示意图。图8B是图8A中的低通滤波电路的频响曲线图。
如图8A所示，低通滤波电路800可以包括压控低通滤波电路810、桥式低通滤波电路820和四阶低通滤波电路830。在一些实施例中，低通滤波电路800也可以称为门限式 低通滤波电路。在一些实施例中，四阶低通滤波电路830可以通过两级放大器(例如，放大器U2A和U2B)实现。具体地，四阶低通滤波电路830可以由二阶分布式低通滤波电路和二阶阻容低通滤波电路实现。
如图8B所示，曲线e1表示压控低通滤波电路810的频响曲线。曲线e2表示桥式低通滤波电路820与四阶低通滤波电路830进行串联连接的电路的频响曲线。曲线e3表示低通滤波电路800的频响曲线。在一些实施例中，通过对压控低通滤波电路810的增益和频响峰进行调节，可以得到如曲线e1的曲线，其可以包含有频响峰812。将曲线e1对应的电路(即，压控低通滤波电路810)和曲线e2对应的电路(即，桥式低通滤波电路820与四阶低通滤波电路830的串联电路)相结合，则可以得到充分保留低频信号的门限式低通滤波电路(对应曲线e3)。从图8B中可以看出，桥式低通滤波电路820与四阶低通滤波电路830进行串联连接的电路(对应曲线e2)在200Hz处相对于100Hz的抑制能力为20dB，而门限式低通滤波电路800(对应曲线e3)在200Hz处相对于100Hz的抑制能力约为50dB，相当于抑制能力提升了31.6倍。
图9A-9B是根据本申请的一些实施例所示的示例性高通滤波电路的结构示意图。图9C是图9A-9B中的高通滤波电路的频响曲线图。
如图9A所示，高通滤波电路900A可以包括由电阻R4和电容C1构成的高通滤波器910和放大器U2B。第一高通滤波器910可以与放大器U2A的输入端相连。在一些实施例中，第一高通滤波器910可以位于信号通路上。在一些实施例中，包含一个高通滤波器且其位于信号通路上的高通滤波电路900A也可以称为一阶主路高通滤波电路。
如图9B所示，高通滤波电路900B的结构可以与高通滤波电路900A相似。两者的区别在于，高通滤波电路900B中的高通滤波器920未位于信号通路上。在一些实施例中，包含一个高通滤波器且其未位于信号通路上的高通滤波电路900B也可以称为一阶旁路高通滤波电路。
需要知道的是，类似于低通滤波电路，本说明书中的高通滤波电路还可以包括二阶、三阶高通滤波电路或更高阶的高通滤波电路，例如，二阶级联主路高通滤波电路或二阶分布式旁路高通滤波电路。在一些实施例中，高阶高通滤波电路可以包括至少一个一阶主路高通滤波电路或至少一个旁路高通滤波电路。在一些实施例中，包括至少一个一阶主路高通滤波电路和至少一个旁路高通滤波电路也可以称为高阶混合高通滤波电路。
如图9C所示，曲线f1表示第一二阶分布式主路高通滤波电路的频响曲线。曲线f2表示第一二阶分布式旁路高通滤波电路的频响曲线。曲线f3表示第二二阶分布式旁路高通滤波电路的频响曲线，其中，第二二阶分布式旁路高通滤波电路的参数与第一二阶分布式旁路高通滤波电路的参数不同。曲线f4表示二阶分布式混合高通滤波电路的频响曲线。曲线f5表示第二二阶分布式主路高通滤波电路的频响曲线，其中，第二二阶分布式主路高通滤波电路的参数与第一二阶分布式主路高通滤波电路的参数不同。从图9C可以看出，不同结构和/或参数的高通滤波电路可以具有不通的频率响应。第一二阶分布式主路高通滤波电路(对应曲线f1)对极低频信号(例如，1Hz内的信号)的抑制作用很强，但其对低频信号(例如，高于1Hz的信号)的抑制作用有限。第一二阶分布式旁路高通滤波电路(对应曲线f2)和第二二阶分布式旁路高通滤波电路(对应曲线f3)对低频信号的抑制作用有限。二阶分布式混合高通滤波电路(对应曲线f4)对极低频信号具有极大抑制。例如，二阶分布式混合高通滤波电路对1Hz内信号的抑制强于第一二阶分布式旁路高通滤波电路(对应曲线f2)和第二二阶分布式旁路高通滤波电路(对应曲线f3)。此外，二阶分布式混合高通滤波电路(对应曲线f4)对5Hz内信号也具有较大抑制能力(强于第一二阶分布式主路高通滤波电路(对应曲线f1)和第二二阶分布式主路高通滤波电路(对应曲线f5))。
应当注意的是，上述对各个电路的描述仅仅是为了示例和说明，而不限定本申请的适用范围。对于本领域技术人员来说，在本申请的指导下可以对电路进行各种修正和改变。然而，这些修正和改变仍在本申请的范围之内。在一些实施例中，由于各个示例性电路中还包括有放大器，因此，上述各个示例性电路除对信号进行对应处理外，还可以对信号进行放大处理。例如，低通滤波电路400A除了对信号进行低通滤波处理外，还可以对滤波后的信号进行放大。因此，低通滤波电路400A也可以称为低通滤波放大电路。此外，若低通滤波放大电路中的放大器包括阻容反馈网络，则该低通滤波放大电路又可称为阻容低通滤波放大电路。同理，例如，高通滤波电路900A除了对信号进行高通滤波外，还可以对滤波后的信号进行放大。因此，高通滤波电路900A也可以称为低通滤波放大电路。此外，若高通滤波放大电路中的放大器包括阻容反馈网络，则该高通滤波放大电路又可称为阻容低高滤波放大电路。在一些实施例中，各个放大器对信号的放大倍数可以相同或不同。例如，放大器对信号的放大倍数可以为2倍、4倍、10倍、20倍、100倍、300倍、500倍、1000倍等。
图10A是根据本申请的一些实施例所示的示例性信号处理电路的电路架构示意图。图10B是图10A中信号处理电路的频响曲线。如图10A所示，信号处理电路1000可以包括第一处理电路1010和第二处理电路1020。第二处理电路1020可以与第一处理电路1010直接相连。
第一处理电路1010可以包括桥式低通滤波电路1012、差分放大器U1和高通滤波器1014。在一些实施例中，桥式低通滤波电路1012可以连接在差分放大器U1的输入端。高通滤波器1014可以连接在差分放大器U1的输出端。
第一处理电路1010可以对初始信号(例如，电极采集的初始信号)中的噪声信号进行衰减并对初始信号中的目标信号进行放大，输出第一处理信号。具体地，桥式低通滤波电路1012可以对初始信号进行低通滤波处理。例如，桥式低通滤波电路1012的上限截止频率可以在100Hz-1000Hz频率范围内。又例如，桥式低通滤波电路1012的上限截止频率可以为140Hz。经桥式低通滤波电路1012处理的信号可以进一步由差分放大器U1进行处理。例如，差分放大器U1可以抑制经滤波处理的信号中的共模信号(例如，工频信号)。又例如，差分放大器U1可以对经滤波处理的信号进行放大处理。在一些实施例中，差分放大器U1对信号的放大倍数可以不大于10倍。在一些实施例中，差分放大器U1对信号的放大倍数可以不大于7倍。在一些实施例中，差分放大器U1对信号的放大倍数可以不大于5倍。在一些实施例中，差分放大器U1对信号的放大倍数可以不大于4倍。在一些实施例中，差分放大器U1对信号的放大倍数可以不大于3倍。在一些实施例中，差分放大器U1对信号的放大倍数可以不大于2倍。在如图10A的信号处理电路中，由于第一处理电路1010只包含一个放大器(即，差分放大器U1)，因此，差分放大器U1的放大倍数称为第一处理电路1010的第一放大倍数。
高通滤波器1014可以对差分放大器U1处理后的信号进行高通滤波处理。例如，高通滤波器1014的下限截止频率可以在5Hz-200Hz频率范围内。又例如，高通滤波器1014的上限截止频率可以为20Hz。在图10A中，经高通滤波器1014处理的信号则为第一处理信号。
第二处理电路1020可以用于对第一处理信号进行放大处理。在一些实施例中，第二处理电路1020可以包括放大电路1022、负反馈电路1024和跟随器1026。在一些实施例中，放大电路1022中可以包括阻容反馈网络(如图6A中由电阻R7和电容C3构成)(即 放大电路1022也可以称为阻容放大电路)，第二处理电路1020对所述第一处理信号的增益倍数可以随第一处理信号的频率变化而变化。第二处理电路1020可以对第一处理信号进行第二倍数的放大处理。在一些实施例中，第二处理电路1020包括多个放大器，第二放大倍数可以是多个放大器的总放大倍数。在一些实施例中，第二放大倍数可以大于第一放大倍数。例如，第二放大倍数可以大于30倍、50倍、100倍、200倍、500倍等。负反馈电路1024可以用于利用滑动变阻器R5实现大范围的增益(即，放大倍数)可调。例如，可以实现增益从0-A的增益变化，其中，A为放大器1022的增益。在一些实施例中，滑动变阻器R5也可以称为分压电阻器。跟随器1026可以用于隔绝输出端对信号处理电路1000的影响。
如图10B所示，当信号处理电路1000的总增益较高时，信号处理电路1000在处理200Hz-400Hz范围内的信号时易达到饱和，且信号处理电路1000对高频信号的抑制不足。在一些实施例中，可以通过调节放大电路1022中阻容反馈网络中电阻值和电容值来优化信号处理电路1000的频响(即，带通效果)。例如，可以将阻容反馈网络中的电阻扩大2倍和将电容的值缩小2倍。在一些实施例中，为了优化信号处理电路1000中的高通滤波器1014的频率响应，可以非比例调节高通滤波器1014中的电阻和电容的值，扩大电容的影响(例如，只增大电容的值)，但此时，也会同时增益了非目标频段的信号。
在一些实施例中，由于提高电路的阶数可以提高电路的频响陡度(即，只大增益目标频段的信号，而抑制非目标频段的信号)，因此，为了提高信号处理电路1000的频响陡度，可以在信号处理电路1000的基础上设计更高阶数的信号处理电路。具体描述可以参见图11及其描述，此处不再赘述。
图11是根据本申请的一些实施例所示的示例性信号处理电路的电路架构示意图。如图11所示，信号处理电路1100可以包括与信号处理电路1000相同的第一处理电路1010。信号处理电路1100还可以包括第二处理电路1120。
第二处理电路1120可以包括放大电路1122、阻容高通滤波放大电路1124、负反馈电路1126和跟随器1128。在电路架构上，信号处理电路1100中的第二处理电路1120相比于信号处理电路1000中的第二处理电路1020可以进一步包括阻容高通滤波放大电路1124，其可以高通滤波器，从而对信号起到高通滤波的作用。阻容高通滤波放大电路1124中还可以包括由电容和电阻并联设置于放大器的输入端和输出端之间的阻容反馈网络。在一 些实施例中，信号处理电路1100也可以称为二阶滤波肌电处理电路。进一步地，相比第二处理电路1020，在第二处理电路1120中，第二处理电路1020中的滑动变阻器R5替换为电阻R5和R6。
在一些实施例中，为了优化频率响应(例如，对1Hz、50Hz的抑制更强，且保持频响峰在500Hz内，增益400-600倍)，可以调节放大电路1122的参数来改变第二处理电路1120对信号的增益。例如，可以将电阻R7和电容C8同比例减小。
图12A是根据本申请的一些实施例所示的示例性信号处理电路的电路架构示意图。图12B是图12A中信号处理电路的频响峰为80Hz时的频响曲线。
如图12A所示，信号处理电路1200可以包括第一处理电路1210和第二处理电路1220。第二处理电路1220可以与第一处理电路1210直接相连。
在一些实施例中，第一处理电路1210可以包括桥式低通滤波电路1212、差分放大器U1和陷波电路1214。桥式低通滤波电路1212和差分放大器U1可以与信号处理电路1000中的桥式低通滤波电路1012和差分放大器U1结构相同。陷波电路1214可以包括双T有源型陷波电路。在一些实施例中，陷波电路1214的陷波点频率可以设置为工频信号的频率(例如，50Hz)。在一些实施例中，陷波电路1214还可以包括级联陷波电路。进一步地，陷波电路1214可以包括多级联陷波电路。多级联陷波电路中的各级联陷波电路的陷波点频率可以分别设置为50Hz、100Hz、150Hz、250Hz等。
第二处理电路1220可以包括阻容高通滤波放大电路1222、阻容低通滤波放大电路1224、压控低通滤波电路1226、负反馈电路1128和跟随器1229。阻容高通滤波放大电路1222、阻容低通滤波放大电路1224、压控低通滤波电路1226、跟随器1229可以依次串联连接。阻容高通滤波放大电路1222可以对信号进行高通滤波和放大处理。阻容低通滤波放大电路1224可以对信号进行低通滤波和放大处理。阻容高通滤波放大电路1222中放大器和阻容低通滤波放大电路1224中放大器对信号的放大能力可以相同或不同。在一些实施例中，放大器对信号的放大倍数可以大于10倍。在一些实施例中，放大器对信号的放大倍数可以大于30倍。在一些实施例中，放大器对信号的放大倍数可以大于100倍。在一些实施例中，放大器对信号的放大倍数可以大于500倍。压控低通滤波电路1226可以与桥式低通滤波遍历1212和/或阻容低通滤波放大电路1224相结合以补偿桥式低通滤波遍历1212和/或阻容低通滤波放大电路1224的在其上限截止频率附近的衰减，使通带更平坦。在第二处理 电路1220中，电阻R5和电阻R6也可以称为分压电阻。通过调节分压电阻的阻值可以调节信号处理电路1200A的频率响应。例如，可以增大分压电阻的阻值以防止信号饱和(尤其是噪声信号饱和)而造成的目标信号丢失。
如图12B所示，曲线g0表示传统的信号处理产品的频响曲线。曲线g1表示分压电阻为第一阻值时信号处理电路1200的频响曲线，曲线g2表示分压电阻为第二阻值时信号处理电路1200的频响曲线，其中，第二阻值大于第一阻值。从图12B中可以看出，由于针对工频信号(50Hz)的陷波电路1214的存在，曲线g1和曲线g2在50Hz处存在凹陷，即工频信号被极大抑制。当信号处理电路1200的频响峰设置为80Hz时，相对于传统信号处理产品，信号处理电路1200包含更少的噪声信号，且在高频范围内的信号被有效抑制。
在一些实施例中，本着对工频信号、工频谐波信号、MA等优先处理，再进行较大增益的原则，可以对信号处理电路1200A进行调整，如图12C所示。
图12C是根据本申请的一些实施例所示的示例性信号处理电路的电路架构示意图。图12D是图12C中信号处理电路的频响峰为80Hz时的频响曲线。如图12C所示，第二处理电路1220中的压控低通滤波电路1226可以连接在阻容高通滤波放大电路1222之前，而阻容低通滤波放大电路1224可以与负反馈电路1228直接连接。在一些实施例中，当压控低通滤波电路1226紧接着设置在陷波电路1214之后时，压控低通滤波电路1226也可以视为设置在第一处理电路中。
如图12D所示，曲线h1表示当分压电阻R5＝R6＝100Ω时，信号处理电路1200C的频响曲线。曲线h2表示当分压电阻R5＝R6＝1kΩ时，信号处理电路1200C的频响曲线。从图12D中可以看出，当分压电阻R5和R6的阻值升高时(例如，从100Ω升高至1kΩ时)，可以降低信号处理电路1200C的频响峰强度，此外，还可以使得信号处理电路1200C的频响峰向高频移动。
图13是根据本申请的一些实施例所示的不同时间测量得到的信号处理电路的频响曲线与仿真频响曲线的对比图。在一些实施例中，为了测试本申请实施例中的信号处理电路的稳定性，可以在采集肌电信号时将采集电路中的一个电极掀起一半(即，电极半脱落)或全部掀起(即，电极完全脱落)。
如图13所示，时间1曲线、时间2曲线是在不同时间、不同电极脱落条件下测得的。在获得时间1曲线的过程中，可将信号采集电极掀起一半，而在获得时间2曲线的过程 中，可以不将电极掀起。从图13中可以看出，利用同一信号处理电路，在不同时间(例如，时间1和时间2)、不同条件(电极半脱落与未脱落)下所测量得到的该信号处理电路的频响曲线一致性高，且与仿真信号之间的差异较小，没有信号饱和问题发生。因此，本申请实施例中的信号处理电路的稳定性强、准确性高，可以应对在测试过程中较大程度的电极脱落问题。
图14是根据本申请的一些实施例所示的利用信号处理电路进行二头弯举实验时采集的肌电信号。图14从上到下分别显示了对肱二头肌、斜方肌和胸大肌采集的信号数据。在进行二头弯举实验过程中，被试者的动作可以依次为两个正常的二头弯举动作、两个耸肩动作和两个夹胸动作。从图14可以看出，经信号处理电路处理的信号信噪比高(信噪比可达到500级别)，工频及其谐波被极大抑制，肌电信号成分变简单(主要包含目标频段的信号)。因此，本申请实施例中的信号处理电路可以顺利完成二头弯举运动中的肌电信号的高质量采集。
本申请实施例可能带来的有益效果包括但不限于：(1)通过采用分时复用的方法，在保证多路信号源采集和处理的情况下，可以达到节约空间成本，降低硬件要求的目的；(2)当多个输入通道同时具有信号时，可以减小各个输入通道之间的串扰；(3)完全重构型策略可以基于获得的采样数据完全复现对应的多路目标信号；(4)在强度表征型策略下可以基于获得的采样数据获取目标信号的强度信息和部分频率信息；(5)通过小增益高精度ADC、程控基线及添加高通滤波电路的方法解决可能出现的基线漂移的问题；(6)通过先处理工频信号及工频谐波信号等强度较大的噪声信号，再进行较大增益，可以防止信号过饱和而造成目标信号丢失；(7)通过将电路的频响峰设置在远离工频信号频率的位置，可以进一步抑制工频信号；(8)通过在反馈放大电路中的反馈网络中增加一个与电阻并联的电容，可以使反馈放大电路对信号的增益随频率变化而变化。
需要说明的是，不同实施例可能产生的有益效果不同，在不同的实施例里，可能产生的有益效果可以是以上任意一种或几种的组合，也可以是其他任何可能获得的有益效果。
上文已对基本概念做了描述，显然，对于本领域技术人员来说，上述发明披露仅仅作为示例，而并不构成对本申请的限定。虽然此处并没有明确说明，本领域技术人员可能 会对本申请进行各种修改、改进和修正。该类修改、改进和修正在本申请中被建议，所以该类修改、改进、修正仍属于本申请示范实施例的精神和范围。
同时，本申请使用了特定词语来描述本申请的实施例。如“一个实施例”、“一实施例”和/或“一些实施例”意指与本申请至少一个实施例相关的某一特征、结构或特点。因此，应强调并注意的是，本说明书中在不同位置两次或多次提及的“一实施例”或“一个实施例”或“一替代性实施例”并不一定是指同一实施例。此外，本申请的一个或多个实施例中的某些特征、结构或特点可以进行适当的组合。
此外，本领域技术人员可以理解，本申请的各方面可以通过若干具有可专利性的种类或情况进行说明和描述，包括任何新的和有用的工序、机器、产品或物质的组合或对他们的任何新的和有用的改进。相应地，本申请的各个方面可以完全由硬件执行、可以完全由软件(包括固件、常驻软件、微码等)执行、也可以由硬件和软件组合执行。以上硬件或软件均可被称为“数据块”、“模块”、“引擎”、“单元”、“组件”或“系统”。此外，本申请的各方面可能表现为位于一个或多个计算机可读介质中的计算机产品，该产品包括计算机可读程序编码。
此外，除非权利要求中明确说明，本申请处理元素和序列的顺序、数字字母的使用或其他名称的使用，并非用于限定本申请流程和方法的顺序。尽管上述披露中通过各种示例讨论了一些目前认为有用的发明实施例，但应当理解的是，该类细节仅起到说明的目的，附加的权利要求并不仅限于披露的实施例，相反，权利要求旨在覆盖所有符合本申请实施例实质和范围的修正和等价组合。例如，虽然以上所描述的系统组件可以通过硬件设备实现，但是也可以只通过软件的解决方案得以实现，如在现有的服务器或移动设备上安装所描述的系统。
同理，应当注意的是，为了简化本申请披露的表述，从而帮助对一个或多个发明实施例的理解，前文对本申请实施例的描述中，有时会将多种特征归并至一个实施例、附图或对其的描述中。但是，这种披露方法并不意味着本申请对象所需要的特征比权利要求中提及的特征多。实际上，实施例的特征要少于上述披露的单个实施例的全部特征。
一些实施例中使用了描述成分、属性数量的数字，应当理解的是，此类用于实施例描述的数字，在一些示例中使用了修饰词“大约”、“近似”或“大体上”来修饰。除非另外说明，“大约”、“近似”或“大体上”表明所述数字允许有±20％的变化。相应地，在一些实施例 中，说明书和权利要求中使用的数值参数均为近似值，该近似值根据个别实施例所需特点可以发生改变。在一些实施例中，数值参数应考虑规定的有效数位并采用一般位数保留的方法。尽管本申请一些实施例中用于确认其范围广度的数值域和参数为近似值，在具体实施例中，此类数值的设定在可行范围内尽可能精确。
针对本申请引用的每个专利、专利申请、专利申请公开物和其他材料，如文章、书籍、说明书、出版物、文档等，特此将其全部内容并入本申请作为参考。与本申请内容不一致或产生冲突的申请历史文件除外，对本申请权利要求最广范围有限制的文件(当前或之后附加于本申请中的)也除外。需要说明的是，如果本申请附属材料中的描述、定义、和/或术语的使用与本申请所述内容有不一致或冲突的地方，以本申请的描述、定义和/或术语的使用为准。
最后，应当理解的是，本申请中所述实施例仅用以说明本申请实施例的原则。其他的变形也可能属于本申请的范围。因此，作为示例而非限制，本申请实施例的替代配置可视为与本申请的教导一致。相应地，本申请的实施例不仅限于本申请明确介绍和描述的实施例。

Claims (18)

  1. 一种信号处理电路，包括模拟电路，所述模拟电路用于对其接收的初始信号进行处理，所述初始信号包括目标信号和噪声信号，其中，所述模拟电路包括：
    第一处理电路，用于提高所述目标信号与所述噪声信号之间的比值，输出第一处理信号；以及
    与所述第一处理电路相连接的第二处理电路，用于对所述第一处理信号进行放大处理，所述第二处理电路对所述第一处理信号的增益倍数随所述第一处理信号的频率变化而变化，其中：
    所述第一处理电路包括共模信号抑制电路、低通滤波电路和高通滤波电路，
    所述共模信号抑制电路用于抑制所述初始信号中的共模信号。
  2. 如权利要求1所述的信号处理电路，其中，所述共模信号抑制电路包括差分放大器。
  3. 如权利要求2所述的信号处理电路，其中，所述低通滤波电路包括在所述差分放大器的输入端形成的桥式电路结构。
  4. 如权利要求2所述的信号处理电路，其中，所述差分放大器的输入阻抗大于10MΩ。
  5. 如权利要求1所述的信号处理电路，其中，所述低通滤波电路的上限截止频率点在100Hz-1000Hz的频率范围之内。
  6. 如权利要求1所述的信号处理电路，其中，所述高通滤波电路的下限截止频率点在5Hz-200Hz的频率范围之内。
  7. 如权利要求1所述的信号处理电路，其中，所述第一处理电路包括陷波电路，所述陷波电路用于抑制工频信号。
  8. 如权利要求7所述的信号处理电路，其中，所述陷波电路包括级联陷波电路，所述级联陷波电路还用于抑制工频信号的谐波。
  9. 如权利要求7所述的信号处理电路，其中，所述陷波电路包括双T有源型陷波电路。
  10. 如权利要求1所述的信号处理电路，其中，所述第一处理电路还包括压控低通滤波电路，所述压控低通滤波电路用于在其目标频率附近提供增益，并与所述低通滤波电路相结合以补偿所述低通滤波电路的衰减。
  11. 如权利要求1所述的信号处理电路，其中，所述第一处理电路在提高所述目标信号与所述噪声信号之间的比值的过程中，包括：
    对所述目标信号进行第一放大倍数的放大处理；以及
    对所述噪声信号进行衰减处理。
  12. 如权利要求11所述的信号处理电路，其中，所述第二处理电路包括放大电路、反馈电路和跟随器，
    所述放大电路用于对所述第一处理信号进行第二放大倍数的放大处理，所述第二放大倍数大于所述第一放大倍数；以及
    所述跟随器用于隔绝所述信号处理电路输出端的影响。
  13. 如权利要求1所述的信号处理电路，其中，所述第二处理电路对所述第一处理信号在第一频率范围的增益响应大于在所述第一频率范围之外的增益响应。
  14. 如权利要求13所述的信号处理电路，其中，所述第一频率范围包括20Hz-140Hz。
  15. 如权利要求1所述的信号处理电路，其中，所述初始信号包括肌电信号。
  16. 如权利要求1所述的信号处理电路，还包括：控制电路、开关电路以及至少两个信号采集电路，其中，
    所述至少两个信号采集电路用于采集至少两路初始信号；
    所述开关电路用于控制所述至少两个信号采集电路与所述模拟电路的导通，使得在同一时间所述至少两个信号采集电路中仅有部分信号采集电路采集的初始信号传输至所述模拟电路；以及
    所述控制电路用于接收经模拟电路处理后的目标信号，并对所述经过处理的目标信号进行采样。
  17. 如权利要求16所述的信号处理电路，其中，所述开关电路包括多个输入通道，所述至少两个信号采集电路中每个信号采集电路单独连接一个输入通道，在同一时间，所述开关电路基于所述控制电路的控制信号选择一个输入通道导通。
  18. 一种信号处理装置，包括：如权利要求1～17中任一项所述的信号处理电路。
PCT/CN2021/102851 2020-12-31 2021-06-28 信号处理电路和装置 WO2022142205A1 (zh)

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