WO2022141013A1 - 一种采样组件和采样方法 - Google Patents

一种采样组件和采样方法 Download PDF

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Publication number
WO2022141013A1
WO2022141013A1 PCT/CN2020/140575 CN2020140575W WO2022141013A1 WO 2022141013 A1 WO2022141013 A1 WO 2022141013A1 CN 2020140575 W CN2020140575 W CN 2020140575W WO 2022141013 A1 WO2022141013 A1 WO 2022141013A1
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WIPO (PCT)
Prior art keywords
sampling
signal
unit
calibration
self
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PCT/CN2020/140575
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English (en)
French (fr)
Inventor
王海飞
庄艳
周万
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华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20967363.1A priority Critical patent/EP4246171A4/en
Priority to JP2023537478A priority patent/JP2024501516A/ja
Priority to PCT/CN2020/140575 priority patent/WO2022141013A1/zh
Priority to KR1020237023009A priority patent/KR20230116919A/ko
Priority to CN202080107148.9A priority patent/CN116547550A/zh
Publication of WO2022141013A1 publication Critical patent/WO2022141013A1/zh
Priority to US18/343,120 priority patent/US20230344437A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
    • H03M1/1057—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by trimming, i.e. by individually adjusting at least part of the quantisation value generators or stages to their nominal values
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/10—Current supply arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

Definitions

  • the present application relates to the field of communications, and more particularly, to a sampling assembly and a sampling method.
  • the present application provides a sampling component and a sampling method, which can compensate the deviation between the input signal and the output signal of the sampling circuit, and can improve the sampling accuracy.
  • the present application provides a sampling assembly, the sampling assembly includes: a self-calibration unit, a sampling unit, a first switch, and a second switch, wherein,
  • the self-calibration unit is configured to control the closing of the first switch so that the first sampling signal is input to the sampling unit;
  • the sampling unit is configured to process the first sampling signal to obtain a second sampling signal, and outputting the second sampling signal to the self-calibration unit;
  • the self-calibration unit is further configured to control the opening of the first switch and the closing of the second switch, and output a first calibration signal to the sampling unit;
  • the sampling unit is further configured to A calibration signal is processed to obtain a second calibration signal, and the second calibration signal is output to the self-calibration unit;
  • the self-calibration unit is further configured to, according to the first calibration signal and the second calibration signal, determine the error signal;
  • the self-calibration unit is further configured to obtain a calibrated third sampling signal according to the second sampling signal and the error signal.
  • the sampling assembly of the present application can obtain an error signal through the mutual cooperation of the self-calibration unit, the first switch, and the second switch, so that the deviation between the input signal and the output signal of the sampling assembly can be compensated, and the sampling accuracy can be improved .
  • the sampling unit includes an amplification unit and/or an analog-to-digital conversion unit.
  • analog-to-digital conversion can be performed directly without processing such as signal amplification. That is to say, the technical solution of the present application can compensate the error caused by the digital-to-analog conversion unit, which helps to improve the signal sampling accuracy.
  • the technical solution of the present application can compensate the error caused by the amplifying unit, and usually the signal amplification link is an important link that causes the error. Therefore, the technical solution of the present application can effectively improve the signal sampling accuracy.
  • the sampling unit includes an amplifying unit and an analog-to-digital conversion unit, so that the technical solution of the present application can compensate the error caused by the amplifying unit and the error caused by the analog-to-digital conversion unit, and can effectively improve the signal sampling accuracy.
  • the sampling unit when the sampling unit includes an amplifying unit and an analog-to-digital conversion unit, the sampling unit further includes a third switch, and the self-calibration unit is further configured to control the second switch to close when When , the third switch is controlled to be closed, so that the third calibration signal output by the amplifying unit is input to the self-calibration unit; the self-calibration unit is specifically configured to The calibration signal and the third calibration signal, determine the error signal.
  • the self-calibration unit includes a calibration unit and a control unit, the calibration unit is configured to obtain the error signal, the control unit is configured to receive the second sampling signal, and The third sampling signal is obtained from the error signal and the second sampling signal; or, the calibration unit is configured to obtain the third sampling signal and output the third sampling signal to the control unit.
  • control unit may include at least one of the following: state machine (state machine), digital signal processor (digital signal processor, DSP), advanced reduced instruction set computer (advanced reduced instruction set computing machines, ARM), linear power control device (linear power controller, LPC), and MC51 microcontroller.
  • the present application provides a sampling method, which is applied to a sampling assembly including a self-calibration unit, a sampling unit, a first switch, and a second switch, and the method includes:
  • the first switch is controlled to be closed by the self-calibration unit, so that the first sampling signal is input to the sampling unit; the first sampling signal is processed by the sampling unit to obtain a second sampling signal, which is sent to the sampling unit.
  • the self-calibration unit outputs the second sampling signal;
  • the self-calibration unit controls the opening of the first switch and the closing of the second switch, and outputs a first calibration signal to the sampling unit; the first calibration signal is obtained by processing the first calibration signal by the sampling unit. a second calibration signal, and output the second calibration signal to the self-calibration unit; determine an error signal by the self-calibration unit according to the first calibration signal and the second calibration signal;
  • a calibrated third sampling signal is obtained by the self-calibration unit according to the second sampling signal and the error signal.
  • the sampling method of the present application can obtain an error signal through the mutual cooperation of the self-calibration unit, the first switch, and the second switch, so that the deviation between the input signal and the output signal of the sampling component can be compensated, and the sampling accuracy can be improved.
  • the sampling unit includes an amplification unit and/or an analog-to-digital conversion unit.
  • analog-to-digital conversion can be performed directly without processing such as signal amplification. That is to say, the technical solution of the present application can compensate the error caused by the digital-to-analog conversion unit, which helps to improve the signal sampling accuracy.
  • the technical solution of the present application can compensate the error caused by the amplifying unit, and usually the signal amplification link is an important link that causes the error. Therefore, the technical solution of the present application can effectively improve the signal sampling accuracy.
  • the sampling unit includes an amplifying unit and an analog-to-digital conversion unit.
  • the technical solution of the present application can compensate for the error caused by the amplifying unit and the error caused by the analog-to-digital conversion unit, and can effectively improve the signal sampling accuracy.
  • the sampling unit when the sampling unit includes an amplifying unit and an analog-to-digital conversion unit, the sampling unit further includes a third switch, and the method further includes: when controlling the second switch to be closed, by The self-calibration unit controls the third switch to be closed, so that the third calibration signal output by the amplifying unit is input to the self-calibration unit; the determining according to the first calibration signal and the second calibration signal
  • the error signal includes: determining the error signal according to the first calibration signal, the second calibration signal and the third calibration signal.
  • the self-calibration unit includes a calibration unit and a control unit, and the self-calibration unit obtains a calibrated third sampled signal according to the second sampled signal and the error signal
  • the method includes: obtaining the error signal through the calibration unit; receiving the second sampling signal through the control unit, and obtaining the third sampling signal according to the error signal and the second sampling signal; or, through The calibration unit obtains the third sampling signal, and outputs the third sampling signal to the control unit.
  • the present application provides a chip including a processor and the sampling component as described in the first aspect or any possible implementation manner of the first aspect.
  • the present application provides an integrated circuit, the integrated circuit including the sampling component as described in the first aspect or any possible implementation manner of the first aspect.
  • the present application provides a power sourcing equipment (PSE), comprising the sampling assembly as described in the first aspect or any possible implementation manner of the first aspect.
  • PSE power sourcing equipment
  • the present application provides an electronic device, the electronic device includes a processor, a memory, and the sampling component as described in the first aspect or any possible implementation manner of the first aspect.
  • the present application provides a power over Ethernet (POE) system, where the system includes the sampling assembly described in the first aspect or any possible implementation manner of the first aspect.
  • POE power over Ethernet
  • the present application provides a computer-readable storage medium, including instructions, which, when executed by a computer, enable the second aspect or the method in any possible implementation manner of the second aspect to be implemented.
  • FIG. 1 is a schematic diagram of the workflow of the POE system.
  • FIG. 2 is a schematic structural diagram of a sampling assembly provided by the present application.
  • FIG. 3 is another schematic structural diagram of the sampling assembly provided by the present application.
  • FIG. 4 is another schematic structural diagram of the sampling assembly provided by the present application.
  • FIG. 5 is a schematic structural diagram of the self-calibration unit provided by the present application.
  • FIG. 6 is a schematic diagram of a possible setting position of the sampling resistor provided by the present application.
  • FIG. 7 is a schematic flow chart of the adoption method provided by the present application.
  • the technical solutions of the embodiments of the present application can be applied to various sampling scenarios, for example, POE scenarios, current detection scenarios of power amplifiers, module power consumption detection scenarios, voltage detection scenarios, current detection scenarios, power detection scenarios, pressure detection scenarios, blood pressure detection scenarios Detection scene, field strength detection scene, gravity detection scene, etc.
  • sampling scenarios for example, POE scenarios, current detection scenarios of power amplifiers, module power consumption detection scenarios, voltage detection scenarios, current detection scenarios, power detection scenarios, pressure detection scenarios, blood pressure detection scenarios Detection scene, field strength detection scene, gravity detection scene, etc.
  • IP Internet protocol
  • APs wireless LAN access points
  • network cameras etc.
  • POE can ensure the normal operation of the existing network while ensuring the security of the existing structured cabling, and minimize the cost.
  • a complete POE system includes two parts: PSE and powered device (PD).
  • the PSE is the device that powers the Ethernet client equipment and is also the manager of the entire POE power supply process.
  • the PD is the PSE load that receives power, that is, the client device of the POE system, such as IP phones, network security cameras, APs, PDAs, or Ethernet devices such as mobile phone chargers (actually, any device with a power not exceeding 13W) can obtain the corresponding power from the twisted pair socket).
  • PSE and PD are based on the Institute of Electrical and Electronic Engineers (IEEE) 802.3af, 802.3AT, 802.3BT standards to establish information about the connection of PD, device type, power consumption level, etc. To supply power to the PD over Ethernet according to the PSE.
  • IEEE Institute of Electrical and Electronic Engineers
  • FIG. 1 is a schematic diagram of the workflow of the POE system.
  • the workflow of the POE system includes detection, classification, powerup, operation, and disconnection.
  • the PSE detects the presence of PD. Only when PD is detected, the PSE will proceed to the next step.
  • An implementation method is that the PSE judges whether the PD exists by detecting the resistance-capacitance value between the power output line pairs.
  • the output voltage of the PSE is 2.8V to 10V, and the voltage polarity is consistent with the output of -48V; the PSE judges whether the PD exists by detecting the resistance-capacitance value between the power output line pairs.
  • the characteristics of PD existence are: a) DC impedance is between 19K ⁇ 26.5Kohm; b) capacitance value does not exceed 150nF.
  • This stage is optional.
  • the PSE determines the PD power consumption.
  • the PSE determines the PD power level by detecting the output current of the power supply.
  • the PSE output voltage is 15.5V to 20.5V, and the voltage polarity is consistent with the -48V output.
  • the PSE supplies power to the PD.
  • the PSE starts to supply power to the PD and outputs a voltage of -48V.
  • the PSE performs real-time monitoring (RTP) and power management (PM).
  • RTP real-time monitoring
  • PM power management
  • the PSE detects whether the PD is disconnected, and this stage is the key link of local detection.
  • the present application provides a sampling component and a sampling method, which can compensate the deviation between the input signal and the output signal of the sampling circuit, and can improve the sampling accuracy.
  • FIG. 2 is a schematic structural diagram of a sampling assembly provided by the present application.
  • sampling assembly of the present application can be applied to POE systems or other systems or scenarios that require sampling.
  • the sampling assembly shown in FIG. 2 may include a first switch 210 , a sampling unit 220 , a self-calibration unit 230 , and a second switch 240 .
  • the first switch 210 is connected to the sampling unit 220
  • the sampling unit 220 is respectively connected to the first switch 210 , the second switch 240 and the self-calibration unit 230
  • the self-calibration unit 230 is connected to the sampling unit 220 and the second switch 240 connect.
  • the self-calibration unit 230 is used to control the closing and opening of the first switch 210 and the second switch 240, and to compensate the sampling signal.
  • the sampling unit 220 is used for processing the received signal, for example, performing amplification, analog-to-digital conversion, and the like on the received signal.
  • the self-calibration unit 230 is configured to control the first switch to be closed, so that the first sampling signal is input to the sampling unit 220 .
  • the sampling unit 220 is configured to process the first sampling signal to obtain a second sampling signal, and output the second sampling signal to the self-calibration unit 230 .
  • the self-calibration unit 230 is further configured to control the first switch 210 to be turned off and the second switch 240 to be turned on, so as to output the first calibration signal to the sampling unit 220 .
  • the sampling unit 220 is further configured to process the first calibration signal to obtain a second calibration signal, and output the second calibration signal to the self-calibration unit 230 .
  • the self-calibration unit 230 is further configured to determine an error signal according to the first calibration signal and the second calibration signal.
  • the self-calibration unit 230 is further configured to obtain a calibrated third sampling signal according to the second sampling signal and the error signal.
  • the sampling component provided by the embodiment of the present application can obtain an error signal through the mutual cooperation of the self-calibration unit 230, the first switch 210, and the second switch 240, so that the deviation between the input signal and the output signal of the sampling component can be measured. Compensation can improve sampling accuracy.
  • the self-calibration unit 230 may periodically control the first switch 210 to be closed or open, so as to realize periodic sampling.
  • the application does not specifically limit the cycle of closing or opening of the first switch 210 , that is, the sampling cycle is not specifically limited.
  • the error signal may be determined in each sampling period, and the second sampling signal may be compensated according to the error signal determined in real time; the error signal may also be determined once every N sampling periods, where N is An integer greater than 1, the same error signal is used to compensate the second sampling signal in the N sampling periods.
  • the embodiments of the present application do not specifically limit the processing that the sampling unit 220 can perform.
  • FIG. 3 is another schematic structural diagram of the sampling assembly provided by the present application.
  • the sampling unit 220 includes a digital-to-analog conversion unit 221, and the digital-to-analog conversion unit 221 is configured to perform digital-to-analog conversion on the first sampled signal.
  • the digital-to-analog conversion unit 221 may include at least one digital-to-analog converter. That is to say, the technical solution of the present application can compensate for the error caused by the digital-to-analog conversion unit 221, which helps to improve the signal sampling accuracy.
  • analog-to-digital conversion can be performed directly without processing such as signal amplification.
  • the sampling unit 220 includes an amplifying unit 222, and the amplifying unit 222 is configured to amplify the first sampled signal.
  • the digital-to-analog conversion unit 222 may include at least one operational amplifier. That is to say, the technical solution of the present application can compensate the error caused by the amplifying unit 222, and the signal amplifying link is usually an important link that causes the error. Therefore, the technical solution of the present application can effectively improve the signal sampling accuracy.
  • signal amplification processing may be performed on the first sampled signal.
  • the sampling unit 220 includes an amplifying unit 222 and a digital-to-analog converting unit 221 .
  • the description of the amplifying unit 222 and the digital-to-analog converting unit 221 can be referred to above. That is to say, the technical solution of the present application can compensate the error caused by the amplifying unit 222 and the error caused by the analog-to-digital conversion unit 221, and can effectively improve the signal sampling accuracy.
  • FIG. 4 is another schematic structural diagram of the sampling assembly provided by the present application.
  • the sampling component may further include a third switch 250 connected to the output end of the amplifying unit 222 and the self-calibration unit 230 .
  • the self-calibration unit 230 is further configured to control the third switch 250 to be closed when the second switch 240 is controlled to be closed, so that the third calibration signal output by the amplifying unit 222 is input to the self-calibration unit 230 .
  • the self-calibration unit 230 is specifically configured to determine an error signal according to the first calibration signal, the second calibration signal and the third calibration signal, and compensate the second sampling signal according to the obtained error signal to obtain the third sampling signal. That is to say, an error signal can be determined for the amplifying unit 222 and the analog-to-digital conversion unit 221 respectively, so as to improve the calibration success rate and reduce the calibration time.
  • FIG. 5 is a schematic structural diagram of the self-calibration unit 230 provided by the present application.
  • the self-calibration unit 230 may include a calibration unit 231 and a control unit 232 .
  • the embodiments of the present application do not specifically limit the function division of the calibration unit 231 and the control unit 232 .
  • the calibration unit 231 obtains the error signal according to the first calibration signal, the second calibration signal and the third calibration signal (optional), and outputs the obtained error signal to the control unit 232; received by the control unit 232
  • the second sampling signal, and the compensated third sampling signal is obtained according to the error signal and the second sampling signal output by the calibration unit 231 .
  • the calibration unit 231 obtains the error signal according to the first calibration signal, the second calibration signal and the third calibration signal (optional), and obtains the compensated error signal according to the obtained error signal and the second sampling signal. and output the third sampling signal to the control unit 232 .
  • the input signal of the sampling component may be a current signal or a voltage signal.
  • the sampling component also needs to include a sampling resistor 250 .
  • FIG. 6 is a schematic diagram of a possible setting position of the sampling resistor provided by the present application.
  • one end of the sampling resistor 250 is connected to the output end of the first switch 210 , and the other end is grounded (ground, GND).
  • one end of the sampling resistor 250 is connected to the input end of the first switch 210 , and one end is grounded.
  • the first sampling signal may also be in a differential form. In this case, one end of the sampling resistor 250 is connected to the output end of the first switch 210, and the other end is not limited.
  • the signal is a voltage signal at both ends of the sampling resistor 250.
  • the sampling component includes a differential operational amplifier
  • the two ends of the sampling resistor 250 can be respectively input to the differential signal input terminal of the differential operational amplifier.
  • sampling resistor 250 may be a physical resistor, or may be a resistor constructed by a metal-oxide semiconductor field effect transistor (MOS-FET) or a transistor, which is not limited.
  • MOS-FET metal-oxide semiconductor field effect transistor
  • the sampling resistor 250 may be integrated in the chip, or may be an external physical resistor, which is not limited.
  • the sampling assembly of the present application can be used as a part of the chip and be disposed inside the chip; a part of the sampling assembly can also be disposed inside the chip, and a part of it can be disposed outside the chip; It is set outside the chip, which is not limited.
  • sampling assembly provided by the present application is described in detail above.
  • sampling method provided by this application is described below.
  • FIG. 7 is a schematic flow chart of the adoption method provided by the present application.
  • the method can be applied to a sampling assembly including a self-calibration unit, a sampling unit, a first switch, and a second switch, and the method includes:
  • Step 710 Control the first switch to be closed by the self-calibration unit, so that the first sampling signal is input to the sampling unit.
  • Step 720 Process the first sampling signal by the sampling unit to obtain a second sampling signal, and output the second sampling signal to the self-calibration unit.
  • Step 730 Control the first switch to be turned off and the second switch to be turned on by the self-calibration unit, and output a first calibration signal to the sampling unit.
  • Step 740 Process the first calibration signal by the sampling unit to obtain a second calibration signal, and output the second calibration signal to the self-calibration unit.
  • Step 750 Determine an error signal by the self-calibration unit according to the first calibration signal and the second calibration signal.
  • Step 760 Obtain a calibrated third sampling signal according to the second sampling signal and the error signal by the self-calibration unit.
  • the sampling unit includes an amplification unit and/or an analog-to-digital conversion unit.
  • the sampling unit when the sampling unit includes an amplifying unit and an analog-to-digital conversion unit, the sampling unit further includes a third switch, and the method further includes: when the second switch is controlled to be closed, by the self-calibration The unit controls the third switch to be closed, so that the third calibration signal output by the amplifying unit is input to the self-calibration unit; the determining an error signal according to the first calibration signal and the second calibration signal, including : determine the error signal according to the first calibration signal, the second calibration signal and the third calibration signal.
  • the self-calibration unit includes a calibration unit and a control unit, and the self-calibration unit obtains a calibrated third sampling signal according to the second sampling signal and the error signal, including: obtaining the error signal by the calibration unit; receiving the second sampling signal through the control unit, and obtaining the third sampling signal according to the error signal and the second sampling signal; or obtaining the third sampling signal through the calibration unit
  • the third sampling signal is obtained, and the third sampling signal is output to the control unit.
  • sampling method of the present application reference may be made to the description of the sampling component, which will not be repeated here.
  • the present application also provides a chip, which includes the sampling component as in any one of the foregoing embodiments.
  • the present application also provides an integrated circuit, the integrated circuit includes the sampling component as in any one of the foregoing embodiments.
  • the present application also provides a PSE, the PSE including the sampling assembly as in any one of the foregoing embodiments.
  • the present application also provides a POE system, which includes the sampling assembly as in any of the foregoing embodiments.
  • the present application also provides a computer-readable storage medium, including instructions, which, when executed by a computer, enable the method shown in FIG. 7 to be implemented.
  • a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer.
  • an application running on a computing device and the computing device may be components.
  • One or more components may reside in a process or thread of execution, and a component may be localized on one computer or distributed between 2 or more computers.
  • these components can execute from various computer readable media having various data structures stored thereon.
  • a component may, for example, pass a signal through a local system with one or more data packets (such as data from two components interacting with another component between a local system, a distributed system, or a network, such as the Internet interacting with other systems via signals). or remote process to communicate.
  • data packets such as data from two components interacting with another component between a local system, a distributed system, or a network, such as the Internet interacting with other systems via signals.
  • B corresponding to A indicates that B is associated with A, and B can be determined according to A.
  • determining B according to A does not mean that B is only determined according to A, and B may also be determined according to A and/or other information.
  • an item includes one or more of the following: A, B, and C
  • the item can be any of the following: A; B, unless otherwise specified. ;C;A and B;A and C;B and C;A,B and C;A and A;A,A and A;A,A and B;A,A and C,A,B and B;A , C and C; B and B, B, B and B, B, B and C, C and C; C, C and C, and other combinations of A, B and C.
  • a total of three elements of A, B and C are used as examples above to illustrate the optional items of the item.
  • the PSE may perform some or all of the steps in the embodiments of the present application, these steps or operations are only examples, and the embodiments of the present application may also perform other operations or variations of various operations.
  • various steps may be performed in different orders presented in the embodiments of the present application, and may not be required to perform all the operations in the embodiments of the present application.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable storage medium.
  • the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution, and the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: a U disk, a removable hard disk, a read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk and other media that can store program codes.

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Abstract

一种采样组件和采样方法，通过自校准单元（230）控制第一开关（210）闭合，使得第一采样信号输入到采样单元（220）；通过采样单元（220）对第一采样信号进行处理得到第二采样信号，并向自校准单元（230）输出第二采样信号；通过自校准单元（230）控制第一开关（210）断开、以及控制第二开关（240）闭合，向采样单元（220）输出第一校准信号；通过采样单元（220）对第一校准信号进行处理得到第二校准信号，并向自校准单元（230）输出第二校准信号；通过自校准单元（230）根据第一校准信号和第二校准信号，确定误差信号；通过自校准单元（230）根据第二采样信号和误差信号，得到校准后的第三采样信号。该方法能够对采样组件的输入信号和输出信号之间的偏差进行补偿，提高采样精度。

Description

一种采样组件和采样方法 技术领域
本申请涉及通信领域，并且更具体地，涉及一种采样组件和采样方法。
背景技术
通常，采样电路的输入信号和输出信号之间会存在偏差，而该偏差可能会随采样电路的个体差异、温度、工作电压等波动。该偏差的存在会严重影响采样电路的采样精度，影响系统的稳定、正确的运行。
发明内容
本申请提供一种采样组件和采样方法，能够对采样电路的输入信号和输出信号之间的偏差进行补偿，能够提高采样精度。
第一方面，本申请提供了一种采样组件，所述采样组件包括：自校准单元、采样单元、第一开关、以及第二开关，其中，
所述自校准单元，用于控制所述第一开关闭合，使得第一采样信号输入到所述采样单元；所述采样单元，用于对所述第一采样信号进行处理得到第二采样信号，并向所述自校准单元输出所述第二采样信号；
所述自校准单元，还用于控制所述第一开关断开、以及控制所述第二开关闭合，向所述采样单元输出第一校准信号；所述采样单元，还用于对所述第一校准信号进行处理得到第二校准信号，并向所述自校准单元输出所述第二校准信号；所述自校准单元，还用于根据所述第一校准信号和所述第二校准信号，确定误差信号；
所述自校准单元，还用于根据所述第二采样信号和所述误差信号，得到校准后的第三采样信号。
这样，本申请的采样组件通过自校准单元、第一开关、以及第二开关的互相配合可以得到误差信号，从而能够对采样组件的输入信号和输出信号之间的偏差进行补偿，能够提高采样精度。
在一些可能的实现方式中，所述采样单元包括放大单元和/或模数转换单元。
例如，在第一采样信号本身足够大的情况下，可以直接进行模数转换，而不需要信号放大等处理。也就是说，本申请的技术方案可以对由数模转化单元引起的误差进行补偿，有助于提高信号采样精度。
又例如，在第一采样信号不够大的情况下，可以对第一采样信号进行信号放大处理。也就是说，本申请的技术方案可以对由放大单元引起的误差进行补偿，而通常信号放大环节是引起误差的重要环节，因此，本申请的技术方案可以有效地提高信号采样精度。
又例如，采样单元包括放大单元和模数转换单元，这样，本申请的技术方案可以对由放大单元引起的误差和模数转换单元引起的误差进行补偿，可以有效地提高信号采样精 度。
在一些可能的实现方式中，当所述采样单元包括放大单元和模数转换单元时，所述采样单元还包括第三开关，所述自校准单元，还用于在控制所述第二开关闭合时，控制所述第三开关闭合，使得所述放大单元输出的第三校准信号输入到所述自校准单元；所述自校准单元，具体用于根据所述第一校准信号、所述第二校准信号和所述第三校准信号，确定所述误差信号。
在一些可能的实现方式中，所述自校准单元包括校准单元和控制单元，所述校准单元用于得到所述误差信号，所述控制单元用于接收所述第二采样信号，并根据所述误差信号和所述第二采样信号得到所述第三采样信号；或者，所述校准单元用于得到所述第三采样信号，并向所述控制单元输出所述第三采样信号。
其中，控制单元可以包括以下中的至少一个：状态机(state machine)、数字信号处理器(digital signal processor，DSP)、高级精简指令集计算机(advanced reduced instruction set computing machines，ARM)、线性功率控制器(linear power controller，LPC)、以及MC51单片机等。
第二方面，本申请提供了一种采样方法，所述方法应用于包括自校准单元、采样单元、第一开关、以及第二开关的采样组件，所述方法包括：
通过所述自校准单元控制所述第一开关闭合，使得第一采样信号输入到所述采样单元；通过所述采样单元对所述第一采样信号进行处理得到第二采样信号，并向所述自校准单元输出所述第二采样信号；
通过所述自校准单元控制所述第一开关断开、以及控制所述第二开关闭合，向所述采样单元输出第一校准信号；通过所述采样单元对所述第一校准信号进行处理得到第二校准信号，并向所述自校准单元输出所述第二校准信号；通过所述自校准单元根据所述第一校准信号和所述第二校准信号，确定误差信号；
通过所述自校准单元根据所述第二采样信号和所述误差信号，得到校准后的第三采样信号。
这样，本申请的采样方法通过自校准单元、第一开关、以及第二开关的互相配合可以得到误差信号，从而能够对采样组件的输入信号和输出信号之间的偏差进行补偿，能够提高采样精度。
在一些可能的实现方式中，所述采样单元包括放大单元和/或模数转换单元。
例如，在第一采样信号本身足够大的情况下，可以直接进行模数转换，而不需要信号放大等处理。也就是说，本申请的技术方案可以对由数模转化单元引起的误差进行补偿，有助于提高信号采样精度。
又例如，在第一采样信号不够大的情况下，可以对第一采样信号进行信号放大处理。也就是说，本申请的技术方案可以对由放大单元引起的误差进行补偿，而通常信号放大环节是引起误差的重要环节，因此，本申请的技术方案可以有效地提高信号采样精度。
又例如，采样单元包括放大单元和模数转换单元，这样，本申请的技术方案可以对由放大单元引起的误差和模数转换单元引起的误差进行补偿，可以有效地提高信号采样精度。
在一些可能的实现方式中，当所述采样单元包括放大单元和模数转换单元时，所述采 样单元还包括第三开关，所述方法还包括：在控制所述第二开关闭合时，通过所述自校准单元控制所述第三开关闭合，使得所述放大单元输出的第三校准信号输入到所述自校准单元；所述根据所述第一校准信号和所述第二校准信号，确定误差信号，包括：根据所述第一校准信号、所述第二校准信号和所述第三校准信号，确定所述误差信号。
在一些可能的实现方式中，所述自校准单元包括校准单元和控制单元，所述通过所述自校准单元根据所述第二采样信号和所述误差信号，得到校准后的第三采样信号，包括：通过所述校准单元得到所述误差信号；通过所述控制单元接收所述第二采样信号，并根据所述误差信号和所述第二采样信号得到所述第三采样信号；或者，通过所述校准单元得到所述第三采样信号，并向所述控制单元输出所述第三采样信号。
第三方面，本申请提供了一种芯片，所述芯片包括处理器以及如第一方面或第一方面的任意一种可能的实现方式中所述的采样组件。
第四方面，本申请提供了一种集成电路，该集成电路包括如第一方面或第一方面的任意一种可能的实现方式中所述的采样组件。
第五方面，本申请提供了一种供电设备(power sourcing equipment，PSE)，包括如第一方面或第一方面的任意一种可能的实现方式中所述的采样组件。
第六方面，本申请提供了一种电子设备，所述电子设备包括处理器、存储器以及如第一方面或第一方面的任意一种可能的实现方式中所述的采样组件。
第七方面，本申请提供了一种以太网供电(power over Ethernet，POE)系统，该系统包括如第一方面或第一方面的任意一种可能的实现方式中所述的采样组件。
第八方面，本申请提供了一种计算机可读存储介质，包括指令，当所述指令被计算机执行时，使得第二方面或第二方面的任意一种可能的实现方式中的方法得以实现。
附图说明
图1是POE系统的工作流程的示意图。
图2是本申请提供的采样组件的示意性结构图。
图3是本申请提供的采样组件的另一示意性结构图。
图4是本申请提供的采样组件的另一示意性结构图。
图5是本申请提供的自校准单元的一种示意性结构图。
图6是本申请提供的采样电阻可能的设置位置的示意图。
图7是本申请提供的采用方法的示意性流程图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例的技术方案可以应用于各种采样场景，例如，POE场景、功率放大器的电流检测场景、模块功耗检测场景、电压检测场景、电流检测场景、功率检测场景、压力检测场景、血压检测场景、场强检测场景、重力检测场景等。
下面以POE场景为例对本申请的技术方案进行描述。
POE在现有的以太网布线基础架构不作任何改动的情况下，在为一些基于互联网协议(internet protocol，IP)的终端(例如，IP电话机、无线局域网接入点(access point，AP)、 和网络摄像机等)传输数据信号的同时，还能为此类设备提供直流供电的技术。POE能在确保现有结构化布线安全的同时保证现有网络的正常运作，最大限度地降低成本。
一个完整的POE系统包括PSE和受电设备(powered device，PD)两部分。PSE是为以太网客户端设备供电的设备，同时也是整个POE供电过程的管理者。而PD是接受供电的PSE负载，即POE系统的客户端设备，例如IP电话、网络安全摄像机、AP、掌上电脑、或移动电话充电器等以太网设备(实际上，任何功率不超过13W的设备都可以从双绞线插座获取相应的电力)。PSE和PD基于电气与电子工程师协会(institute of electrical and electronic engineers，IEEE)802.3af、802.3AT、802.3BT标准建立有关PD的连接情况、设备类型、功耗级别等方面的信息联系，并以此为根据PSE通过以太网向PD供电。
图1是POE系统的工作流程的示意图。
如图1所示，POE系统的工作流程包括检测(detection)、分级(classification)、供电(powerup)、运行(operation)和去连接(disconnection)等。
1)检测
在该阶段，PSE检测PD是否存在。只有检测到PD，PSE才会进行下一步的操作。
一种实现方式为PSE通过检测电源输出线对之间的阻容值来判断PD是否存在。
例如，在检测阶段，PSE输出电压为2.8V～10V，电压极性与－48V输出一致；PSE通过检测电源输出线对之间的阻容值来判断PD是否存在。其中，PD存在的特征为：a)直流阻抗在19K～26.5Kohm之间；b)容值不超过150nF。
2)分级
该阶段为可选过程。
在该阶段，PSE确定PD功耗。
一种实现方式为PSE通过检测电源输出电流来确定PD功率等级。
例如，在分级阶段，PSE输出电压大小为15.5V～20.5V，电压极性与－48V输出一致。
3)供电
在该阶段，PSE给PD供电。
例如，当检测到PSE端口下挂设备属于合法的PD时，并且PSE完成对此PD的分类(可选)，PSE开始对该PD进行供电，输出－48V的电压。
4)运行
在该阶段，PSE执行实时监控(real time protection，RTP)和电源管理(power management，PM)。
5)去连接
在该阶段，PSE检测PD是否断开，此阶段为本地检测的关键环节。
由上述内容可知，PSE对信号的准确检测，对于POE系统的运行至关重要。
通常，POE系统中的采样电路的输入信号和输出信号之间会存在偏差，而该偏差可能会随采样电路的个体差异、温度、工作电压、批次等波动。该偏差的存在会严重影响采样电路的采样精度，影响POE系统的稳定、正确的运行。
本申请提供了一种采样组件和采样方法，能够对采样电路的输入信号和输出信号之间的偏差进行补偿，能够提高采样精度。
图2是本申请提供的采样组件的示意性结构图。
本申请的采样组件可以应用于POE系统或者其他需要进行采样的系统或场景。
图2所示的采样组件可以包括第一开关210、采样单元220、自校准单元230、以及第二开关240。如图2所示，第一开关210与采样单元220连接，采样单元220分别与第一开关210、第二开关240和自校准单元230连接，自校准单元230与采样单元220、第二开关240连接。其中，自校准单元230用于控制第一开关210和第二开关240的闭合与断开，以及对采样信号进行补偿。采样单元220用于对接收到的信号进行处理，例如，对接收到的信号进行放大、模数转换等。
下面对采样组件各单元的具体功能进行描述。
自校准单元230用于控制第一开关闭合，使得第一采样信号输入到采样单元220。采样单元220用于对第一采样信号进行处理得到第二采样信号，并向自校准单元230输出第二采样信号。
自校准单元230还用于控制第一开关210断开、以及控制第二开关240闭合，向采样单元220输出第一校准信号。采样单元220还用于对第一校准信号进行处理得到第二校准信号，并向自校准单元230输出第二校准信号。自校准单元230还用于根据第一校准信号和第二校准信号，确定误差信号。
自校准单元230还用于根据第二采样信号和误差信号，得到校准后的第三采样信号。
这样，本申请实施例提供的采样组件通过自校准单元230、第一开关210、以及第二开关240的互相配合可以得到误差信号，从而能够对采样组件的输入信号和输出信号之间的偏差进行补偿，能够提高采样精度。
在一些实现方式中，自校准单元230可以周期性地控制第一开关210闭合或断开，从而实现周期性采样。本申请对于第一开关210的闭合或断开的周期在不作具体限定，即对于采样周期不作具体限定。在本申请中，可以在每个采样周期内均进行误差信号的确定，并根据实时确定的误差信号对第二采样信号进行补偿；也可以每N个采样周期进行一次误差信号的确定，N为大于1的整数，在这N个采样周期内使用相同的误差信号对第二采样信号进行补偿。
需要说明的是，本申请对于先执行误差信号的确定还是先得到第二采样信号不作具体限定。
本申请的实施例对于采样单元220能进行的处理不作具体限定。
图3是本申请提供的采样组件的另一示意性结构图。
在一些实现方式中，如图3所示，采样单元220包括数模转换单元221，数模转换单元221用于对第一采样信号进行数模转换。其中，数模转换单元221可以包括至少一个数模转换器。也就是说，本申请的技术方案可以对由数模转化单元221引起的误差进行补偿，有助于提高信号采样精度。
例如，在第一采样信号本身足够大的情况下，可以直接进行模数转换，而不需要信号放大等处理。
在另一些实现方式中，如图3所示，采样单元220包括放大单元222，放大单元222用于对第一采样信号进行放大。其中，数模转换单元222可以包括至少一个运算放大器。也就是说，本申请的技术方案可以对由放大单元222引起的误差进行补偿，而通常信号放大环节是引起误差的重要环节，因此，本申请的技术方案可以有效地提高信号采样精度。
例如，在第一采样信号不够大的情况下，可以对第一采样信号进行信号放大处理。
在又一些实现方式中，如图3所示，采样单元220包括放大单元222和数模转换单元221。放大单元222和数模转换单元221的描述可以参见上文。也就是说，本申请的技术方案可以对由放大单元222引起的误差和模数转换单元221引起的误差进行补偿，可以有效地提高信号采样精度。
图4是本申请提供的采样组件的另一示意性结构图。
如图4所示，当采样单元220包括放大单元222和数模转换单元221时，采样组件还可以包括第三开关250，第三开关250与放大单元222的输出端和自校准单元230连接。在此情况下，自校准单元230还用于在控制第二开关240闭合时，控制第三开关250闭合，使得放大单元222输出的第三校准信号输入到自校准单元230。自校准单元230具体用于根据第一校准信号、第二校准信号和第三校准信号，确定误差信号，并根据得到的误差信号对第二采样信号进行补偿，得到第三采样信号。也就是说，可以针对放大单元222和模数转换单元221可以分别确定误差信号，提升校准成功率，降低校准时间。
图5是本申请提供的自校准单元230的一种示意性结构图。
如图5所示，自校准单元230可以包括校准单元231和控制单元232。本申请的实施例对于校准单元231和控制单元232的功能的划分不作具体限定。
在一些实现方式中，由校准单元231根据第一校准信号、第二校准信号和第三校准信号(可选的)得到误差信号，并向控制单元232输出得到的误差信号；由控制单元232接收第二采样信号，并根据校准单元231输出的误差信号和第二采样信号得到补偿后的第三采样信号。
在另一些实现方式中，由校准单元231根据第一校准信号、第二校准信号和第三校准信号(可选的)得到误差信号，并根据得到的误差信号和第二采样信号，得到补偿后的第三采样信号，并向控制单元232输出第三采样信号。
在本申请中，采样组件的输入信号可以是电流信号，也可以是电压信号。在一些实现方式中，若采样组件的输入信号为电流信号，采样组件还需包括采样电阻250。
图6是本申请提供的采样电阻可能的设置位置的示意图。如图6的(a)图所示，采样电阻250一端与第一开关210的输出端连接，一端接地(ground，GND)。如图6的(b)图所示，采样电阻250一端与第一开关210的输入端连接，一端接地。如图6的(c)图所示，第一采样信号还可以是差分的形式，在此情况下，采样电阻250一端与第一开关210的输出端连接，对另一端不限制，第一采样信号为采样电阻250两端的电压信号，可选地，若采样组件包括差分运算放大器，采样电阻250两端可以分别输入到差分运算放大器差分信号输入端。
需要说明的是，采样电阻250可以是实体的电阻，也可能是用金属-氧化物半导体场效应管(metal-oxide semiconductor field effect transistor，MOS-FET)或晶体管搭建的电阻，不予限制。采样电阻250可以集成在芯片内，也可以是外置实体电阻，不予限制。
需要说明的是，若本申请的采样组件应用于芯片的采样，采样组件可以作为芯片的一部分，设置在芯片的内部；也可以一部分设置在芯片的内部，一部分设置在芯片的外部；还可以全部设置在芯片的外部，对此不予限制。
上面对本申请提供的采样组件进行了详细描述。下面对本申请提供的采样方法进行描 述。
图7是本申请提供的采用方法的示意性流程图。该方法可以应用于包括自校准单元、采样单元、第一开关、以及第二开关的采样组件，所述方法包括：
步骤710，通过所述自校准单元控制所述第一开关闭合，使得第一采样信号输入到所述采样单元。
步骤720，通过所述采样单元对所述第一采样信号进行处理得到第二采样信号，并向所述自校准单元输出所述第二采样信号。
步骤730，通过所述自校准单元控制所述第一开关断开、以及控制所述第二开关闭合，向所述采样单元输出第一校准信号。
步骤740，通过所述采样单元对所述第一校准信号进行处理得到第二校准信号，并向所述自校准单元输出所述第二校准信号。
步骤750，通过所述自校准单元根据所述第一校准信号和所述第二校准信号，确定误差信号。
步骤760，通过所述自校准单元根据所述第二采样信号和所述误差信号，得到校准后的第三采样信号。
可选地，所述采样单元包括放大单元和/或模数转换单元。
可选地，当所述采样单元包括放大单元和模数转换单元时，所述采样单元还包括第三开关，所述方法还包括：在控制所述第二开关闭合时，通过所述自校准单元控制所述第三开关闭合，使得所述放大单元输出的第三校准信号输入到所述自校准单元；所述根据所述第一校准信号和所述第二校准信号，确定误差信号，包括：根据所述第一校准信号、所述第二校准信号和所述第三校准信号，确定所述误差信号。
可选地，所述自校准单元包括校准单元和控制单元，所述通过所述自校准单元根据所述第二采样信号和所述误差信号，得到校准后的第三采样信号，包括：通过所述校准单元得到所述误差信号；通过所述控制单元接收所述第二采样信号，并根据所述误差信号和所述第二采样信号得到所述第三采样信号；或者，通过所述校准单元得到所述第三采样信号，并向所述控制单元输出所述第三采样信号。
对本申请的采样方法更详细的描述可以参见采样组件的描述，在此不再赘述。
本申请还提供了一种芯片，该芯片包括如上述各实施例中任一实施例中的采样组件。
本申请还提供了一种集成电路，该集成电路包括如上述各实施例中任一实施例中的采样组件。
本申请还提供了一种PSE，该PSE包括如上述各实施例中任一实施例中的采样组件。
本申请还提供了一种POE系统，该系统包括如上述各实施例中任一实施例中的采样组件。
本申请还提供了一种计算机可读存储介质，包括指令，当所述指令被计算机执行时，使得图7所示的方法得以实现。
在本说明书中使用的术语“部件”、“模块”、“系统”等用于表示计算机相关的实体、硬件、固件、硬件和软件的组合、软件、或执行中的软件。例如，部件可以是但不限于，在处理器上运行的进程、处理器、对象、可执行文件、执行线程、程序或计算机。通过图示，在计算设备上运行的应用和计算设备都可以是部件。一个或多个部件可驻留在进 程或执行线程中，部件可位于一个计算机上或分布在2个或更多个计算机之间。此外，这些部件可从在上面存储有各种数据结构的各种计算机可读介质执行。部件可例如根据具有一个或多个数据分组(例如来自与本地系统、分布式系统或网络间的另一部件交互的二个部件的数据，例如通过信号与其它系统交互的互联网)的信号通过本地或远程进程来通信。
应理解，说明书通篇中提到的“实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各个实施例未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。
应理解，在本申请实施例中，编号“第一”、“第二”…仅仅为了区分不同的对象，比如为了区分不同的开关，并不对本申请实施例的范围构成限制，本申请实施例并不限于此。
还应理解，在本申请中，“当…时”、“若”以及“如果”均指在某种客观情况下网元会做出相应的处理，并非是限定时间，且也不要求网元实现时一定要有判断的动作，也不意味着存在其它限定。
还应理解，在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。
还应理解，在本申请各实施例中，“A对应的B”表示B与A相关联，根据A可以确定B。但还应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
还应理解，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本申请中出现的类似于“项目包括如下中的一项或多项：A，B，以及C”表述的含义，如无特别说明，通常是指该项目可以为如下中任一个：A；B；C；A和B；A和C；B和C；A，B和C；A和A；A，A和A；A，A和B；A，A和C，A，B和B；A，C和C；B和B，B，B和B，B，B和C，C和C；C，C和C，以及其他A，B和C的组合。以上是以A，B和C共3个元素进行举例来说明该项目的可选用条目，当表达为“项目包括如下中至少一种：A，B，……，以及X”时，即表达中具有更多元素时，那么该项目可以适用的条目也可以按照前述规则获得。
可以理解的，本申请实施例中，PSE可以执行本申请实施例中的部分或全部步骤，这些步骤或操作仅是示例，本申请实施例还可以执行其它操作或者各种操作的变形。此外，各个步骤可以按照本申请实施例呈现的不同的顺序来执行，并且有可能并非要执行本申请实施例中的全部操作。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器ROM、随机存取存储器RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种采样组件，其特征在于，所述采样组件包括：自校准单元、采样单元、第一开关、以及第二开关，其中，
    所述自校准单元，用于控制所述第一开关闭合，使得第一采样信号输入到所述采样单元；
    所述采样单元，用于对所述第一采样信号进行处理得到第二采样信号，并向所述自校准单元输出所述第二采样信号；
    所述自校准单元，还用于控制所述第一开关断开、以及控制所述第二开关闭合，向所述采样单元输出第一校准信号；
    所述采样单元，还用于对所述第一校准信号进行处理得到第二校准信号，并向所述自校准单元输出所述第二校准信号；
    所述自校准单元，还用于根据所述第一校准信号和所述第二校准信号，确定误差信号；
    所述自校准单元，还用于根据所述第二采样信号和所述误差信号，得到校准后的第三采样信号。
  2. 根据权利要求1所述的采样组件，其特征在于，所述采样单元包括放大单元和/或模数转换单元。
  3. 根据权利要求2所述的采样组件，其特征在于，当所述采样单元包括放大单元和模数转换单元时，所述采样单元还包括第三开关，
    所述自校准单元，还用于在控制所述第二开关闭合时，控制所述第三开关闭合，使得所述放大单元输出的第三校准信号输入到所述自校准单元；
    所述自校准单元，具体用于根据所述第一校准信号、所述第二校准信号和所述第三校准信号，确定所述误差信号。
  4. 根据权利要求1至3中任一项所述的采样组件，其特征在于，所述自校准单元包括校准单元和控制单元，
    所述校准单元用于得到所述误差信号，所述控制单元用于接收所述第二采样信号，并根据所述误差信号和所述第二采样信号得到所述第三采样信号；或者，
    所述校准单元用于得到所述第三采样信号，并向所述控制单元输出所述第三采样信号。
  5. 一种采样方法，其特征在于，所述方法应用于包括自校准单元、采样单元、第一开关、以及第二开关的采样组件，所述方法包括：
    通过所述自校准单元控制所述第一开关闭合，使得第一采样信号输入到所述采样单元；
    通过所述采样单元对所述第一采样信号进行处理得到第二采样信号，并向所述自校准单元输出所述第二采样信号；
    通过所述自校准单元控制所述第一开关断开、以及控制所述第二开关闭合，向所述采样单元输出第一校准信号；
    通过所述采样单元对所述第一校准信号进行处理得到第二校准信号，并向所述自校准 单元输出所述第二校准信号；
    通过所述自校准单元根据所述第一校准信号和所述第二校准信号，确定误差信号；
    通过所述自校准单元根据所述第二采样信号和所述误差信号，得到校准后的第三采样信号。
  6. 根据权利要求5所述的方法，其特征在于，所述采样单元包括放大单元和/或模数转换单元。
  7. 根据权利要求6所述的方法，其特征在于，当所述采样单元包括放大单元和模数转换单元时，所述采样单元还包括第三开关，
    所述方法还包括：
    在控制所述第二开关闭合时，通过所述自校准单元控制所述第三开关闭合，使得所述放大单元输出的第三校准信号输入到所述自校准单元；
    所述根据所述第一校准信号和所述第二校准信号，确定误差信号，包括：
    根据所述第一校准信号、所述第二校准信号和所述第三校准信号，确定所述误差信号。
  8. 根据权利要求5至7中任一项所述的方法，其特征在于，所述自校准单元包括校准单元和控制单元，
    所述通过所述自校准单元根据所述第二采样信号和所述误差信号，得到校准后的第三采样信号，包括：
    通过所述校准单元得到所述误差信号；通过所述控制单元接收所述第二采样信号，并根据所述误差信号和所述第二采样信号得到所述第三采样信号；
    或者，
    通过所述校准单元得到所述第三采样信号，并向所述控制单元输出所述第三采样信号。
  9. 一种芯片，其特征在于，包括如权利要求1至4中任一项所述的采样组件。
  10. 一种集成电路，其特征在于，包括如权利要求1至4中任一项所述的采样组件。
  11. 一种计算机可读存储介质，其特征在于，包括指令，当所述指令被计算机执行时，使得如权利要求5至8中任一项所述的方法得以实现。
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