WO2022137821A1 - Analog-digital converter and electronic device - Google Patents

Abstract

The present invention reduces the size of a circuit in an SAR ADC in which a circuit for cancelling ripples is provided.　According to the present invention, a digital-analog converter generates at least one of a pair of analog signals in accordance with a predetermined control signal. A comparator compares the pair of analog signals, and generates and outputs a comparison result. A logic circuit generates the control signal on the basis of the comparison result. A plurality of switches, on the basis of the control signal, open or close paths between an output terminal of the comparator and sources or drains of a plurality of positive-side transistors having different sizes and a plurality of negative-side transistors having different sizes. A positive-side common capacitor has one end connected to a node of a predetermined positive-side reference voltage, and has the other end connected to, in a shared manner, the gates of the plurality of positive-side transistors. A negative-side capacitor has one end connected to a node of a negative-side reference voltage which is lower than the positive-side reference voltage, and has the other end connected to, in a shared manner, the gates of the plurality of negative-side transistors.

Description

Analog-to-digital converters and electronic devices

This technology relates to analog-to-digital converters. More specifically, the present invention relates to a serial comparison type analog-to-digital converter and an electronic device.

SARADC (Successive Approximation Register Analog to Digital Converter) is widely used in various electronic devices because of its high resolution and low power consumption. Here, the SARADC is a circuit in which a comparator sequentially compares a sampled analog signal and a reference signal generated by a DAC (Digital to Analog Converter), and a logic circuit controls the DAC so that they match. In this SARADC, when the level of the reference signal is changed, a fluctuation called ripple may occur in the output signal of the DAC, and the ripple may cause an error in the comparison result of the comparator. Therefore, a SARADC has been proposed in which a capacitance portion including four capacitances and a plurality of switches is arranged bit by bit to generate a signal having a phase opposite to that of the ripple (see, for example, Patent Document 1).

In the above-mentioned conventional technique, the ripple is canceled by generating a signal having a phase opposite to that of the ripple. However, in the above-mentioned SARADC, since it is necessary to provide four capacitances for each bit, there is a problem that the circuit scale increases as the resolution of the SARADC increases. For example, when the resolution is 5 bits, a total of 20 capacities must be arranged in the five capacities.

This technology was created in view of such a situation, and aims to reduce the circuit scale in SARADC provided with a circuit that cancels ripple.

The present technology has been made to solve the above-mentioned problems, and the first aspect thereof is a digital-analog converter that generates at least one of a pair of analog signals according to a predetermined control signal, and the above-mentioned pair. A comparator that compares analog signals to generate and output a comparison result, a logic circuit that generates the control signal based on the comparison result, multiple positive transistors of different sizes, and multiple negatives of different sizes. A plurality of switches that open and close the path between the side transistor, one of the source and drain of each of the plurality of positive transistors and the plurality of negative transistors, and the output terminal of the comparator based on the control signal. One end is connected to a node with a predetermined positive reference voltage, and the other end is commonly connected to the gate of each of the plurality of positive transistors. It is an analog-digital converter having one end connected to a node of a reference voltage and a negative side common capacitance having the other end connected in common to each gate of the plurality of negative side transistors. This has the effect of reducing the circuit scale.

Further, in the first aspect, the pair of analog signals is a differential signal, and the digital-to-analog converter may generate the differential signal. This has the effect of reducing the circuit scale of the analog-to-digital converter with differential input.

Further, in this first aspect, the path between the other end of each of the positive side common capacitance and the negative side common capacitance and the common voltage between the positive side reference voltage and the negative side reference voltage is opened and closed. A sampling switch may be further provided. This has the effect that the reference voltage is sampled on the positive side common capacitance and the negative side common capacitance.

Further, in this first aspect, the sampling switch may shift to the closed state within a predetermined sampling period. This has the effect of being sampled within the sampling period.

Further, in this first aspect, the sampling switch may shift to the closed state within the period from the end of the analog-to-digital conversion to the start of sampling. This has the effect of sampling within the period from the end of the analog-to-digital conversion to the start of sampling.

Further, in this first aspect, a latch circuit that holds the comparison result and supplies it to the logic circuit may be further provided. This has the effect of preserving the comparison results.

Further, in this first aspect, each of the plurality of positive side transistors and the plurality of negative side transistors may be nMOS transistors. This has the effect that a current flows through the differential pair of the nMOS transistor.

Further, in this first aspect, each of the plurality of positive side transistors and the plurality of negative side transistors may be pMOS transistors. This has the effect that a current flows through the differential pair of the pMOS transistor.

Further, in this first aspect, a plurality of pairs of common side transistors having different sizes are further provided, and each gate of the plurality of pairs of common side transistors is between the positive side reference voltage and the negative side reference voltage. It may be connected to a node with a common voltage. This has the effect of applying a common voltage to the gate of the common-side transistor.

Further, in this first aspect, a plurality of pairs of first common side transistors having different sizes and a plurality of pairs of second common side transistors having different sizes are further provided, and the positive side common capacitance is the first positive side. The negative side common capacitance includes a common capacitance and a second positive side common capacitance, the negative side common capacitance includes a first negative side common capacitance and a second negative side common capacitance, and the plurality of positive side transistors are a plurality of firsts having different sizes. The plurality of negative side transistors include a plurality of positive side transistors and a plurality of second positive side transistors having different sizes, and the plurality of negative side transistors include a plurality of first negative side transistors having different sizes and a plurality of second negative side transistors having different sizes. The gates of the plurality of first positive-side transistors are commonly connected to the first positive-side common capacitance, and the respective gates of the plurality of second positive-side transistors are common to the second positive-side common. Commonly connected to the capacitance, each gate of the plurality of first negative transistor is commonly connected to the first negative common capacitance, and each gate of the plurality of second negative transistors is connected to the first negative transistor. 2 It may be connected in common to the common capacity on the negative side. This has the effect of eliminating the need for a common voltage.

The second aspect of the present technology is a comparison between a digital-analog converter that generates at least one of a pair of analog signals according to a predetermined control signal and the pair of analog signals to generate and output a comparison result. A device, a logic circuit that generates the control signal based on the comparison result and outputs a digital signal, a plurality of positive-side transistors having different sizes, a plurality of negative-side transistors having different sizes, and a plurality of positive-side transistors. A plurality of switches that open and close the path between one of the source and drain of the transistor and the plurality of negative transistors and the output terminal of the comparator based on the control signal, and a predetermined positive reference voltage. One end is connected to the node, and one end is connected to the positive common capacitance in which the other end is commonly connected to the gate of each of the plurality of positive transistors and the node having a negative reference voltage lower than the positive reference voltage. This is an electronic device including a negative side common capacitance in which the other end is commonly connected to each gate of the plurality of negative side transistors, and a digital signal processing circuit for processing the digital signal. This has the effect of reducing the circuit scale of electronic devices.

It is a block diagram which shows one configuration example of the electronic device in 1st Embodiment of this technique. It is a block diagram which shows one configuration example of SARADC in the 1st Embodiment of this technique. It is a circuit diagram which shows one structural example of CDAC in 1st Embodiment of this technique. It is a circuit diagram which shows one structural example of the comparator in the 1st Embodiment of this technique. It is a circuit diagram which shows one structural example of the latch circuit in 1st Embodiment of this technique. It is a circuit diagram which shows one configuration example of the ripple canceller in 1st Embodiment of this technique. It is a figure for demonstrating the connection state of the CDAC and the ripple canceller in the 1st Embodiment of this technique. It is a figure for demonstrating an example of control of the switch of the ripple canceller in 1st Embodiment of this technique. It is a circuit diagram which shows one configuration example of the ripple canceller in the comparative example. It is a timing chart which shows an example of the operation of SARADC in the 1st Embodiment of this technique. It is an example of the whole view of SARADC in the 1st Embodiment of this technique. It is an example of the whole view of SARADC in the 2nd Embodiment of this technique. It is a timing chart which shows an example of the operation of SARADC in the 2nd Embodiment of this technique. It is a circuit diagram which shows one configuration example of the differential amplifier circuit in 4th Embodiment of this technique. It is a circuit diagram which shows one structural example of the latch circuit in 4th Embodiment of this technique. It is a circuit diagram which shows one configuration example of the ripple canceller in 4th Embodiment of this technique. It is a circuit diagram which shows one configuration example of the ripple canceller in 5th Embodiment of this technique. It is a circuit diagram which shows one structural example of the comparator part in 5th Embodiment of this technique. It is a block diagram which shows the schematic configuration example of a vehicle control system. It is explanatory drawing which shows an example of the installation position of the image pickup unit.

Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. First embodiment (example of reducing the number of capacities)
2. 2. Second embodiment (example of reducing the number of capacities and changing the sample timing)
3. 3. Third embodiment (example in which the number of capacitances is reduced and the polarity of the transistor is changed)
4. Fourth embodiment (example of reducing the number of capacities and eliminating the need for a common voltage)
5. Application example to mobile body

<1. First Embodiment>
[Example of electronic device configuration]
FIG. 1 is a block diagram showing a configuration example of an electronic device 100 according to a first embodiment of the present technology. The electronic device 100 converts an analog signal into a digital signal and processes it, and includes an analog signal generation unit 110, a SARADC 200, and a digital signal processing unit 120. As the electronic device 100, an image pickup device, an audio device, a communication device, and the like are assumed.

The analog signal generation unit 110 generates an analog signal AIN and supplies it to the SARADC 200 via the signal line 119. As the analog signal AIN, a pixel signal, an audio signal, or an RF (Radio Frequency) signal is assumed.

The SARADC200 converts the input analog signal AIN into a digital signal DOUT by a sequential comparison method. The SARADC 200 supplies the digital signal DOUT to the digital signal processing unit 120 via the signal line 209.

The digital signal processing unit 120 performs predetermined signal processing on the digital signal DOUT. As signal processing, image processing such as demodulation processing, audio compression processing, demodulation processing, and the like are assumed.

The number of SARADC200 is not limited to one, and may be two or more. For example, in an image pickup apparatus, SARADC200 may be arranged for each row.

[SARAD C configuration example]
FIG. 2 is a block diagram showing a configuration example of the SARADC200 according to the first embodiment of the present technology. The SARADC 200 includes sampling switches 211 and 212, a CDAC (Capacitor DAC) 300, a latch circuit 430, a comparator 400, and a SAR (Successive Approximation Register) logic circuit 220. Further, the SARADC 200 further includes a ripple canceller 500.

A differential analog signal from the analog signal generation unit 110 is input to the sampling switches 211 and 212. This differential signal (ie, an analog signal) includes a positive signal AIN_p and a negative signal AIN_n. The sampling switches 211 and 212 open and close the path between the analog signal generation unit 110 and the CDAC 300 in synchronization with the sampling clock CLK. For example, while the sampling clock CLK is at a high level, the sampling switches 211 and 212 are closed and the differential signal is sampled.

The CDAC300 generates an analog reference signal by DA (Digital to Analog) conversion. The CDAC 300 holds a sampled differential signal (analog signal), and differentially outputs the difference between the analog signal and the internally generated reference signal (analog signal) to the comparator 400.

The comparator 400 compares the positive side and the negative side of the differential signal from the CDAC 300. The comparator 400 supplies the comparison result to the latch circuit 430. The latch circuit 430 holds the comparison result. The latch circuit 430 supplies the held comparison result to the SAR logic circuit 220.

The SAR logic circuit 220 controls the level of the reference signal based on the comparison result of the comparator 400. The SAR logic circuit 220 updates the level of the reference signal so that the positive side and the negative side of the output of the CDAC 300 are balanced by the sequential comparison method. Assuming that the resolution of the SARADC 200 is M (M is an integer) bit, the number of successive comparisons is M times. Further, the SAR logic circuit 220 holds each of the comparison results of M times, and supplies a bit string in which bits indicating the comparison results are arranged to the digital signal processing unit 120 as a digital signal DOUT.

The ripple canceller 500 cancels the ripple of the output signal of the CDAC 300. The circuit configuration of the ripple canceller 500 will be described later.

[CCDAC configuration example]
FIG. 3 is a circuit diagram showing a configuration example of the CDAC 300 according to the first embodiment of the present technology. The figure illustrates a circuit when the resolution is 5 bits. The CDAC 300 includes a positive capacity 311 to 316, a negative capacity 317 to 322, a positive switching unit 330, and a negative switching unit 340. The positive side switching circuits 331 to 336 are arranged in the positive side switching unit 330, and the negative side switching circuits 341 to 346 are arranged in the negative side switching unit 340. In the figure, the positive side capacities 314 and 315, the negative side capacities 320 and 321, the positive side switching circuits 334 and 335, and the negative side switching circuits 344 and 345 are omitted.

Further, a positive signal line 308 and a negative signal line 309 are wired in the CDAC 300. The positive signal line 308 is wired between the positive input terminal and the positive output terminal of the CDAC 300. The negative signal line 309 is wired between the negative input terminal and the negative output terminal of the CDAC 300. The voltage of the positive signal line 308 is output to the comparator 400 as the positive voltage V _{cdac_p} . The voltage of the negative signal line 309 is output to the comparator 400 as the negative voltage V _{cdac_n} .

One end of the positive capacitances 311 to 316 is commonly connected to the positive signal line 308. The other ends of these positive capacitances 311 to 316 are connected to the positive switching circuits 331 to 336. Further, the capacities of the positive capacities 311 to 315 are different from each other. For example, assuming that the predetermined unit capacity value is C, the capacity values of the positive side capacities 311, 312, 313, 314, 315 and 316 are set to 16C, 8C, 4C, 2C, C and C.

One end of the negative capacitance 317 to 322 is commonly connected to the negative signal line 309. The other ends of these negative capacitances 317 to 322 are connected to the negative switching circuits 341 to 346. Further, the capacities of the negative capacities 317 to 321 are different from each other. For example, the capacity values of the negative capacities 317, 318, 319, 320, 321 and 322 are set to 16C, 8C, 4C, 2C, C and C.

The capacity of 16C and the corresponding switching circuit correspond to MSB (Most Significant Bit) out of 5 bits. The 8C capacitance and the corresponding switching circuit correspond to the second bit, and the 4C capacitance and the corresponding switching circuit correspond to the third bit. The 2C capacitance and the corresponding switching circuit correspond to the 4th bit, and one of the C capacitances and the corresponding switching circuit correspond to the LSB (Least Significant Bit). The other of the capacitances of C is used as a dummy capacitance.

The positive switching circuits 331 to 335 have one of the positive reference voltage VREFP, the common voltage VCOM and the negative reference voltage VREFN at the other end of the corresponding positive capacitance according to the control signals Dac_p and Dac_n from the SAR logic circuit 220. It connects to. The size of each of the control signals Dac_p and Dac_n is 5 bits. The positive side switching circuit 336 sets the other end of the dummy positive side capacitance 316 to either the positive side reference voltage VREFP, the common voltage VCOM, or the negative side reference voltage VREFN according to a control signal (not shown) from the SAR logic circuit 220. It connects to.

The positive side reference voltage VREFP is a constant voltage higher than the common voltage VCOM, and the negative side reference voltage VREFN is a constant voltage lower than the common voltage VCOM. The value of the positive reference voltage VREFF can be expressed as + VREF, and the value of the negative reference voltage VREFN can be expressed as −VREF.

Negative side switching circuits 341 to 345, according to the control signals Dac_p and Dac_n from the SAR logic circuit 220, set the other end of the corresponding negative capacitance to either the positive reference voltage VREFP, the common voltage VCOM, or the negative reference voltage VREFN. It connects to. The negative side switching circuit 346 has one of the positive side reference voltage VREFP, the common voltage VCOM, and the negative side reference voltage VREFN at the other end of the dummy positive side capacitance 316 according to the control signal (not shown) from the SAR logic circuit 220. It connects to.

Further, the negative side switching circuit 341 is composed of, for example, switches 351 to 353. The same applies to the positive side switching circuits 331 to 336 and other negative side switching circuits.

The SAR logic circuit 220 connects all of the positive capacitances 311 to 316 and the negative capacitances 317 to 322 to the common voltage VCOM by a control signal during the period when the sampling switches 211 and 212 are closed (that is, the sampling period). .. This keeps the sampled differential signal.

Then, the SAR logic circuit 220 refers to the comparison result of the comparator 400, and controls the connection destination of the capacitance in the CDAC 300 by the control signal based on the comparison result.

For example, when the positive side is equal to or greater than the negative side in the first comparison result, the SAR logic circuit 220 connects the negative side reference voltage VREFN to the positive side capacitance 311 and connects the positive side reference voltage VREFN to the negative side capacitance 317. do. On the other hand, when the positive side is less than the negative side in the first comparison result, the SAR logic circuit 220 connects the positive side reference voltage VREFP to the positive side capacitance 311 and the negative side reference voltage VREFN to the negative side capacitance 317. do. By these controls, -1 / 2VREF or + 1 / 2VREF is added to the positive side, and + 1 / 2VREF or -1 / 2VREF is added to the negative side.

Further, when the positive side is equal to or greater than the negative side in the second comparison result, the SAR logic circuit 220 connects the negative side reference voltage VREFN to the positive side capacitance 312 and connects the positive side reference voltage VREFN to the negative side capacitance 318. do. On the other hand, when the positive side is less than the negative side in the second comparison result, the SAR logic circuit 220 connects the positive side reference voltage VREFP to the positive side capacitance 312 and connects the negative side reference voltage VREFN to the negative side capacitance 318. do. By these controls, -1/4 VREF or + 1/4 VREF is added to the positive side, and + 1/4 VREF or -1 / 4 VREF is added to the negative side.

Hereinafter, the same control is repeated by the SAR logic circuit 220 until the number of comparisons reaches five. When the resolution (M bit) is other than 5 bits, each of M + 1 positive capacitance, negative capacitance, positive switching circuit, and negative switching circuit including a dummy is arranged. The capacity of the m (m is an integer from 0 to M-1) bit is set to be twice that of the m + 1 bit.

As described above, the method of controlling the reference voltage based on the result of M sequential comparisons is called the sequential comparison method.

A single-ended signal can be input to the SARADC200 instead of the differential signal. In this case, no capacitance or switch is required on either the positive side or the negative side of the CDAC 300. Further, a sampled and held single-ended signal is input to one input terminal of the comparator 400, and a reference voltage generated by the CDAC 300 is input to the other input terminal.

[Comparator control example]
FIG. 4 is a circuit diagram showing a configuration example of the comparator 400 according to the first embodiment of the present technology. The comparator 400 includes an enable control unit 410 and a differential amplifier circuit 420.

The enable control unit 410 generates an enable signal En_Comp from the output of the latch circuit 430 and the sampling clock CLK. The enable control unit 410 includes an inverter 411, a NOR (logical sum) gate 412, and an AND (logical product) gate 413.

The inverter 411 inverts the sampling clock CLK and supplies it to the AND gate 413.

The NOR gate 412 supplies the AND gate 413 with the negative logic sum of the positive voltage V _{out_p} and the negative voltage V _{out_n} of the latch circuit 430.

The AND gate 413 supplies the logical product of the signal from the inverter 411 and the signal from the NOR gate 412 as an enable signal En_Comp to the differential amplifier circuit 420 and the ripple canceller 500.

The positive side voltage V _{cdac_p} and the negative side voltage V _{cdac_n} from the CDAC 300 are input to the differential amplifier circuit 420. The differential amplifier circuit 420 compares their voltages. The comparison result is differentially output to the SAR logic circuit 220 latch circuit 430 via the positive side signal line 408 and the negative side signal line 409. The differential amplifier circuit 420 includes pMOS (p-channel Metal Oxide Semiconductor) transistors 421 and 422 and nMOS (n-channel MOS) transistors 423 to 425.

The pMOS transistor 421 and the nMOS transistor 423 are connected in series between the power supply node and the drain of the nMOS transistor 425. The pMOS transistor 422 and the nMOS transistor 423 are also connected in series between the power supply node and the drain of the nMOS transistor 425. The source of the nMOS transistor 425 is connected to the grounded node.

Further, an enable signal En_Comp is input to each gate of the pMOS transistors 421 and 422 and the nMOS transistor 425. The negative voltage V _{cdac_n} is input to the gate of the nMOS transistor 423, and the positive voltage V _{cdac_p} is input to the gate of the nMOS transistor 424.

Further, the voltage of the connection node of the pMOS transistor 421 and the nMOS transistor 423 is output as a negative voltage V _{gm_n} . The voltage of the connection node of the pMOS transistor 422 and the nMOS transistor 424 is output as the positive side voltage V _{gm_p} .

[Latch circuit configuration example]
FIG. 5 is a circuit diagram showing a configuration example of the latch circuit 430 according to the first embodiment of the present technology. The latch circuit 430 includes pMOS transistors 431 to 434 and nMOS transistors 435 to 440.

The differential amplifier circuit 420 outputs the positive voltage V _{gm_p} of the differential signal from the positive output terminal to the latch circuit 430, and outputs the negative voltage V _{gm_n} of the differential signal from the negative output terminal to the latch circuit 430. ..

In the latch circuit 430, the pMOS transistors 431 and 432 are connected in series to the power supply voltage node. The nMOS transistors 436 and 437 are connected in parallel between the drain of the pMOS transistor 432 on the ground side and the node of the ground voltage. The nMOS transistor 435 is inserted between the connection node of the pMOS transistors 431 and 432 and the node of the ground voltage.

Further, the pMOS transistors 433 and 434 are connected in series to the node of the power supply voltage. The nMOS transistors 438 and 439 are connected in parallel between the drain of the pMOS transistor 434 on the ground side and the node of the ground voltage. The nMOS transistor 440 is inserted between the connection node of the pMOS transistors 433 and 434 and the node of the ground voltage.

Further, the positive voltage Vgm_p from the differential amplifier circuit 420 is input to the respective gates of the pMOS transistor 431 and the nMOS transistors 435 and 436. The negative voltage Vgm_n from the differential amplifier circuit 420 is input to the respective gates of the pMOS transistor 433 and the nMOS transistors 439 and 440.

Further, the connection nodes of the pMOS transistor 432 and the nMOS transistor 437 are connected to the respective gates of the pMOS transistor 434 and the nMOS transistor 438. The voltage of this connection node is output to the SAR logic circuit 220 and the comparator 400 as the positive voltage _{Vout_p} .

Further, the connection nodes of the pMOS transistor 434 and the nMOS transistor 438 are connected to the respective gates of the pMOS transistor 432 and the nMOS transistor 437. The voltage of this connection node is output to the SAR logic circuit 220 and the comparator 400 as a negative voltage V _{out_n} .

According to the connection configuration exemplified in the figure, when one of the positive side voltage V _{gm_p} and the negative side voltage V _{gm_n} is high level and the other is low level, the latch circuit 430 shifts to the through state. At this time, the positive side voltage V _{gm_p} and the negative side voltage V _{gm_n} are output as they are as the positive side voltage V _{out_p} and the negative side voltage V _{out_n} .

Further, when the positive side voltage Vgm_p and the negative side voltage Vgm_n are in equilibrium, the latch circuit 430 shifts to the holding state, and the immediately preceding state is held.

Further, the differential amplifier circuit 420 starts the comparison operation when the enable signal En_Comp changes from the low level to the high level. At the start of the operation, V _{gm_p} and V _{gm_n} are discharged from the power supply voltage to the ground voltage. The discharge speeds of V _{gm_p} and V _{gm_n} change depending on the magnitude of the difference between V _{cdac_p} and V _{cdac_n} , and the output logic of the latch circuit 430 is determined by the difference in the discharge speeds.

[Ripple canceller configuration example]
FIG. 6 is a circuit diagram showing a configuration example of the ripple canceller 500 according to the first embodiment of the present technology. The figure illustrates a circuit when the resolution is 5 bits. The ripple canceller 500 includes a capacitance unit 510 and a comparator unit 521 to 525. Sampling switches 511 and 512, a positive side common capacity 513, and a negative side common capacity 514 are arranged in the capacity unit 510. In the figure, the comparator units 524 and 525 are omitted.

The sampling switch 511 opens and closes the path between the common signal line 507 of the common voltage VCOM and the positive signal line 508 according to the sampling clock CLK. The sampling switch 512 opens and closes the path between the common signal line 507 and the negative signal line 509 according to the sampling clock CLK. For example, the sampling switches 511 and 512 are closed while the sampling clock CLK is at a high level.

One end of the positive side common capacitance 513 is connected to the node of the positive side reference voltage VREFP, and the other end is connected to the positive side signal line 508. One end of the negative side common capacitance 514 is connected to the node of the negative side reference voltage VREFN, and the other end is connected to the negative side signal line 509. When the charges stored in these charges are stable, the sampling switches 511 and 512 shift to the open state.

Here, it is desirable that the positive reference voltage VREFP and the negative reference voltage VREFN are in a stable state without ripple.

The comparator section 521 includes switches 531 to 536, common side transistors 537 and 538, a positive side transistor 539, a negative side transistor 540, and a switch transistor 541. As these transistors, nMOS transistors are used.

The switch 531 opens and closes the path between the drain of the common side transistor 537 and the positive side signal line 408 according to the control signal from the SAR logic circuit 220. This positive signal line 408 is connected to the positive output terminal of the comparator 400 as described above.

The switch 532 opens and closes the path between the drain of the common side transistor 538 and the negative side signal line 409 according to the control signal from the SAR logic circuit 220. The negative signal line 409 is connected to the negative output terminal of the comparator 400 as described above.

The switch 533 opens and closes the path between the drain of the positive transistor 539 and the negative signal line 409 according to the control signal from the SAR logic circuit 220. The switch 534 opens and closes the path between the drain of the positive transistor 539 and the positive signal line 408 according to the control signal from the SAR logic circuit 220.

The switch 535 opens and closes the path between the drain of the negative transistor 540 and the positive signal line 408 according to the control signal from the SAR logic circuit 220. The switch 536 opens and closes the path between the drain of the negative transistor 540 and the negative signal line 409 according to the control signal from the SAR logic circuit 220.

The sources of the common side transistors 537 and 538 are commonly connected to the drain of the switch transistor 541, and their gates are commonly connected to the common signal line 507 of the common voltage VCOM.

The source of the positive transistor 539 is connected to the drain of the switch transistor 541, and its gate is connected to the positive common capacitance 513 via the positive signal line 508. The source of the negative transistor 540 is connected to the drain of the switch transistor 541 and its gate is connected to the negative common capacitance 514 via the negative signal line 509.

The source of the switch transistor 541 is connected to the node of the ground voltage, and the enable signal En_Comp is input to the gate.

The circuit configurations of the comparator units 522 to 525 are the same as those of the comparator unit 521. However, the size of each transistor of these comparators is different. Here, the "size" of the transistor indicates the size of the gate of the transistor (gate width or gate length). For example, when the gate width is constant, the gate length is used as the size.

When the size of the transistor in the comparator section 525 is "1", the size of each transistor in the comparator section 521, 522, 523 and 524 is set to "16", "8", "4" and "2". Will be done.

The comparator section 521 having a size of "16" corresponds to MSB. The comparator section 522 corresponds to the second bit, and the comparator section 523 corresponds to the third bit. The comparator section 524 corresponds to the 4th bit, and the comparator section 525 having a size of "1" corresponds to the LSB.

Immediately after sampling, only the switches 531 and 532 on the common side of all bits are controlled to be closed, and the switches 533 to 536 on the positive and negative sides of the corresponding bits are opened and closed according to the comparison result. The detailed control contents will be described later.

If the resolution (M bits) is other than 5 bits, M comparator units are arranged. The size of the transistor at the m-th bit is twice that of the m + 1-th bit. Further, the number of bits of the resolution and the number of the comparator units are matched, but the configuration is not limited to this. The number of comparator units may be slightly smaller than the number of resolution bits. However, there is a risk that the ripple canceling effect, which will be described later, will be reduced.

FIG. 7 is a diagram for explaining the connection state of the CDAC 300 and the ripple canceller 500 in the first embodiment of the present technology. Of the M-bit control signals Dac_p, the mth bit is Dac_p [m]. Similarly, in the control signal Dac_n, the mth bit is Dac_n [m]. The initial value of each bit of the control signals Dac_p and Dac_n is, for example, a logical value “0”.

The SAR logic circuit 220 refers to the m-th comparison result of the comparator 400, and updates Dac_n [m] to the logic value "1" when the positive side is equal to or greater than the negative side. At this time, Dac_p [m] remains "0". On the other hand, when the positive side is less than the negative side, the SAR logic circuit 220 updates Dac_p [m] to "1". At this time, Dac_n [m] remains "0".

In the CDAC300, when both Dac_p [m] and Dac_n [m] are "0", the positive capacitance and the negative capacitance of the m-th bit are connected to the common voltage VCOM.

When Dac_p [m] is "1" and Dac_n [m] is "0", the positive capacitance of the m-th bit is connected to the positive reference voltage VREFP, and the negative capacitance is the negative reference voltage. Connected to VREFN.

When Dac_p [m] is "0" and Dac_n [m] is "1", the positive capacitance of the m-th bit is connected to the negative reference voltage VREFN, and the negative capacitance is the positive reference voltage. Connected to VREFP.

Next, in the ripple canceller 500, when both Dac_p [m] and Dac_n [m] are "0", the switches 531 and 532 of the m-th bit shift to the closed state. As a result, the drains of the common side transistors 537 and 538 of the m-th bit are connected to the positive side output terminal and the negative side output terminal of the comparator 400, respectively. At this time, all the switches other than the switches 531 and 532 shift to the open state.

Further, when Dac_p [m] is "1" and Dac_n [m] is "0", the switches 533 and 535 of the m-th bit shift to the closed state. As a result, the drain of the positive transistor 539 is connected to the negative output terminal of the comparator 400, and the drain of the negative transistor 540 is connected to the positive output terminal of the comparator 400. At this time, all the switches other than the switches 533 and 535 shift to the open state.

Further, when Dac_p [m] is "0" and Dac_n [m] is "1", the switches 534 and 536 of the m-th bit shift to the closed state. As a result, the drain of the positive transistor 539 is connected to the positive output terminal of the comparator 400, and the drain of the negative transistor 540 is connected to the negative output terminal of the comparator 400. At this time, all the switches other than the switches 534 and 536 shift to the open state.

FIG. 8 is a diagram for explaining an example of control of a switch of a ripple canceller according to the first embodiment of the present technique. In the figure, it is assumed that the control up to the third bit is completed. Further, in the figure, the comparator 400 is omitted.

Based on the first comparison result, the SAR logic circuit 220 connects the positive capacitance 311 of 16C to the positive reference voltage VREFP and the negative capacitance 317 of 16C to the negative reference voltage VREFN by the control signal.

Based on the result of the second comparison, the SAR logic circuit 220 connects the positive capacitance 312 of 8C to the negative reference voltage VREFN and the negative capacitance 318 of 8C to the positive reference voltage VREFP by the control signal.

Based on the result of the third comparison, the SAR logic circuit 220 connects the positive capacitance 313 of 4C to the positive reference voltage VREFP and the negative capacitance 319 of 4C to the negative reference voltage VREFN by the control signal.

Here, assuming that a ripple component of Δ is generated in the positive reference voltage VREFP, the ripple component V _dac generated in the differential output of the CDAC 300 is expressed by the following equation.
V _dac = {(16-8 + 4) C / 32C} ・ Δ ・ ・ ・ Equation 1

On the other hand, the positive transistor of the first bit comparator section 521 is connected to the negative output terminal of the comparator 400 via the negative signal line 409, and the negative transistor is connected to the comparator via the positive signal line 408. It is connected to the positive output terminal of 400. In the figure, a white triangle indicates a positive transistor, and a black triangle indicates a common transistor. The gray triangle indicates the negative transistor.

Further, the positive transistor of the second bit comparator section 522 is connected to the positive output terminal, and the negative transistor is connected to the negative output terminal. The positive transistor of the third bit comparator section 523 is connected to the negative output terminal, and the negative transistor is connected to the positive output terminal.

The ripple component V _cancel generated in the ripple canceller 500 by the above connection is expressed by the following equation.
V _cancel =-(16C / 32) Δ'+ (8C / 32) Δ'-(4C / 32) Δ'
=-{(16-8 + 4) / 32} ・ Δ'・ ・ ・ Equation 2

The value of Δ'depends on the size of the smallest transistor in the ripple canceller 500. The size of the minimum transistor is adjusted to a value in which Δ in Equation 1 and Δ'in Equation 2 substantially match.

When Δ and Δ'are substantially the same, the absolute values of the ripple component of the CDAC 300 and the ripple component generated in the ripple canceller 500 are the same from Equations 1 and 2, and the symbols are reversed. Therefore, when they are added at the output terminal of the comparator 400, the ripple component of the CDAC 300 is canceled. By canceling the ripple component, it is possible to reduce the error of the comparison result of the comparator 400.

FIG. 9 is a circuit diagram showing a configuration example of the ripple canceller in the comparative example. This comparative example is the circuit described in Non-Patent Document 1. In this comparative example, the resolution is set to M bits, and M comparator sections and M capacitive sections are arranged in the ripple canceller. A differential pair of nMOS transistors and a switch transistor are arranged in each of the comparator sections, and four capacitances and six switches are arranged in each of the capacitive sections. Further, the capacity of the LSB and the size of the differential pair are the largest, and the capacity and the size are halved after the second bit.

In the comparative example, the ripple component of CDAC can be canceled by controlling the switch. However, it is necessary to arrange four capacitances for each bit, and the higher the resolution, the larger the circuit scale.

Also, in the comparative example, the larger the value of the capacity in the capacity section, the lower the on-resistance of the switch to which the capacity is connected needs to be lowered. Therefore, when the switch is realized by an nMOS transistor, it is necessary to increase the size of the transistor as the capacitance value is larger. This nMOS transistor needs to be driven in conjunction with the CDAC 300, but as the size of the nMOS transistor increases, the power consumption for driving may increase.

Furthermore, in the comparative example, the higher the resolution, the more wiring connecting the capacitance section and the comparator section. When the switch to which the common voltage VCOM of the capacitance portion is connected is in the open state, each wiring has a very high impedance. Therefore, it may be affected by disturbance. In particular, the farther the capacitive portion and the differential pair are, the more the wiring between them needs to be routed over a long distance, and the more easily it is affected by disturbance.

On the other hand, in the ripple canceller 500 illustrated in FIG. 6, the gates of M pairs of transistors (positive side transistor 539 and negative side transistor 540) having different sizes are common to the positive side common capacitance 513 and the negative side common capacitance 514. Is connected to. In this configuration, the number of capacities is only two regardless of the resolution, so that the circuit scale can be reduced as compared with the comparative example.

Further, in FIG. 6, by providing switches 531 to 536 on the drain side of the transistor in the capacitance section, the size of those switches can be made smaller than that of the comparative example. This makes it possible to reduce the power consumption for driving those switches.

Further, in FIG. 6, regardless of the resolution, only three wires are required between the capacitance section and the comparator section, so that the influence of disturbance can be suppressed more than in the comparative example.

[Operation example of SARADC]
FIG. 10 is a timing chart showing an example of the operation of the SARADC200 according to the first embodiment of the present technique. The sampling clock CLK becomes a high level over the sampling period from the timing T0 to T1. Within this period, the CDAC 300 captures and retains the sampled differential signal.

Within the period from timing T1 to timing T2, the differential amplifier circuit 420 in the comparator 400 performs M comparisons in synchronization with the enable signal En_Comp. Based on the comparison result, the SAR logic circuit 220 updates the control signals Dac_p and Dac_n M times.

According to the update of the control signals Dac_p and Dac_n, the CDAC 300 switches the connection destination of the capacitance to one of the positive side reference voltage VREFP and the negative side reference voltage VREFN. At this time, a ripple component is generated in the positive side reference voltage VREFP and the negative side reference voltage VREFN. On the other hand, the positive signal line 508 and the negative signal line 509 in the ripple canceller 500 generate components of _Δp and _Δn . These Δp and _Δn remove the ripple component generated in the _CDAC300 .

FIG. 11 is an example of an overall view of the SARADC200 according to the first embodiment of the present technology. When the differential signal is input to the SARADC 200, the CDAC 300 generates an analog differential signal based on the control signal from the SAR logic circuit 220 and outputs it to the comparator 400. On the other hand, when the single-ended signal is input to the SARADC 200, the CDAC 300 generates an analog single-ended signal and outputs it to the comparator 400. In this way, the CDAC 300 generates at least one of the pair of analog signals and outputs it to the comparator 400. The CDAC300 is an example of the digital-to-analog converter described in the claims.

The comparator 400 compares the input differential signals and generates a comparison result. The latch circuit 430 holds the comparison result and supplies it to the SAR logic circuit 220. The SAR logic circuit 220 generates a control signal based on the comparison result and supplies the control signal to the CDAC 300 and the comparator unit 521 and the like. The SAR logic circuit 220 is an example of the logic circuit described in the claims.

In the ripple canceller 500, one end of the positive side common capacitance 513 is connected to the node of the positive side reference voltage VREFP, and one end of the negative side common capacitance 514 is connected to the node of the negative side reference voltage VREFN.

The sampling switches 511 and 512 open and close the path between the other ends of the positive side common capacity 513 and the negative side common capacity 514 and the node of the common voltage VCOM in synchronization with the sampling clock CLK.

Further, each gate of the M positive transistors 539 having different sizes is commonly connected to the positive common capacitance 513 via the positive signal line 508. Each gate of the M negative transistors 540 of different sizes is commonly connected to the negative common capacitance 514 via the negative signal line 509.

Each gate of M pairs of common side transistors of different sizes is commonly connected to a node with a common voltage VCOM.

The switches 531 to 536 open and close the path between the drain of each transistor such as the common side transistor and the output terminal of the comparator 400 based on the control signal.

As described above, according to the first embodiment of the present technology, since M comparator units are commonly connected to the positive side common capacity 513 and the negative side common capacity 514, a plurality of capacities are arranged for each bit. The circuit scale can be reduced as compared with.

<2. Second Embodiment>
In the first embodiment described above, the sampling switches 511 and 512 in the ripple canceller 500 performed sampling within the sampling period. It is preferable that these sampling switches 511 and 512 sample in a stable voltage state without ripple. The SARADC200 of the second embodiment is different from the first embodiment in that the sampling switches 511 and 512 perform sampling within the period from the end of conversion to the start of sampling.

FIG. 12 is an example of an overall view of the SARADC200 according to the second embodiment of the present technology. The SARADC200 of the second embodiment differs from the first embodiment in that the sampling switches 511 and 512 open and close according to the comparison completion flag Conv_End from the SAR logic circuit 220.

The SAR logic circuit 220 of the second embodiment closes the sampling switches 511 and 512 by the comparison completion flag Conv_End within the period from the end of AD (Analog to Digital) conversion to the start of sampling.

FIG. 13 is a timing chart showing an example of the operation of the SARADC200 in the second embodiment of the present technology. The SAR logic circuit 220 of the second embodiment supplies a high-level comparison completion flag Conv_End within the period from the timing T11 at the end of the AD conversion to the timing T12 at the start of the next sampling.

According to the high-level comparison completion flag Conv_End, the sampling switches 511 and 512 shift to the closed state and perform sampling.

Depending on the SARADC200, the voltage state may be more stable during the period from the end of AD conversion to the start of sampling than the sampling period. In this case, the influence of ripple can be reduced by performing the control shown in the figure.

As described above, according to the second embodiment of the present technique, the sampling switches 511 and 512 shift to the closed state within the period from the end of the AD conversion to the start of sampling, so that the voltage state becomes stable. You can sample while you are.

<3. Third Embodiment>
In the first embodiment described above, the differential pair of the nMOS transistor is arranged in the differential amplifier circuit 420 or the ripple canceller 500, but the differential pair of the pMOS transistor can be arranged instead of them. The SARADC200 of the third embodiment is different from the first embodiment in that the differential pair of the pMOS transistor is arranged instead of the differential pair of the nMOS transistor.

FIG. 14 is a circuit diagram showing a configuration example of the differential amplifier circuit 460 according to the third embodiment of the present technology. The differential amplifier circuit 460 of the third embodiment includes pMOS transistors 461 to 463 and nMOS transistors 464 and 465. The circuit configuration of the differential amplifier circuit 460 is the same as that of the differential amplifier circuit 420 illustrated in FIG. 4, except that the polarities of the respective transistors are opposite to each other. In the fourth embodiment, the differential amplifier circuit 460 starts the comparison operation when the enable signal En_Comp changes from the high level to the low level. Further, the inverter 450 is inserted in front of the positive input terminal of the differential amplifier circuit 460.

FIG. 15 is a circuit diagram showing a configuration example of the latch circuit 470 according to the third embodiment of the present technology. The latch circuit 470 of the third embodiment includes pMOS transistors 471 to 476 and nMOS transistors 477 to 480. The circuit configuration of the latch circuit 470 is the same as that of the latch circuit 430 illustrated in FIG. 13, except that the polarities of the respective transistors are opposite to each other.

FIG. 16 is a circuit diagram showing a configuration example of the ripple canceller 500 according to the third embodiment of the present technology. The ripple canceller 500 of the third embodiment has a switch transistor 551, common side transistors 552 and 552, a positive side transistor 554, a negative side transistor 555, and switches 531 to 536 in the comparator section 521. Be prepared. As these transistors, pMOS transistors are used. The same applies to the comparator section after the comparator section 522.

It should be noted that the second embodiment can be applied to the third embodiment.

As described above, according to the third embodiment of the present technique, since the differential pair of the pMOS transistor is used instead of the differential pair of the nMOS transistor, when the enable signal En_Comp changes from the high level to the low level. The comparator 400 starts the comparison operation.

<4. Fourth Embodiment>
In the first embodiment described above, the common voltage VCOM is supplied in the ripple canceller 500 in addition to the reference voltage (VREFP and VREFN), but this configuration requires a circuit to generate the common voltage VCOM. Become. Further, when the input common voltage of the SARADC200 and the VCOM are different, the ripple canceling effect may be reduced. The SARADC 200 of the fourth embodiment is different from the first embodiment in that the supply of the common voltage VCOM to the ripple canceller 500 is not required.

FIG. 17 is a circuit diagram showing a configuration example of the ripple canceller 500 according to the fourth embodiment of the present technology. The ripple canceller 500 of the fourth embodiment includes positive side common capacities 611 and 612, sampling switches 613 to 616, and negative side common capacities 617 and 618 in the capacitance unit 510.

One end of each of the positive side common capacities 611 and 612 is commonly connected to the node of the positive side reference voltage VREFP. The respective capacity values of these positive side common capacities 611 and 612 are set to half of the positive side common capacities 513 of the first embodiment. The positive side common capacities 611 and 612 are examples of the first positive side common capacity and the second positive side common capacity described in the claims.

The sampling switch 613 opens and closes the path between the other end of the common capacitance 611 on the positive side and the sampling switch 615 in synchronization with the sampling clock CLK. The sampling switch 614 opens and closes the path between the other end of the positive common capacitance 612 and the sampling switch 616 in synchronization with the sampling clock CLK.

One end of each of the negative side common capacities 617 and 618 is commonly connected to the node of the negative side reference voltage VREFN. The respective capacity values of these negative side common capacities 617 and 618 are set to half of the negative side common capacities 514 of the first embodiment. The negative side common capacities 617 and 618 are examples of the first negative side common capacity and the second negative side common capacity described in the claims.

The sampling switch 615 opens and closes the path between the other end of the negative common capacitance 617 and the sampling switch 613 in synchronization with the sampling clock CLK. The sampling switch 616 opens and closes the path between the other end of the negative common capacitance 618 and the sampling switch 614 in synchronization with the sampling clock CLK.

Further, the connection node of the positive side common capacitance 611 and the sampling switch 613 is connected to the positive side signal line 501, and the connection node of the positive side common capacitance 612 and the sampling switch 614 is connected to the positive side signal line 502.

Further, the connection nodes of the sampling switches 613 and 615 are connected to the common signal line 503, and the connection nodes of the sampling switches 614 and 616 are connected to the common signal line 504. The common signal line 503 is connected to the positive input terminal of the comparator 400 (that is, the positive output terminal of the CDAC 300), and _{Vcdac_p} is supplied. The common signal line 504 is connected to the negative input terminal of the comparator 400 (that is, the negative output terminal of the CDAC 300), and _{Vcdac_n} is supplied.

Further, the connection node of the negative side common capacity 617 and the sampling switch 615 is connected to the negative side signal line 505, and the connection node of the negative side common capacity 618 and the sampling switch 616 is connected to the negative side signal line 506.

FIG. 18 is a circuit diagram showing a configuration example of the comparator section 521 according to the fourth embodiment of the present technology. In the comparator section 521 of the fourth embodiment, the common side transistors 621 to 624 are arranged in place of the common side transistors 537 and 538. Further, the positive transistor 625 and 626 are arranged in place of the positive transistor 539, and the negative transistors 627 and 628 are arranged in place of the negative transistor 540. The size of each of the transistors in the fifth embodiment is set to half that of the first embodiment. The size of each transistor of the comparator section 521, 522, 523, 524 and 525 is set to "8", "4", "2", "1" and "1/2".

Further, the drains of the common side transistors 621 and 622 are connected to the switch 531 and their gates are connected to the common signal line 503. The drains of the common side transistors 623 and 624 are connected to the switch 532, and their gates are connected to the common signal line 504.

The common- side transistors 621 and 622 are examples of the first common-side transistor described in the claims, and the common- side transistors 623 and 624 are examples of the second common-side transistors described in the claims. be.

The drains of the positive transistors 625 and 626 are connected to both switches 533 and 534. The gate of the positive transistor 625 is connected to the positive signal line 501, and the gate of the positive transistor 626 is connected to the positive signal line 502. The positive transistor 625 and 626 are examples of the first positive transistor and the second positive transistor described in the claims.

The drains of the negative transistors 627 and 628 are connected to both switches 535 and 536. The gate of the negative transistor 627 is connected to the negative signal line 505, and the gate of the negative transistor 628 is connected to the negative signal line 506. The negative transistor 627 and 628 are examples of the first negative transistor and the second negative transistor described in the claims.

When the switches 531 and 532 on the common side are in the closed state, the four transistors on the common side perform a discharge operation. Assuming that the transconductance of a transistor having a size of 8/32 (= 1/4) is 1/4 × _gm , the current _Ic flowing through the switches 531 and 532 is expressed by the following equation.
I _c = (g _m / 4) × (V _{cdac_p} + V _{cdac_n} )
= ( _{Gm / 2) × (V cdac_com )}・ ・ ・ Equation 3

Here, V _{cdac_com} is equal to the common voltage of V _{cadc_p} and V _{cadc_n} , which are differential signals. If V _{cdac_com} = VCOM, then _Ic is the same as the current that the common side transistors 537 and 538 of the first embodiment try to pass. As described above, even when there is no common voltage VCOM, it is possible to pass a current equivalent to that of the first embodiment, and a desired circuit operation can be realized.

On the other hand, even when one of the switches 533 and 534 and one of the switches 535 and 536 are in the closed state, the transistors to which they are connected perform the discharge operation at the timing of the comparative operation. At this time, the current flowing through the switch on the drain side is expressed by the following equations.
I _p = (g _m / 4) × (V _{cdac_p} + V _{cdac_n} + 2 × Δ _p )
= ( _{Gm / 2) × (V cdac_com +} Δ _p ) ・ ・ ・ Equation 4
In ₌ (g _m / 4) × (V _{cdac_p} + V _{cdac_n} + 2 × Δ _n )
= ( _{Gm / 2) × (V cdac_com +} Δ _n ) ・ ・ ・ Equation 5

Δp and Δn of Equations 4 and 5 are ripple components generated in the positive reference voltage _VREFP and the negative reference voltage _VREFN , respectively. If V _{cdac_com =} VCOM, the currents _Ic and In are the same as the currents that the positive and negative transistors of the first embodiment try to flow. As described above, even when there is no common voltage VCOM, it is possible to pass a current equivalent to that of the first embodiment, and a desired circuit operation can be realized.

It should be noted that the second and third embodiments can be applied to the fourth embodiment.

Thus, according to the fourth embodiment of the present technique, each of the transistors is separated into two halves in size, and each of the capacitances is separated into two halves in capacitance value. Since the current equivalent to that of the embodiment is generated, the common voltage VCOM becomes unnecessary.

<5. Application example to mobile>
The technique according to the present disclosure (the present technique) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on a moving body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.

FIG. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technique according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001. In the example shown in FIG. 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 has a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating braking force of the vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, turn signals or fog lamps. In this case, the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches. The body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.

The outside information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image pickup unit 12031 is connected to the vehicle outside information detection unit 12030. The vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The out-of-vehicle information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or a character on the road surface based on the received image.

The image pickup unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received. The image pickup unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the image pickup unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects the in-vehicle information. For example, a driver state detection unit 12041 that detects a driver's state is connected to the vehicle interior information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether or not the driver has fallen asleep.

The microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.

Further, the microcomputer 12051 controls the driving force generating device, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the outside information detection unit 12030 or the inside information detection unit 12040, so that the driver can control the driver. It is possible to perform coordinated control for the purpose of automatic driving that runs autonomously without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.

The audio image output unit 12052 transmits an output signal of at least one of audio and an image to an output device capable of visually or audibly notifying information to the passenger or the outside of the vehicle. In the example of FIG. 19, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

FIG. 20 is a diagram showing an example of the installation position of the image pickup unit 12031.

In FIG. 20, as the image pickup unit 12031, the image pickup unit 12101, 12102, 12103, 12104, 12105 is provided.

The image pickup units 12101, 12102, 12103, 12104, 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100. The image pickup unit 12101 provided on the front nose and the image pickup section 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The image pickup units 12102 and 12103 provided in the side mirror mainly acquire images of the side of the vehicle 12100. The image pickup unit 12104 provided in the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100. The image pickup unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

Note that FIG. 20 shows an example of the shooting range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging range of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and the imaging range 12114 indicates the imaging range. The imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 can be obtained.

At least one of the image pickup units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image pickup units 12101 to 12104 may be a stereo camera including a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.

For example, the microcomputer 12051 has a distance to each three-dimensional object within the image pickup range 12111 to 12114 based on the distance information obtained from the image pickup unit 12101 to 12104, and a temporal change of this distance (relative speed with respect to the vehicle 12100). By obtaining can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform coordinated control for the purpose of automatic driving or the like that autonomously travels without relying on the driver's operation.

For example, the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles, and other three-dimensional objects based on the distance information obtained from the image pickup units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.

At least one of the image pickup units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging unit 12101 to 12104. Such recognition of a pedestrian is, for example, a procedure for extracting feature points in an image captured by an image pickup unit 12101 to 12104 as an infrared camera, and pattern matching processing is performed on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine. When the microcomputer 12051 determines that a pedestrian is present in the captured image of the image pickup unit 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 determines the square contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

The above is an example of a vehicle control system to which the technique according to the present disclosure can be applied. The technique according to the present disclosure can be applied to, for example, the image pickup unit 12031 among the configurations described above. Specifically, the electronic device 100 of FIG. 1 can be applied to the image pickup unit 12031. By applying the technique according to the present disclosure to the image pickup unit 12031, the circuit scale thereof can be reduced.

It should be noted that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention within the scope of claims have a corresponding relationship with each other. Similarly, the matters specifying the invention within the scope of claims and the matters in the embodiment of the present technology having the same name have a corresponding relationship with each other. However, the present technique is not limited to the embodiment, and can be embodied by applying various modifications to the embodiment without departing from the gist thereof.

It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.

The present technology can have the following configurations.
(1) A digital-to-analog converter that generates at least one of a pair of analog signals according to a predetermined control signal.
A comparator that compares the pair of analog signals, generates a comparison result, and outputs the comparison result.
A logic circuit that generates the control signal based on the comparison result,
With multiple positive transistors of different sizes,
With multiple negative transistors of different sizes,
A plurality of switches that open and close the path between one of the sources and drains of the plurality of positive transistors and the plurality of negative transistors and the output terminal of the comparator based on the control signal.
A positive common capacitance with one end connected to a node with a predetermined positive reference voltage and the other end connected to the gates of each of the plurality of positive transistors.
An analog-to-digital converter having one end connected to a node having a negative reference voltage lower than the positive reference voltage and the other end connected in common to each gate of the plurality of negative transistors. ..
(2) The pair of analog signals are differential signals.
The digital-to-analog converter is the analog-to-digital converter according to (1) above, which generates the differential signal.
(3) Further provided with a sampling switch that opens and closes a path between the other end of each of the positive side common capacitance and the negative side common capacitance and the common voltage between the positive side reference voltage and the negative side reference voltage. The analog-to-digital converter according to (1) or (2) above.
(4) The analog-to-digital converter according to (3) above, wherein the sampling switch shifts to a closed state within a predetermined sampling period.
(5) The analog-digital converter according to (3) above, wherein the sampling switch shifts to a closed state within a period from the end of analog-digital conversion to the start of sampling.
(6) The analog-to-digital converter according to any one of (1) to (5) above, further comprising a latch circuit that holds the comparison result and supplies the logic circuit.
(7) The analog-to-digital converter according to any one of (1) to (6) above, wherein each of the plurality of positive side transistors and the plurality of negative side transistors is an nMOS transistor.
(8) The analog-to-digital converter according to any one of (1) to (6) above, wherein each of the plurality of positive side transistors and the plurality of negative side transistors is a pMOS transistor.
(9) A plurality of pairs of common-side transistors having different sizes are further provided.
The analog according to any one of (1) to (8) above, wherein each gate of the plurality of pairs of common side transistors is connected to a node having a common voltage between the positive side reference voltage and the negative side reference voltage. Digital converter.
(10) Multiple pairs of first common side transistors of different sizes,
Further equipped with a plurality of pairs of second common side transistors of different sizes,
The positive side common capacity includes a first positive side common capacity and a second positive side common capacity.
The negative side common capacity includes a first negative side common capacity and a second negative side common capacity.
The plurality of positive transistors are
Multiple first positive transistors of different sizes,
Includes multiple second positive transistors of different sizes
The plurality of negative transistors are
Multiple first negative transistors of different sizes,
Includes multiple second negative transistors of different sizes
Each gate of the plurality of first positive transistor is connected in common to the common capacitance on the first positive side.
Each gate of the plurality of second positive transistors is commonly connected to the second positive common capacitance.
Each gate of the plurality of first negative transistors is commonly connected to the first negative common capacitance.
The analog-to-digital converter according to any one of (1) to (8), wherein each gate of the plurality of second negative transistors is commonly connected to the second negative common capacitance.
(11) A digital-to-analog converter that generates at least one of a pair of analog signals according to a predetermined control signal.
A comparator that compares the pair of analog signals, generates a comparison result, and outputs the comparison result.
A logic circuit that generates the control signal and outputs a digital signal based on the comparison result,
With multiple positive transistors of different sizes,
With multiple negative transistors of different sizes,
A plurality of switches that open and close the path between one of the sources and drains of the plurality of positive transistors and the plurality of negative transistors and the output terminal of the comparator based on the control signal.
A positive common capacitance with one end connected to a node with a predetermined positive reference voltage and the other end connected to the gates of each of the plurality of positive transistors.
A negative-side common capacitance having one end connected to a node having a negative reference voltage lower than the positive-side reference voltage and the other end connected to each gate of the plurality of negative-side transistors.
An electronic device including a digital signal processing circuit for processing the digital signal.

100 Electronic equipment 110 Analog signal generator 120 Digital signal processor 200 SARADC
211, 212, 511, 512, 613-616 Sampling switch 220 SAR logic circuit 300 CDAC
311 to 316 Positive side capacity 317 to 322 Negative side capacity 330 Positive side switching unit 331 to 336 Positive side switching circuit 340 Negative side switching unit 341 to 346 Negative side switching circuit 351 to 353 Negative side switching circuit 351 to 536 Switch 400 Comparator 410 Enable control Part 411 Inverter 412 NOR (negative logical sum) gate 413 AND (logical product) gate 420, 460 differential amplification circuit 421, 422, 431 to 434, 461 to 463, 471 to 476 pMOS transistor 423 to 425, 435 to 440, 464, 465, 477 to 480 nMOS transistor 430, 470 Latch circuit 500 Ripple canceller 510 Capacity part 513, 611, 612 Positive side common capacity 514, 617, 618 Negative side common capacity 521 to 525 Comparator part 537, 538, 552, 552 , 621-624 Common side transistor 537, 554, 625, 626 Positive side transistor 540, 555, 627, 628 Negative side transistor 541, 551 Switch transistor 12031 Imaging unit

Claims (11)

1. A digital-to-analog converter that produces at least one of a pair of analog signals according to a given control signal.
   A comparator that compares the pair of analog signals, generates a comparison result, and outputs the comparison result.
   A logic circuit that generates the control signal based on the comparison result,
   With multiple positive transistors of different sizes,
   With multiple negative transistors of different sizes,
   A plurality of switches that open and close the path between one of the sources and drains of the plurality of positive transistors and the plurality of negative transistors and the output terminal of the comparator based on the control signal.
   A positive common capacitance with one end connected to a node with a predetermined positive reference voltage and the other end connected to the gates of each of the plurality of positive transistors.
   An analog-to-digital converter having one end connected to a node having a negative reference voltage lower than the positive reference voltage and the other end connected in common to each gate of the plurality of negative transistors. ..
2. The pair of analog signals are differential signals and are
   The analog-to-analog converter according to claim 1, wherein the digital-to-analog converter is used to generate the differential signal.
3. A claim further comprising a sampling switch that opens and closes a path between the other end of each of the positive side common capacitance and the negative side common capacitance and the common voltage between the positive side reference voltage and the negative side reference voltage. 1. The analog-to-digital converter according to 1.
4. The analog-to-digital converter according to claim 3, wherein the sampling switch shifts to a closed state within a predetermined sampling period.
5. The analog-to-digital converter according to claim 3, wherein the sampling switch shifts to a closed state within a period from the end of analog-to-digital conversion to the start of sampling.
6. The analog-to-digital converter according to claim 1, further comprising a latch circuit that holds the comparison result and supplies the logic circuit.
7. The analog-to-digital converter according to claim 1, wherein each of the plurality of positive-side transistors and the plurality of negative-side transistors is an nMOS transistor.
8. The analog-to-digital converter according to claim 1, wherein each of the plurality of positive-side transistors and the plurality of negative-side transistors is a pMOS transistor.
9. Further equipped with multiple pairs of common side transistors of different sizes,
   The analog-to-digital converter according to claim 1, wherein each gate of the plurality of pairs of common side transistors is connected to a node having a common voltage between the positive side reference voltage and the negative side reference voltage.
10. Multiple pairs of first common side transistors of different sizes,
    Further equipped with a plurality of pairs of second common side transistors of different sizes,
    The positive side common capacity includes a first positive side common capacity and a second positive side common capacity.
    The negative side common capacity includes a first negative side common capacity and a second negative side common capacity.
    The plurality of positive transistors are
    Multiple first positive transistors of different sizes,
    Includes multiple second positive transistors of different sizes
    The plurality of negative transistors are
    Multiple first negative transistors of different sizes,
    Includes multiple second negative transistors of different sizes
    Each gate of the plurality of first positive transistor is connected in common to the common capacitance on the first positive side.
    Each gate of the plurality of second positive transistors is commonly connected to the second positive common capacitance.
    Each gate of the plurality of first negative transistors is commonly connected to the first negative common capacitance.
    The analog-to-digital converter according to claim 1, wherein each gate of the plurality of second negative transistors is commonly connected to the second negative common capacitance.
11. A digital-to-analog converter that produces at least one of a pair of analog signals according to a given control signal.
    A comparator that compares the pair of analog signals, generates a comparison result, and outputs the comparison result.
    A logic circuit that generates the control signal and outputs a digital signal based on the comparison result,
    With multiple positive transistors of different sizes,
    With multiple negative transistors of different sizes,
    A plurality of switches that open and close the path between one of the sources and drains of the plurality of positive transistors and the plurality of negative transistors and the output terminal of the comparator based on the control signal.
    A positive common capacitance with one end connected to a node with a predetermined positive reference voltage and the other end connected to the gates of each of the plurality of positive transistors.
    A negative-side common capacitance having one end connected to a node having a negative reference voltage lower than the positive-side reference voltage and the other end connected to each gate of the plurality of negative-side transistors.
    An electronic device including a digital signal processing circuit for processing the digital signal.

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