WO2022134155A1 - Method for manufacturing three-dimensional ferroelectric memory device - Google Patents

Method for manufacturing three-dimensional ferroelectric memory device Download PDF

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WO2022134155A1
WO2022134155A1 PCT/CN2020/140981 CN2020140981W WO2022134155A1 WO 2022134155 A1 WO2022134155 A1 WO 2022134155A1 CN 2020140981 W CN2020140981 W CN 2020140981W WO 2022134155 A1 WO2022134155 A1 WO 2022134155A1
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layer
memory device
gate
substrate
manufacturing
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French (fr)
Chinese (zh)
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孔繁生
周华
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光华临港工程应用技术研发(上海)有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

Definitions

  • the invention relates to the field of electronic storage, in particular to a manufacturing method of a three-dimensional ferroelectric storage device.
  • Ferroelectric memory uses the ferroelectric effect of ferroelectric materials under the action of an external electric field to store information. Ferroelectric memories are widely used in small devices in the consumer field because they have an almost infinite write life and can be stored quickly with very low power requirements.
  • FIG. 1 shows a schematic circuit diagram of an exemplary ferroelectric memory cell 100 .
  • the ferroelectric memory cell 100 is a memory element of a ferroelectric memory device, and may include various designs and configurations.
  • the ferroelectric memory cell 100 is a “1T-1C” cell, which includes a capacitor 102 and a transistor 104 .
  • Transistor 104 is an NMOS transistor.
  • the source S of the transistor 104 is electrically connected to the bit line BL.
  • the gate of transistor 104 is electrically connected to word line WL.
  • the drain D of the transistor 104 is electrically connected to the lower electrode 112 of the capacitor 102 .
  • the upper electrode 110 of the capacitor 102 is connected to the plate line PL.
  • the present invention provides a method for manufacturing a three-dimensional ferroelectric memory device, comprising:
  • a ferroelectric capacitor is formed on the drain.
  • the ferroelectric capacitor includes a first electrode layer, a ferroelectric material layer and a second electrode layer in sequence from bottom to top.
  • the ferroelectric material layer includes HfO 2 or CuInP 2 S 6 .
  • the method further includes: forming a gate dielectric layer on the sidewall of the hole.
  • nanowires include polysilicon.
  • the method further includes: forming an isolation layer on the substrate.
  • forming the gate on the substrate includes:
  • the gate material layer is patterned to form a gate.
  • ferroelectric capacitor after forming the ferroelectric capacitor, it also includes:
  • a conductive material is filled in the openings to form interconnect structures in contact with the source electrodes and the gate electrodes, respectively.
  • the manufacturing method of the three-dimensional ferroelectric memory device further includes repeating the above steps to form a multi-layer stacked memory device structure.
  • the three-dimensional ferroelectric memory device is constructed by vertical nanowire surrounding gate (GAA), the die size of the three-dimensional ferroelectric memory device is reduced, the power consumption is reduced, and the avoidance of problems such as signal propagation delay.
  • GAA vertical nanowire surrounding gate
  • Figure 1 shows a schematic circuit diagram of an exemplary ferroelectric memory cell
  • FIG. 2 is a flowchart of a method for manufacturing a three-dimensional ferroelectric memory device according to an embodiment of the present invention
  • 3A-3E are schematic cross-sectional views of devices respectively obtained by sequentially performing steps of a method according to an embodiment of the present invention.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown may be expected due to, for example, manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
  • the present invention provides a manufacturing method of a three-dimensional ferroelectric memory device, as shown in FIG. 2 and FIGS. 3A-3E, including:
  • Step S201 providing a substrate 300
  • Step S202 Doping the substrate 300 to form the source electrode 310;
  • Step S203 forming a gate electrode 342 on the substrate 300;
  • Step S204 forming an interlayer dielectric layer 352 covering the substrate 300;
  • Step S205 patterning the interlayer dielectric layer 352 and the gate electrode 342 to form a hole exposing the source electrode 310 ;
  • Step S206 depositing a channel material layer in the hole to form several nanowires 330 surrounded by the gate 342;
  • Step S207 Doping the channel material layer to form the drain electrode 320;
  • Step S208 forming a ferroelectric capacitor on the drain 320 .
  • step S201 is performed, as shown in FIG. 3A , a substrate 300 is provided.
  • the substrate 300 may be at least one of the following materials: single crystal silicon, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI) ), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.
  • the substrate 300 is a silicon substrate.
  • step S202 is performed, as shown in FIG. 3A , the substrate 300 is doped to form a source electrode 310 .
  • a protective layer and/or a mask layer may be formed on the substrate 300 first, then ion implantation is performed to form the source electrode 310, and the protective layer and/or the protective layer are removed after the ion implantation. / or mask layer.
  • the energy, dose and depth of the ion implantation can be selected according to actual needs, and are not limited to a certain numerical range.
  • a patterned mask layer is formed on the substrate 300 to expose the region where the source electrode 310 needs to be formed;
  • ion implantation is performed using the mask layer as a mask, and the implanted ions are N-type ions to form the source electrode 310 .
  • the implanted ion energy is 1kev-10kev
  • the implanted ion dose is 5 ⁇ 10 14 -5 ⁇ 10 16 atoms/cm 2 .
  • step S203 is performed, as shown in FIG. 3A , a gate electrode 342 is formed on the substrate 300 .
  • an isolation layer 351 is formed on the substrate 300, and the isolation layer 351 may use an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, such as polyvinyl phenol, An insulating layer such as polyimide or siloxane is formed.
  • the isolation layer 351 can be deposited by using low pressure chemical vapor deposition (LPCVD), laser ablation, etc. formed by chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method, or atomic layer deposition (ALD) method.
  • LPCVD low pressure chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • a gate material layer is formed on the isolation layer 351, and the gate material layer includes one of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer and a metal silicide layer or variety.
  • the method for forming the gate material layer may adopt any prior art familiar to those skilled in the art, and details are not described herein again.
  • the gate material layer is patterned.
  • a mask layer (not shown) is formed on the gate material layer, and a gate pattern is formed on the mask layer; then the gate material is etched by using the mask layer as a mask layer to transfer the pattern into the gate material layer to form gate 342 .
  • the method of patterning the gate material layer may be dry etching or wet etching. Dry etching processes include, but are not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may be used.
  • the source gas for dry etching may include HBr and/or CF 4 gas.
  • step S204 is performed, as shown in FIG. 3B , an interlayer dielectric layer 352 covering the substrate 300 is formed.
  • the interlayer dielectric layer 352 and the above-mentioned isolation layer 351 can be made of the same material and formed by the same method, and details are not described herein again.
  • step S205 is performed, as shown in FIG. 3B , the interlayer dielectric layer 352 and the gate electrode 342 are patterned to form a hole exposing the source electrode 310 .
  • a mask layer (not shown) is formed on the interlayer dielectric layer 352, and a channel pattern is formed on the mask layer; then the layer is etched by using the mask layer as a mask
  • the inter-dielectric layer 352 , the gate electrode 342 and the isolation layer 351 are formed to form a hole exposing the source electrode 310 , as shown in FIG. 3B .
  • the method for patterning the interlayer dielectric layer 352 , the gate electrode 342 and the isolation layer 351 may adopt any prior art familiar to those skilled in the art, and details are not described herein again.
  • step S206 is performed. As shown in FIG. 3C , a channel material layer is deposited in the hole to form a plurality of nanowires 330 surrounded by the gate electrode 342 .
  • a gate dielectric layer 341 is formed on the sidewalls of the holes.
  • the gate dielectric layer 341 includes an oxide layer, such as a silicon dioxide (SiO 2 ) layer.
  • the method for forming the gate dielectric layer may adopt any prior art familiar to those skilled in the art, including physical vapor deposition (PVD) and chemical vapor deposition (CVD), preferably chemical vapor deposition (CVD), Such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • LTCVD low temperature chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • RTCVD rapid thermal chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the channel material layer includes, but is not limited to, polysilicon.
  • the method for forming the polysilicon nanowires 330 may be a low pressure chemical vapor deposition (LPCVD) process.
  • the process conditions for forming the polysilicon layer include: the reaction gas is silane (SiH 4 ), and the flow rate of the silane can range from 100 to 200 cubic centimeters per minute (sccm), such as 130 sccm; the temperature in the reaction chamber can range from 700 to 700 to 750 degrees Celsius; the pressure in the reaction chamber can be 250-350mTorr, such as 300mTorr; the reaction gas can also include a buffer gas, the buffer gas can be helium (He) or nitrogen, and the flow range of the helium and nitrogen It can be 5 to 20 liters per minute (slm), such as 8 slm, 10 slm or 15 slm.
  • sccm cubic centimeters per minute
  • sccm cubic centimeters per minute
  • the temperature in the reaction chamber can range from 700 to 700 to
  • step S207 is performed, as shown in FIG. 3D , the channel material layer is doped to form the drain electrode 320 .
  • ion implantation is performed on the channel material layer to form the drain electrode 320 .
  • the energy, dose and depth of the ion implantation can be selected according to actual needs, and are not limited to a certain numerical range.
  • the implanted ions are N-type ions.
  • the step of performing annealing is also included after forming the drain.
  • the annealing temperature is 200-500° C.
  • the thermal annealing step time is 1-200 s, but it is not limited to the numerical range.
  • step S208 is performed, as shown in FIG. 3E , a ferroelectric capacitor is formed on the drain 320 .
  • the ferroelectric capacitor includes a first electrode layer 371 , a ferroelectric material layer 372 and a second electrode layer 373 in sequence from bottom to top.
  • the first electrode layer 371 and the second electrode layer 373 serve as the plates of the ferroelectric capacitor, and can be made of common electrode materials of ferroelectric capacitors such as TiN and Pt.
  • the deposition method of the first electrode layer 371 and the second electrode layer 373 may be a low pressure chemical vapor deposition (LPCVD) method formed by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, or an atomic layer deposition (ALD) method. ), laser ablation deposition (LAD) and selective epitaxial growth (SEG), preferably in the present invention a physical vapor deposition (PVD) method.
  • LPCVD low pressure chemical vapor deposition
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • LAD laser ablation
  • ferroelectric materials can exhibit spontaneous polarization in the absence of an external electric field.
  • the polarization can be redirected by ionic displacement in the crystal, and polarization switching can be triggered by an external electric field, so that the ferroelectric material can have two electrically controlled nonvolatile states.
  • the ferroelectric material layer includes, but is not limited to, HfO 2 or CuInP 2 S 6 .
  • FIG. 3F it also includes the step of forming an interconnect structure in contact with the source electrode 310 and the gate electrode 342:
  • the interlayer dielectric layer 352 is patterned to form a first opening that exposes the gate electrode 342; in this step, the interlayer dielectric layer 352 and the isolation layer are further patterned 351 to form a second opening that leads out of the source electrode 310 .
  • the first opening is filled with conductive material to form a first interconnect structure 361 to be electrically connected to the gate electrode 342, while the second opening is filled with conductive material to form a second interconnect structure 362, which is connected to the gate electrode 342.
  • the source electrode 310 is electrically connected.
  • the interconnect structure is made of conductive materials, including but not limited to tungsten (W), aluminum (Al), copper (Cu).
  • the above steps are described by taking the example of forming a single-layer memory cell layer, wherein the memory cell layer includes several memory cells, and each memory cell includes a transistor including nanowires and a ferroelectric capacitor connected thereto.
  • the present invention also includes repeating the above steps to form a multi-layer stacked memory device structure. That is, a silicon material layer is deposited again as a substrate on the above-mentioned memory cell layer, and then steps such as nanowires, gates, drains, and ferroelectric capacitors are formed to form a three-dimensional stacked memory device structure, which includes several layers of the above-mentioned memory cells.
  • Floor the above steps are described by taking the example of forming a single-layer memory cell layer, wherein the memory cell layer includes several memory cells, and each memory cell includes a transistor including nanowires and a ferroelectric capacitor connected thereto.
  • the present invention also includes repeating the above steps to form a multi-layer stacked memory device structure. That is, a silicon material layer is deposited again as
  • the three-dimensional ferroelectric memory device is constructed by vertical nanowire surrounding gate (GAA), the die size of the three-dimensional ferroelectric memory device is reduced, the power consumption is reduced, and the avoidance of problems such as signal propagation delay.
  • GAA vertical nanowire surrounding gate

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Abstract

Disclosed is a method for manufacturing a three-dimensional ferroelectric memory device. The method comprises: providing a substrate; doping the substrate to form a source electrode; forming a plurality of nanowires on the substrate, wherein the extension direction of the nanowires is perpendicular to the substrate; forming a gate electrode material layer on the substrate; patterning the gate electrode material layer to form a gate electrode surrounding the nanowires; forming a drain electrode on the nanowires; and forming a ferroelectric capacitor, wherein the ferroelectric capacitor is electrically connected to the drain electrode. According to the method for manufacturing a three-dimensional ferroelectric memory device provided in the present invention, the three-dimensional ferroelectric memory device is constructed by means of a gate-all-around (GAA)-vertical-nanowire, so that the size of a tube core of the three-dimensional ferroelectric memory device is reduced, the power consumption is reduced, and the problems of signal propagation delay, etc., are avoided.

Description

一种三维铁电存储器件的制造方法A kind of manufacturing method of three-dimensional ferroelectric memory device
说明书manual
技术领域technical field
本发明涉及电子存储领域，具体而言涉及一种三维铁电存储器件的制造方法。The invention relates to the field of electronic storage, in particular to a manufacturing method of a three-dimensional ferroelectric storage device.
背景技术Background technique
铁电存储器(FeRAM)是利用铁电材料在外电场作用下的铁电效应来进行信息存储的。由于铁电存储器有近乎无限次的写入寿命，且能够在非常低的电能需求下快速地存储，因此，在消费领域的小型设备中得到广泛地应用。Ferroelectric memory (FeRAM) uses the ferroelectric effect of ferroelectric materials under the action of an external electric field to store information. Ferroelectric memories are widely used in small devices in the consumer field because they have an almost infinite write life and can be stored quickly with very low power requirements.
图1示出了示例性铁电存储单元100的电路示意图。铁电存储单元100是铁电存储器件的存储元件，并且可以包括各种设计和配置。如图1所示，铁电存储单元100是“1T-1C”单元，其包括电容器102和晶体管104。晶体管104为NMOS晶体管。晶体管104的源极S电连接到位线BL。晶体管104的栅极电连接到字线WL。晶体管104的漏极D电连接到电容器102的下电极112。电容器102的上电极110连接到板线PL。FIG. 1 shows a schematic circuit diagram of an exemplary ferroelectric memory cell 100 . The ferroelectric memory cell 100 is a memory element of a ferroelectric memory device, and may include various designs and configurations. As shown in FIG. 1 , the ferroelectric memory cell 100 is a “1T-1C” cell, which includes a capacitor 102 and a transistor 104 . Transistor 104 is an NMOS transistor. The source S of the transistor 104 is electrically connected to the bit line BL. The gate of transistor 104 is electrically connected to word line WL. The drain D of the transistor 104 is electrically connected to the lower electrode 112 of the capacitor 102 . The upper electrode 110 of the capacitor 102 is connected to the plate line PL.
近年来，为了满足大量数据存储的发展需求，存储器件的制造技术已从平面二维集成转为三维集成。因此，有必要提出一种新的三维铁电存储器件的制造方法。In recent years, in order to meet the development needs of large-scale data storage, the manufacturing technology of memory devices has shifted from planar two-dimensional integration to three-dimensional integration. Therefore, it is necessary to propose a new fabrication method of three-dimensional ferroelectric memory devices.
发明内容SUMMARY OF THE INVENTION
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。A series of concepts in simplified form have been introduced in the Summary section, which are described in further detail in the Detailed Description section. The Summary of the Invention section of the present invention is not intended to attempt to limit the key features and essential technical features of the claimed technical solution, nor is it intended to attempt to determine the protection scope of the claimed technical solution.
本发明提供了一种三维铁电存储器件的制造方法，包括：The present invention provides a method for manufacturing a three-dimensional ferroelectric memory device, comprising:
提供衬底；provide a substrate;
对所述衬底进行掺杂，以形成源极；doping the substrate to form a source;
在所述衬底上形成栅极；forming a gate on the substrate;
形成覆盖所述衬底的层间介电层；forming an interlayer dielectric layer overlying the substrate;
图案化所述层间介电层和所述栅极，以形成露出所述源极的孔洞；patterning the interlayer dielectric layer and the gate to form a hole exposing the source;
在所述孔洞中沉积沟道材料层，以形成所述栅极环绕的数条纳米线；depositing a layer of channel material in the hole to form a plurality of nanowires surrounding the gate;
对所述沟道材料层进行掺杂，以形成漏极；doping the channel material layer to form a drain;
在所述漏极上形成铁电电容器。A ferroelectric capacitor is formed on the drain.
进一步，所述铁电电容器由下至上依次包括第一电极层，铁电材料层和第二电极层。Further, the ferroelectric capacitor includes a first electrode layer, a ferroelectric material layer and a second electrode layer in sequence from bottom to top.
进一步，所述铁电材料层包括HfO 2或CuInP 2S 6。 Further, the ferroelectric material layer includes HfO 2 or CuInP 2 S 6 .
进一步，在所述孔洞中沉积所述沟道材料层之前还包括：在所述孔洞的侧壁上形成栅极介电层。Further, before depositing the channel material layer in the hole, the method further includes: forming a gate dielectric layer on the sidewall of the hole.
进一步，所述纳米线包括多晶硅。Further, the nanowires include polysilicon.
进一步，在所述衬底上形成栅极之前还包括：在所述衬底上形成隔离层。Further, before forming the gate electrode on the substrate, the method further includes: forming an isolation layer on the substrate.
进一步，在所述衬底上形成栅极包括：Further, forming the gate on the substrate includes:
在所述隔离层上形成栅极材料层；forming a gate material layer on the isolation layer;
图案化所述栅极材料层，以形成栅极。The gate material layer is patterned to form a gate.
进一步，在形成所述铁电电容器之后还包括：Further, after forming the ferroelectric capacitor, it also includes:
图案化所述层间介电层，以分别形成露出所述源极和所述栅极的开口；patterning the interlayer dielectric layer to form openings exposing the source electrode and the gate electrode, respectively;
在所述开口中填充导电材料，以分别形成与所述源极和所述栅极相接的互连结构。A conductive material is filled in the openings to form interconnect structures in contact with the source electrodes and the gate electrodes, respectively.
进一步，所述三维铁电存储器件的制造方法还包括重复上述步骤，以形成多层层叠的存储器件结构。Further, the manufacturing method of the three-dimensional ferroelectric memory device further includes repeating the above steps to form a multi-layer stacked memory device structure.
根据本发明提供的三维铁电存储器件的制造方法，通过垂直纳米线环绕栅极(GAA)构建三维铁电存储器件，减小了三维铁电存储器件的管芯尺寸，降低了功耗，避免了信号传播延迟等问题。According to the manufacturing method of the three-dimensional ferroelectric memory device provided by the present invention, the three-dimensional ferroelectric memory device is constructed by vertical nanowire surrounding gate (GAA), the die size of the three-dimensional ferroelectric memory device is reduced, the power consumption is reduced, and the avoidance of problems such as signal propagation delay.
附图说明Description of drawings
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。The following drawings of the present invention are incorporated herein as a part of the present invention for understanding of the present invention. The accompanying drawings illustrate embodiments of the present invention and their description, which serve to explain the principles of the present invention.
附图中：In the attached picture:
图1示出了示例性铁电存储单元的电路示意图；Figure 1 shows a schematic circuit diagram of an exemplary ferroelectric memory cell;
图2为根据本发明的一个实施例的三维铁电存储器件的制造方法的流程图；2 is a flowchart of a method for manufacturing a three-dimensional ferroelectric memory device according to an embodiment of the present invention;
图3A-3E为根据本发明的一个实施例的方法依次实施的步骤所分别获得的器件的示意性剖面图。3A-3E are schematic cross-sectional views of devices respectively obtained by sequentially performing steps of a method according to an embodiment of the present invention.
具体实施方式Detailed ways
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features known in the art have not been described in order to avoid obscuring the present invention.
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。It should be understood that the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers Layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式， 除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown may be expected due to, for example, manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
为了彻底理解本发明，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。For a thorough understanding of the present invention, detailed steps and detailed structures will be proposed in the following description to explain the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
本发明提供了一种三维铁电存储器件的制造方法，如图2和图3A-3E所示，包括：The present invention provides a manufacturing method of a three-dimensional ferroelectric memory device, as shown in FIG. 2 and FIGS. 3A-3E, including:
步骤S201：提供衬底300；Step S201: providing a substrate 300;
步骤S202：对所述衬底300进行掺杂，以形成源极310；Step S202: Doping the substrate 300 to form the source electrode 310;
步骤S203：在所述衬底300上形成栅极342；Step S203: forming a gate electrode 342 on the substrate 300;
步骤S204：形成覆盖所述衬底300的层间介电层352；Step S204: forming an interlayer dielectric layer 352 covering the substrate 300;
步骤S205：图案化所述层间介电层352和所述栅极342，以形成露出所述源极310的孔洞；Step S205 : patterning the interlayer dielectric layer 352 and the gate electrode 342 to form a hole exposing the source electrode 310 ;
步骤S206：在所述孔洞中沉积沟道材料层，以形成所述栅极342环绕的数条纳米线330；Step S206: depositing a channel material layer in the hole to form several nanowires 330 surrounded by the gate 342;
步骤S207：对所述沟道材料层进行掺杂，以形成漏极320；Step S207: Doping the channel material layer to form the drain electrode 320;
步骤S208：在所述漏极320上形成铁电电容器。Step S208 : forming a ferroelectric capacitor on the drain 320 .
下面结合附图对所述三维存储器件的制造方法进行详细的说明。The manufacturing method of the three-dimensional memory device will be described in detail below with reference to the accompanying drawings.
首先，执行步骤S201，如图3A所示，提供衬底300。First, step S201 is performed, as shown in FIG. 3A , a substrate 300 is provided.
示例性地，衬底300可以是以下所提到的材料中的至少一种：单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。在本发明的示例性实施例中，衬底300为硅衬底。Illustratively, the substrate 300 may be at least one of the following materials: single crystal silicon, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI) ), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc. In an exemplary embodiment of the present invention, the substrate 300 is a silicon substrate.
接下来，执行步骤S202，如图3A所示，对所述衬底300进行掺杂，以形成源极310。Next, step S202 is performed, as shown in FIG. 3A , the substrate 300 is doped to form a source electrode 310 .
具体地，在该步骤中，可以先在所述衬底300上形成保护层和/或掩膜层，然后执行离子注入进而形成所述源极310，并在离子注入之后去除所述保护层和/或掩膜层。Specifically, in this step, a protective layer and/or a mask layer may be formed on the substrate 300 first, then ion implantation is performed to form the source electrode 310, and the protective layer and/or the protective layer are removed after the ion implantation. / or mask layer.
其中，所述离子注入的能量、剂量以及深度均可以根据实际需要进行选择，并不局限于某一数值范围。The energy, dose and depth of the ion implantation can be selected according to actual needs, and are not limited to a certain numerical range.
在本发明的示例性实施例中，在所述衬底300上形成图案化的掩膜层，以露出需要形成源极310的区域；In an exemplary embodiment of the present invention, a patterned mask layer is formed on the substrate 300 to expose the region where the source electrode 310 needs to be formed;
然后以所述掩膜层为掩膜执行离子注入，注入的离子为N型离子，以形成所述源极310。Then, ion implantation is performed using the mask layer as a mask, and the implanted ions are N-type ions to form the source electrode 310 .
可选地，在该步骤中所述注入的离子能量为1kev-10kev，注入的离子剂量为5×10 14-5×10 16原子/cm 2。 Optionally, in this step, the implanted ion energy is 1kev-10kev, and the implanted ion dose is 5×10 14 -5×10 16 atoms/cm 2 .
接下来，执行步骤S203，如图3A所示，在所述衬底300上形成栅极342。Next, step S203 is performed, as shown in FIG. 3A , a gate electrode 342 is formed on the substrate 300 .
参照图3A，首先在所述衬底300上形成隔离层351，所述隔离层351可使用诸如氧化硅层、氮化硅层、或氮氧化硅层的无机绝缘层，诸如包含聚乙烯苯酚、聚酰亚胺、或硅氧烷等的绝缘层等来形成。示例性地，所述隔离层351的沉积可以选用化学气相沉积(CVD)法、物理气相沉积(PVD)法或原子层沉积(ALD)法等形成的低压化学气相沉积(LPCVD)、激光烧蚀沉积(LAD)以及选择外延生长(SEG)中的一种。3A, first, an isolation layer 351 is formed on the substrate 300, and the isolation layer 351 may use an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, such as polyvinyl phenol, An insulating layer such as polyimide or siloxane is formed. Exemplarily, the isolation layer 351 can be deposited by using low pressure chemical vapor deposition (LPCVD), laser ablation, etc. formed by chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method, or atomic layer deposition (ALD) method. One of deposition (LAD) and selective epitaxial growth (SEG).
接下来，在所述隔离层351上形成栅极材料层，栅极材料层包括多晶硅层、金属层、导电性金属氮化物层、导电性金属氧化物层和金属硅化物层中的一种或多种。所述栅极材料层的形成方法可以采用本领域技术人员所熟习的任何现有技术，在此不再赘述。Next, a gate material layer is formed on the isolation layer 351, and the gate material layer includes one of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer and a metal silicide layer or variety. The method for forming the gate material layer may adopt any prior art familiar to those skilled in the art, and details are not described herein again.
接下来，图案化所述栅极材料层。Next, the gate material layer is patterned.
示例性地，在所述栅极材料层上形成掩膜层(未示出)，所述掩膜层上形 成栅极的图案；然后以所述掩膜层为掩膜蚀刻所述栅极材料层，以将所述图案转移至所述栅极材料层中，进而形成栅极342。Exemplarily, a mask layer (not shown) is formed on the gate material layer, and a gate pattern is formed on the mask layer; then the gate material is etched by using the mask layer as a mask layer to transfer the pattern into the gate material layer to form gate 342 .
示例性地，图案化所述栅极材料层的方法可选用干法刻蚀或者湿法刻蚀的方法。干法刻蚀工艺包括但不限于：反应离子刻蚀(RIE)、离子束刻蚀、等离子体刻蚀、激光烧蚀或者这些方法的任意组合。也可以使用单一的刻蚀方法，或者也可以使用多于一个的刻蚀方法。干法刻蚀的其源气体可以包括HBr和/或CF 4气体。 Exemplarily, the method of patterning the gate material layer may be dry etching or wet etching. Dry etching processes include, but are not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may be used. The source gas for dry etching may include HBr and/or CF 4 gas.
接下来，执行步骤S204，如图3B所示，形成覆盖所述衬底300的层间介电层352。Next, step S204 is performed, as shown in FIG. 3B , an interlayer dielectric layer 352 covering the substrate 300 is formed.
示例性地，所述层间介电层352与上述隔离层351可采用相同的材料，并通过相同的方法形成，在此不再赘述。Exemplarily, the interlayer dielectric layer 352 and the above-mentioned isolation layer 351 can be made of the same material and formed by the same method, and details are not described herein again.
接下来，执行步骤S205，如图3B所示，图案化所述层间介电层352和所述栅极342，以形成露出所述源极310的孔洞。Next, step S205 is performed, as shown in FIG. 3B , the interlayer dielectric layer 352 and the gate electrode 342 are patterned to form a hole exposing the source electrode 310 .
示例性地，在所述层间介电层352上形成掩膜层(未示出)，所述掩膜层上形成沟道的图案；然后以所述掩膜层为掩膜蚀刻所述层间介电层352、所述栅极342和所述隔离层351，以将形成露出所述源极310的孔洞，如图3B所示。Exemplarily, a mask layer (not shown) is formed on the interlayer dielectric layer 352, and a channel pattern is formed on the mask layer; then the layer is etched by using the mask layer as a mask The inter-dielectric layer 352 , the gate electrode 342 and the isolation layer 351 are formed to form a hole exposing the source electrode 310 , as shown in FIG. 3B .
示例性地，图案化所述层间介电层352、所述栅极342和所述隔离层351的方法可以采用本领域技术人员所熟习的任何现有技术，在此不再赘述。Exemplarily, the method for patterning the interlayer dielectric layer 352 , the gate electrode 342 and the isolation layer 351 may adopt any prior art familiar to those skilled in the art, and details are not described herein again.
接下来，执行步骤S206，如图3C所示，在所述孔洞中沉积沟道材料层，以形成所述栅极342环绕的数条纳米线330。Next, step S206 is performed. As shown in FIG. 3C , a channel material layer is deposited in the hole to form a plurality of nanowires 330 surrounded by the gate electrode 342 .
首先，在所述孔洞的侧壁上形成栅极介电层341。First, a gate dielectric layer 341 is formed on the sidewalls of the holes.
示例性地，栅极介电层341包括氧化物层，例如二氧化硅(SiO 2)层。所述栅极介电层的形成方法可以采用本领域技术人员所熟习的任何现有技术，包括物理气相沉积法(PVD)和化学气相沉积法(CVD)，优选化学气相沉积法(CVD)，如低温化学气相沉积(LTCVD)、低压化学气相沉积(LPCVD)、快热化学气相沉积(RTCVD)、等离子体增强化学气相沉积(PECVD)。 Illustratively, the gate dielectric layer 341 includes an oxide layer, such as a silicon dioxide (SiO 2 ) layer. The method for forming the gate dielectric layer may adopt any prior art familiar to those skilled in the art, including physical vapor deposition (PVD) and chemical vapor deposition (CVD), preferably chemical vapor deposition (CVD), Such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD).
示例性地，所述沟道材料层包括但不限于多晶硅。Exemplarily, the channel material layer includes, but is not limited to, polysilicon.
示例性地，所述多晶硅纳米线330的形成方法可选用低压化学气相沉积(LPCVD)工艺。形成所述多晶硅层的工艺条件包括：反应气体为硅烷(SiH 4)， 所述硅烷的流量范围可为100～200立方厘米/分钟(sccm)，如130sccm；反应腔内温度范围可为700～750摄氏度；反应腔内压力可为250～350mTorr，如300mTorr；所述反应气体中还可包括缓冲气体，所述缓冲气体可为氦气(He)或氮气，所述氦气和氮气的流量范围可为5～20升/分钟(slm)，如8slm、10slm或15slm。 Exemplarily, the method for forming the polysilicon nanowires 330 may be a low pressure chemical vapor deposition (LPCVD) process. The process conditions for forming the polysilicon layer include: the reaction gas is silane (SiH 4 ), and the flow rate of the silane can range from 100 to 200 cubic centimeters per minute (sccm), such as 130 sccm; the temperature in the reaction chamber can range from 700 to 700 to 750 degrees Celsius; the pressure in the reaction chamber can be 250-350mTorr, such as 300mTorr; the reaction gas can also include a buffer gas, the buffer gas can be helium (He) or nitrogen, and the flow range of the helium and nitrogen It can be 5 to 20 liters per minute (slm), such as 8 slm, 10 slm or 15 slm.
接下来，执行步骤S207，如图3D所示，对所述沟道材料层进行掺杂，以形成漏极320。Next, step S207 is performed, as shown in FIG. 3D , the channel material layer is doped to form the drain electrode 320 .
具体地，在该步骤中，对沟道材料层执行离子注入进而形成所述漏极320。Specifically, in this step, ion implantation is performed on the channel material layer to form the drain electrode 320 .
其中，所述离子注入的能量、剂量以及深度均可以根据实际需要进行选择，并不局限于某一数值范围。The energy, dose and depth of the ion implantation can be selected according to actual needs, and are not limited to a certain numerical range.
在本发明的示例性实施例中，注入的离子为N型离子。In an exemplary embodiment of the present invention, the implanted ions are N-type ions.
在形成所述漏极之后还包括执行退火的步骤。在本发明的示例性实施例中，所述退火温度为200-500℃，所述热退火步骤时间为1-200s，但并不局限于所述数值范围。The step of performing annealing is also included after forming the drain. In an exemplary embodiment of the present invention, the annealing temperature is 200-500° C., and the thermal annealing step time is 1-200 s, but it is not limited to the numerical range.
接下来，执行步骤S208，如图3E所示，在所述漏极320上形成铁电电容器。Next, step S208 is performed, as shown in FIG. 3E , a ferroelectric capacitor is formed on the drain 320 .
示例性地，所述铁电电容器由下至上依次包括第一电极层371，铁电材料层372和第二电极层373。所述第一电极层371和第二电极层373作为铁电电容器的极板，可以由TiN、Pt等铁电电容的常见电极材料构成。所述第一电极层371和第二电极层373的沉积方法可以为化学气相沉积(CVD)法、物理气相沉积(PVD)法或原子层沉积(ALD)法等形成的低压化学气相沉积(LPCVD)、激光烧蚀沉积(LAD)以及选择外延生长(SEG)中的一种，在本发明中优选为物理气相沉积(PVD)法。Exemplarily, the ferroelectric capacitor includes a first electrode layer 371 , a ferroelectric material layer 372 and a second electrode layer 373 in sequence from bottom to top. The first electrode layer 371 and the second electrode layer 373 serve as the plates of the ferroelectric capacitor, and can be made of common electrode materials of ferroelectric capacitors such as TiN and Pt. The deposition method of the first electrode layer 371 and the second electrode layer 373 may be a low pressure chemical vapor deposition (LPCVD) method formed by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, or an atomic layer deposition (ALD) method. ), laser ablation deposition (LAD) and selective epitaxial growth (SEG), preferably in the present invention a physical vapor deposition (PVD) method.
示例性地，铁电材料在没有外部电场的情况下可以表现出自发极化。所述极化可以通过晶体中的离子位移而重新定向，并且极化切换可以通过外部电场触发，从而铁电材料可以具有两种电控非易失性状态。在本发明的示例性实施例中，所述铁电材料层包括但不限于HfO 2或CuInP 2S 6。 Illustratively, ferroelectric materials can exhibit spontaneous polarization in the absence of an external electric field. The polarization can be redirected by ionic displacement in the crystal, and polarization switching can be triggered by an external electric field, so that the ferroelectric material can have two electrically controlled nonvolatile states. In an exemplary embodiment of the present invention, the ferroelectric material layer includes, but is not limited to, HfO 2 or CuInP 2 S 6 .
接下来，参照图3F，还包括形成与所述源极310和所述栅极342相接的 互连结构的步骤：Next, referring to FIG. 3F , it also includes the step of forming an interconnect structure in contact with the source electrode 310 and the gate electrode 342:
图案化所述层间介电层352，以形成第一开口，所述第一开口露出所述栅极342；在该步骤中还进一步图案化所述层间介电层352和所述隔离层351，以形成第二开口，所述第二开口路出所述源极310。The interlayer dielectric layer 352 is patterned to form a first opening that exposes the gate electrode 342; in this step, the interlayer dielectric layer 352 and the isolation layer are further patterned 351 to form a second opening that leads out of the source electrode 310 .
然后第一开口中填充导电材料，形成第一互连结构361，以与所述栅极342电连接，同时在所述第二开口中填充导电材料，以形成第二互连结构362，与所述源极310电连接。Then, the first opening is filled with conductive material to form a first interconnect structure 361 to be electrically connected to the gate electrode 342, while the second opening is filled with conductive material to form a second interconnect structure 362, which is connected to the gate electrode 342. The source electrode 310 is electrically connected.
示例性地，所述互连结构采用导电材料制成，包括但不限于钨(W)、铝(Al)、铜(Cu)。Exemplarily, the interconnect structure is made of conductive materials, including but not limited to tungsten (W), aluminum (Al), copper (Cu).
上述步骤以形成一层的存储单元层为示例进行了说明，所述存储单元层中包括数个存储单元，每一存储单元均包括包含纳米线的晶体管和与之相连的铁电电容器。本发明还包括重复上述步骤，以形成多层层叠的存储器件结构。即在上述存储单元层上再次沉积硅材料层作为衬底，然后形成纳米线、栅极、漏极、铁电电容器等步骤，从而形成三维堆叠的存储器件结构，其包括数层上述的存储单元层。The above steps are described by taking the example of forming a single-layer memory cell layer, wherein the memory cell layer includes several memory cells, and each memory cell includes a transistor including nanowires and a ferroelectric capacitor connected thereto. The present invention also includes repeating the above steps to form a multi-layer stacked memory device structure. That is, a silicon material layer is deposited again as a substrate on the above-mentioned memory cell layer, and then steps such as nanowires, gates, drains, and ferroelectric capacitors are formed to form a three-dimensional stacked memory device structure, which includes several layers of the above-mentioned memory cells. Floor.
根据本发明提供的三维铁电存储器件的制造方法，通过垂直纳米线环绕栅极(GAA)构建三维铁电存储器件，减小了三维铁电存储器件的管芯尺寸，降低了功耗，避免了信号传播延迟等问题。According to the manufacturing method of the three-dimensional ferroelectric memory device provided by the present invention, the three-dimensional ferroelectric memory device is constructed by vertical nanowire surrounding gate (GAA), the die size of the three-dimensional ferroelectric memory device is reduced, the power consumption is reduced, and the avoidance of problems such as signal propagation delay.
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。The present invention has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can also be made according to the teachings of the present invention, and these variations and modifications all fall within the protection claimed in the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (9)

  1. 一种三维铁电存储器件的制造方法，其特征在于，包括：A method for manufacturing a three-dimensional ferroelectric memory device, comprising:
    提供衬底；provide a substrate;
    对所述衬底进行掺杂，以形成源极；doping the substrate to form a source;
    在所述衬底上形成栅极；forming a gate on the substrate;
    形成覆盖所述衬底的层间介电层；forming an interlayer dielectric layer overlying the substrate;
    图案化所述层间介电层和所述栅极，以形成露出所述源极的孔洞；patterning the interlayer dielectric layer and the gate to form a hole exposing the source;
    在所述孔洞中沉积沟道材料层，以形成所述栅极环绕的数条纳米线；depositing a layer of channel material in the hole to form a plurality of nanowires surrounding the gate;
    对所述沟道材料层进行掺杂，以形成漏极；doping the channel material layer to form a drain;
    在所述漏极上形成铁电电容器。A ferroelectric capacitor is formed on the drain.
  2. 如权利要求1所述的三维铁电存储器件的制造方法，其特征在于，所述铁电电容器由下至上依次包括第一电极层，铁电材料层和第二电极层。The method for manufacturing a three-dimensional ferroelectric memory device according to claim 1, wherein the ferroelectric capacitor comprises a first electrode layer, a ferroelectric material layer and a second electrode layer in order from bottom to top.
  3. 如权利要求2所述的三维铁电存储器件的制造方法，其特征在于，所述铁电材料层包括HfO 2或CuInP 2S 6。 The method for manufacturing a three-dimensional ferroelectric memory device according to claim 2, wherein the ferroelectric material layer comprises HfO 2 or CuInP 2 S 6 .
  4. 如权利要求1所述的三维铁电存储器件的制造方法，其特征在于，在所述孔洞中沉积所述沟道材料层之前还包括：The method for manufacturing a three-dimensional ferroelectric memory device according to claim 1, wherein before depositing the channel material layer in the hole, the method further comprises:
    在所述孔洞的侧壁上形成栅极介电层。A gate dielectric layer is formed on the sidewalls of the holes.
  5. 如权利要求1所述的三维铁电存储器件的制造方法，其特征在于，所述纳米线包括多晶硅。The method for manufacturing a three-dimensional ferroelectric memory device according to claim 1, wherein the nanowires comprise polysilicon.
  6. 如权利要求1所述的三维铁电存储器件的制造方法，其特征在于，在所述衬底上形成栅极之前还包括：The method for manufacturing a three-dimensional ferroelectric memory device according to claim 1, wherein before forming the gate on the substrate, the method further comprises:
    在所述衬底上形成隔离层。An isolation layer is formed on the substrate.
  7. 如权利要求6所述的三维铁电存储器件的制造方法，其特征在于，在所述衬底上形成栅极包括：The method for manufacturing a three-dimensional ferroelectric memory device according to claim 6, wherein forming a gate on the substrate comprises:
    在所述隔离层上形成栅极材料层；forming a gate material layer on the isolation layer;
    图案化所述栅极材料层，以形成栅极。The gate material layer is patterned to form a gate.
  8. 如权利要求1所述的三维铁电存储器件的制造方法，其特征在于，在形成所述铁电电容器之后还包括：The method for manufacturing a three-dimensional ferroelectric memory device according to claim 1, wherein after forming the ferroelectric capacitor, the method further comprises:
    图案化所述层间介电层，以分别形成露出所述源极和所述栅极的开口；patterning the interlayer dielectric layer to form openings exposing the source electrode and the gate electrode, respectively;
    在所述开口中填充导电材料，以分别形成与所述源极和所述栅极相接的互连结构。A conductive material is filled in the openings to form interconnect structures in contact with the source electrodes and the gate electrodes, respectively.
  9. 如权利要求1所述的三维铁电存储器件的制造方法，其特征在于，还 包括重复上述步骤，以形成多层层叠的存储器件结构。The method of manufacturing a three-dimensional ferroelectric memory device according to claim 1, further comprising repeating the above steps to form a multi-layer stacked memory device structure.
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