WO2022126754A1 - 芯片封装结构、芯片封装方法及电子设备 - Google Patents

芯片封装结构、芯片封装方法及电子设备 Download PDF

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WO2022126754A1
WO2022126754A1 PCT/CN2020/140816 CN2020140816W WO2022126754A1 WO 2022126754 A1 WO2022126754 A1 WO 2022126754A1 CN 2020140816 W CN2020140816 W CN 2020140816W WO 2022126754 A1 WO2022126754 A1 WO 2022126754A1
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chip
substrate
antenna
intermediate frequency
frequency signal
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PCT/CN2020/140816
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English (en)
French (fr)
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何文卿
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闻泰科技(深圳)有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device

Definitions

  • the present disclosure relates to the field of chip technology, and in particular, to a chip packaging structure, a chip packaging method, and an electronic device.
  • Millimeter wave usually refers to electromagnetic waves with a wavelength of 1 to 10 millimeters. It is located in the wavelength range where microwaves and far-infrared waves overlap, so it has the characteristics of both spectrums and is widely used in 5G communications, radio astronomy and other fields. .
  • the millimeter-wave transceiver system generally includes a millimeter-wave transceiver module, a millimeter-wave transceiver component, and a millimeter-wave antenna that are connected in sequence. The conversion of the wave signal, the millimeter wave antenna is set to send and receive the millimeter wave signal.
  • the communication between the millimeter-wave transceiver module and the millimeter-wave transceiver module is carried out through a cable with a connector, and the physical distance between the two is relatively long, so the intermediate frequency signal transmitted between the two is attenuated greatly. , making it difficult to guarantee the communication quality.
  • the technical problem to be solved by the present disclosure is to solve the problem that the communication quality is difficult to guarantee when the physical distance between the existing millimeter-wave transceiver module and the millimeter-wave transceiver component is long.
  • the embodiments of the present disclosure provide a chip packaging structure, a chip packaging method, and an electronic device, which can reduce the attenuation of an intermediate frequency signal of a millimeter-wave transceiver system and ensure communication quality.
  • the present disclosure provides a chip packaging structure, including:
  • a first chip disposed on the substrate and electrically connected to the substrate;
  • a second chip disposed on the first chip and electrically connected to the first chip
  • an antenna disposed on the second chip and electrically connected to the second chip
  • the first chip, the second chip and the antenna work in at least one of the following manners:
  • the first chip is configured to output an intermediate frequency signal
  • the second chip is configured to process the intermediate frequency signal to output a millimeter wave signal
  • the antenna is configured to transmit the millimeter wave signal
  • the antenna is configured to receive a millimeter wave signal
  • the second chip is configured to process the millimeter wave signal to output an intermediate frequency signal
  • the first chip is configured to receive and process the intermediate frequency signal.
  • the substrate has opposite first and second sides, the substrate is provided with through holes penetrating through the first side and the second side, and the first chip is disposed on the On the first side, the second chip is disposed on the side of the first chip close to the substrate and passes through the through hole, and the antenna is disposed on a side of the second chip away from the first chip. side.
  • the antenna is located at least partially outside the through hole.
  • a ground shield structure is connected between a side of the first chip close to the substrate and the first side of the substrate, and the ground shield structure surrounds the second chip.
  • a shield cover is provided on the first side of the substrate, and the shield cover covers the first chip.
  • a BGA packaging process is used for packaging between the first chip and the substrate, and an LGA packaging process is used for packaging between the second chip and the first chip.
  • the first chip is provided with a plurality of first pins
  • the second chip is provided with a plurality of second pins
  • the plurality of second pins and the plurality of first pins are provided The pins are connected one by one.
  • the chip package structure further includes a plastic package covering the substrate, the first chip and the second chip.
  • the present disclosure provides a chip packaging method, including:
  • the first chip, the second chip and the antenna work in at least one of the following manners:
  • the first chip is configured to output an intermediate frequency signal
  • the second chip is configured to process the intermediate frequency signal to output a millimeter wave signal
  • the antenna is configured to transmit the millimeter wave signal
  • the antenna is configured to receive a millimeter wave signal
  • the second chip is configured to process the millimeter wave signal to output an intermediate frequency signal
  • the first chip is configured to receive and process the intermediate frequency signal.
  • the present disclosure provides an electronic device, including the chip packaging structure described in any one of the foregoing embodiments or the chip packaging structure fabricated by the chip packaging method described in the foregoing embodiments.
  • the chip package structure provided by the embodiment of the present disclosure includes a substrate, a first chip, a second chip, and an antenna.
  • the first chip is disposed on the substrate and is electrically connected to the substrate
  • the second chip is disposed on the first chip and is connected to the substrate.
  • the first chip is electrically connected
  • the antenna is disposed on the second chip and is electrically connected to the second chip.
  • the chip package structure integrates the first chip (equivalent to the transceiver module of the existing millimeter wave transceiver system) and the second chip (equivalent to the transceiver component of the existing millimeter wave transceiver system), to a large extent.
  • the electronic device using the above chip package structure has the characteristics of low signal attenuation and high communication quality.
  • FIG. 1 is a front view of a chip packaging structure provided by a first embodiment of the present disclosure
  • FIG. 2 is a bottom view of the chip package structure provided by the first embodiment of the present disclosure
  • FIG. 3 is a front view of the first chip provided by the first embodiment of the present disclosure.
  • FIG. 4 is a bottom view of the first chip provided by the first embodiment of the present disclosure.
  • FIG. 5 is a top view of the second chip provided by the first embodiment of the present disclosure.
  • FIG. 6 is a bottom view of the second chip provided by the first embodiment of the present disclosure.
  • FIG. 7 is a front view of the first chip and the second chip provided by the first embodiment of the present disclosure after mounting;
  • FIG. 8 is a bottom view of the first chip and the second chip provided by the first embodiment of the present disclosure after mounting;
  • FIG. 9 is a front view of a chip package structure provided by a second embodiment of the present disclosure.
  • FIG. 10 is a top view of the chip package structure provided by the second embodiment of the present disclosure.
  • Icon 100-chip package structure; 110-substrate; 112-through hole; 114-first side; 116-second side; 120-first chip; 122-first pin; 124-third pin; 130 - the second chip; 132 - the second pin; 140 - the antenna; 150 - the ground shielding structure; 160 - the shield.
  • Millimeter waves usually refer to electromagnetic waves with a wavelength of 1 to 10 mm, which are located in the wavelength range where microwaves and far-infrared waves overlap, so they have the characteristics of both spectrums.
  • the existing millimeter-wave transceiver system generally includes a baseband part, a transceiver module, a transceiver component, and an antenna array that are sequentially connected in communication.
  • the baseband part is set to output the baseband signal
  • the transceiver module is set to input the baseband signal and process it to output an intermediate frequency signal
  • the transceiver module is set to input the intermediate frequency signal and process it to output the millimeter wave signal
  • the antenna array is set to Transmit the above-mentioned millimeter-wave signal; or, the antenna array is set to receive the millimeter-wave signal
  • the transceiver component is set to input the above-mentioned millimeter-wave signal and process it to output an intermediate frequency signal
  • the transceiver module is set to input the above-mentioned intermediate frequency signal and process it to output an intermediate frequency signal.
  • a baseband signal is output, and the baseband part is set to input the above-mentioned baseband signal.
  • an embodiment of the present disclosure provides a chip packaging structure, which integrates a transceiver module and a transceiver component, thereby greatly shortening the physical distance between the two, thereby shortening the distance between the two. It can effectively reduce the attenuation of the intermediate frequency signal transmitted between the two, and ensure the communication quality.
  • the chip packaging structure eliminates the need for connectors and cable structures, which not only reduces manufacturing costs, but also eliminates the need to worry about the connector loosening and falling off during the movement of the millimeter-wave transceiver system, which affects the stability of signal connections.
  • the chip package structure provided by the embodiments of the present disclosure can be used in various electronic devices involving millimeter-wave transceiving, such as a millimeter-wave transceiving system.
  • the chip package structure 100 includes a substrate 110 , a first chip 120 , a second chip 130 and an antenna 140 .
  • the first chip 120 is disposed on the substrate 110 and is electrically connected to the substrate 110
  • the second chip 130 is disposed on the first chip 120 and is electrically connected to the first chip 120
  • the antenna 140 is disposed on the second chip 130 and is connected to the second chip 130 electrical connections.
  • the first chip 120 is configured to output an intermediate frequency signal
  • the second chip 130 is configured to process the intermediate frequency signal output by the first chip 120 to output a millimeter wave signal
  • the antenna 140 is configured to transmit the millimeter wave signal output by the second chip 130; and /or, the antenna 140 is configured to receive millimeter-wave signals
  • the second chip 130 is configured to process the millimeter-wave signals received by the antenna 140 to output an intermediate frequency signal
  • the first chip 120 is configured to receive and process the intermediate frequency output by the second chip 130 Signal.
  • the chip package structure 100 can be easily The physical distance between the two is greatly shortened, thereby effectively reducing the attenuation of the intermediate frequency signal propagating between the two, and ensuring the communication quality within the entire chip packaging structure 100 .
  • the substrate 110 is a PCB (Printed Circuit Board, printed circuit board or printed circuit board).
  • the substrate 110 has an opposing first side 114 and a second side 116, the first side 114 is provided with a plurality of pads arranged in an array.
  • the substrate 110 is provided with a through hole 112 , and the through hole 112 is rectangular and penetrates through the first side 114 and the second side 116 .
  • the first chip 120 is substantially square and disposed on the first side 114 .
  • a plurality of first pins 122 and a plurality of third pins 124 are disposed on the side of the first chip 120 close to the substrate 110 .
  • the plurality of first pins 122 are all metal contact pins and are arranged in the central area of the side of the first chip 120 close to the second chip 130 .
  • the first pin 122 with a larger area is approximately disposed at the intersection of two diagonal lines on the side of the first chip 120 close to the second chip 130 .
  • the remaining first pins 122 with smaller areas are generally arranged along a box-shaped path and are arranged around the first pins 122 with larger areas.
  • the plurality of third pins 124 are arranged in an edge region of a side of the first chip 120 close to the second chip 130 approximately along a box-shaped path and are disposed around the plurality of first pins 122 .
  • the plurality of third pins 124 are all metal ball pins, and the plurality of third pins 124 are connected to part of the pads on the substrate 110 in a one-to-one correspondence. That is, a BGA (Ball Grid Array Package, ball grid array package) packaging process is used for packaging between the first chip 120 and the substrate 110 .
  • the first chip 120 and the substrate 110 may also be packaged using an LGA (Land Grid Array, grid array package) packaging process.
  • the second chip 130 is substantially square and disposed on the side of the first chip 120 close to the substrate 110 .
  • a plurality of second pins 132 are disposed on the side of the second chip 130 close to the first chip 120 , and the plurality of second pins 132 are connected to the plurality of first pins 122 in a one-to-one correspondence, so that the second chip 130 and the Physical and electrical connections of the first chip 120 . That is, the second chip 130 and the first chip 120 are packaged using the LGA packaging process. Of course, in other embodiments, the second chip 130 and the first chip 120 may also be packaged using a BGA packaging process.
  • the second chip 130 passes through the through hole 112 , so that the second chip 130 and the substrate 110 share at least a part of the thickness space of the chip package structure 100 , thereby reducing the overall thickness and volume of the chip package structure 100 .
  • the second chip 130 includes an amplifying unit, a phase shifting unit, etc. to process the intermediate frequency signal output by the first chip 120 , so as to convert the intermediate frequency signal into a millimeter wave signal, or to process the millimeter wave signal received by the antenna 140 . Processing is performed to convert the millimeter wave signal into an intermediate frequency signal.
  • the antenna 140 can be of different types as required.
  • the antenna 140 is a phased array antenna 140, and the phased array antenna 140 can control the phase to change the direction of the maximum value of the antenna 140, so as to achieve fast and flexible beam scanning The purpose of this is to improve the transmission and reception performance of millimeter-wave signals.
  • the antenna 140 is disposed on the side of the second chip 130 away from the first chip 120 .
  • the antenna 140 is at least partially located outside the through hole 112 to expand the transmission angle range or the reception angle range of the millimeter wave signal.
  • the antenna 140 is completely located outside the through hole 112 to ensure the maximum transmission angle range or reception angle range. In other embodiments, the antenna 140 may be completely located in the through hole 112 .
  • the substrate 110 is provided with the through holes 112, which may cause signal leakage. Therefore, in order to shield the signal leakage and ensure the performance of the antenna 140 to transmit and receive millimeter-wave signals, in this embodiment, the side of the first chip 120 close to the substrate 110 and A grounding shielding structure 150 is connected between the first sides 114 of the substrate 110 , and the grounding shielding structure 150 surrounds the second chip 130 .
  • the grounding shielding structure 150 can ensure that after the through hole 112 is dug out of the substrate 110 to expose the phased array antenna 140, the shielding effect can still be effectively achieved.
  • a shielding cover 160 is provided on the first side 114 of the substrate 110 , and the shielding cover 160 covers the first chip 120 to prevent the first chip The clutter leaked by 120 is radiated out to ensure the receiving and transmitting performance of the antenna 140 for millimeter waves.
  • the chip package structure 100 further includes a plastic package (not shown in the figure) covering the substrate 110 , the first chip 120 and the second chip 130 , so as to prevent the chip package structure 100 from being easily damaged.
  • the plastic package may cover the antenna 140 together, or may not cover the antenna 140 .
  • the above is the structure of the chip packaging structure 100 provided by the embodiment of the present disclosure, and the chip packaging method for manufacturing the above-mentioned chip packaging structure 100 will be described in detail below.
  • the chip packaging method provided by the embodiment of the present disclosure includes the following steps:
  • Step S100 Mount the second chip 130 with the antenna 140 on the first chip 120 .
  • the first chip 120 and the second chip 130 are bonded by a BGA packaging process. Since the area of the first chip 120 is larger than that of the second chip 130, after the two are mounted and welded, a stepped structure is formed as a whole. Before the first chip 120 and the second chip 130 are mounted and welded, the ground shielding structure 150 needs to be fabricated on the first chip 120 in advance, and the antenna 140 needs to be fabricated on the second chip 130. After the two are mounted and welded, the ground shielding structure The structure 150 is disposed around the second chip 130, and the antenna 140 is located on the side of the second chip 130 away from the first chip 120 (see FIGS. 7 and 8 for details).
  • Step S200 Mount the first chip 120 on the substrate 110 .
  • the first chip 120 and the substrate 110 are mounted and welded using an LGA packaging process. After the two are mounted and welded, the first chip 120 is located on the first side 114 of the substrate 110 , and the second chip 130 is inserted through the through hole 112 and protrudes from the end of the through hole 112 away from the first chip 120 , so that the second chip 130 is The antenna 140 on the chip 130 is completely located outside the through hole 112 , and the side of the ground shielding structure 150 away from the first chip 120 is attached to the first side 114 of the substrate 110 (see FIGS. 1 and 2 for details).
  • Step S300 installing the shielding cover 160 on the first side 114 of the substrate 110 .
  • the shielding cover 160 may be mounted on the substrate 110 in different ways according to requirements, such as welding, bonding and the like.
  • the shielding cover 160 covers the first chip 120 after being installed.
  • the chip package structure 100 can realize the transmission and reception of millimeter wave signals.
  • the first chip 120 first processes the baseband signal output by the baseband part to output the intermediate frequency signal to the second chip 130; then the second chip 130 processes the intermediate frequency signal output by the first chip 120 to The millimeter wave signal is output to the antenna 140, and finally the millimeter wave signal output by the second chip 130 is transmitted by the antenna 140; when a signal needs to be received, the millimeter wave signal is first received by the antenna 140, and then the second chip 130 receives the millimeter wave signal from the antenna 140.
  • the millimeter wave signal is processed to output the intermediate frequency signal to the first chip 120, and finally the intermediate frequency signal output by the second chip 130 is processed by the first chip 120 to output the baseband signal to the baseband part; when it is necessary to transmit and receive signals at the same time, It is sufficient to execute the above two processes at the same time.
  • the chip package structure 100 provided by the embodiment of the present disclosure includes the substrate 110 , the first chip 120 , the second chip 130 and the antenna 140 .
  • the first chip 120 is disposed on the substrate 110 and is electrically connected to the substrate 110
  • the second chip 130 The antenna 140 is disposed on the first chip 120 and is electrically connected to the first chip 120
  • the antenna 140 is disposed on the second chip 130 and is electrically connected to the second chip 130 .
  • the chip package structure 100 integrates the first chip 120 (equivalent to the transceiver module of the existing millimeter wave transceiver system) and the second chip 130 (equivalent to the transceiver module of the existing millimeter wave transceiver system), so that the The physical distance between the two is greatly shortened, thereby shortening the distance of signal propagation between the two, thereby effectively reducing the attenuation of the intermediate frequency signal propagating between the two, and reducing the energy consumption inside the chip packaging structure 100 , to ensure the communication quality inside the chip packaging structure 100 .
  • the first chip 120 and the second chip 130 no longer need connectors and cables for communication, not only can the production cost of the chip package structure 100 be reduced, but also there is no need to worry about the process of the connector moving with the electronic device in the chip package structure 100 loose and affect the stability of the signal connection.
  • this embodiment also provides a chip packaging structure 100 , whose overall structure, working process and technical effects are basically the same as those of the chip packaging structure 100 provided by the first embodiment, the difference is that The relative positional relationship between the substrate 110 and the second chip 130 .
  • the substrate 110 is no longer provided with the through hole 112 , and the second chip 130 is disposed on the side of the first chip 120 away from the substrate 110 .
  • the shielding case 160 also does not need to be provided on it. Therefore, the chip package structure 100 provided in this embodiment has a simpler structure and a simpler manufacturing method.
  • the present disclosure provides a chip package structure including a substrate, a first chip, a second chip and an antenna, the first chip is disposed on the substrate and is electrically connected to the substrate, the second chip is disposed on the first chip and is electrically connected to the first chip, and the antenna It is disposed on the second chip and is electrically connected with the second chip.
  • the first chip is configured to input or output an intermediate frequency signal
  • the second chip is configured to convert the intermediate frequency signal and the millimeter wave signal
  • the antenna is configured to transmit or receive the millimeter wave signal.
  • the chip packaging structure and the corresponding chip packaging method can greatly shorten the physical distance between the first chip and the second chip by integrating the first chip and the second chip, thereby effectively reducing the attenuation of the intermediate frequency signal propagating between the two. , to ensure the communication quality inside the chip package structure.
  • the electronic device includes the above-mentioned chip package structure, which has the characteristics of small signal attenuation and high communication quality, and has strong industrial practicability.

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种芯片封装结构（100）、芯片封装方法及电子设备，芯片封装结构（100）包括基板（110）、第一芯片（120）、第二芯片（130）及天线（140），第一芯片（120）设置于基板（110）上且与基板（110）电连接，第二芯片（130）设置于第一芯片（120）上且与第一芯片（120）电连接，天线（140）设置于第二芯片（130）上且与第二芯片（130）电连接。第一芯片（120）设置为输入或者输出中频信号，第二芯片（130）设置为转换中频信号和毫米波信号，天线（140）设置为发射或者接收毫米波信号。芯片封装结构（100）及对应的芯片封装方法通过将第一芯片（120）和第二芯片（130）集成设置，从很大程度上缩短二者之间的物理距离，从而有效减小在二者之间传播的中频信号的衰减，保证芯片封装结构（100）内部的通信质量。电子设备包括上述的芯片封装结构（100），具有信号衰减小，通信质量高的特点。

Description

芯片封装结构、芯片封装方法及电子设备
本公开要求于2020年12月15日提交中国专利局、申请号为202011476967.9、发明名称为“芯片封装结构、芯片封装方法及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及芯片技术领域，尤其涉及一种芯片封装结构、芯片封装方法及电子设备。
背景技术
毫米波(millimeter wave)通常指代波长为1～10毫米的电磁波，它位于微波与远红外波相交叠的波长范围，因而兼有两种波谱的特点，广泛应用于5G通信、射电天文等领域。毫米波收发系统一般包括依次通信连接的毫米波收发模组、毫米波收发组件及毫米波天线，毫米波收发模组设置为基带信号和中频信号的转换，毫米波收发组件设置为中频信号和毫米波信号的转换，毫米波天线设置为收发毫米波信号。
但是相关技术中，毫米波收发模组和毫米波收发组件之间通过带有连接器的线缆进行通信，二者之间的物理距离较远，因此两者之间传播的中频信号衰减较大，导致通信质量难以保证。
发明内容
(一)要解决的技术问题
本公开要解决的技术问题是解决现有的毫米波收发模组和毫米波收发组件之间物理距离较远时，通信质量难以保证的问题。
(二)技术方案
为了解决上述技术问题，本公开实施例提供了一种芯片封装结构、 芯片封装方法和电子设备，其能够减小毫米波收发系统的中频信号衰减，保证通信质量。
第一方面，本公开提供一种芯片封装结构，包括：
基板；
第一芯片，设置于所述基板上且与所述基板电连接；
第二芯片，设置于所述第一芯片上且与所述第一芯片电连接；
天线，设置于所述第二芯片上且与所述第二芯片电连接；
其中，所述第一芯片、所述第二芯片和所述天线采用下列方式中的至少一种方式工作：
所述第一芯片设置为输出中频信号，所述第二芯片设置为对所述中频信号进行处理，以输出毫米波信号，所述天线设置为发射所述毫米波信号；以及
所述天线设置为接收毫米波信号，所述第二芯片设置为对所述毫米波信号进行处理，以输出中频信号，所述第一芯片设置为接收并处理所述中频信号。
在一些实施例中，所述基板具有相对的第一侧和第二侧，所述基板开设有贯穿所述第一侧和所述第二侧的通孔，所述第一芯片设置于所述第一侧，所述第二芯片设置于所述第一芯片靠近所述基板的一侧且穿设于所述通孔，所述天线设置于所述第二芯片远离所述第一芯片的一侧。
在一些实施例中，所述天线至少部分位于所述通孔外。
在一些实施例中，所述第一芯片靠近所述基板的一侧和所述基板的第一侧之间连接有接地屏蔽结构，所述接地屏蔽结构围绕所述第二芯片。
在一些实施例中，所述基板的第一侧设置有屏蔽罩，所述屏蔽罩罩住所述第一芯片。
在一些实施例中，所述第一芯片与所述基板之间采用BGA封装工艺进行封装，所述第二芯片与所述第一芯片之间采用LGA封装工艺进行封装。
在一些实施例中，所述第一芯片设置有多个第一引脚，所述第二 芯片设置有多个第二引脚，所述多个第二引脚与所述多个第一引脚一一对应地连接。
在一些实施例中，芯片封装结构还包括包覆所述基板、第一芯片及第二芯片的塑封体。
第二方面，本公开提供一种芯片封装方法，包括：
在第一芯片上贴装带有天线的第二芯片；
将第一芯片贴装于基板上；
其中，所述第一芯片、所述第二芯片和所述天线采用下列方式中的至少一种方式工作：
所述第一芯片设置为输出中频信号，所述第二芯片设置为对所述中频信号进行处理，以输出毫米波信号，所述天线设置为发射所述毫米波信号；以及
所述天线设置为接收毫米波信号，所述第二芯片设置为对所述毫米波信号进行处理，以输出中频信号，所述第一芯片设置为接收并处理所述中频信号。
第三方面，本公开提供一种电子设备，包括前述实施方式任一项所述的芯片封装结构或者由前述实施方式所述的芯片封装方法制作的芯片封装结构。
(三)有益效果
本公开实施例提供的上述技术方案与相关技术相比具有如下优点：
本公开实施例提供的芯片封装结构包括基板、第一芯片、第二芯片及天线，第一芯片设置于基板上且与所述基板电连接，第二芯片设置于所述第一芯片上且与所述第一芯片电连接，天线设置于所述第二芯片上且与所述第二芯片电连接。该芯片封装结构通过将第一芯片(相当于现有的毫米波收发系统的收发模组)和第二芯片(相当于现有的毫米波收发系统的收发组件)集成设置，从很大程度上缩短二者之间的物理距离，从而缩短了二者之间信号传播的距离，进而有效减小在二者之间传播的中频信号的衰减，保证芯片封装结构内部的通信质量。相应地，采用上述芯片封装结构的电子设备具有信号衰减小，通信质 量高的特点。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本公开第一实施例提供的芯片封装结构的正视图；
图2为本公开第一实施例提供的芯片封装结构的仰视图；
图3为本公开第一实施例提供的第一芯片的正视图；
图4为本公开第一实施例提供的第一芯片的仰视图；
图5为本公开第一实施例提供的第二芯片的俯视图；
图6为本公开第一实施例提供的第二芯片的仰视图；
图7为本公开第一实施例提供的第一芯片和第二芯片贴装后的正视图；
图8为本公开第一实施例提供的第一芯片和第二芯片贴装后的仰视图；
图9为本公开第二实施例提供的芯片封装结构的正视图；
图10为本公开第二实施例提供的芯片封装结构的俯视图。
图标：100-芯片封装结构；110-基板；112-通孔；114-第一侧；116-第二侧；120-第一芯片；122-第一引脚；124-第三引脚；130-第二芯片；132-第二引脚；140-天线；150-接地屏蔽结构；160-屏蔽罩。
具体实施方式
毫米波通常指代波长为1～10毫米的电磁波，它位于微波与远红外波相交叠的波长范围，因而兼有两种波谱的特点。现有的毫米波收发系统一般包括依次通信连接的基带部分、收发模组、收发组件及天线阵列。其中，基带部分设置为输出基带信号，收发模组设置为输入 上述基带信号并进行处理，以输出中频信号，收发组件设置为输入上述中频信号并进行处理，以输出毫米波信号，天线阵列设置为发射上述毫米波信号；或者，天线阵列设置为接收毫米波信号，收发组件设置为输入上述毫米波信号并进行处理，以输出中频信号，收发模组设置为输入上述的中频信号并进行处理，以输出基带信号，基带部分设置为输入上述基带信号。
但是，现有的毫米波收发系统中，收发模组和收发组件之间是通过带有连接器的线缆实现通信的，两者之间的物理距离远，导致两者之间传播的中频信号衰减很大，通信质量无法保证。同时，连接器在随整个毫米波收发系统移动过程中很容易松动甚至脱落，影响信号连接的稳定性。
针对上述情况，本公开实施例提供了一种芯片封装结构，该芯片封装结构将收发模组和收发组件集成设置，从很大程度上缩短了两者之间的物理距离，从而缩短两者之间中频信号的传播距离，进而有效减小在二者之间传播的中频信号的衰减，保证通信质量。同时，该芯片封装结构省去连接器和线缆结构，不但可以降低制造成本，而且不用再担心连接器在毫米波收发系统移动过程中出现松动和脱落而影响信号连接的稳定性。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本公开的实施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本公开的描述中，需要说明的是，若出现术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。此外，若出现术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
需要说明的是，在不冲突的情况下，本公开的实施例中的特征可以相互结合。
第一实施例：
本公开实施例提供的芯片封装结构可以用于各种涉及毫米波收发的电子设备中，比如毫米波收发系统。
下面介绍该芯片封装结构的具体构造。
请参照图1和图2，该芯片封装结构100包括基板110、第一芯片120、第二芯片130及天线140。第一芯片120设置于基板110上且与基板110电连接，第二芯片130设置于第一芯片120上且与第一芯片120电连接，天线140设置于第二芯片130上且与第二芯片130电连接。第一芯片120设置为输出中频信号，第二芯片130设置为对第一芯片120输出的中频信号进行处理，以输出毫米波信号，天线140设置为发射第二芯片130输出的毫米波信号；和/或，天线140设置为接收毫米波信号，第二芯片130设置为对天线140接收的毫米波信号进行处理，以输出中频信号，第一芯片120设置为接收并处理第二芯片130输出的中频信号。
通过将第一芯片120(相当于现有的毫米波收发系统的收发模组)和第二芯片130(相当于现有毫米波收发系统的收发组件)集成设置，本芯片封装结构100可以从很大程度上缩短二者之间的物理距离，从而有效减小在二者之间传播的中频信号的衰减，保证整个芯片封装结构100内部的通信质量。
其中，基板110为PCB(Printed Circuit Board，印制电路板或者印刷线路板)。基板110具有相对的第一侧114和第二侧116，第一 侧114设置有多个阵列排布的焊盘。基板110开设有通孔112，通孔112呈长方形且贯穿第一侧114和第二侧116。
请参照图3和图4，第一芯片120大致呈方形且设置于第一侧114。第一芯片120靠近基板110的一侧设置多个第一引脚122和多个第三引脚124。多个第一引脚122均为金属触点引脚且排列于第一芯片120靠近第二芯片130的一侧的中心区域。在一些实施例中，多个第一引脚122中，面积较大的一个第一引脚122大致设置于第一芯片120靠近第二芯片130的一侧的两条对角线的交点处，其余面积较小的第一引脚122大致沿方框形路径排列且围绕面积较大的第一引脚122设置。
多个第三引脚124大致沿方框形路径排列于第一芯片120靠近第二芯片130的一侧的边缘区域且围绕多个第一引脚122设置。多个第三引脚124均为金属球形引脚，多个第三引脚124与基板110上的部分焊盘一一对应地连接。即第一芯片120与基板110之间采用BGA(Ball Grid Array Package，球栅阵列封装)封装工艺进行封装。当然，其它实施例中，第一芯片120和基板110也可以采用LGA(Land Grid Array，栅格阵列封装)封装工艺进行封装。
请参照图5和图6，第二芯片130大致呈方形且设置于第一芯片120靠近基板110的一侧。第二芯片130靠近第一芯片120的一侧设置有多个第二引脚132，多个第二引脚132与多个第一引脚122一一对应地连接，从而实现第二芯片130和第一芯片120的物理连接和电连接。即第二芯片130与第一芯片120采用LGA封装工艺进行封装。当然，其它实施例中，第二芯片130与第一芯片120也可以采用BGA封装工艺进行封装。
第二芯片130穿设于通孔112，这样可以使得第二芯片130和基板110至少共用一部分芯片封装结构100的厚度空间，从而减小芯片封装结构100整体的厚度及体积。
需要说明的是，第二芯片130包括放大单元、移相单元等，以对第一芯片120输出的中频信号进行处理，从而将中频信号转换为毫米波信号，或者对天线140接收的毫米波信号进行处理，从而将毫米波信号转换为中频信号。
天线140可以根据需要采用不同的类型，本实施例中，天线140为相控阵天线140，相控阵天线140可以通过控制相位以改变天线140方向图最大值的指向，以达到波束快速灵活扫描的目的，从而提高对毫米波信号的发射和接收性能。
请再参照图1和图2，天线140设置于第二芯片130远离第一芯片120的一侧。为了保证毫米波信号的发射和接收效果，本实施例中，天线140至少部分位于通孔112外，以扩大毫米波信号的发射角度范围或者接收角度范围。可选地，天线140完全位于通孔112外，以保证最大的发射角度范围或者接收角度范围。其它实施例中，天线140也可以完全位于通孔112内。
由于基板110设有通孔112，可能导致信号的泄漏，因此为了屏蔽信号的泄漏，保证天线140发射和接收毫米波信号的性能，本实施例中，第一芯片120靠近基板110的一侧和基板110的第一侧114之间连接有接地屏蔽结构150，接地屏蔽结构150围绕第二芯片130。接地屏蔽结构150可以保证在基板110挖出通孔112露出相控阵天线140后，仍然可以有效地起到屏蔽效果。
为了进一步提高对泄漏的信号的屏蔽效果，请再参照图1，本实施例中，基板110的第一侧114设置有屏蔽罩160，屏蔽罩160罩住第一芯片120，以防止第一芯片120泄漏的杂波辐射出去，保证天线140对毫米波的接收和发射性能。
在一些实施例中，芯片封装结构100还包括包覆基板110、第一芯片120及第二芯片130的塑封体(图中未示出)，以避免芯片封装结构100被轻易损坏。其中，需要说明的是，塑封体可以将天线140一并包覆，也可以不包覆天线140。
以上便是本公开实施例提供的芯片封装结构100的构造，下面详细介绍制作上述芯片封装结构100的芯片封装方法。本公开实施例提供的芯片封装方法包括以下步骤：
步骤S100：在第一芯片120上贴装带有天线140的第二芯片130。
详细地，第一芯片120和第二芯片130采用BGA封装工艺进行贴片焊接。由于第一芯片120的面积大于第二芯片130，因此两者贴装焊 接后，整体形成阶梯结构。在第一芯片120和第二芯片130贴装焊接之前，还需要提前在第一芯片120上制作接地屏蔽结构150，在第二芯片130上制作天线140，当两者贴装焊接后，接地屏蔽结构150围绕第二芯片130设置，天线140位于第二芯片130远离第一芯片120的一侧(详见图7和图8)。
步骤S200：将第一芯片120贴装于基板110上。
详细地，第一芯片120和基板110采用LGA封装工艺进行贴装焊接。二者贴装焊接后，第一芯片120位于基板110的第一侧114，第二芯片130则穿设于通孔112并从通孔112远离第一芯片120的一端伸出，以使第二芯片130上的天线140完全位于通孔112外，同时接地屏蔽结构150远离第一芯片120的一侧与基板110的第一侧114贴合(详见图1和图2)。
步骤S300：在基板110的第一侧114安装屏蔽罩160。
详细地，屏蔽罩160可以根据需要采用不同的方式安装于基板110，比如焊接、粘接等。屏蔽罩160安装后罩住第一芯片120。
以上便是本公开实施例提供的芯片封装结构100的制作流程，下面详细介绍该芯片封装结构100的工作过程：
本芯片封装结构100能够实现毫米波信号的发射和接收。需要发射信号时，首先由第一芯片120对基带部分输出的基带信号进行处理，以向第二芯片130输出中频信号；之后由第二芯片130对第一芯片120输出的中频信号进行处理，以向天线140输出毫米波信号，最后由天线140将第二芯片130输出的毫米波信号发射出去；需要接收信号时，首先由天线140接收毫米波信号，之后由第二芯片130对天线140接收的毫米波信号进行处理，以向第一芯片120输出中频信号，最后由第一芯片120对第二芯片130输出的中频信号进行处理，以向基带部分输出基带信号；需要同时发射和接收信号时，同时执行上述两个流程即可。
综上，本公开实施例提供的芯片封装结构100包括基板110、第一芯片120、第二芯片130及天线140，第一芯片120设置于基板110上且与基板110电连接，第二芯片130设置于第一芯片120上且与第一 芯片120电连接，天线140设置于第二芯片130上且与第二芯片130电连接。该芯片封装结构100通过将第一芯片120(相当于现有的毫米波收发系统的收发模组)和第二芯片130(相当于现有的毫米波收发系统的收发组件)集成设置，可以从很大程度上缩短二者之间的物理距离，从而缩短了二者之间信号传播的距离，进而有效减小在二者之间传播的中频信号的衰减，降低芯片封装结构100内部的能耗，保证芯片封装结构100内部的通信质量。
同时，由于第一芯片120和第二芯片130通信不再需要连接器和线缆，因此不但可以降低芯片封装结构100的生产成本，而且不用担心连接器在芯片封装结构100随电子设备移动的过程中松脱而影响信号连接的稳定性。
第二实施例：
请参照图9和图10，本实施例也提供了一种芯片封装结构100，其整体构造、工作过程及取得的技术效果与第一实施例提供的芯片封装结构100基本相同，不同之处在于基板110和第二芯片130的相对位置关系。
本实施例中，基板110不再设置通孔112，第二芯片130设置于第一芯片120远离基板110的一侧，此时，第一芯片120上不需要再设置接地屏蔽结构150，基板110上也不需要设置屏蔽罩160。因此，本实施例提供的芯片封装结构100具有结构更加简单，相应的制作方法也更加简单。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开提供芯片封装结构包括基板、第一芯片、第二芯片及天线，第一芯片设置于基板上且与基板电连接，第二芯片设置于第一芯片上且与第一芯片电连接，天线设置于第二芯片上且与第二芯片电连接。 第一芯片设置为输入或者输出中频信号，第二芯片设置为转换中频信号和毫米波信号，天线设置为发射或者接收毫米波信号。芯片封装结构及对应的芯片封装方法通过将第一芯片和第二芯片集成设置，从很大程度上缩短二者之间的物理距离，从而有效减小在二者之间传播的中频信号的衰减，保证芯片封装结构内部的通信质量。电子设备包括上述的芯片封装结构，具有信号衰减小，通信质量高的特点，具有很强的工业实用性。

Claims (10)

  1. 一种芯片封装结构，包括：
    基板；
    第一芯片，设置于所述基板上且与所述基板电连接；
    第二芯片，设置于所述第一芯片上且与所述第一芯片电连接；
    天线，设置于所述第二芯片上且与所述第二芯片电连接；
    其中，所述第一芯片、所述第二芯片和所述天线采用下列方式中的至少一种方式工作：
    所述第一芯片设置为输出中频信号，所述第二芯片设置为对所述中频信号进行处理，以输出毫米波信号，所述天线设置为发射所述毫米波信号；以及
    所述天线设置为接收毫米波信号，所述第二芯片设置为对所述毫米波信号进行处理，以输出中频信号，所述第一芯片设置为接收并处理所述中频信号。
  2. 根据权利要求1所述的芯片封装结构，其中，所述基板具有相对的第一侧和第二侧，所述基板开设有贯穿所述第一侧和所述第二侧的通孔，所述第一芯片设置于所述第一侧，所述第二芯片设置于所述第一芯片靠近所述基板的一侧且穿设于所述通孔，所述天线设置于所述第二芯片远离所述第一芯片的一侧。
  3. 根据权利要求2所述的芯片封装结构，其中，所述天线至少部分位于所述通孔外。
  4. 根据权利要求2所述的芯片封装结构，其中，所述第一芯片靠近所述基板的一侧和所述基板的第一侧之间连接有接地屏蔽结构，所述接地屏蔽结构围绕所述第二芯片。
  5. 根据权利要求2所述的芯片封装结构，其中，所述基板的第一侧设置有屏蔽罩，所述屏蔽罩罩住所述第一芯片。
  6. 根据权利要求1-5任一项所述的芯片封装结构，其中，所述第一芯片与所述基板之间采用BGA封装工艺进行封装，所述第二芯片与所述第一芯片之间采用LGA封装工艺进行封装。
  7. 根据权利要求1-5任一项所述的芯片封装结构，其中，所述第一芯片设置有多个第一引脚，所述第二芯片设置有多个第二引脚，所述多个第二引脚与所述多个第一引脚一一对应地连接。
  8. 根据权利要求1-5任一项所述的芯片封装结构，其中，芯片封装结构还包括包覆所述基板、第一芯片及第二芯片的塑封体。
  9. 一种芯片封装方法，包括：
    在第一芯片上贴装带有天线的第二芯片；
    将所述第一芯片贴装于基板上；
    其中，所述第一芯片、所述第二芯片和所述天线采用下列方式中的至少一种方式工作：
    所述第一芯片设置为输出中频信号，所述第二芯片设置为对所述中频信号进行处理，以输出毫米波信号，所述天线设置为发射所述毫米波信号；以及
    所述天线设置为接收毫米波信号，所述第二芯片设置为对所述毫米波信号进行处理，以输出中频信号，所述第一芯片设置为接收并处理所述中频信号。
  10. 一种电子设备，包括权利要求1-8任一项所述的芯片封装结构或者由权利要求9所述的芯片封装方法制作的芯片封装结构。
PCT/CN2020/140816 2020-12-15 2020-12-29 芯片封装结构、芯片封装方法及电子设备 WO2022126754A1 (zh)

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