WO2022126635A1

WO2022126635A1 - Read/write controller, memory and electronic device

Info

Publication number: WO2022126635A1
Application number: PCT/CN2020/137718
Authority: WO
Inventors: 蔡江铮; 布明恩; 欧阳晟
Original assignee: 华为技术有限公司
Priority date: 2020-12-18
Filing date: 2020-12-18
Publication date: 2022-06-23
Also published as: CN116457886A

Abstract

A read/write controller, a memory and an electronic device, which are used for improving the write flexibility of the memory. The read/write controller comprises a clock generation circuit, a multi-state write circuit, a row decoding circuit and a column decoding circuit. The clock generation circuit provides a first clock signal to the multi-state write circuit, and provides a second clock signal to the row decoding circuit and the column decoding circuit. By configuring a separate working clock to the multi-state write circuit, the read/write controller is enabled to flexibly configure the current working clock of the multi-state write circuit according to the current process deviation, which not only helps to improve the flexibility of a multi-state write operation, but also enables the write operation to better match the current process deviation by adjusting the current working clock of the multi-state write circuit, thereby improving the capability of the read/write controller to cope with different process deviations. Furthermore, the multi-state write circuit can also write at least two states into a memory array in one clock cycle of the first clock signal, thus further contributing to improving the writing efficiency of the read/write controller.

Description

A read-write controller, memory and electronic equipment

technical field

The present application relates to the technical field of memory, and in particular, to a read-write controller, a memory and an electronic device.

Background technique

In recent years, with the development and popularization of semiconductor technology, many new types of memory have emerged, such as ferroelectric random access memory (FeRAM), phase change random access memory (PCRAM) , magnetic random access memory (magnetic random access memory, MRAM) and resistive random access memory (resistive random access memory, ReRAM) and so on. These new types of memories have smaller memory cell size and can achieve faster access speed with lower power consumption, and have been more and more widely used at this stage.

However, the memory in the prior art uses the same clock signal as the operating clock for each of its internal circuits. In this way, the write operation of the memory is actually coupled with other operations, so that the memory can only execute the write operation and other operations according to the same working clock, but cannot execute the writing according to the working clock required by itself. operate. This approach reduces the write flexibility of the memory.

In view of this, the present application provides a read-write controller to improve the writing flexibility of a memory.

SUMMARY OF THE INVENTION

The present application provides a read-write controller, a memory and an electronic device to improve the writing flexibility of the memory.

In a first aspect, the present application provides a read/write controller, including a clock generation circuit, a multi-state write circuit, a row decoding circuit and a column decoding circuit. The clock generating circuit includes a first clock output terminal and a second clock output terminal, and the clock frequency of the first clock signal output by the first clock output terminal is higher than the clock frequency of the second clock signal output by the second clock output terminal. The first clock output terminal can be connected to the input terminal of the multi-state write circuit, and the output terminal of the multi-state write circuit can be connected to the storage array. In this way, the multi-state write circuit can be provided by the first clock signal output by the first clock output terminal. Under the operating clock, at least two states are written to the memory array in one clock cycle. The second clock output terminal can be connected to the input terminal of the row decoding circuit and the input terminal of the column decoding circuit respectively, and the output terminal of the row decoding circuit and the output terminal of the column decoding circuit can be respectively connected to the storage array. The circuit and the column decoding circuit can perform respective decoding operations under the operating clock provided by the second clock signal.

In the above design, by configuring different operating clocks for the multi-state write circuit and other circuits in the read-write controller (such as the row decoding circuit and the column decoding circuit), the read-write controller can use a separate operating clock to execute Multi-state write operation, this method realizes the decoupling of multi-state write operation and other operations, which not only helps to improve the flexibility of multi-state write operation, but also does not adjust the working clock corresponding to read and write operations. affect the normal operation of other circuits. Moreover, the multi-state write circuit in this way can write at least two states in one clock cycle, instead of writing one state in each clock cycle, so this way also helps to improve the read-write controller's performance. write efficiency. In addition, by providing a separate working clock for the multi-state write circuit, the above design can flexibly configure the current working clock of the multi-state write circuit according to the current process deviation of the memory, so as to make the write operation of the read-write controller match the current Process deviation, improve the ability of the read-write controller to deal with different process deviations.

In a possible design, the read/write controller may further include a sense amplifier, the clock control end of the sense amplifier may be connected to the first clock output end, the first input end of the sense amplifier may be connected to the reference unit in the storage array, and the sense amplifier The second input terminal of the sensor can be connected to at least one storage unit in the storage array, and the output terminal of the sense amplifier can be connected to a reading device. In the above design, a separate operating clock is configured through the sense amplifier, so that the read-write controller can also use a separate operating clock to perform the read operation. This method realizes the decoupling of the read operation from other operations, which is helpful for Improve the flexibility of read operations. Furthermore, the design sets the same working clock for the sense amplifier and the multi-state writing circuit, without distributing the working clock separately, so it can further reduce the complexity of the circuit structure and the circuit cost while independently controlling the read and write operations.

In a possible design, when the memory array is in the readout mode, within one cycle of the first clock signal, if the first clock signal switches from the second level to the first level, the sense amplifier obtains the reference cell The reference signal in and the storage signal in at least one storage unit, and the data stored in the storage unit is obtained by calculating according to the reference signal and the storage signal. The design can flexibly adjust the turn-on time of the sense amplifier by adjusting the level switching time of the clock signal. For example, the sense amplifier can be turned on in advance when the bit line is charged and discharged quickly to improve the read efficiency, or when the charge and discharge of the bit line is slow. Turn on the sense amplifier to improve the accuracy of reading. This method not only makes the read-write controller adapt to different reading scenarios, but also does not require additional components such as inverters, which helps to reduce the cost and cost of the read-write controller. The complexity of the circuit structure.

In this application, the clock generation circuit capable of generating two clock signals may have various possibilities, such as:

In a possible design, the clock generating circuit may further include a first clock generator and a frequency divider. The output end of the first clock generator is connected to the first clock output end and the input end of the frequency divider, respectively. The frequency divider The output terminal is connected to the second clock output terminal. In this way, the first clock generator can generate the first clock signal and provide it to the first clock output terminal and the frequency divider respectively. On the one hand, the first clock signal can be provided to the multi-state writing circuit (and the sense amplifier) through the first clock output terminal. ), on the other hand, it can also be divided into a lower frequency second clock signal by a frequency divider and supplied to the second clock output terminal, which is supplied to the row decoding circuit and the column decoding circuit by the second clock output terminal. The design can obtain two different frequency clock signals through a clock generator and a frequency divider.

In another possible design, the clock generation circuit may further include a second clock generator and a frequency multiplier, and the output end of the second clock generator is respectively connected to the second clock output end and the input end of the frequency multiplier, and the frequency multiplier is The output end of the device is connected to the first clock output end. In this way, the second clock generator can generate the second clock signal and provide it to the second clock output terminal and the frequency multiplier respectively. On the one hand, the second clock signal can be provided to the row decoding circuit and the column decoding circuit through the second clock output terminal. The circuit, on the other hand, can also be divided into a higher frequency first clock signal by a frequency multiplier and then supplied to the first clock output terminal, which is then supplied to the multi-state writing circuit (and the sense amplifier) by the first clock output terminal. The design can obtain two different frequency clock signals through a clock generator and a frequency multiplier.

In yet another possible design, the clock generating circuit may further include a third clock generator and a fourth clock generator, the output end of the third clock generator is connected to the first clock output end, and the output end of the fourth clock generator Connect the second clock output. As such, a third clock generator can generate and provide a first clock signal to a first clock output for supply to the multi-state write circuit (and sense amplifier) via the first clock output, and a fourth clock generator can generate a second The clock signal is also supplied to the second clock output terminal to be supplied to the row decoding circuit and the column decoding circuit through the second clock output terminal. The design can obtain two clock signals with different frequencies through two clock generators.

In one possible design, the multi-state write circuit may include an inverter, a first metal oxide semiconductor (MOS) transistor and a second MOS transistor, an input terminal of the inverter and a second MOS transistor. The gates of the MOS tubes are respectively connected to the input terminals of the multi-state writing circuit, the output terminals of the inverters are connected to the gates of the first MOS tubes, the sources of the first MOS tubes are connected to the first power supply, and the sources of the second MOS tubes are connected to For the second power supply, the drain of the first MOS transistor and the drain of the second MOS transistor are connected to the storage array. This design can realize continuous writing of at least two states to the memory cell in one clock cycle through only one inverter and two MOS tubes, which not only simplifies the circuit structure, but also enables the two MOS tubes to be at the same level of the clock signal. In the opposite state, the read-write controller can realize the switching of the writing state by controlling the level switching of the clock signal.

In a possible design, when the memory array is in the write mode, within one cycle of the first clock signal, if the first clock signal switches from the first level to the second level, the multi-state write circuit will write to the The memory array writes the first state, and if the first clock signal switches from the second level to the first level, the multi-state write circuit writes the second state to the memory array. In this design, by adjusting the level switching moment of the first clock signal, the multi-state writing circuit can start to write the second state just after the writing time corresponding to the process deviation, so as to accurately track the process deviation of the memory and improve the The ability of the read-write controller to withstand the effects of various process variations.

In a second aspect, the present application provides a memory, including a storage array and the read-write controller according to any one of the above first aspects, the read-write controller can be connected to the storage array, the storage array can be used to store data, read and write The controller can write data to the storage array, or read data from the storage array.

In a third aspect, the present application provides an electronic device, comprising a printed circuit board (PCB) and the memory provided in the second aspect above, where the memory is provided on a surface of the PCB.

Specifically, the electronic devices include, but are not limited to: smart phones, smart watches, tablet computers, virtual reality (VR) devices, augmented reality (AR) devices, in-vehicle devices, desktop computers, personal computers, handheld computer or personal digital assistant.

The above-mentioned aspects or other aspects of the present application will be described in detail in the following embodiments.

Description of drawings

FIG. 1 exemplarily shows a schematic diagram of the internal structure of a memory to which an embodiment of the present application is applicable;

FIG. 2 exemplarily shows a schematic structural diagram of a read-write controller provided by an embodiment of the present application;

FIG. 3 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application;

FIG. 4 exemplarily shows a schematic diagram of a multi-state write solution provided by an embodiment of the present application;

FIG. 5 exemplarily shows a schematic diagram of another multi-state write scheme provided by an embodiment of the present application;

FIG. 6 exemplarily shows a performance comparison diagram of a multi-state write circuit provided by an embodiment of the present application;

FIG. 7 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application;

FIG. 8 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application;

FIG. 9 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application;

FIG. 10 exemplarily shows a comparison diagram of a reading scheme provided by an embodiment of the present application;

FIG. 11 exemplarily shows a read-write control sequence diagram provided by an embodiment of the present application;

FIG. 12 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application;

FIG. 13 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application;

FIG. 14 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application.

Detailed ways

The read-write controller disclosed in this application can be applied to devices with read-write functions, for example, can be applied to storage devices that only have read-write functions, such as memories, and can also be applied to electronic devices with read-write functions and other functions. equipment. In some embodiments of the present application, the read-write controller may be an independent unit, and the unit may be embedded in an electronic device and can perform read-write control of the memory of the electronic device. In other embodiments of the present application, the read-write controller may also be a unit packaged inside the electronic device, and is used to implement the read-write control function of the memory of the electronic device. The electronic device may be a portable electronic device including functions such as a personal digital assistant and/or a music player, such as a mobile phone, a tablet computer, a wearable device with wireless communication capabilities (eg, a smart watch), or a vehicle-mounted device. Exemplary embodiments of portable electronic devices include, but are not limited to, carry-on

Or portable electronic devices with other operating systems. The aforementioned portable electronic device may also be, for example, a laptop computer (Laptop) having a touch-sensitive surface (eg, a touch panel). It should also be understood that, in some other embodiments of the present application, the above-mentioned electronic device may also be a desktop computer having a touch-sensitive surface (eg, a touch panel).

Illustratively, the memory may be volatile memory, or may include both volatile and nonvolatile memory. Volatile memory may be random access memory (RAM), which acts as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (synchlink DRAM, SLDRAM) ) and direct memory bus random access memory (direct rambus RAM, DR RAM), and new types of memories such as FeRAM, PCRAM, MRAM and ReRAM. When the memory further includes non-volatile memory, the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory Memory (erasable PROM, EPROM), electrically erasable programmable read-only memory

(electrically EPROM, EEPROM) or flash memory. When the memory includes both volatile memory and non-volatile memory, the read-write controller in this application can be used to read data in the non-volatile memory and/or the volatile memory, and can also be used to Write data to volatile memory. It should be noted that the memory described herein is intended to include, but not be limited to, these and any other suitable types of memory.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be understood that in the following description of the present application, "a plurality" can be understood as "at least two". Words such as "first" and "second" are only used for the purpose of distinguishing and describing, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. For example, the "first clock signal" and "second clock signal" mentioned below are only used to indicate different clock signals, and do not have differences in order, priority or importance.

FIG. 1 exemplarily shows a schematic diagram of the internal structure of a memory to which an embodiment of the present application is applied.

It should be understood that the illustrated memory 100 is only an example, and that the memory 100 may have more or fewer components than those shown, two or more components may be combined, or may have different component configurations . The various components shown in the figures may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and/or application specific integrated circuits.

As shown in FIG. 1 , the memory 100 may include a memory array 110 and a read-write controller 120 . The read/write controller 120 may include a clock generation circuit 121 , a read/write driving circuit 122 , a row decoding circuit 123 , a word line (WL) circuit 124 , a column decoding circuit 125 , a sense amplifier 126 and an input/output driving circuit 127 Wait. Among them, each component in the read-write controller 120 refers to functional components, and these components can be set as separate components, or can be implemented in one device, or can be set in at least two devices in any combination. This application does not specifically limit this.

Each component in the memory 100 will be described in detail below with reference to FIG. 1 :

The storage array 110, used for storing data, is a matrix array formed by a plurality of storage cells arranged in rows and columns. Wherein, each storage unit in the plurality of storage units can store 1-bit binary data, such as 0 or 1. Multiple storage units may be located on different disks or on different tracks of the same disk. When multiple storage units are located on different disks, this arrangement actually combines multiple disks into one disk for use: when data needs to be stored, the data is split into multiple data segments and stored separately on multiple disks In; when data needs to be fetched, multiple disks act together to output their corresponding data segments in parallel. Using this arrangement to store data in the memory can not only effectively improve the reading and writing efficiency of the data through parallel access of multiple disks, but also improve the space utilization of the memory through the array arrangement.

The clock generating circuit 121 is used to provide the working clock to each component in the read-write controller 120 . The clock generation circuit 121 may have a plurality of clock output terminals, and each clock output terminal of the plurality of clock output terminals may be connected to one or more components in the read/write controller 120, so as to send the clock output terminal to the connected device through each clock output terminal. One or more components provide the operating clock. As shown in FIG. 1 , in this example, the clock generation circuit 121 may include five clock output terminals, namely, clock output terminal A ₁ , clock output terminal A ₂ , clock output terminal A ₃ , clock output terminal A ₄ and clock output terminal A 4 , and clock output terminal A 2 . Terminal A5 _; the clock output terminal A1 is respectively connected to the sense amplifier 126 and the input and output driving circuit 127, and the clock generating circuit 121 can provide the same working clock to the sensitive amplifier 126 and the input and output driving circuit 127 through the clock output terminal _A1 _; the clock output terminal A ₂ is connected to the read-write drive circuit 122, and the clock generation circuit 121 can provide a working clock to the read-write drive circuit 122 through the clock output terminal A ₂ ; the clock output terminal A ₃ is connected to the word line circuit 124, and the clock generation circuit 121 can pass the clock output terminal. A3 provides the working clock to the word line circuit 124 _; the clock output terminal _A4 is connected to the row decoding circuit 123, and the clock generating circuit 121 can provide the working clock to the row decoding circuit 123 through the clock output terminal A4 _; the clock output terminal _A5 is connected to _The column decoding circuit 125 and the clock generating circuit 121 can provide the column decoding circuit 125 with a working clock through the clock output terminal A5. Illustratively, although not shown in FIG. 1 , the memory array 110 may also have an operating clock. The operating clock of the storage array 110 may be provided by the clock generating circuit 121, or may be provided by a separate clock generator packaged inside the storage array 110, or may be provided by other components in the electronic device, which are not specifically limited in this application.

The row decoding circuit 123 is used for decoding the row address information to obtain the row where the target storage unit is located.

The word line circuit 124 may include a plurality of word lines corresponding to a plurality of rows of memory cells in the memory array 110, the input end of each word line is connected to the output end of the row decoding circuit 123, and the output end of each word line Connect to the control terminal of the corresponding row of storage units. After the row decoding circuit 123 decodes and obtains the row where the target memory cell is located, it can also send a decoding selection signal to the target word line connected to the row where the target memory cell is located in the word line circuit 124 to instruct the target word line to work, and send a decoding selection signal to the target word line. The other word lines in word line circuit 124 send decode off signals to instruct the other word lines to wait. When the target word line is working, it can output the first word line signal (such as a high level) to the connected memory cell row to turn on the connected memory cell row, and other word lines can output to the connected memory cell row while waiting. A second word line signal (eg, low) to turn off the connected row of memory cells.

The column decoding circuit 125 is used for decoding the column address information to obtain the column where the target memory cell is located.

The read-write driving circuit 122 is used for reading and writing data in the target storage unit. The input terminal of the read-write driving circuit 122 is connected to the output terminal of the column decoding circuit 125 (not shown in FIG. 1 ), and the output terminal of the read-write driving circuit 122 is connected to each memory cell. After the column decoding circuit 125 decodes the column where the target memory cell is located, it can send instruction information to the read-write driving circuit 122 to instruct the read-write driving circuit 122 to read and write the data of the column where the target memory cell is located. At this time, only the row where the target memory cell is located is turned on, so the data read and written by the read-write driving circuit 122 is the data in the target memory cell.

According to the above content, the read-write driving circuit 122 can cooperate with other circuits in the read-write controller 120 to realize the read-write operation of the data in the storage array. The following is a detailed introduction from the two aspects of writing data and reading data:

The read-write driving circuit 122 can combine the row decoding circuit 123 , the word line circuit 124 and the column decoding circuit 125 to write data into the memory array 110 . Assuming that the external device 200 (such as a read-write device or a processor) wants to write “0” to the target memory cell located at the third row and fourth column of the memory array 110 , the external device 200 can first send a message to the read-write driving circuit 122 A write request, and the write request carries the row address information and column address information of the target memory cell. The read-write drive circuit 122 sends the row address information carried in the write request to the row decoding circuit 123, and the row decoding circuit 123 decodes the row address information to determine the row where the target memory cell is located. Therefore, the row decoding The circuit 123 sends a decoding selection signal to the target word line corresponding to the memory cells in the third row in the word line circuit 124, so that the target word line turns on the memory cells in the third row. After that, the read-write driving circuit 122 can also send the column address information carried in the write request to the column decoding circuit 125, and the column decoding circuit 125 decodes the column address information to obtain the fourth column of the column where the target memory cell is located, Therefore, the column decoding circuit 125 returns a response to the read-write driving circuit 122 to instruct the read-write driving circuit 122 to write data to the target memory cells in the third row that have been turned on in the memory cells in the fourth column. Among them, the read-write drive circuit 122 is provided with a write circuit (such as a multi-state write circuit), and the read-write drive circuit triggers the clock generation circuit 121 to output the level corresponding to the data to be written to the write circuit. 0", the clock generation circuit 121 is triggered to output a high level to the write circuit, and the high level and the local reference level of the write circuit form a first voltage difference to drive the write circuit to write "0" to the target memory cell, When "1" needs to be written, the clock generation circuit 121 is triggered to output a low level to the write circuit, the low level and the local reference level of the write circuit form a second voltage difference to drive the write circuit to write to the target memory cell Enter "1". It can be seen from this that in the scenario of continuously writing two states, the generation time of the first voltage difference and the second voltage difference corresponding to the two states to be written determines when to start writing the two states.

The read-write driving circuit 122 can also read the data in the memory array 110 in conjunction with the row decoding circuit 123 , the word line circuit 124 , the column decoding circuit 125 and the sense amplifier 126 . Assuming that the external device 200 wants to read the data stored in the target storage unit located at the third row and the fourth column of the storage array 110, the external device 200 can first send a read request to the read-write driving circuit 122, and in the read The fetch request carries the row address information and column address information of the target memory cell. The read-write driving circuit 122 can first open the target memory at the third row and the fourth column of the memory array 110 in conjunction with the row decoding circuit 123, the word line circuit 124 and the column decoding circuit 125 according to the same logic as the above-mentioned write operation. unit. After that, the read-write drive circuit 122 can trigger (eg, output a low level) the opened target memory cell (and the reference cell) through the level of the clock generation circuit 121. The charge and discharge operation will be described later. No description) to perform charging and discharging, and then after a fixed time delay or through the control of the reference unit, the sense amplifier is turned on, so that the sense amplifier 126 determines according to the potential difference between the target memory cell and the reference cell to store in the opened target memory cell. The data. It can be seen that in the reading scenario, the ON time of the sense amplifier determines when to start reading data.

The input and output driving circuit 127 is used to strengthen the driving to realize the interaction between the read-write controller 120 and the external device 200 . For example, when the external device 200 requests to read the data in the memory array 110 , the I/O driving circuit 127 can first obtain the data read by the sense amplifier 126 , and then increase the driving electrical signal (eg, driving current) to output to the external device 200 the data. For another example, when the external device 200 requests to write data into the storage array 110, the I/O driving circuit 127 can first increase the driving electrical signal (eg, driving current) to obtain the data to be written from the external device 200, and then The data to be written is sent to the writing circuit in the read-write driving circuit 122, so that the writing circuit can write the data to be written into the storage array 110 according to the above-mentioned writing logic.

Although not shown in FIG. 1 , the memory 100 may also include other components, such as a main memory data register (MDR) and a main memory address register (MAR), etc., which will not be repeated here.

At this stage, the clock generation circuit provides the same working clock with a fixed frequency to each component in the read-write controller through each clock output terminal (eg, the above-mentioned clock output terminal A ₁ to clock output terminal A ₅ ). This actually couples the read and write operations of the read-write controller and other operations (such as decoding operations, row-opening operations, column-opening operations, and driver-enhancing operations, etc.) It can perform various operations according to the same working clock, but cannot perform read and write operations according to its own required working clock, so the read-write controller has poor read-write flexibility. Moreover, the current read-write control scheme depends on the specific circuit structure. As long as the circuit structure is fixed, each time node involved in the read-write control process is basically fixed, which leads to the adjustability of the read-write control. poor. For example, when two states are continuously written, the second state can only be written at a fixed time interval corresponding to the circuit structure after starting to write the first state. However, the memory may require different write times under the influence of different process deviations. For example, when the process deviation is large, the read-write controller may take a long time to accurately write the first state to the storage array. In this case, the read-write controller actually needs a longer time interval to improve the accuracy of the written data. When the process variation is small, the read-write controller may be able to accurately write the first state to the storage array in a very short time. In this case, the read-write controller actually needs a short time interval to Maximize write speed while accurately writing data. Obviously, the read-write method of the fixed time interval in the prior art cannot make the read-write performance of the read-write controller meet the requirements of different process scenarios, resulting in a weak ability of the read-write controller to cope with the influence of different process deviations.

Based on this, the present application provides a read-write controller, which is used to provide a separate working clock for key circuits (such as multi-state write circuits and sense amplifiers) related to read-write in the read-write controller, so as to improve the read-write control On the basis of the read-write flexibility of the controller, the ability of the read-write controller to cope with the influence of different process deviations is further improved.

Based on the memory shown in FIG. 1 , the specific structure of the read-write controller provided by the present application is described below with specific embodiments. It should be noted that the "connection" in the following embodiments of the present application refers to electrical connection, and the connection of two electrical elements may be a direct or indirect connection between two electrical elements. For example, the connection between A and B can be either a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components, such as the connection between A and B, or the direct connection between A and C, C and B are directly connected, and A and B are connected through C. It should be understood that the "1" and "0" in the 1 level and the 0 level in the digital signal are "1" and "0" in the logic operation, not the voltage value of the signal voltage of the digital signal. In most cases, the 1 level in the digital signal means that the signal voltage of the digital signal is greater than the threshold voltage, and the 0 level means that the signal voltage of the digital signal is less than the threshold voltage. For ease of expression, in the following embodiments of the present application, a high level is used to represent a 1 level in the digital signal, and a low level is used to represent a 0 level in the digital signal.

[Example 1]

FIG. 2 exemplarily shows a schematic structural diagram of a read-write controller provided by an embodiment of the present application. As shown in FIG. 2 , in the embodiment of the present application, the read-write controller 120 includes a clock generation circuit 121 and a key read-write circuit. 130 and the non-critical read-write circuit 140, the critical read-write circuit 130 and the non-critical read-write circuit 140 are respectively connected to the storage array 110. The clock generating circuit 121 includes a first clock output terminal (B ₁ ) and a second clock output terminal (B ₂ ). _The clock output terminal B1 is connected to the clock control terminal of the key read-write circuit 130, and the clock generation circuit 121 can output the first clock signal (Input) to the key read-write circuit ₁₃₀ through the clock output terminal B1, so that the key read-write circuit 130 can be The key read and write operations to the memory array 110 are implemented under the working clock provided by the clock signal Input. _The clock output terminal B2 is connected to the clock control terminal of the non-critical reading and writing circuit 140, and the clock generating circuit 121 can output a _second clock signal (Inner) to the non-critical reading and writing circuit 140 through the clock output terminal B2, so as to facilitate non-critical reading and writing The circuit 140 performs other operations, such as row decoding, row decoding, word line selection and enhanced driving, on the memory array 110 under the operating clock provided by the clock signal Inner except the above-mentioned key read and write operations. The clock frequency of the clock signal Input is higher than the clock frequency of the clock signal Inner.

In this embodiment of the present application, the key read-write circuit 130 refers to a circuit that can decide when to start reading and writing data in the target storage unit according to its own operating clock, such as the multi-state write circuit described below and/or FIG. 1 . The illustrated sense amplifier can also include other circuits that can decide when to start reading and writing, such as the circuit for generating the first voltage difference and the second voltage difference in the read-write driving circuit 122 shown in FIG. In the scenario where only one state is written, the circuit for determining the writing time of one state, etc., is not specifically limited. Correspondingly, the non-critical read-write circuit 140 refers to one or more other circuits other than the critical read-write circuit 130, for example, the row decoding circuit 123, the column decoding circuit 125, the read-write driver shown in FIG. 1 may be included. The circuit 122 (or a circuit other than the circuit for generating the first voltage difference and the second voltage difference in the read-write driving circuit 122 ) or the input-output driving circuit 127 or the like. In this way, by configuring different working clocks for key read-write circuits and non-critical read-write circuits, it is helpful to realize the decoupling of key read-write operations and other operations. The flexibility of the key read-write circuit can be effectively improved, and the normal operation of the non-critical read-write circuit will not be affected.

For ease of understanding, the following embodiments of the present application are described by taking the key read-write circuit including the multi-state write circuit as an example. It should be understood that all the contents introduced below are also applicable to the read/write controller 120 in FIG. 2 , which will not be repeated in this application.

FIG. 3 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application. As shown in FIG. 3 , in this example, the critical read-write circuit 130 includes a multi-state write circuit 128, and the non-critical read-write circuit 130 includes a multi-state write circuit 128. The circuit 140 includes a row decoding circuit 123 and a column decoding circuit 125 . In this example, when the memory is in the write mode, the clock generation circuit 121 can output the _first clock signal (Input) to the multi-state write circuit 128 through the clock output terminal B1, and the multi-state write circuit 128 can provide the clock signal Input according to the clock signal Input. At least two states are written to the memory array 110 within one clock cycle of the operating clock. The clock generation circuit 121 can also output a _second clock signal (Inner) to the row decoding circuit 123 and the column decoding circuit 125 through the clock output terminal B2, so that the row decoding circuit 123 and the column decoding circuit 125 are in the clock signal Inner. The row decoding and column decoding described above are performed under the provided working clock. For example, the row decoding circuit 123 can decode the row address information under the working clock provided by the clock signal Inner to determine the row where the target memory cell is located and send the data to the target memory cell. The word line circuit sends an instruction, and the column decoding circuit 125 can decode the column address information under the operating clock provided by the clock signal Inner to determine the column where the target memory cell is located and return a response to the read-write driving circuit.

In this embodiment of the present application, the clock frequency of the clock signal Input is higher than the clock frequency of the clock signal Inner. In this way, under one level state of the clock signal Inner, the clock signal Input can correspond to at least two level changes, and correspondingly, the multi-state writing circuit 128 can also correspond to at least two output voltages. Compared with the voltage controlled by the same level of the clock signal Inner, the two output voltages can form at least two voltage differences. In this way, the read/write controller 120 can be based on the at least two voltages within one clock cycle of the clock signal Input. The voltage difference completes the write control of at least two states. Moreover, the multi-state write circuit 128 performs at least two-state write operations under a fast operating clock, while other circuits perform other operations in the memory (such as row decoding, row decoding, etc.) under a slow operating clock. , word line selection and enhanced drive, etc.), and can also write at least two states quickly while minimizing the power consumption required for other operations of the memory.

It should be noted that the multi-state write circuit 128 shown in FIG. 3 may correspond to the word line circuit 124 shown in FIG. 1 . For example, the multi-state write circuit 128 refers to the word line circuit 124 , or the multi-state write circuit 128 is A functional component in word line circuit 124 . When the multi-state write circuit 128 is a functional component in the word line circuit 124, other circuits in the word line circuit 124 except the multi-state write circuit 128 still operate based on the clock signal Inner. The above content actually provides the operation clock for the row decoding circuit 123 and the column decoding circuit 125 through the clock signal Inner, which is only an optional implementation. In other optional implementation manners, the clock signal Inner may also be used to provide an operating clock to any one or any plurality of circuits except the multi-state write circuit 128 shown in FIG. 1 . For example, in one case, the clock output terminal B2 can also be connected to the clock control terminal of the read _- write driving circuit 122, the clock control terminal of the row decoding circuit 123, the clock control terminal of the column decoding circuit 125, and the input and output drivers respectively. The clock control terminal of the circuit 127 and the clock control terminal of other circuits except the multi-state write circuit in the word line circuit 124, so that the clock generation circuit 121 can also provide the clock signal Inner to the read _- write controller through the clock output terminal B2 All other circuits in 120 except the multi-state write circuit 128. This embodiment not only enables the read-write controller to control the write operation of the multi-state write circuit based on a separate working clock, but also minimizes the number of clocks that the read-write controller needs to generate, which is helpful for simplifying the overall read-write controller. Reduce the cost of the read-write controller based on the control logic.

As shown in Figure 3 above, the read-write controller is configured with different operating clocks for the multi-state write circuit and other circuits in the read-write controller (such as the row decoding circuit and the column decoding circuit), so that the multi-state write circuit A multi-state write operation can be performed using a separate operating clock (for the convenience of explaining the scheme, this article exemplarily refers to "an operation of writing at least two states in one clock cycle" with "multi-state write operation"), in this way there are Helps achieve decoupling of multi-state write operations from other operations. In this way, by adjusting the operating clock corresponding to the multi-state write circuit, not only the flexibility of the multi-state write operation can be effectively improved, but also the normal operation of other circuits will not be affected.

In this embodiment of the present application, the multi-state write circuit 128 can write at least two states within one clock cycle of the clock signal Input. There are many possibilities for the multi-state write circuit 128 that can realize this function, and two possible solutions are exemplarily introduced below.

Option One

FIG. 4 exemplarily shows a schematic diagram of a multi-state write scheme provided by an embodiment of the present application, wherein:

(a) of FIG. 4 illustrates the circuit structure of the multi-state write scheme, as shown in (a) of FIG. 4 , in this scheme, the multi-state write circuit 128 may include a reverse delay chain 1281 and two metal oxide semiconductor (MOS) transistors of the same type, such as P-channel MOS transistor _P11 and P-channel MOS transistor _P12 , or N-channel MOS transistors _P11 and N MOS transistor P ₁₂ of the channel. The reverse delay chain 1281 may be composed of an odd number of inverters connected end to end. An inverter is a basic electronic device that accepts an input signal and outputs an output signal that is inverted from the input signal. Generally speaking, the input signal of the inverter can be a digital signal, and the level of the input signal can be divided into high level and low level. If the inverter receives a high level input signal, the inverter can output a low level. If the inverter receives a low-level input signal, the inverter can output a high-level output signal. The source of the MOS transistor _P11 can be connected to the power supply _V11 , the gate of the MOS transistor _P11 and the input terminal of the reverse delay chain 1281 can be connected to the clock output terminal B1 respectively, and the drain _of the MOS transistor _P11 can be connected to storage array 110 . The source of the MOS transistor P ₁₂ can be connected to the power supply V ₁₂ , the gate of the MOS transistor P ₁₂ can be connected to the output terminal of the reverse delay chain 1281 , and the drain of the MOS transistor P ₁₂ can be connected to the memory array 110 .

Fig. 4(b) shows the control sequence when at least two states are written according to this circuit structure, wherein the "Input" line in Fig. 4(b) shows the level of the clock signal Input Changes, the "write signal" line in (b) of FIG. 4 shows the change of the write signal. Referring to Fig. 4 (a) and Fig. 4 (b), taking the two states of "0" and "1" written in one clock cycle (such as cycle 1) of the clock signal Input as an example, Assuming that MOS transistor _P11 and MOS transistor _P12 are both P-channel MOS transistors, and regardless of the write signal delay and the pressure loss of MOS transistor _P11 and MOS transistor _P12 , if the reverse delay chain 1281 has a total of There are 27 inverters, and the time required for the signal to transmit from the input end of each inverter in the reverse delay chain 1281 to the output end is 0.1ns (ns is the time unit, that is, nanoseconds), then the reverse The delay time of the delay chain 1281 is 2.7ns (ie, 0.1ns×27). When the cycle duration of one cycle of the clock signal Input is greater than 2.7ns, if the clock generation circuit 121 outputs the clock signal Input according to the “Input” line shown in (b) in FIG. 4 , then: when the clock signal Input is at a low power Usually, the low-level signal is directly loaded _on the gate of the MOS transistor P11 after being transmitted through the link L11, so that the source and drain of the MOS transistor _P11 are turned off, and on the other hand, it is transmitted through the link L12. After the reverse processing of the phase device (it is still a low-level signal), it is loaded on the gate of the MOS transistor _P12 to make the source and drain of the MOS transistor _P12 cut off. In this case, the MOS transistor _P11 and the MOS transistor _P11 Both are turned off, the voltage at point K is 0, and the read/write controller 120 does not write data to the storage array 110 . When the clock signal Input is switched from a low level to a high level "1", the read-write drive circuit 122 in the read-write controller 120 is at the voltage corresponding to this level state (assuming it is V ₁₀ ), the high level On the one hand, the signal is directly loaded _on the gate of the MOS transistor P11 after being transmitted through the link L11, so that the source and drain of the MOS transistor _P11 are turned on, and on the other hand, the 27 inverters on the link L12 are reversely processed. After that (it is still a high-level signal), the gate is loaded on the gate of the MOS transistor _P12 with a delay of _2.7ns , so that the source and the drain of the MOS transistor P12 are turned on. In this case, before 2.7ns after the clock signal Input is switched from a low level to a high level, the MOS transistor P11 is turned _on and the MOS transistor _P12 is turned off, the voltage at point K is _V11 , and the read-write drive circuit 122 A voltage difference V ₁₀ -V ₁₁ is formed between the voltage V ₁₀ in the multi-state write circuit 128 and the voltage V ₁₁ of the multi-state write circuit 128 , so the read-write drive circuit 122 can write the voltage difference V ₁₀ -V ₁₁ to the memory array 110 status (eg write "0"). After 2.7ns, the MOS transistor P11 is turned on and the MOS transistor P12 is also turned on, the voltage at point K is switched from V ₁₁ to V ₁₁ +V ₁₂ , the voltage V ₁₀ in the read-write drive circuit 122 and the multi-state write circuit 128 _A voltage difference V ₁₀ _-V ₁₁ -V ₁₂ is formed between the voltages V ₁₁ +V ₁₂ _of the Such as writing "1"). In this way, according to the timing control logic shown in (b) of FIG. 4 , the multi-state write circuit 128 shown in (a) of FIG. 4 can write to the memory array 110 within one clock cycle of the Input of the clock signal. Two states are written.

In the above solution, the time interval between the start of writing of the first state and the start of writing of the second state (ie, the writing duration of one state) depends on the delay duration of the reverse delay chain 1281 , the delay duration of the reverse delay chain 1281 is related to the number of inverters included in the reverse delay chain 1281 . Generally speaking, the number of inverters set in the read/write controller 120 cannot be changed after the read/write controller 120 is shipped from the factory. In this case, the scheme can actually write each state with a fixed write duration. However, considering that different process deviations may require different writing durations, if some process deviations are used to write a state, it only takes 0.3ns, while some process deviations require 1ns to write a state. The multi-state write circuit 128 of this structure can also meet the requirements of different process deviations, so as to improve the ability of the read-write controller 120 to resist the influence of different process deviations, then: each inverter in the reverse delay chain 1281 can also be used. Connect a first switch component before and lead a line with a second switch component to the gate of the MOS transistor _P12 before the first switch component, by controlling the on-off of each first switch component and each second switch component. The required number of inverters are configured to be valid and other inverters to be invalid, so as to change the delay time of the reverse delay chain 1281 . Although this method needs to set more switch components and more inverters in the multi-state write circuit 128, it may make the circuit structure of the read/write controller 120 more complicated, and increase the size of the read/write controller 120. However, the delay time of the reverse delay chain 1281 can be adjusted, which is helpful for the read/write controller 120 to flexibly adjust the write time of one state when writing at least two states continuously.

Option II

FIG. 5 exemplarily shows a schematic diagram of another multi-state write scheme provided by an embodiment of the present application, wherein:

Figure (a) in FIG. 5 illustrates the circuit structure of the multi-state writing scheme. As shown in (a) in Figure 5, in this scheme, the multi-state writing circuit 128 may include an inverter (T ) and two metal oxide semiconductor (MOS) transistors of the same type, such as P-channel MOS transistor P ₂₁ and P-channel MOS transistor P ₂₂ , or N-channel MOS transistor P ₂₁ and N MOS transistor P ₂₂ of the channel. The input terminal of the inverter T and the gate of the MOS transistor P ₂₁ can be connected to the clock output terminal B ₁ respectively, the output terminal of the inverter T can be connected to the gate of the MOS transistor P ₂₂ , and the source of the MOS transistor P ₂₁ The power supply _V21 is connected, the drain of the MOS transistor _P21 is connected to the memory array 110, the source of the MOS transistor _P22 is connected to the power supply _V22 , and the drain of the MOS transistor _P22 is connected to the memory array.

Figure (b) in FIG. 5 illustrates the control sequence when at least two states are written according to this circuit structure, wherein the “Inner” line in (b) in Figure 5 illustrates the level of the clock signal Inner Changes, the “Input” line in (b) in FIG. 5 shows the level change of the clock signal Input, and the “write signal” line in (b) in FIG. 5 shows the write signal. Changes. Referring to Fig. 5 (a) and Fig. 5 (b), taking the two states of "0" and "1" written in one clock cycle (such as cycle 1) of the clock signal Input as an example, Assuming that both the MOS transistor _P11 and the MOS transistor _P12 are P-channel MOS transistors, and regardless _of the write signal delay and the pressure loss of the MOS transistor _P11 and the MOS transistor P12, if the clock generation circuit 121 is as shown in FIG. 5 In the figure (b), the "Inner" line outputs the clock signal Inner and the "Input" line outputs the clock signal Input, then in a level state of the clock signal Inner (such as a high level "1"), the read-write control The voltage corresponding to the read-write drive circuit 122 in the device 120 is in this level state (assuming V ₂₀ ): when the clock signal Input is switched to a high level, the high-level signal is directly loaded on the MOS after being transmitted through the link L21 The gate of the transistor _P21 turns on the source and drain of the MOS transistor _P21 , which is converted into a low-level signal after reverse processing by the inverter T on the link L22 and is loaded on the gate of the MOS transistor _P22 to The source and drain of the MOS transistor _P22 are turned off. In this case, the MOS transistor P21 is turned on and the MOS transistor _P22 is turned off, and the voltage _at point K is _V21 . In this case, the voltage difference between the voltage V ₂₀ in the read-write drive circuit 122 and the voltage V ₂₁ output by the multi-state write circuit 128 is V ₂₀ -V ₂₁ , so the read-write drive circuit 122 can write to the memory array. 110 writes the state corresponding to the voltage difference V ₂₀ -V ₂₁ (eg, writes "0"). When the clock signal Input is switched from a high level to a low level, the low level signal is directly loaded on the gate of the MOS transistor _P21 after being transmitted through the link L21 to turn off the source and drain of the MOS transistor _P21 , The inverter T on the circuit L22 is converted into a high-level signal after reverse processing and is loaded on the gate of the MOS transistor _P22 to turn on the source and drain of the MOS transistor _P22 . In this case, the MOS transistor _P21 It is turned off and the MOS transistor P ₂₁ is turned on, and the voltage at point K is V ₂₂ . In this case, the voltage difference between the voltage V ₂₀ in the read-write drive circuit 122 and the voltage V ₂₂ output by the multi-state write circuit 128 is V ₂₀ -V ₂₂ , so the read-write drive circuit 122 can send the memory array to the 110 writes the state corresponding to the voltage difference V ₂₀ -V ₂₂ (eg, writes "1"). After that, if the clock signal Inner switches to another level state (such as a high level "0"), the read-write drive circuit 122 controls the memory to sleep according to the level state and the level state of the multi-state write circuit 128, that is, to maintain The memory is not being written to. In this way, according to the timing control logic shown in (b) of FIG. 5 , the multi-state circuit 128 shown in (a) of FIG. 5 can write to the memory array 110 within one clock cycle of the clock signal Input two states.

In the above solution, by controlling the clock frequency of the clock signal Input to be higher than the clock frequency of the clock signal Inner, the write operation of at least two states can be realized under one level state of the clock signal Inner: for example, when the clock signal Input is One state will be written to the memory array 110 based on the voltage difference V ₂₀ -V ₂₁ when the high level is high, and another state will be written to the memory array 110 based on the voltage difference V ₂₀ -V ₂₂ when the clock signal Input is switched from high level to low level. state, so the above scheme is actually triggering the write operation of another state when the clock signal Input is level switched. In this case, the time interval from starting to write one state to starting to write another state (that is, the writing duration of one state) depends on the level switching moment of the clock signal Input (for example, the falling edge of the above example Triggering time): the later the clock signal Input triggers the level switching, the longer the writing time left for a state, the read-write driving circuit 122 will stop after a longer writing time from the start of writing a state Write this state and start writing another state; the earlier the clock signal Input triggers the level switch, the shorter the writing time left for one state, and the read and write drive circuit 122 starts to write a state after a very short period of time. Write time to stop writing to that state and start writing to another state.

Based on this, in an optional implementation manner, it is considered that the level switching moment of the clock signal Input is related to the cycle duration of one cycle of the clock signal Input (the longer the cycle duration of one cycle is, the longer the clock signal Input will be. Switch the level earlier, when the period of a cycle is shorter, the clock signal Input will switch the level later). Therefore, the read/write controller 120 can also adjust the period corresponding to the clock signal Input through the clock generation circuit 121. The time interval when the multi-state write circuit 128 writes different states is changed to improve the ability of the multi-state write circuit 128 to resist the influence of different process variations. For example, when the current process deviation is large and it takes a long time for the read-write controller 120 to write a state into the memory array 110, the read-write controller 120 can configure the frequency of the clock signal Input through the clock generation circuit 121 as Smaller value, in this way, the cycle duration of the current cycle of the clock signal Input is relatively prolonged, which means that the clock signal Input will start switching levels after a long time, so that the current state being written can correspond to more Write time, which helps to ensure that the current state being written is successfully written into the storage array 110 before starting to write another state, which effectively improves the writing accuracy when two states are continuously written. When the current process variation is so small that the read/write controller 120 can write a state into the memory array 110 in a short time, the read/write controller 120 may configure the frequency of the clock signal Input through the clock generation circuit 121 to be A larger value, in this way, the cycle duration of the current cycle of the clock signal Input is relatively short, which means that the clock signal Input will start switching levels after a short period of time, so the state currently being written corresponds to less This helps to start writing another state as soon as possible when the current state can be quickly written to the storage array 110, so as to improve the writing speed of consecutively writing two states. The current process deviation may be detected by the user in real time, or may be preset in the description parameters of the memory by those skilled in the art, which is not specifically limited.

The following describes the comparison of the write performance between the multi-state write scheme shown in FIG. 4 and the multi-state write scheme shown in FIG. 5 when dealing with different process deviations with a specific example:

FIG. 6 exemplarily shows a performance comparison diagram of a multi-state write circuit provided by an embodiment of the present application. As shown in FIG. 6 , the uppermost node line (ie, the “Input” line shown in FIG. 6 ) is the clock The level change line of the signal Input, the two lines in the middle correspond to the multi-state write circuit with an inverted delay chain (that is, the multi-state write circuit 128 shown in (a) in FIG. 4 , which is assumed to be called multi-state Write circuit 1), wherein the solid line in these two lines (ie the "1.1-write one state" line shown in Figure 6) is the control line corresponding to the multi-state write circuit 1 when writing the first state , the dotted line in these two lines (ie, the “1.2-write another state” line shown in FIG. 6 ) is the corresponding control line when the multi-state write circuit 1 writes the second state. The following two lines correspond to the multi-state write circuit that realizes multi-state writing by switching the level state (that is, the multi-state write circuit 128 shown in (a) of FIG. 5, which is assumed to be called the multi-state write circuit 2) , the solid line in these two lines (ie the "2.1-write a state" line shown in Figure 6) is the control line corresponding to the multi-state writing circuit 2 when writing the first state, these two The dotted line in the line (ie, the "2.2-write another state" line shown in FIG. 6 ) is the corresponding control line when the multi-state write circuit 2 writes the second state.

Table 1 exemplarily shows the write performance comparison table of these two multi-state write circuits:

Table 1

Referring to FIG. 6 and Table 1, in this example, the delay duration of the inverting delay chain is 2.7ns, and the process variation of the memory causes at least 14.5ns to be successfully written into the memory array for a state. in this case:

After detecting that the clock signal Input is switched to a high level, the read-write controller using the multi-state writing circuit 1 starts to write the first state to the storage array (due to the delay in signal transmission, it is detected that the clock signal Input starts to switch to a high level. The time E ₁₁ of the level is later than the time E ₁₀ ) when the clock signal Input actually starts to switch to the high level. After that, after the delay time of 2.7ns in the reverse delay chain (ie time E ₁₂ ), the read/write controller using the multi-state write circuit 1 stops writing the first state and starts writing the second state. Obviously, 2.7ns is very short compared to 14.5ns. Under the process deviation of 14.5ns, such a short time is not enough for the memory to write the first state to the storage array, and the first state has not been successfully written yet. If the second state is written ahead of time, it is very likely that the memory will be written with the wrong data or lost. Therefore, the write performance of the read/write controller using the multi-state write circuit 1 cannot meet the requirements of the process deviation of 14.5ns, resulting in a weak ability to resist the influence of the process deviation;

After detecting that the clock signal Input switches to a high level, the read-write controller using the multi-state write circuit 2 starts to write the first state to the storage array (due to the delay in signal transmission, it is detected that the clock signal Input starts to switch to a high level. The time of the level is later than the time when the clock signal Input actually starts to switch to the high level, and the time E ₂₁ when the first state is started to be written is later than the time E ₂₀ when the clock signal Input actually triggers the rising edge). After that, the read-write controller using the multi-state write circuit 2 determines that the current process deviation is 14.5ns. Therefore, the read-write controller can maintain the high level of the clock signal Input for a period of 14.5ns through the clock generation circuit, so as to The first state continues to be written in the 14.5ns duration, until after 14.5ns, the read-write controller controls the clock signal Input to switch from high level to low level through the clock generation circuit (that is, after 14.5ns, the clock signal Input is triggered The falling edge of the clock signal Input2 can also be changed by setting the corresponding cycle duration of the clock signal Input2 to 29ns to change the falling edge of the clock signal Input) to stop writing the first state and start writing the second state (due to There is a delay in signal transmission, so it is detected that the time when the clock signal Input starts to switch to a low level is later than the time when the clock signal Input actually starts to switch to a low level, and the time E ₂₃ starts to write the second state is also later than the clock The time E ₂₂ ) when the signal Input actually triggers the falling edge.

According to the above content, in the above-mentioned multi-state writing circuit 2, the timing of the falling edge of the clock signal Input is adjusted by the clock generating circuit, so that the read-write controller using the multi-state writing circuit 2 can be just at 14.5 corresponding to the process deviation. After ns, it starts to write the second state. In this way, the duration of 14.5ns is enough for the read-write controller to successfully write the first state into the memory of this process deviation. The scheme utilizes the adjustable falling edge of the clock signal, and can accurately track the process deviation of the memory by adjusting the coming moment of the falling edge. into performance.

It should be noted that the above content only introduces the specific implementation process of the multi-state write access scheme by taking "writing to another state triggered by a falling edge" as an example, and this application does not limit that writing to another state is specifically triggered by a falling edge. Still triggered by a rising edge. For the solution of writing to another state by triggering a rising edge, please refer to the above content for corresponding settings, which will not be described in detail in this application.

It should be noted that, the above content only describes the implementation process of writing at least two states by taking the multi-state writing circuit 128 including one inverter and two MOS transistors of the same type as an example. It should be understood that as long as the circuit structure of "turning on the MOS transistor P ₂₁ and the MOS transistor P ₂₂ through different levels" can be realized, it is within the protection scope of the present application. For example, in another optional implementation manner, the multi-state writing circuit 128 may also include an inverting delay chain composed of an odd number of inverters connected end to end and two MOS transistors of the same type, and the connection relationship is still as follows shown in Figure 5. In this case, since the clock signal Input is directly loaded on the MOS tube _P21 on the one hand, and on the other hand, it is converted into an opposite clock signal after reverse processing by an odd number of inverters and then loaded on the MOS tube _P22 , so The MOS transistor _P21 and the MOS transistor _P22 of the same type are turned on and turned off at the same level. In this way, in the case where the power supply connected to the source of the MOS transistor _P21 is different from the power supply connected to the source of the MOS transistor _P22 , the MOS transistor _P21 and the MOS transistor _P22 of the same type are at the level of the clock signal Input. When a change occurs, the voltage applied to the memory array can also be changed, so this method can also change the writing duration of a state by adjusting the timing at which the clock signal Input switches the level. In another optional implementation manner, the multi-state writing circuit 128 may also include two different types of MOS transistors, and does not include an inverter or includes an inversion delay chain formed by an even number of inverters connected end to end . In this case, on the one hand, the clock signal is directly loaded on a certain type of MOS transistor _P21 , and on the other hand, it is converted into the same clock signal after reverse processing by an even number of inverters and then loaded on another type of MOS transistor P21. MOS transistor P ₂₂ (or directly loaded on another type of MOS transistor P ₂₂ without inverter processing), so different types of MOS transistor P ₂₁ and MOS transistor P ₂₂ are turned on at the same level a deadline. In this way, when the power supply connected to the source of the MOS transistor _P21 and the power supply connected to the source of the MOS transistor _P22 are different, the different types of the MOS transistor _P21 and the MOS transistor _P22 are at the level of the clock signal Input. When a change occurs, the voltage applied to the memory array can also be changed, so this method can also change the writing duration of a state by adjusting the timing at which the clock signal Input switches the level. There are many optional implementation manners, which will not be repeated here.

The above content mainly introduces the specific implementation process of the read-write controller writing at least two states. In the following, based on the read/write controller 120 shown in FIG. 5 in the first embodiment (for ease of understanding, the read/write drive circuit will not be described below), the specific implementation process of the read/write controller to read data will be further introduced from the second embodiment. . It should be noted that the second embodiment is only introduced by taking the read-write controller 120 shown in FIG. 5 as an example, and each solution in the second embodiment is also applicable to any read-write controller in the above-mentioned first embodiment, such as The read/write controller 120 shown in FIG. 3 or FIG. 4 will not be described in detail in this application.

In the second embodiment, the read/write controller may further include a sense amplifier, such as the sense amplifier 126 shown in FIG. 1 , and the storage array may include a reference unit (eg R) and at least one storage unit, such as storage unit 1, storage unit 2. ......, the storage unit M×N, where M and N are both positive integers. Wherein, the storage unit 1 to the storage unit M×N may be arranged in the form of an M×N matrix. The read operation of the target memory cell can be performed in conjunction with the sense amplifier. Before the read operation starts, the read-write controller first precharges the two bit lines corresponding to the reference cell R and the target memory cell to the same high level. After the precharge is completed, the read-write controller drives the target memory cell selected by the word line circuit to charge and discharge its corresponding bit line according to the data stored therein (called a preparation stage). Because the size of the target memory cell is small and its driving capability is very weak, the electrical signal on the bit line corresponding to the target memory cell varies less with charging and discharging, resulting in two electrical signals output from the reference cell R and the target memory cell. The difference in the signal is also small. In this case, the read-write controller can also turn on the sense amplifier. The turned-on sense amplifier will calculate the differential input signal according to the electrical signals output from the two bit lines, and amplify the differential input signal into a larger output signal. This larger output signal is judged to determine whether the data stored in the memory cell is a "0" or a "1" (referred to as the decision stage). It can be seen that the turn-on moment of the sense amplifier is the watershed between the preparation stage and the decision stage. Once the sense amplifier is turned on, the sense amplifier can read the electrical signals on the two bit lines (hereinafter the two electrical signals are referred to as reference signals and store signal), and perform the subsequent decision process. The earlier the sense amplifier is turned on, the differential input signal between the target memory cell and the reference cell R may not yet be formed, resulting in less accurate data read by the sense amplifier. And the later the sense amplifier is turned on, the differential input signal between the target memory cell and the reference cell R may have already been formed, so that the operation of the sense amplifier to read out data is not timely. It can be seen that when to control the opening of the sense amplifier is particularly important for improving the read performance of the read-write controller.

For ease of understanding, the following description is given by taking the charging and discharging of the target memory cell triggered by a high level and the activation of the sense amplifier triggered by a low level as an example. It should be understood that the solution of triggering the charging and discharging of the target memory cell at a low level or the solution of triggering the activation of the sense amplifier at a high level can be implemented by reference, and will not be repeated here.

[Example 2]

FIG. 7 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application. As shown in FIG. 7 , in this example, the read-write controller 120 may further include an odd-numbered inverter head and tail The reverse delay chain 129 and the sense amplifier 126 are connected together, the input end of the reverse delay chain 129 is connected to the clock output end B ₂ , and the output end of the reverse delay chain 129 is connected to the clock control end (C ₁₁ ) of the sense amplifier 126 ), the first input terminal (C ₁₂ ) of the sense amplifier 126 is connected to the reference cell R in the memory array 110, and the second input terminal (C ₁₃ ) of the sense amplifier 126 is connected to the target memory cell (such as the memory cell MN) in the memory array 110 ), the output terminal (C ₁₄ ) of the sense amplifier 126 is connected to the reading device 200 . _In a specific implementation, when the memory is in the read mode, the clock generation circuit 121 can output the clock signal Inner through the clock output terminal B2, and when the clock signal Inner is at a high level, the high level triggers the target memory unit MN to The corresponding bit line performs the charge and discharge operation, and on the other hand, the reverse delay chain 129 is reversed to a low level and then delayed and transmitted to the sense amplifier 126 to turn on the sense amplifier 126. In this way, the sense amplifier 126 starts at the target memory cell MN. After charging and discharging, the reference signal of the reference unit R and the storage signal of the target storage unit MN are obtained after the delay time corresponding to the reverse delay chain 129, and the data stored in the target storage unit MN is calculated based on these two signals.

Using the reading scheme as shown in FIG. 7, the turn-on moment of the sense amplifier 126 actually depends on the delay time of the reverse delay chain 129, and the delay time of the reverse delay chain 129 depends on the reverse delay chain The number of inverters included in 129. In general, after the read/write controller 120 leaves the factory, the number of inverters in the reverse delay chain 129 is fixed, so this solution can actually only enter the judgment stage after a fixed-length preparation stage. If the turn-on time of the sense amplifier 126 is to be adjusted, a third switch assembly can also be connected before each inverter in the reverse delay chain 129, and a fourth switch with a strip can be connected before the third switch assembly. The circuit of the component is connected to the clock control terminal C ₁₁ of the sense amplifier 126, and the required number of inverters are configured to be valid by controlling the on-off of each third switch component and each fourth switch component, and other inverters are invalid, so as to change the inverter. Delay time to delay chain 129. Although this method requires more switch components and more inverters, the delay time of the reverse delay chain 129 can be adjusted, which is helpful for the read/write controller 120 to flexibly adjust the sensitivity of the sense amplifier 126. Open time.

FIG. 8 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application. As shown in FIG. 8 , in this example, the read-write controller 120 may further include a sense amplifier 126 . The clock control terminal (C ₂₁ ) and the first input terminal (C ₂₂ ) are respectively connected to the reference unit R in the storage array 110, and the second input terminal (C ₂₃ ) of the sense amplifier 126 is connected to the target storage unit in the storage array 110 (eg memory unit MN), the output terminal (C ₂₄ ) of the sense amplifier 126 is connected to the reading device 200 . In a specific implementation, a potential difference threshold is preset locally in the reference unit R. When the memory is in the read mode, the clock generation circuit 121 can output the clock signal Inner through the clock output terminal _B2 . When the clock signal Inner is at a high level, the high level The level-triggered target memory cell MN performs a charge-discharge operation on the corresponding bit line. During the charging and discharging process, the reference cell R can also detect the electrical signal on the bit line corresponding to the target memory cell MN, and determine the electrical signal on the bit line corresponding to the target memory cell MN and the bit line corresponding to the reference cell R When the potential difference between the electrical signals on the above reaches a locally preset potential difference threshold, the reference unit R may send a sense amplifier enable (sense amplifier enable, SAE) signal to the clock control terminal of the sense amplifier 126 to turn on the sense amplifier 126 . In this way, the sense amplifier 126 can start to acquire the reference signal of the reference cell R and the storage signal of the target memory cell MN when the electrical signal on the bit line corresponding to the target memory cell MN reaches a certain change, and calculates the target based on these two signals. The data stored in the storage unit MN. The SAE signal may be an electrical signal with an enabling function, such as a voltage signal or a current signal. The locally preset potential difference threshold stored in the reference unit R may be set by those skilled in the art according to experience, or may be determined by experiments, which is not specifically limited.

Using the reading scheme as shown in FIG. 8 , the turn-on moment of the sense amplifier 126 is actually determined by the locally preset potential difference threshold stored in the reference cell R, and the reference cell R will charge and discharge the target memory cell to the voltage on the bit line. The SAE signal is sent when the electrical signal and the electrical signal on the bit line of the reference unit R reach a locally preset potential difference threshold. However, the locally preset potential difference threshold actually belongs to a preset value, which basically cannot be changed after the memory is shipped from the factory, which leads to poor adjustability of the turn-on moment of the sense amplifier 126 . Under different process deviation scenarios, the sense amplifier 126 may need to correspond to different turn-on times. For example, in a scenario where the process deviation is small, although the target memory cell has not been charged and discharged until the potential difference reaches the locally preset potential difference threshold, the potential difference between the two bit lines of the target memory cell and the reference cell R is sufficient for execution Judgment, in this case, even if it does not continue to charge and discharge but directly enters the judgment stage, more accurate data can be read out. Obviously, the solution of using the reference unit R to control the opening of the sense amplifier 126 cannot be applied to this working scenario.

FIG. 9 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application. As shown in FIG. 9 , in this example, the read-write controller 120 may further include a sense amplifier 126 . The clock control terminal (C ₃₁ ) is connected to the clock output terminal B ₁ , the first input terminal (C ₃₂ ) of the sense amplifier 126 is connected to the reference unit R in the memory array 110 , and the second input terminal (C ₃₃ ) of the sense amplifier 126 is connected to the storage For a target memory cell (eg, memory cell MN) in the array 110 , the output terminal (C ₃₄ ) of the sense amplifier 126 is connected to the reading device 200 . In _a specific implementation, when the memory is in the read mode, the clock generation circuit 121 can output the clock signal Input to the sense amplifier 126 through the clock output terminal _B1 , and output the clock signal Inner through the clock output terminal B2. When the clock signal Inner is at a high level, the high level signal can trigger the target memory cell MN to perform a charge-discharge operation on the corresponding bit line. The read/write controller 120 can also turn on the sense amplifier 126 at any time as needed. For example, when the sense amplifier 126 needs to be turned on, the clock signal Input is switched to a low level through the clock generation circuit 121. In this way, the low level signal can be directly applied to the On the clock control terminal of the sense amplifier 126 (triggering the SAE signal) to turn on the sense amplifier 126, the sense amplifier 126 calculates and obtains the data stored in the target memory unit MN based on the acquired reference signal and the stored signal.

Using the reading scheme as shown in FIG. 9 , by using an independent clock signal to provide the operating clock for the sense amplifier 126, the turn-on time of the sense amplifier 126 can be flexibly adjusted by adjusting the level switching time of the independent clock signal, which not only can The read-write controller 120 is adapted to different reading scenarios without additional components such as inverters, thereby helping to reduce the cost of the read-write controller 120 and the complexity of the circuit structure. Further, considering that the read operation and the write operation of the read/write controller 120 are generally not performed at the same time, the solution sets the same operating clock for the sense amplifier 126 and the multi-state write circuit 128, without distributing the operating clock separately. , this method can further reduce the complexity of the circuit structure and reduce the circuit cost while independently controlling the read and write operations.

In an optional implementation manner, considering that the solution of using the clock signal Input to turn on the sense amplifier 126 in advance has a faster reading speed, and the solution of using the reference unit R to turn on the sense amplifier 126 has better reading accuracy, Therefore, in order to take into account both the reading speed and the reading accuracy, the read-write controller 120 may also combine the reference unit R and the clock signal Input to comprehensively turn on the sense amplifier 126 . In this case, the clock control terminal C ₃₁ of the sense amplifier 126 can also be connected to the clock output terminal B ₁ and the reference unit R through a switch, and the control terminal of the switch is connected to the read-write drive circuit 122 . In scenarios where the current circuit environment has good process deviation consistency, or does not require high reading accuracy, or requires high reading speed, the read-write driving circuit 122 can control the switch to connect to the clock control of the sense amplifier 126 The clock control terminal C ₃₁ of the sense amplifier 126 and the reference unit R are disconnected from the terminal C ₃₁ and the clock output terminal B ₁ . In this way, even if the target memory cell has not been charged or discharged to the locally preset potential difference threshold stored in the reference cell R, as long as the potential difference between the two bit lines of the target memory cell and the reference cell R is sufficient to execute the decision, the sense amplifier 126 can be turned on in advance under the control of the clock signal Input to execute the decision in advance, which helps the read/write controller 120 to read data as soon as possible. In the scenario where the current circuit environment has a large process deviation, or requires high reading accuracy, or does not require high reading speed, the read-write driving circuit 122 can control the switch to connect to the clock control terminal C of the sense amplifier 126. ₃₁ and the reference unit R, disconnect the clock control terminal C ₃₁ and the clock output terminal B ₁ of the sense amplifier 126 . In this way, when the target storage unit is charged and discharged, the reference unit R can acquire the electrical signal on the bit line corresponding to the target storage unit in real time, and calculate the potential difference between the electrical signal and the electrical signal on the bit line corresponding to the reference unit R, When the potential difference of the electrical signals on the two bit lines is greater than the locally preset potential difference threshold stored in the reference unit R, the reference unit R can turn on the sense amplifier 126, so that the sense amplifier 126 can be between the target memory unit and the reference unit R. The judgment is started only when the potential difference between them is large enough, which helps to improve the reading accuracy of the read/write controller 120 .

The following describes a comparison of the reading performance between the reading scheme shown in FIG. 7 and the reading scheme shown in FIG. 9 with a specific example. Wherein, this example is performed at an ambient temperature of 25°C (°C is a unit of temperature, ie, Celsius) and a TT process angle.

FIG. 10 exemplarily shows a comparison diagram of a reading scheme provided by an embodiment of the present application. As shown in FIG. 10 , the three lines above correspond to the reading method of using the reference unit to turn on the sense amplifier shown in FIG. 7 (called It is the reading mode 1), wherein the node line in these three lines (that is, the “Innner” line shown in FIG. 10 ) is the level change line of the clock signal Inner corresponding to the reading mode 1. Among these three lines, The solid line (that is, the "SAE1" line shown in Figure 10) is the change line of the SAE signal received by the sense amplifier in the reading mode 1, and the dotted line among these three lines (that is, the "Q1" line shown in Figure 10) It is the change line of the read data signal of the sense amplifier in read mode 1. The following three lines correspond to the reading method (called reading method 2) of turning on the sense amplifier by switching the level state shown in FIG. ” line) is the level change line of the clock signal Input corresponding to reading mode 2, the solid line in these three lines (that is, the “SAE2” line shown in Figure 10) is the reading mode 2 The sense amplifier receives The SAE signal change line, the dotted line among these three lines (ie, the “Q2” line shown in FIG. 10 ) is the readout data signal change line of the sense amplifier in read mode 2.

Table 2 exemplarily shows the reading performance comparison table of the above two reading schemes:

Table 2

Referring to Figure 10 and Table 2, in this example, the target memory cell needs at least 92.34ns to complete charging and discharging. in this case:

When using the reference cell to turn _on the sense amplifier, the target memory cell detects that the clock signal Inner is switched to a high level at time _Y11 as shown in FIG. The corresponding bit lines are charged and discharged, and the charging and discharging are completed after 92.34 ns. The reference unit detects the charge and discharge at the time Y ₁₂ as shown in FIG. 10 to meet the potential difference threshold preset locally by the reference unit, so that the reference unit can trigger the SAE signal of the sense amplifier at the time Y ₁₂ as shown in FIG. 10 . Turn on the sense amplifier. So far, the preparation stage is over, and the sense amplifier enters the decision stage. In this case, due to the late turn-on time of the sense amplifier, the potential difference of the electrical signals output on the two bit lines is large, and the sense amplifier only needs a relatively short time (such as 1.66ns) to complete the decision. Therefore, The sense amplifier can read out data at time Y ₁₃ as illustrated in FIG. 10 . Based on this, the read method using the reference cell to turn on the sense amplifier takes a total of 94ns to read out data.

When the sense amplifier is turned on by switching the level state, the target memory unit detects that the clock signal Inner is switched to a high level at time Y ₂₁ as shown in FIG. 10 , so the target memory unit is at time Y ₂₁ as shown in FIG. 10 . The corresponding bit line starts charging and discharging, and ends charging and discharging after 92.34 ns. When the read-write controller determines the process deviation of the current circuit environment so that a potential difference can be formed at a time interval of 39.9ns for charging and discharging, the read-write controller can switch the clock signal Input to a low power level through the clock generation circuit at the moment Y ₂₂ as shown in Figure 10. level to trigger the sense amp to turn on in advance. So far, the preparation stage is over, and the sense amplifier enters the decision stage. In this case, since the sense amplifier is turned on in advance, the potential difference of the electrical signals output on the two bit lines is small, so the sense amplifier may take a longer time (such as 9.1ns) to judge the reading. Therefore, the sense amplifier Data can be read out at time Y ₃₃ as illustrated in FIG. 10 . Based on this, the reading method of turning on the sense amplifier by switching the level state only needs 49ns to read data.

According to the above content, the reading method of turning on the sense amplifier by switching the level state can turn on the sense amplifier in advance. Although this method makes the decision time of the sense amplifier longer, the whole readout time is longer than that of the reference unit turning on the sense amplifier. The reading method is optimized by 47.8%, which is 56.8% better than the reading method in which the sense amplifier is turned on in the reference unit in the preparation stage. As for how long to turn on the sense amplifier in advance, it can be set by those skilled in the art based on experience, or it can be calculated according to experiments. The duration of the phase can reduce the probability of reading errors caused by rapid reading in some extreme cases.

Below in conjunction with the read-write controller shown in FIG. 9, the specific implementation process of the read-write scheme in the present application is introduced with a specific timing control flow:

FIG. 11 exemplarily shows a read-write control sequence diagram provided by an embodiment of the present application. As shown in FIG. 11 , the read-write control sequence involves the following control signals: input clock signal Input, input clock signal Inner, write enable An enable signal WEN, a read enable signal REN, an input/output signal DATA, a word line signal WL, a sense amplifier enable signal SAE, and a readout data signal Q. Among them, the input and output signal DATA refers to the signal received by the read-write controller from the external device, such as the write request signal sent by the external device to the read-write controller and the read request sent by the external device to the read-write controller. signal etc. The write enable signal WEN and the read enable signal REN are used to enable the write mode and read mode of the read-write controller respectively. Switch to the write mode, when the read enable signal REN is triggered (eg low level trigger), the read-write controller switches to the read mode accordingly. The read data signal Q refers to the signal that the read-write controller sends the read data to the external device. The word line signal WL is implemented in the entire read-write logic of the read-write controller, not only can the row of memory cells be opened according to the row of the target memory cell decoded by the row decoding circuit, so that the read-write drive circuit can open the row in the row. In the storage unit, read and write operations are performed on the target storage unit according to the column of the target storage unit decoded by the column decoding circuit, and the data to be written can also be written into the target storage unit when the write operation is performed, and when the read operation is performed. During the out operation, the charging and discharging of the target storage unit is triggered according to the data stored in the target storage unit. The sense amplifier enable signal SAE is used to turn on the sense amplifier. When the sense amplifier enable signal SAE is triggered (eg, triggered at a high level), the sense amplifier acquires the electrical signals output from the two bit lines and starts the decision. Among these control signals, the write enable signal WEN, the read state of the word line signal WL, the read enable signal REN, the input and output signals DATA and the read data signal Q can be triggered by the input clock signal Inner, while the word line signal WL The write status and sense amplifier enable signal SAE can be triggered by the input clock signal Input.

In a specific implementation of the write operation, the input clock signal Input, the input clock signal Inner, the write enable signal WEN, the input and output signal DATA and the word line signal WL can be combined to complete the write operation. Specifically, as shown in Figure 11, when the external device needs to continuously write two data into the memory, the external device can send a write request to the read-write controller at the time h1, and the write request belongs to an input Output signal DATA. The write request triggers the write enable signal WEN at time h2 (if the signal transmission delay is not considered, the time h2 is the time h1; if the signal transmission delay is considered, the time h2 is later than the time h1) The write controller switches to write mode. When in the write mode, in a level state of the clock signal Inner (as shown in Figure 11, it is in a high level state from time x1 to time x2), the read-write drive circuit has a fixed level, and the word line has a fixed level. The circuit triggers the word line signal WL to be at different levels according to the level change of the input clock signal Input. For example, when the input clock signal Input switches to a high level at the h3 time, the word line circuit will be based on the high level at the h4 time ( If the signal transmission delay is not considered, then the h4 time is the h3 time. If the signal transmission delay is considered, the h4 time is later than the h3 time) to trigger the word line signal WL to be at a high level. The voltage difference between the level of the driving circuit and the high level of the word line signal WL gradually writes the first state (eg "0") into the memory array until the input clock signal Input switches to a low level. When the input clock signal Input switches to a low level at the time h5, the word line circuit will be at the time h6 based on the low level (if the signal transmission delay is not considered, the time h6 is the time h5, if the signal transmission delay is considered, Then the time h6 is later than the time h5) to trigger the word line signal WL to be at a low level. In this way, the read-write drive circuit ends the writing process according to the voltage difference between the level of the read-write drive circuit and the low level of the word line signal WL. one state and initiates writing to the second state (eg "1"). During the writing process, the read-write controller can also adjust the time h5 within the time period t1 through the clock generation circuit to change the arrival time of the time h6. For example, when the process bias is large, the memory needs a longer time to write the first time In this state, the read-write controller can adjust the time h5 to a later time value in the time period t1 through the clock generation circuit, so that the time h6 can also come later, so that the word line signal WL can be switched Switching to low a long time after going high gives the memory more time to write the first state. For another example, when the process bias is small and the memory can be written to the first state in a very short time, the read-write controller can adjust the time h5 to an earlier time value in the time period t1 through the clock generation circuit. In this way, the time h6 can also come earlier, so that the word line signal WL can be switched to the low level within a short time after switching to the high level, and the memory can quickly start writing the second state. After that, when the writing of the second state is completed, the word line signal WL can be restored to the sleep level at the moment h7, thereby ending the writing operation. Correspondingly, the write enable signal WEN switches to a low level state at time h8, so that the read-write controller exits the write mode. At this point, the read-write controller completes the write operation.

In the specific implementation of the read operation, the input clock signal Input, the input clock signal Inner, the read enable signal REN, the input and output signal DATA, the word line signal WL, the sense amplifier enable signal SAE and the read data signal Q can be passed through Combined action to synthesize the read operation. Specifically, as shown in FIG. 11 , when the external device needs to read the data in the memory, the external device can send a read request to the read-write controller at time m1, and the read request belongs to an input and output signal DATA . The read request triggers the read enable signal REN at time m2 (if the signal transmission delay is not considered, the time m2 is the time m1; if the signal transmission delay is considered, the time m2 is later than the time m1) The write controller switches to read mode. When in the readout mode, the read-write controller starts the discharge operation according to the level change of the input clock signal Inner. For example, when the input clock signal Inner switches to a high level at the time of y1, the word line circuit will start the discharge operation based on the high level. Time m4 (if the signal transmission delay is not considered, the time m4 is the time y1; if the signal transmission delay is considered, the time m4 is later than the time y1) to trigger the word line signal WL to switch to a low level (the low level can be It is the same as the low level in the write state, or it can be different, not limited), so that the bit line corresponding to the target memory cell is charged and discharged, until the input clock signal Inner switches to the low level at the moment of y2 to trigger the word line The signal WL switches to the sleep level, or until the charging and discharging of the target memory cell is completed. During the charging and discharging process, since the input clock signal Input is at a high level between the time m3 and the time m5, the sense amplifier is not triggered to be turned on. Until the input clock signal Input switches to a low level at the m5 time, the low level will be at the m6 time (if the signal transmission delay is not considered, the m6 time is the m5 time, and if the signal transmission delay is considered, the m6 time is late. At time m5) trigger the sense amplifier enable signal SAE to switch to high level to turn on the sense amplifier, at this time the sense amplifier reads the electrical signal output on the bit line corresponding to the target memory cell and the output on the bit line corresponding to the reference cell The data stored in the target storage unit is determined according to the two electrical signals. During the discharge process, the read-write controller can also adjust the time m5 within the time period t2 through the clock generation circuit to change the arrival time of the time m6. For example, when it is determined that the current circuit environment is good and the currently used opening time is late, The read-write controller can trigger the falling edge of the input clock signal Input in advance through the clock generation circuit, that is, the time m5 can be controlled in advance. In this way, the time m6 can also come in advance, so that the sense amplifier can be turned on earlier and enter the judgment stage earlier. , to shorten the readout time. After that, after the judgment is completed, the read-write controller can send the read data to the external device at time m7 through the read data signal Q. So far, the read-write controller completes the read operation.

According to the above content, by setting a separate working clock for the multi-state writing circuit and the sense amplifier, the read-write controller can switch the level of the separate working clock to advance or delay to write another state or read out the judgment, In this way, the writing duration and the reading duration of the read-write controller can have a wide adjustable range. Even under the influence of severe process deviation, the read-write controller can adjust the write duration and read duration to meet the requirements of the process deviation under the support of the wide adjustable range, and try to take into account the read and write as much as possible. Accuracy and read-write efficiency, effectively improve the read-write performance of the read-write controller.

In the following, based on the read/write controller 120 shown in FIG. 9 in the second embodiment, the possible structure of the clock generation circuit 121 is further introduced from the third embodiment. It should be noted that the third embodiment is only introduced by taking the read/write controller 120 shown in FIG. 9 as an example, and each solution in the third embodiment is also applicable to any read/write in the above-mentioned first or second embodiment. The controller, such as the read/write controller 120 shown in FIG. 3 , FIG. 4 , FIG. 7 or FIG. 7 , will not be described in detail in this application.

[Example 3]

In this embodiment of the present application, the clock generation circuit 121 capable of generating the clock signal Input and the clock signal Inner may have various possibilities. Three possible implementations are exemplified below:

Embodiment 1

FIG. 12 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application. As shown in FIG. 12 , in this example, the clock generation circuit 121 may further include a first clock generator 1211 and a frequency divider The output terminal of the first clock generator 1211 is connected to the clock output terminal B ₁ and the input terminal of the frequency divider 1212 respectively, and the output terminal of the frequency divider 1212 is connected to the clock output terminal B ₂ . In this case, the first clock generator 1211 can generate the clock signal Input and provide it to the clock output terminal B1 and the frequency divider 1212, respectively. In this way, the clock signal Input can be output to multiple clock outputs through the clock output terminal B1 _on the _one hand. The state writing circuit 128 and the sense amplifier 126, on the other hand, can also be divided into a lower frequency clock signal Inner via the frequency divider 1212 and then provided to the clock output terminal B ₂ , so that the lower frequency clock signal Inner can be divided by the clock output terminal B ₂ . The clock signal Inner is output to one or more other circuits in addition to the multi-state write circuit 128 and the sense amplifier 126 . According to the clock generating circuit 121 shown in FIG. 12 , the read-write driving circuit 122 can send the first indication information to the first clock generator 1211 when the level of the clock signal Input needs to be switched in advance. In this way, the first clock generator 1211 After receiving the first indication information, the level can be switched in advance according to the instruction of the first indication information. Wherein, the first indication information may further indicate how far in advance to switch. Alternatively, the read-write driving circuit 122 can send the second indication information to the first clock generator 1211 when the level of the clock signal Input needs to be delayed and switched. In this way, after receiving the second indication information, the first clock generator 1211 can The switching level is delayed according to the instruction of the second instruction information. Wherein, the second indication information may further indicate how long to delay the handover.

In this embodiment of the present application, the frequency divider 1212 may be any device capable of realizing a frequency reduction function, such as a D flip-flop as shown in FIG. 12 . In this case, assuming that it takes 20ns to write a state under a certain process deviation, and the delay of one inverter is 100-200ps, the multi-state writing is realized through the inverting delay chain 1281 as shown in Figure 4. The solution, to achieve a delay of 20ns requires at least 100-200 inverters. According to the scheme of switching the level state to realize multi-state writing shown in Figure 12, when the frequency divider is a D flip-flop, only 4-7 inverters and 2-4 transmission gates need to be set inside the D flip-flop. Frequency division operation can be realized. Obviously, the read/write controller shown in FIG. 12 can have fewer circuit components, which helps to save the space occupied by the read/write controller.

Exemplarily, the frequency divider 1212 can also divide the clock signal Input into a plurality of clock signals with different frequencies, and provide them to other circuits except the multi-state writing circuit 128 and the sense amplifier 126 respectively. In this way, other circuits can also correspond to different operating clocks respectively, which helps to independently adjust other operations in the memory and further improves the flexibility of the read-write controller.

Embodiment 2

FIG. 13 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application. As shown in FIG. 13 , in this example, the clock generation circuit 121 may further include a second clock generator 1213 and a frequency multiplier The output terminal of the second clock generator 1213 is connected to the clock output terminal B ₂ and the input terminal of the frequency multiplier 1214 respectively, and the output terminal of the frequency multiplier 1214 is connected to the clock output terminal B ₁ . In this case, the _second clock generator 1213 can generate the clock signal Inner and provide it to the clock output terminal B ₂ and the frequency multiplier 1214, respectively. One or more other circuits other than the writing circuit 128 and the sense amplifier 126, on the other hand, can be multiplied by the frequency multiplier 1214 to a higher frequency clock signal Input and then provided to the clock output terminal B ₁ , so as to pass the clock output terminal B ₁ outputs the higher frequency clock signal Input to the multi-state write circuit 128 and the sense amplifier 126. Wherein, the frequency multiplier 1214 can be any device capable of realizing the frequency up-conversion function, such as a phase-locked loop. According to the clock generation circuit 121 shown in FIG. 13 , when the read-write driving circuit 122 needs to switch the level of the clock signal Input in advance, it can send the third instruction information to the frequency multiplier 1214 . In this way, the frequency multiplier 1214 receives the After the third indication information, the level can be switched in advance according to the instruction of the third indication information. Wherein, the third indication information may further indicate how far in advance to switch. Alternatively, the read-write driving circuit 122 can send the fourth indication information to the frequency multiplier 1214 when the level of the clock signal Input needs to be delayed and switched. In this way, the frequency multiplier 1214 can follow the fourth indication after receiving the fourth indication information. Information indicating the delay switching level. Wherein, the fourth indication information may further indicate how long to delay the handover.

Exemplarily, the frequency multiplier 1214 may further divide the clock signal Inner into two clock signals with different frequencies, and provide them to the multi-state writing circuit 128 and the sense amplifier 126 respectively. In this way, the multi-state write circuit 128 and the sense amplifier 126 can also correspond to different operating clocks respectively, which helps to individually adjust the read and write operations in the memory and further improves the flexibility of the read and write controller 120 .

Embodiment 3

FIG. 14 exemplarily shows a schematic structural diagram of another read-write controller provided by an embodiment of the present application. As shown in FIG. 14 , in this example, the clock generation circuit 121 may further include a third clock generator 1215 and a fourth clock generator 1215 . In the clock generator 1216, the output terminal of the third clock generator 1215 is connected to the clock output terminal B ₁ , and the output terminal of the fourth clock generator 1216 is connected to the clock output terminal B ₂ . In this case, the third clock generator 1215 may generate and provide the clock signal Input to the clock output terminal B ₁ to output the clock signal Input to the multi-state write circuit 128 and the sense amplifier 126 through the clock output terminal B ₁ . Fourth clock generator 1216 may generate and provide clock signal Inner to clock output B ₂ to output clock signal Inner to one or more other than multi-state write circuit 128 and sense amplifier 126 through clock output B ₂ . circuit. According to the clock generating circuit 121 shown in FIG. 14 , when the read-write driving circuit 122 needs to switch the level of the clock signal Input in advance, it can send the fifth instruction information to the third clock generator 1215 . In this way, the third clock generator 1215 After receiving the fifth indication information, the level can be switched in advance according to the instruction of the fifth indication information. Wherein, the fifth indication information may further indicate how far in advance to switch. Alternatively, the read-write driving circuit 122 can send the sixth indication information to the third clock generator 1215 when the level of the clock signal Input needs to be delayed and switched. In this way, after receiving the sixth indication information, the third clock generator 1215 can The switching level is delayed according to the instruction of the sixth instruction information. Wherein, the sixth indication information may further indicate how long to delay the handover.

It should be noted that the above-mentioned Embodiment 3 merely exemplarily introduces three possible structures of the clock generating circuit. It should be understood that the present application does not limit the clock generation circuit to only have these structures. As long as the clock generation circuit capable of generating two clock signals with different frequencies is within the scope of protection of the present application, the present application will not address them one by one. Repeat.

It should be understood that the above-mentioned embodiments of the present application may also be combined with each other to obtain new embodiments, which will not be introduced one by one in this application.

It should be understood that each component in the above embodiments of the present application refers to functional devices, and the present application does not limit the specific implementation of these functional components. For example, the MOS transistors described above can also be replaced with other devices, such as transistors, which can be switched on and off through level switching.

Based on the above embodiments, embodiments of the present application further provide a memory, including any of the above-mentioned read-write controllers and a storage array. The read-write controller can be connected to the storage array, and is used for reading and writing data in the storage array according to the solutions introduced in the above embodiments.

Based on the above embodiments, the embodiments of the present application further provide an electronic device, the electronic device includes the above-mentioned memory and a PCB, and the memory is provided on the surface of the PCB.

Illustratively, the electronic device includes, but is not limited to, a smartphone, a smart watch, a tablet, a VR device, an AR device, an in-vehicle device, a desktop computer, a personal computer, a handheld computer, or a personal digital assistant.

In the above-mentioned embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented in software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer may be a general purpose computer, special purpose computer, computer network, or other programmable device. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server, or data center Transmission to another website site, computer, server, or data center by wire (eg, coaxial cable, optical fiber, digital subscriber line, DSL) or wireless (eg, infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes an integration of one or more available media. The available media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, high-density digital video discs (DVDs)), or semiconductor media (eg, solid state discs, SSD)) etc.

The terms "component", "module", "system" and the like are used in this specification to refer to a computer-related entity, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device may be components. One or more components may reside within a process and/or thread of execution, and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. A component may, for example, be based on a signal having one or more data packets (eg, data from two components interacting with another component between a local system, a distributed system, and/or a network, such as the Internet interacting with other systems via signals) Communicate through local and/or remote processes.

Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware accomplish. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above may refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution, and the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program codes .

Although a few possible embodiments have been described in this application, additional changes and modifications to these embodiments may occur to those skilled in the art once the basic inventive concepts are known. Therefore, the appended claims are intended to be construed to include the embodiments of the present application and all changes and modifications that fall within the scope of the present application.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the protection scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

A read-write controller is characterized in that it includes a clock generation circuit, a multi-state write circuit, a row decoding circuit and a column decoding circuit; the clock generation circuit includes a first clock output terminal and a second clock output terminal, wherein the the clock frequency of the first clock signal output by the first clock output terminal is higher than the clock frequency of the second clock signal output by the second clock output terminal;

The first clock output terminal is connected to the input terminal of the multi-state write circuit, and the output terminal of the multi-state write circuit is connected to the storage array; the multi-state write circuit is used to perform one clock cycle according to the first clock signal internally writing at least two states to the storage array;

The second clock output terminal is respectively connected to the input terminal of the row decoding circuit and the input terminal of the column decoding circuit, and the output terminal of the row decoding circuit and the output terminal of the column decoding circuit are respectively connected the memory array; the second clock signal is used to provide a working clock for the row decoding circuit and the column decoding circuit.
The read-write controller according to claim 1, wherein the read-write controller further comprises a sense amplifier, the clock control end of the sense amplifier is connected to the first clock output end, and the first clock output end of the sense amplifier is connected. An input terminal is connected to a reference unit in the storage array, a second input terminal of the sense amplifier is connected to at least one storage unit in the storage array, and an output terminal of the sense amplifier is connected to a reading device.
The read-write controller of claim 2, wherein when the memory array is in a readout mode, within one cycle of the first clock signal:

If the first clock signal is switched from the second level to the first level, the sense amplifier acquires the reference signal in the reference unit and the storage signal in the at least one storage unit.
The read-write controller according to any one of claims 1 to 3, wherein the clock generating circuit further comprises a first clock generator and a frequency divider; the output ends of the first clock generator are respectively The first clock output end is connected to the input end of the frequency divider, and the output end of the frequency divider is connected to the second clock output end.
The read-write controller according to any one of claims 1 to 3, wherein the clock generating circuit further comprises a second clock generator and a frequency multiplier; the output ends of the second clock generator are respectively The second clock output end is connected to the input end of the frequency multiplier, and the output end of the frequency multiplier is connected to the first clock output end.
The read/write controller according to any one of claims 1 to 3, wherein the clock generation circuit further comprises a third clock generator and a fourth clock generator, and the output of the third clock generator The terminal is connected to the first clock output terminal, and the output terminal of the fourth clock generator is connected to the second clock output terminal.
The read-write controller according to any one of claims 1 to 6, wherein the multi-state write circuit comprises an inverter, a first metal-oxide-semiconductor type MOS transistor and a second MOS transistor, The input terminal of the inverter and the gate of the second MOS transistor are respectively connected to the input terminal of the multi-state writing circuit, and the output terminal of the inverter is connected to the gate of the first MOS transistor. The source of the first MOS transistor is connected to the first power supply, the source of the second MOS transistor is connected to the second power supply, and the drain of the first MOS transistor and the drain of the second MOS transistor are connected to the storage array.
The read-write controller of claim 7, wherein when the storage array is in a write mode, within one cycle of the first clock signal:

When the first clock signal is switched from a first level to a second level, the multi-state write circuit writes a first state to the memory array;

The multi-state write circuit writes a second state to the memory array when the first clock signal switches from the second level to the first level.
A memory, characterized by comprising a storage array and the read-write controller according to any one of claims 1 to 8, wherein the read-write controller is connected to the storage array;

the storage array for storing data;

The read-write controller is used for writing data into the storage array, or reading data from the storage array.
An electronic device is characterized by comprising a printed circuit board (PCB) and the memory according to claim 9, wherein the memory is provided on the surface of the PCB.