WO2022121996A1

WO2022121996A1 - Method and apparatus for implementing network time synchronization

Info

Publication number: WO2022121996A1
Application number: PCT/CN2021/136912
Authority: WO
Inventors: 栾冬梅; 成伟; 王力
Original assignee: 苏州盛科通信股份有限公司
Priority date: 2020-12-11
Filing date: 2021-12-09
Publication date: 2022-06-16
Also published as: CN112615694B; CN112615694A

Abstract

Disclosed in embodiments of the present invention are a method and apparatus for implementing network time synchronization. The method comprises: a PHY chip records an entry timestamp at which the PHY chip receives a PTP time packet sent by a switch chip and an exit timestamp at which the PHY chip sends the PTP time packet, and sends the entry timestamp and the exit timestamp to a data processing unit; the data processing unit calculates a two-way time difference according to the entry timestamp and the exit timestamp, sends the two-way time difference to the switch chip, and sets a delay value of the switch chip according to the two-way time difference; and the switch chip updates, according to the delay value, a time at which the switch chip sends the PTP time packet. The embodiments of the present invention implement the high-precision network time synchronization of a PHY chip, reduce the overall cost and power consumption of a system, and improve the stability of the system.

Description

A method and device for realizing network time synchronization

The present invention claims the priority of the Chinese patent application with the application number of 202011459234.4 and the title of the invention "A method and device for realizing network time synchronization", which was submitted to the Chinese Patent Office on December 11, 2020, the entire contents of which are incorporated herein by reference. invention.

technical field

The present invention relates to the technical field of network communication, and in particular, to a method and device for realizing network time synchronization.

Background technique

In communication networks, the normal operation of many services requires network time synchronization, that is, the time or frequency difference between devices in the entire network is kept within a reasonable error level. Especially in the 5G era, the requirements for time synchronization are getting higher and higher. .

At present, there are various protocols that can realize network time synchronization. For example, PTP (Precision Time Protocol, Precision Time Protocol) is a network precision time synchronization protocol, which can realize phase synchronization and clock synchronization. In the fields of industry, power, data center, and metro data backhaul, high-precision time synchronization is required.

The existing solutions for realizing network time synchronization through the PTP protocol generally include the following two technical solutions:

Technical solution 1: The PHY (physical transceiver) is used as a transparent transmission link, and the entire link delay is calculated through a switching chip that supports the PTP function, and the delay is recorded in the Latency (delay) field of the switching chip. Time correction synchronization. However, the disadvantage of scheme 1 is that the synchronization technology of 1588V2 clock (1588V2 clock is a high-precision clock using the IEEE 1588V2 protocol) needs to be established on the assumption that the transmission and reception link between the Master (master) and the Slave (slave). On the basis of delay symmetry, if it is asymmetrical, there will be compensation errors; in fact, the data path from the internal RX (receiving end) to TX (transmitting end) of the PHY and the data path from TX to RX cannot guarantee the symmetry of the delay, and the data signal encoding and decoding processing and The congestion situation of the bidirectional link is different, so the compensation error calculated in this way is relatively large.

Technical solution 2: On the network switching system, the Ethernet switching chip and the PHY support the 1588 protocol at the same time, and provide the PTP function. Both the Switch (switch) and the PHY need to identify the PTP message, and need to maintain their own time. The time stamp is captured when the message leaves the PHY, and the CPU (central processing unit) is informed. The CPU uses the PTP function to calculate the difference between itself and the master clock. Offset (offset), and then synchronize the offset to the switch chip and PHY. However, the disadvantage of scheme 2 is that many time-related modules need to be integrated on the PHY device, such as independent time maintenance mechanism, offset adjustment mechanism, PTP event message mechanism, timestamp generation and reporting mechanism, etc. In other words, the area and power consumption increase; secondly, in the entire time synchronization scheme, the CPU and PHY interact frequently, and the logic is complex, which brings hidden dangers to the stability of the entire system.

Therefore, it is necessary to provide a new technical solution for realizing network time synchronization on this basis, so as to solve the problems of the above solution, such as high requirements for PHY, complex system, hidden dangers in system stability, and the like.

SUMMARY OF THE INVENTION

The purpose of the embodiments of the present invention is to overcome the defects of the prior art and provide a method and apparatus for realizing network time synchronization, so as to realize high-precision network time synchronization of Ethernet PHY chips and reduce the overall cost and power consumption of the system.

In order to achieve the above object, the embodiment of the present invention proposes the following technical solution: a method for realizing network time synchronization, the method includes:

S1, the PHY chip receives the PTP time packet sent by the switching chip, records the incoming timestamp of the PTP time packet received by the receiving end and the outgoing timestamp of the PTP time packet sent by the transmitting end, and records the incoming timestamp of the PTP time packet sent by the receiver. The incoming timestamp and the outgoing timestamp are sent to the data processing unit;

S2, the data processing unit calculates a two-way time difference value according to the incoming time stamp and outgoing time stamp, sends the two-way time difference value to the switch chip, and sets the delay of the switch chip according to the two-way time difference value value;

S3, the switching chip updates the time at which the switching chip sends the PTP time packet according to the delay value.

Optionally, in the S1, the PHY chip periodically sends the incoming timestamp and the outgoing timestamp to the data processing unit.

Optionally, in the S1, the PHY chip sends the incoming time stamp and the outgoing time stamp to the data processing unit through an MDIO (Management Data Input/Output, management data input/output) signal line.

Optionally, in the S2, the bidirectional time difference is the difference between the outgoing timestamp and the incoming timestamp.

Optionally, in the S3, the time when the updated switching chip sends the PTP time packet is the time after adding the delay value.

The embodiment of the present invention also discloses an apparatus for realizing network time synchronization, the apparatus comprising:

The switch chip is used to send the PTP time message to the PHY chip;

The PHY chip is used to receive the switching chip, record the incoming timestamp of the PTP time packet received by the receiver and the outgoing timestamp of the PTP time packet sent by the transmitter, and record the incoming timestamp of the PTP time packet. and the out-timestamp is sent to the data processing unit, and

A data processing unit, configured to calculate a two-way time difference value according to the incoming timestamp and outgoing time stamp, send the two-way time difference value to the switch chip, and set the delay value of the switch chip according to the two-way time difference value ;

The switching chip is further configured to update the time at which the switching chip sends the PTP time packet according to the delay value.

Optionally, the PHY chip periodically sends the incoming timestamp and the outgoing timestamp to the data processing unit.

Optionally, the PHY chip sends the incoming time stamp and the outgoing time stamp to the data processing unit through an MDIO signal line.

Optionally, the bidirectional time difference is a difference between the outgoing timestamp and the incoming timestamp.

Optionally, the time when the updated switching chip sends the PTP time packet is the time after adding the delay value.

The beneficial effects of the embodiments of the present invention are:

The embodiment of the present invention compensates for the delay in the PHY chip by calculating the bidirectional time difference and setting the delay field in the switching chip according to the bidirectional time difference, so as to ensure that the round-trip path is symmetrical when the PTP time packet is calculated. This method combines the PTP function of the switching chip. For the PHY chip that does not support the 1588 protocol, the time synchronization of the network system is more efficiently and accurately realized, and because the PHY chip does not need to support the 1588 protocol, the requirements for the PHY chip are low. Only need to realize the time stamp recording and reporting of in and out, the whole system scheme is simple, the overall system cost and power consumption are reduced, and the system stability is improved.

Description of drawings

The accompanying drawings described herein are used to provide an understanding of the present invention and constitute a part of the present application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the attached image:

1 is a schematic flowchart of a method for implementing network time synchronization according to an embodiment of the present invention;

FIG. 2 is a schematic block diagram of an apparatus for implementing network time synchronization according to an embodiment of the present invention.

Detailed ways

The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention.

The method and device for realizing network time synchronization disclosed in the embodiment of the present invention, by combining the PTP function of the switching chip, adopts the bidirectional time difference value of the compensation message transmitted in the PHY chip, which is equivalent to calling the output of the PHY chip. Timestamp realizes high-precision network time synchronization of the Ethernet PHY chip.

As shown in FIG. 1 , a method for realizing network time synchronization disclosed by an embodiment of the present invention includes the following steps:

S1, the PHY chip receives the PTP time packet sent by the switching chip, records the incoming timestamp of the PTP time packet received by the receiver and the outgoing timestamp of the PTP time packet sent by the sender, and records the incoming timestamp and The output timestamp is sent to the data processing unit.

Optionally, the switching chip sends the PTP time packet to the PHY chip, and the time when the switching chip sends the PTP time packet is defined as the timestamp Ts0, and the delay time passing through the PHY chip is not added to Ts0 at this time.

The receiving end RX of the PHY chip receives the PTP time message sent by the switching chip, records the incoming time stamp of the PTP time message it receives, and records it as time stamp Ts1; the PHY chip sends the PTP time message from its sending end TX Sending out, the PHY chip records the outgoing timestamp of the PTP time packet sent by its outgoing port TX, which is recorded as the timestamp Ts2.

After that, the PHY chip sends both the recorded time stamp Ts1 and the time stamp Ts2 to the data processing unit DSP. In this embodiment, the PHY chip optionally periodically sends the recorded time stamps Ts1 and Ts2 to the data processing unit DSP. And in this embodiment, the PHY chip and the data processing unit DSP are connected through the MDIO (Management Data Input/Output, management data input and output) signal line, so the PHY chip sends the incoming timestamp and the outgoing timestamp through the MDIO signal line. to the data processing unit.

S2, the data processing unit calculates the two-way time difference value according to the incoming time stamp and the outgoing time stamp, sends the two-way time difference value to the switch chip, and sets the delay value of the switch chip according to the two-way time difference value.

Optionally, in this embodiment, the bidirectional time difference value is ΔTs, and the bidirectional time difference value ΔTs may be the difference between the timestamp Ts2 and the timestamp Ts1, that is, ΔTs=Ts2−Ts1, and the bidirectional time difference is ΔTs. The value is the delay time passing through the PHY chip.

The data processing unit sends the two-way time difference value to the delay register of the switch chip. The delay value Latency set in the switch chip is the two-way time difference value of ΔTs, that is, the delay value of the switch chip is the same as the two-way time difference value. As a result, the PTP time packet corrects the time delay passing through the PHY chip on the MAC (media access control, media access control sublayer) side of the switching chip, which is equivalent to timestamping from the exit of the PHY chip. Reduce link asymmetry.

Optionally, in this embodiment, the switching chip updates the time Ts0 at which it sends the PTP time packet, for example, updates the time Ts0 at which the switching chip sends the PTP time packet to the time Ts0 plus the delay value.

Correspondingly, as shown in FIG. 2 , an apparatus for realizing network time synchronization disclosed in an embodiment of the present invention includes a switching chip, a PHY chip, and a data processing unit, wherein,

The switch chip is used to send PTP time packets to the PHY chip.

The PHY chip is used to receive the switching chip, record the incoming timestamp of the PTP time packet received by the receiver and the outgoing timestamp of the PTP time packet sent by the sender, and send the incoming timestamp and outgoing timestamp to the data processing unit . Optionally, in this embodiment, the PHY chip periodically sends the incoming timestamp and the outgoing timestamp to the data processing unit through the MDIO signal line.

The data processing unit is used to calculate the bidirectional time difference according to the incoming time stamp and the outgoing time stamp. Optionally, the bidirectional time difference is the difference between the outgoing timestamp and the incoming timestamp, that is, the difference between the outgoing timestamp and the incoming timestamp. The data processing unit sends the bidirectional time difference value to the switching chip, and sets the delay value of the switching chip according to the bidirectional time difference value.

The switch chip is further configured to update the time at which the switch chip sends the PTP time packet according to the delay value, and the time at which the updated switch chip sends the PTP time packet is the time after adding the delay value.

Moreover, for the working principles of the switching chip, the PHY chip and the data processing unit, reference may be made to the descriptions in the above-mentioned methods S1 to S3, which will not be repeated here.

In the embodiment of the present invention, the time stamps of the packets entering and leaving the PHY chip are recorded, and the time stamp data is periodically sent to the DSP, and the DSP calculates a reasonable bidirectional time difference ΔTs. Set the delay field in the switch chip to compensate for the delay in the PHY chip, and ensure that the round-trip path is symmetrical when the PTP time packet is calculated. This method combines the PTP function of the switching chip. For the PHY chip that does not support the 1588 protocol, the time synchronization of the network system is more efficiently and accurately realized, and because the PHY chip does not need to support the 1588 protocol, the requirements for the PHY chip are low. Only need to realize the time stamp recording and reporting of incoming and outgoing, the whole system scheme is simple, which reduces the overall system cost and power consumption, and improves system stability and reduces hidden dangers.

The technical content and technical features of the embodiments of the present invention have been disclosed as above. However, those skilled in the art may still make various replacements and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should be It is not limited to the contents disclosed in the embodiments, but includes various substitutions and modifications without departing from the present invention, and is covered by the claims of this patent application.

Claims

A method for realizing network time synchronization, the method comprising:

S1, the PHY chip receives the PTP time packet sent by the switching chip, records the incoming timestamp of the PTP time packet received by the receiving end and the outgoing timestamp of the PTP time packet sent by the transmitting end, and records the incoming timestamp of the PTP time packet sent by the receiver. The incoming timestamp and the outgoing timestamp are sent to the data processing unit;

S2, the data processing unit calculates a two-way time difference value according to the incoming time stamp and outgoing time stamp, sends the two-way time difference value to the switch chip, and sets the delay of the switch chip according to the two-way time difference value value;

S3, the switching chip updates the time at which the switching chip sends the PTP time packet according to the delay value.
The method for realizing network time synchronization according to claim 1, wherein, in the S1, the PHY chip periodically sends the incoming time stamp and the outgoing time stamp to the data processing unit.
The method for realizing network time synchronization according to claim 1, wherein, in the S1, the PHY chip sends the incoming time stamp and the outgoing time stamp to a data processing unit through an MDIO signal line.
The method for realizing network time synchronization according to claim 1, wherein, in the S2, the bidirectional time difference is the difference between the outgoing timestamp and the incoming timestamp.
The method for realizing network time synchronization according to claim 1, wherein, in said S3, the time when the updated switching chip sends the PTP time packet is the time after adding the delay value.
A device for realizing network time synchronization, the device comprising:

The switch chip is set to send the PTP time message to the PHY chip;

The PHY chip is set to receive the switching chip, record the incoming timestamp of the PTP time packet received by the receiver and the outgoing timestamp of the PTP time packet sent by the transmitter, and record the incoming timestamp. stamp and the out-time stamp are sent to the data processing unit, and

The data processing unit is configured to calculate a two-way time difference value according to the incoming time stamp and outgoing time stamp, send the two-way time difference value to the switch chip, and set the delay of the switch chip according to the two-way time difference value value;

The switching chip is further configured to update the time at which the switching chip sends the PTP time packet according to the delay value.
The apparatus for realizing network time synchronization according to claim 6, wherein the PHY chip periodically sends the incoming time stamp and the outgoing time stamp to the data processing unit.
The apparatus for realizing network time synchronization according to claim 6, wherein the PHY chip sends the incoming time stamp and the outgoing time stamp to the data processing unit through an MDIO signal line.
The apparatus for realizing network time synchronization according to claim 6, wherein the bidirectional time difference is a difference between the outgoing timestamp and the incoming timestamp.
The device for realizing network time synchronization according to claim 6, wherein the time when the updated switching chip sends the PTP time message is the time after adding the delay value.