WO2022121038A1

WO2022121038A1 - Array substrate and preparation method therefor

Info

Publication number: WO2022121038A1
Application number: PCT/CN2020/141314
Authority: WO
Inventors: 杜彦英
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2020-12-11
Filing date: 2020-12-30
Publication date: 2022-06-16
Also published as: CN112599578B; CN112599578A

Abstract

Disclosed is an array substrate, comprising a display area and a non-display area surrounding the display area. The array substrate comprises a substrate and a plurality of elements to be tested which are arranged on the substrate. The array substrate further comprises: at least one test area which is arranged in the non-display area and provided with a plurality of test holes in each test area, each test hole extends to a part of the surface of an element to be tested, and a test element is used for penetrating through the test hole and coupling to the corresponding element to be tested so as to perform a sheet resistance test or a resistance test on the element to be tested, wherein in each test area, the test holes are uniformly arranged in a straight line; or in each test area, adjacent test holes are arranged in a staggered manner, and the cross sections of the test holes are arranged in a regular tetrahedron manner.

Description

Array substrate and preparation method thereof

technical field

The present application relates to the field of display technology, and in particular, to an array substrate and a preparation method thereof.

Background technique

With the vigorous development of active-matrix organic light-emitting diode (AMOLED) display technology, AMOLED has begun to be widely used in handheld terminals and large-scale displays, especially low-temperature polysilicon array substrates with small size and high The resolution AMOLED screen has become the most popular new favorite in the market. Due to the inherent uniformity defect of low-temperature polysilicon technology, the array substrate of this type of screen adopts a relatively complex compensation circuit structure. This design puts forward higher requirements for engineering capabilities, and the high cost of AMOLED also makes its yield rate extremely important. and difficult key issues.

Due to the scheme of pixel compensation circuit and driving circuit (Gate on Array, GOA)/(Gate in Panel, GIP), AMOLED uses up to 10~14 masks, between metal layers and metal layers, semiconductor layers and semiconductor layers. Contacts and interconnects become more challenging, and the thickness and etch non-uniformity often present in larger area substrates, especially as the center and corner non-uniformities inherent in plasma processing, add to this difficulty. Therefore, in order to reduce the This defect requires a real-time on-site detection method to improve the yield and bring better protection.

At present, it is generally adopted in the industry to test the square resistance and contact resistance after the metal layer is formed and after the SD metal annealing. Only defective products can be detected but there is no possibility of recovery.

Therefore, there is an urgent need to provide a new array substrate and a preparation method thereof for targeted real-time detection to solve the above problems.

technical problem

The present application provides an array substrate and a preparation method thereof. By forming test holes corresponding to the elements to be tested of the array substrate in the multilayer insulating layers of the array substrate, in each test area, the test holes are in the shape of Uniformly arranged in a straight line, or, in each test area, adjacent test holes are arranged staggered, the cross-section of the test holes is arranged in a regular tetrahedron, and the test holes extend to part of the surface of the component to be tested. The component runs through the test hole to perform square resistance test or resistance test on the component to be tested, so as to detect and monitor the process yield of forming the component to be tested, and to ensure the film thickness and etching uniformity of the metal film layer during the preparation process.

technical solutions

In a first aspect, an embodiment of the present application provides an array substrate having a display area and a non-display area surrounding the display area, the array substrate includes a substrate and a plurality of to-be-tested devices disposed on the substrate element, the array substrate further includes: at least one test area, the test area is arranged in the non-display area, each of the test areas has a plurality of test holes, and each of the test holes extends to a Part of the surface of the element to be tested, the test element penetrates the test hole to perform a square resistance test or a resistance test on the element to be tested; wherein, in each of the test areas, the test hole is linear and uniform Or, in each of the test areas, adjacent test holes are arranged in a staggered manner, and the cross sections of the test holes are arranged in a regular tetrahedron.

In the array substrate, each of the test holes includes a single channel or four channels insulated from each other.

In the array substrate, the element to be tested is at least one of a thin film transistor, a pixel electrode and a storage capacitor disposed on the array substrate.

In the array substrate, the element to be tested is at least one of an active layer, a gate, and a source and drain of the thin film transistor.

In the array substrate, the array substrate further includes a multi-layer insulating layer disposed on the substrate, and the plurality of test holes are disposed in the multi-layer insulating layer and extend to each of the Part of the surface of the component to be tested.

In a second aspect, an embodiment of the present application further provides a method for preparing an array substrate, the preparation method includes the following steps: forming at least one element to be tested on a substrate, and forming a plurality of test holes through a patterning process, wherein each One of the test holes extends to a part of the surface of the element to be tested, the test element penetrates the test hole and performs a square resistance test or a resistance test on the element to be tested.

In a third aspect, embodiments of the present application further provide an array substrate having a display area and a non-display area surrounding the display area, the array substrate including a substrate and a plurality of to-be-to-be-disposed on the substrate A test element, the array substrate further includes: at least one test area, the test area is disposed in the non-display area, each of the test areas has a plurality of test holes, and each of the test holes extends to a part of the surface of the element to be tested, the test element penetrates the test hole to perform a square resistance test or a resistance test on the element to be tested.

In the array substrate, in each of the test areas, the test holes are evenly arranged in a straight line.

In the array substrate, in each of the test areas, adjacent test holes are arranged in a staggered manner, and the cross sections of the test holes are arranged in a regular tetrahedron.

In the array substrate, the array substrate further includes a multi-layer insulating layer disposed on the substrate, and the plurality of elements to be tested are insulated from each other by the multi-layer insulating layer; wherein the plurality of The test holes are arranged in the multi-layer insulating layers and respectively extend to a part of the surface of each of the components to be tested.

In a fourth aspect, an embodiment of the present application further provides a method for preparing an array substrate, the preparation method comprising the steps of: forming at least one element to be tested on a substrate, and forming a plurality of test holes through a patterning process, wherein each One of the test holes extends to a part of the surface of the element to be tested, the test element penetrates the test hole and performs a square resistance test or a resistance test on the element to be tested.

In the preparation method, the test holes are formed by applying photoresist, exposing, developing and etching; The element to be tested is subjected to square resistance test or resistance test, and according to the test result, supplementary etching or supplementary film formation is performed on the test hole; and the photoresist is stripped.

In a fifth aspect, an embodiment of the present application further provides a display panel including the above-mentioned array substrate.

beneficial effect

Compared with the prior art, by arranging at least one test hole on the multi-layer insulating layer of the array substrate, in each test area, the test holes are uniformly arranged in a straight line, or, in each test area. In the area, adjacent test holes are staggered, the cross sections of the test holes are arranged in a regular tetrahedron, the test holes extend to a part of the surface of the component to be tested, and the test components are used to penetrate the test holes and connect with all the test holes. The element to be tested is coupled to perform a square resistance test or a resistance test on the element to be tested, so as to detect and monitor the formation of the element to be tested in real time, such as the active layer, gate, source and drain of thin film transistors, storage capacitors, and pixels. For the process yield of the electrode, the test hole is re-etched or the film layer is supplemented according to the test result, so as to ensure the film thickness and etching uniformity of the metal film layer during the preparation process.

Description of drawings

FIG. 1a is a schematic diagram of the distribution of test areas of the array substrate of the present application.

1b and 1c are enlarged schematic views of the test area in FIG. 1a.

Fig. 1d and Fig. 1e are schematic cross-sectional views of the test hole in Fig. 1b or Fig. 1c.

2a to 2c are partial structural schematic views of the array substrate of the present application.

FIG. 3 is a schematic diagram of the testing process of the array substrate of the present application.

Embodiments of the present invention

The present application provides an electrode structure, a method for preparing the same, and a thin film transistor. In order to make the purpose, technical solutions and effects of the present application clearer and clearer, the present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

1a to FIG. 1e, FIG. 1a is a schematic diagram of the distribution of the test area of the array substrate of the present application, FIG. 1b and FIG. 1c are enlarged schematic diagrams of the test area in FIG. 1a, and FIG. 1d and FIG. Schematic cross-section of the hole. In an embodiment of the present application, an array substrate is provided. As shown in FIG. 1a, the array substrate has a display area 10 and a non-display area complementary to the display area 10, and the array substrate includes a substrate 1 and a plurality of components to be tested 300 (see FIG. 3 ) disposed on the substrate 1 , the array substrate further includes at least one test area 100 , and the test area 100 is disposed in the non-display area. Please refer to FIG. 3 , and as shown in FIG. 1 b and FIG. 3 , each of the test areas 100 has a plurality of test holes 101 , and each of the test holes 101 extends to a portion of the element to be tested 300 On the surface, the test element 200 penetrates the test hole 101 to perform a square resistance test or a resistance test on the to-be-tested element 300 (see FIG. 3 ).

See Figures 2a to 2c. In the embodiment of the present application, the element to be tested 300 is at least one of a thin film transistor, a pixel electrode 3 or a storage capacitor 4 disposed on the array substrate. In the embodiment of the present application, preferably, the device to be tested 300 is at least one of the active layer 21 , the gate 23 or the source and drain 25 of the thin film transistor.

Specifically, as shown in FIG. 2a to FIG. 2c, the array substrate includes the plurality of thin film transistors disposed on the substrate 1, the pixel electrodes 3 disposed on the plurality of thin film transistors, and the storage capacitor 4 . Wherein, each of the thin film transistors includes the active layer 21, the gate electrode 23 and the source and drain electrodes 25 which are insulated from each other, and the pixel electrode 3 is electrically connected to the source and drain electrodes 25; The storage capacitor 4 is arranged in the same layer as the thin film transistor. In this embodiment, the element to be tested 300 is the active layer 21 , the gate 23 , the source and drain 25 , the pixel electrode 3 and the storage capacitor 4 of the thin film transistor at least one of.

In the present application, as shown in FIG. 1a, the test area 100 is located in the non-display area. The non-display area is an ineffective layout area, which is equivalent to that the plurality of test holes 101 are arranged in the ineffective layout area. As shown in FIG. 1a, preferably, the test area 100 is located at at least one of four corners, four sides and a center of the array substrate. In addition, before preparing the test holes 101, it is necessary to determine the reserved positions of the test holes 101. When reserving the positions of the test holes 101, the reserved area is larger than the diameter of the plurality of test holes 101. area.

As shown in FIG. 1b, in a preferred embodiment, the test holes 101 can be evenly arranged in a test area 100 in a straight line. As shown in FIG. 1 c , in another preferred embodiment, in the test area 100 , adjacent test holes 101 are arranged in a staggered manner, and the test holes 101 are arranged in a regular tetrahedron.

As shown in FIG. 1d and FIG. 3, in a preferred embodiment, the test hole 101 has a single channel 1011, and the test element 200 is a single probe; in another preferred embodiment, as shown in FIG. As shown in 1e and FIG. 3 , the test hole 101 includes four channels 1012 that are insulated from each other, and the test element 200 is preferably four probes. In this embodiment, the test element 200 is used to pass through the test hole 101 and contact the surface of the element to be measured 300 , and the test element 200 is used to pass the test hole 101 to the element to be measured. 300 for square resistance test or resistance test.

The test hole 101 has a taper structure, and the test hole 101 avoids key structures such as metal layers, traces, light-emitting devices, etc. of the array substrate. Setting the test hole 101 in the non-display area does not It will cause damage to the key structure of the array substrate.

As shown in FIG. 2a, in this embodiment, the test hole 101 includes an active layer test hole 51, a gate test hole 52, and a storage capacitor test hole 53; as shown in FIG. 2b, the test hole 101 includes a source-drain test hole 54 ; and as shown in FIG. 2 c , the test hole 101 further includes a pixel electrode test hole 55 .

As shown in FIG. 2a to FIG. 2c, the thin film transistor includes the active layer 21 disposed on the substrate 1, disposed on the active layer 21 and covering the active layer 21 and all The buffer layer 22 on the substrate 1 , the gate electrode 23 disposed on the buffer layer 22 , the gate insulation disposed on the gate electrode 23 and covering the gate electrode 23 and the buffer layer 22 layer 24 , the storage capacitor 4 disposed on the gate insulating layer 24 , and an interlayer dielectric disposed on the storage capacitor 4 and covering the storage capacitor 4 and the gate insulating layer 24 layer 26 , wherein the source and drain electrodes 25 are disposed on the interlayer dielectric layer 26 .

In this embodiment, as shown in FIG. 2 b and FIG. 2 c , the array substrate further includes a flat layer 6 and a pixel defining layer 7 . Wherein, the flat layer 6 is disposed on the source and drain 25 and covers the source and drain 25 and the interlayer dielectric layer 26, and the pixel electrode 3 is disposed on the flat layer 6; the The pixel defining layer 7 is disposed on the pixel electrode 3 and covers the pixel electrode 3 and the flat layer 6 .

In the present application, the array substrate further includes a multi-layer insulating layer formed on the substrate 1, and the plurality of components to be tested 300 are insulated from each other by the multi-layer insulating layer; wherein, a plurality of test holes 101 are disposed in the multi-layer insulating layers and respectively extend to a part of the surface of each of the components to be tested 300 .

In the embodiment of the present application, the multi-layer insulating layers are the buffer layer 22 , the gate insulating layer 24 , the interlayer dielectric layer 26 , the planarization layer 6 and the pixel defining layer 7 .

In the present application, in the test area 100 , a test element 200 is used for penetrating a test hole 101 , and the test element 200 is used for respectively connecting with the element to be measured, that is, the active layer 21 . , the gate 23 , the source and drain 25 , the pixel electrode 3 and the surface of the storage capacitor 4 are coupled to measure the square resistance or resistance of the element to be measured 300 . Wherein, the test element 200 is preferably a four-point probe, and the test element 200, that is, the four-point probe, simultaneously passes through one of the measurement holes 101 having the four channels 1012 to measure any one of the to-be-measured The surface of the element 300 is subjected to square resistance measurements or resistance measurements.

The present application also provides a method for preparing an array substrate as described above, and a method for preparing an array substrate is described in detail below. The preparation method comprises the following steps:

Step S01 : forming at least one element to be tested 300 on a substrate 1 , and forming a plurality of test holes through a patterning process, wherein each of the test holes extends to a part of the surface of the element to be tested 300 , and the element 200 is tested A square resistance test or a resistance test is performed on the element to be tested 300 through the test hole.

In this step, in this embodiment, the element to be tested 300 is formed on the substrate 1 , and the element to be tested 300 is a thin film transistor, a pixel electrode 3 and a storage capacitor 4 disposed on the array substrate at least one of ; further, the element to be tested 300 is at least one of the active layer 21 , the gate 23 and the source and drain 25 of the thin film transistor.

In this step, the array substrate further includes a multi-layer insulating layer formed on the substrate 1, and the plurality of elements to be tested 300 are insulated from each other by the multi-layer insulating layer; wherein, a plurality of test holes are formed Inside the multi-layer insulating layers and respectively extending to a part of the surface of each of the components to be tested 300 .

The multi-layer insulating layers include a buffer layer 22 , a gate insulating layer 24 , and an interlayer insulating layer 26 which are arranged at intervals in sequence.

In this step, the test holes are formed by applying photoresist, exposing, developing and etching; and stripping the test holes.

The test hole includes the active layer test hole 51 , the gate test hole 52 , and the storage capacitor test hole 53 formed in sequence. In this step, the active layer test hole 51 , the gate test hole 52 and the storage capacitor test hole 53 are formed through a patterning process, which specifically includes: coating photoresist on the interlayer insulating layer 26 . The resist is exposed and developed, and the multi-layer insulating layers of the array substrate are etched to form active layer test holes 51 , gate test holes 52 and storage capacitor test holes 53 in sequence.

In this step, the active layer test hole 51 sequentially penetrates the interlayer insulating layer 26 , the gate insulating layer 24 and the buffer layer 22 and extends to a part of the surface of the active layer 21 ; and , the gate test hole 52 sequentially penetrates the interlayer insulating layer 26 and the gate insulating layer 24, and extends to a part of the surface of the gate 23; and, the storage capacitor test hole 53 penetrates the The interlayer insulating layer 26 extends to a part of the surface of the storage capacitor 4 .

In this step, after the test hole is formed, and before the corresponding photoresist is peeled off, the test element 200 is passed through the test hole to perform a square resistance test or a resistance test on the corresponding test element 300 .

Specifically, in this step, after the active layer test hole 51 , the gate test hole 52 and the storage capacitor test hole 53 are etched, and before the corresponding photoresist is peeled off , and also includes using the test element 200 to pass through the active layer test hole 51 to perform a square resistance test or resistance test on the surface of the active layer 21 , and use the test element 200 to pass through the gate test hole 52 In order to perform square resistance test or resistance test on the surface of the gate 23, and use the test element 200 to pass through the storage capacitor test hole 53 to test the square resistance or test resistance of the surface of the storage capacitor 4 operate. According to the test results, the test holes are re-etched or film-forming is supplemented. and finally peel off the photoresist corresponding to the test hole.

Wherein, in this step, the active layer 21 is a semiconductor layer, the material of the active layer 21 is preferably low-temperature polysilicon (Poly-Si), and the active layer 21 can also be amorphous silicon (a-Si) Si), indium gallium zinc oxide (IGZO).

In this step, the gate 23 is any one of a single-layer metal film layer and a metal composite film layer, the gate 23 can preferably be copper or silver, and the gate 23 can also be selected from copper molybdenum alloy. In addition, the source and drain 25 are any one of a single-layer metal film layer or a metal composite film, for example, the source and drain 25 may be copper or silver, and the source and drain 25 may also be a copper-molybdenum alloy . In this step, the materials of the buffer layer 22 , the gate insulating layer 24 and the interlayer dielectric layer 26 may be any one of silicon nitride, silicon oxide and silicon oxynitride. In this step, the storage capacitor 4 includes upper and lower electrodes (not shown) spaced apart from each other. The material of the storage capacitor 4 is preferably copper.

In this step, at least one pixel electrode 3 , a flat layer 6 and a pixel defining layer 7 are formed in sequence, and a source-drain test hole 54 and a pixel electrode test hole 55 are formed through a patterning process.

In this step, a flat layer 6 covering the source and drain electrodes 25 is formed on the source and drain electrodes 25 , a pixel electrode 3 is formed on the flat layer 6 , and a pixel is formed on the pixel electrode 3 A definition layer 7 , the pixel definition layer 7 covers the pixel electrode 3 . And source and drain test holes 54 and pixel electrode test holes 55 are formed on the flat layer 6 and the pixel defining layer 7 through a patterning process.

In this step, the test holes are formed by applying photoresist, exposure, development and etching processes; wherein, the test holes include the source and drain test holes 54 and the pixel electrode test holes formed in sequence 55. Specifically, as shown in FIG. 2b, a photoresist is coated on the pixel defining layer 7, the photoresist is exposed and developed, and an etching process is performed on the pixel defining layer 7 and the A source-drain test hole 54 is formed on the flat layer 6 so that the source-drain test hole 54 penetrates the pixel defining layer 7 and the flat layer 6 in sequence, and the source-drain test hole 54 extends to the source and drain and a pixel electrode contact hole 55 is formed on the pixel defining layer 7 , and the pixel electrode testing hole 55 penetrates the pixel defining layer 7 and extends to a portion of the surface of the pixel electrode 3 .

In this step, after the test hole is formed and before the corresponding photoresist is peeled off, a square resistance test or a resistance test is performed on the corresponding element to be tested through the test hole through the test element 200 . Specifically, in this step S02, after the source-drain test hole 54 is etched and before the photoresist is stripped, the test element 200 is used to pass through the source-drain test hole 54 pair The surface of the source and drain 25 is subjected to square resistance test or resistance test.

And in this step S02, after the pixel electrode test hole 55 is etched and before the photoresist is peeled off, use the test element 200 to pass through the pixel electrode test hole 55 to the pixel electrode 3. The surface of the test square resistance or test resistance. And, according to the test results, the test holes, that is, the source-drain test holes 54 and the pixel electrode test holes 55, are etched or supplemented to form a film. Finally, the photoresist corresponding to the test hole is peeled off. In this step, the pixel electrode 3 can be any one of ITO/Ag/ITO, Ag/ITO, Al/WOx, and Ag/IZO, and the material of the pixel electrode 3 can also be selected as ITO.

In this step, optionally, the material of the flat layer 6 may be an inorganic insulating material such as silicon nitride or silicon oxide, or an organic insulating material, and the organic material includes but is not limited to polymethyl methacrylate, Siloxane, soluble polytetrafluoroethylene; and, the pixel defining layer 7 is preferably an insulating material such as silicon nitride.

In fact, the present application also provides a test method for an array substrate, the test method includes the steps:

S11: After forming the active layer test hole 51, the gate test hole 52 and the storage capacitor test hole 53, before peeling off the photoresist, use the test element 200 to pass through the active layer test hole 51 to the active layer test hole 51. The layer 21 is subjected to a square resistance test or a resistance test, the gate 23 is subjected to a square resistance test or a resistance test using the test element 200 through the gate test hole 52, and the test element 200 is used to pass through the storage capacitor test hole. 53 carry out a square resistance test or a resistance test to the storage capacitor 4;

S12: After the source and drain test holes 54 and the pixel electrode test holes 55 are formed, before stripping the photoresist, use the test element 200 to pass through the source and drain test holes 54 to perform a square resistance test or resistance test on the source and drain electrodes 25 For testing, use the test element 200 to pass through the pixel electrode test hole 55 to perform a square resistance test or a resistance test on the pixel electrode 3 .

Therefore, in the preparation method of the array substrate, it involves a test method in which the test element 200 passes through the test hole 101 to perform a resistance test or a square resistance test on the to-be-tested element 300, that is, when After the test hole 101 is etched and before the photoresist is peeled off, use the test element 200 to pass through the test hole 101 to perform a square resistance test or a resistance test on the element to be tested 300; if the test results meet the expected specifications , it means that the test hole 101 tested is well etched, if the test result does not meet the expected specifications, it means that the test hole 101 is not etched uniformly, for example, when no resistance is measured or the measurement result is insulation, you can Supplementary etching, etc. Correspondingly, the same design can be used when the different through holes are etched for the first time with special structural design and different through holes are not expected to be etched through. In the embodiment of the present application, the array substrate and the preparation method of the array substrate can greatly improve the monitoring capability of the plurality of test holes, and can timely remedy and restore the test holes.

In addition, the present application also provides a display panel, including the above-mentioned array substrate, and the display panel includes but is not limited to display panels such as OLED, LCD, and AMOLED.

In the array substrate, its manufacturing method, and the display panel described in the present application, the array substrate includes at least one element to be tested 300 . A plurality of test holes 101 are provided, and the test holes 101 respectively extend to each of the components to be tested 300 such as the active layer 21 , the gate 23 , the source and drain 25 of the thin film transistor, and the storage capacitor 4 and a part of the surface of the pixel electrode 3, the test element 200 is used to penetrate through the test hole 101 and are respectively coupled with the test element 300, so as to detect and form the test element 300, that is, the active layer 21, The process yield of the gate electrode 23 , the source and drain electrodes 25 , the storage capacitor 4 , and the pixel electrode 3 is ensured, and the film thickness and etching uniformity of the metal film layer during the preparation process are guaranteed.

For the specific implementation of the above operations, reference may be made to the foregoing embodiments, and details are not described herein again.

It can be understood that for those of ordinary skill in the art, equivalent replacements or changes can be made according to the technical solutions and inventive concepts of the present application, and all these changes or replacements should belong to the protection scope of the appended claims of the present application.

Claims

An array substrate has a display area and a non-display area surrounding the display area, the array substrate includes a substrate and a plurality of elements to be tested arranged on the substrate, characterized in that the array The base plate also includes:

at least one test area, the test area is arranged in the non-display area, each of the test areas has a plurality of test holes, each of the test holes extends to a part of the surface of the component to be tested, A test element penetrates the test hole to perform a square resistance test or a resistance test on the element to be tested;

Wherein, in each of the test areas, the test holes are evenly arranged in a straight line; or, in each of the test areas, the adjacent test holes are staggered, and the cross-section of the test holes is four-sided. Asana arrangement.
The array substrate according to claim 1, wherein each of the test holes comprises a single channel or four channels insulated from each other.
The array substrate according to claim 1, wherein the element to be tested is at least one of a thin film transistor, a pixel electrode and a storage capacitor disposed on the array substrate.
The array substrate according to claim 3, wherein the element to be tested is at least one of an active layer, a gate, and a source and drain of the thin film transistor.
An array substrate has a display area and a non-display area surrounding the display area, the array substrate includes a substrate and a plurality of components to be tested arranged on the substrate, characterized in that the array The base plate also includes:

at least one test area, the test area is arranged in the non-display area, each of the test areas has a plurality of test holes, each of the test holes extends to a part of the surface of the component to be tested, A test element penetrates through the test hole to perform a square resistance test or a resistance test on the to-be-tested element.
The array substrate according to claim 5, wherein in each of the test areas, the test holes are uniformly arranged in a straight line.
The array substrate according to claim 5, wherein in each of the test areas, adjacent test holes are arranged in a staggered manner, and the cross sections of the test holes are arranged in a regular tetrahedron.
The array substrate according to claim 5, wherein each of the test holes comprises a single channel or four channels insulated from each other.
The array substrate according to claim 5, wherein the element to be tested is at least one of a thin film transistor, a pixel electrode and a storage capacitor disposed on the array substrate.
The array substrate according to claim 9, wherein the element to be tested is at least one of an active layer, a gate, and a source and drain of the thin film transistor.
The array substrate according to claim 10, wherein the array substrate further comprises a multi-layer insulating layer disposed on the substrate, and the plurality of elements to be tested are insulated from each other by the multi-layer insulating layer; Wherein, the plurality of test holes are arranged in the multi-layer insulating layer and respectively extend to a part of the surface of each of the components to be tested.
A preparation method of an array substrate, characterized in that the preparation method comprises the following steps:

At least one element to be tested is formed on a substrate, and a plurality of test holes are formed through a patterning process, wherein each of the test holes extends to a part of the surface of the element to be tested, the test element penetrates the test hole and The element to be tested is subjected to a square resistance test or a resistance test.
The method for preparing an array substrate according to claim 12, wherein the test hole is formed by applying photoresist, exposing, developing and etching; and, after the test hole is formed, a test element is passed A square resistance test or a resistance test is performed on the corresponding element to be tested through the test hole, and according to the test result, supplementary etching or supplementary film formation is performed on the test hole; and the photoresist is stripped.
A display panel, comprising the array substrate according to any one of claims 5 to 11.