WO2022111309A1 - 一种码块识别方法及装置 - Google Patents

一种码块识别方法及装置 Download PDF

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Publication number
WO2022111309A1
WO2022111309A1 PCT/CN2021/130372 CN2021130372W WO2022111309A1 WO 2022111309 A1 WO2022111309 A1 WO 2022111309A1 CN 2021130372 W CN2021130372 W CN 2021130372W WO 2022111309 A1 WO2022111309 A1 WO 2022111309A1
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WO
WIPO (PCT)
Prior art keywords
code block
bit pattern
template
code
bit
Prior art date
Application number
PCT/CN2021/130372
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English (en)
French (fr)
Inventor
李日欣
钟其文
徐丽
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21896810.5A priority Critical patent/EP4239918A4/en
Publication of WO2022111309A1 publication Critical patent/WO2022111309A1/zh
Priority to US18/324,372 priority patent/US20230299880A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a code block identification method and device.
  • the sender will send the client signal in the form of code blocks.
  • the client signal may be sent in the form of a start code block, a data code block and an end code block (also referred to as a code block stream).
  • the receiving end After the receiving end receives the code block stream, if it wants to acquire the client signal from the code block stream, it needs to identify the start code block from the code block stream.
  • the present application provides a code block identification method and device, which can effectively improve the situation that the start code block cannot be identified due to occasional code errors, and improve the fault tolerance of the system.
  • an embodiment of the present application provides a code block identification method, the method includes: acquiring a code block stream, where the code block stream includes a first code block; determining a to-be-identified bit pattern, the to-be-identified bit pattern Including a first bit pattern, the first bit pattern is the bit pattern corresponding to the first code block; comparing the to-be-identified bit pattern and the template bit pattern to obtain inconsistent bit numbers, the template bit pattern includes the first bit pattern A template bit pattern, where the first template bit pattern is a template bit pattern corresponding to the first boundary code block; in the case that the number of inconsistent bits is less than or equal to a first threshold, identifying that the first code block is the The first boundary code block.
  • the first bit pattern corresponds to the first template bit pattern, that is, the position of the first bit pattern in the to-be-identified bit pattern corresponds to the position of the first template bit pattern in the template bit pattern.
  • the first template bit pattern is used to identify the first bit pattern.
  • the bit positions in the first bit pattern correspond to the bit positions in the first template bit pattern.
  • the 0th bit in the first bit pattern corresponds to the 0th bit in the first template bit pattern
  • the first bit in the first bit pattern corresponds to the 1st bit in the first template bit pattern bit
  • the second bit in the first bit pattern corresponds to the second bit in the first template bit pattern, and so on.
  • the description of the first bit pattern and the first template bit pattern is also applicable to the second bit pattern and the second template bit pattern shown in this application, and the third bit pattern and the third template bit pattern. detail.
  • the method provided by the embodiments of the present application can effectively improve the determination that the first code block is not the first boundary code block when the number of bits inconsistent between the first code block and the first boundary code block (such as the S code block) is not 0 bits. happening. Therefore, the situation that the first code block cannot be identified as the first boundary code block due to occasional code errors is improved, and the fault tolerance of the system is improved.
  • the first code block is a P1 B/P2 B code block
  • the P1 is the number of payload bits of the first code block
  • the P2 is the first code block
  • the total number of bits of , P2-P1 represents the number of synchronization header bits of the first code block, the P1 and the P2 are positive integers respectively, and the P2 is greater than the P1.
  • the first bit pattern includes a pattern formed by bits 0 to 9 of the first code block, and a start bit of the first code block is the 0 bits.
  • the first code block by obtaining the 0th bit to the ninth bit of the first code block, it is possible to identify whether the first code block is the first boundary code block, which is not only convenient and simple to implement, but also ensures that the first code block is is identified as the reliability of the first boundary code block.
  • the first bit pattern may also include a pattern formed by the 0th bit to the 65th bit of the first code block, and the like, and the specific structure of the first bit pattern is not limited in this embodiment of the present application.
  • the 0th bit of the first code block and the first bit of the first code block are a synchronization header of the first code block
  • the second bit to the ninth bit of the first code block are the control block type field of the first code block.
  • the second to ninth bits of the first code block may also be data bytes of the first code block.
  • the second to ninth bits are the first data bytes of the data code block.
  • the identifying that the first code block is the first boundary code block when the number of inconsistent bits is less than or equal to a first threshold includes:
  • the to-be-identified bit pattern and the template bit pattern have inconsistent bits, and the number of the inconsistent bits is less than or equal to the first threshold, identifying the first code block as the first boundary code block.
  • the communication device when the number of inconsistent bits between the bit pattern to be identified and the template bit pattern is greater than or equal to 1, and the number of inconsistent bits is less than or equal to the first threshold, the communication device can still identify the first A code block is the first boundary code block.
  • identifying the first code block as the first boundary code block includes: in the first bit When the pattern is inconsistent with the first template bit pattern, and the number of inconsistent bits is less than or equal to the first threshold, the first code block is identified as the first boundary code block.
  • the first code block is the first boundary code block.
  • the first code block can still be identified as the first boundary code block.
  • the code block stream further includes a second code block
  • the to-be-identified bit pattern further includes a second bit pattern
  • the second bit pattern is a bit corresponding to the second code block pattern
  • the template bit pattern further includes a second template bit pattern, and the second template bit pattern corresponds to the second bit pattern.
  • the second template bit pattern is a template bit pattern corresponding to any of the following code blocks: a second boundary code block, an idle code block, a sequence code block, a signal code block, and an error code block .
  • the second code block may be a code block before the first code block.
  • the second code block may be a code block adjacent to the first code block and located before the first code block.
  • the second bit pattern includes a pattern formed by bits 0 to 9 of the second code block, and a start bit of the second code block is the first bit of the second code block. 0 bits.
  • the 0th bit and the 1st bit of the second code block may be the synchronization header of the second code block.
  • the second to ninth bits of the second code block may be the control block type field of the second code block.
  • the code block stream further includes a third code block
  • the bit pattern to be identified further includes a third bit pattern
  • the third bit pattern is a bit corresponding to the third code block pattern
  • the template bit pattern further includes a third template bit pattern
  • the third template bit pattern corresponds to the third bit pattern
  • the third template bit pattern is a template bit pattern corresponding to a data code block.
  • the third code block may be a code block subsequent to the first code block.
  • the third code block may be a code block adjacent to the first code block and located after the first code block.
  • the identifying that the first code block is the first boundary code block when the number of inconsistent bits is less than or equal to a first threshold value includes: in the first code block When a bit pattern is consistent with the first template bit pattern, and the number of inconsistent bits is less than or equal to the first threshold, the first code block is identified as the first boundary code block.
  • the identifying that the first code block is the first boundary code block when the number of inconsistent bits is less than or equal to a first threshold includes: determining a second bit The second bit pattern is the bit pattern corresponding to the second code block; the second bit pattern is compared with the second template bit pattern; when the number of inconsistent bits is less than or equal to the first threshold, and all In a case where the number of bits that are inconsistent between the second bit pattern and the second template bit pattern is less than or equal to a second threshold, the first code block is identified as the first boundary code block.
  • the communication device may identify that the first code block is the first boundary code block.
  • the communication device may compare the bit pattern to be identified with the template bit pattern, such as the first bit pattern and the first template bit pattern, to obtain the number of bits that are inconsistent between the first bit pattern and the first template bit pattern. And the communication device can also compare the second bit pattern with the second template bit pattern to obtain the number of bits that are inconsistent between the second bit pattern and the second template bit pattern. in the case where the number of bits of the first bit pattern inconsistent with the first template bit pattern is less than or equal to the first threshold, and in the case where the number of bits of the second bit pattern inconsistent with the second template bit pattern is less than or equal to the second threshold , identifying the first code block as the first boundary code block.
  • the template bit pattern such as the first bit pattern and the first template bit pattern
  • the communication device may first compare the to-be-identified bit pattern (eg, the first bit pattern) with the template bit pattern (eg, the first template bit pattern), and when the number of inconsistent bits between the to-be-identified bit pattern and the template bit pattern is less than or equal to the first In the case of a threshold, the communication device then compares the second bit pattern with the second template bit pattern. Thus, in the case where the number of bits of the second bit pattern that are inconsistent with the second template bit pattern is less than or equal to the second threshold, the first code block is identified as the first boundary code block.
  • the inconsistent number of bits between the second bit pattern and the second template bit pattern is not included in the above-mentioned first threshold.
  • the second threshold may be 0 or 1, etc., which is not limited in this embodiment of the present application.
  • the identifying that the first code block is the first boundary code block when the number of inconsistent bits is less than or equal to a first threshold includes: determining a second bit the second bit pattern is the bit pattern corresponding to the second code block; compare the second bit pattern with the second template bit pattern; when the number of inconsistent bits is less than or equal to the first threshold, and the first When the two-bit pattern matches the second template bit pattern, the first code block is identified as the first boundary code block.
  • the identifying that the first code block is the first boundary code block when the number of inconsistent bits is less than or equal to a first threshold includes: determining a third bit The third bit pattern is the bit pattern corresponding to the third code block; the third bit pattern is compared with the third template bit pattern; when the number of inconsistent bits is less than or equal to the first threshold, and all In a case where the number of bits that are inconsistent between the third bit pattern and the third template bit pattern is less than or equal to a second threshold, the first code block is identified as the first boundary code block.
  • the third code block may be a data code block.
  • the method further includes: determining a first code block from the code block stream according to the first code block. A code group, the first code group starts with the first code block.
  • the first code group includes 195 data code blocks and one end code block.
  • the communication device can demultiplex a plurality of first time slots corresponding to the code group starting with the S code block, so as to obtain the corresponding first time slots of the plurality of first time slots.
  • the client signal is not only simple to implement, but also can effectively ensure the reliability of the code group to be identified.
  • the first code group carries T client signals, where T is a positive integer.
  • the first code group may carry T client signals.
  • the first code group may also not carry client signals, etc., which is not limited in this embodiment of the present application.
  • T 24.
  • the present application provides a communication apparatus for executing the method in the first aspect or any possible implementation manner of the first aspect.
  • the communication apparatus includes corresponding means for performing the method of the first aspect or any possible implementation of the first aspect.
  • the communication device may include a transceiving unit and a processing unit.
  • the present application provides a communication device, where the communication device includes a processor, configured to execute the method shown in the first aspect or any possible implementation manner of the first aspect.
  • the process of receiving a code block (or code block stream) in the above method can be understood as a process of receiving an input code block (or code block stream) by the processor.
  • the processor receives the incoming code block (or code block stream)
  • the transceiver receives the code block (or code block stream) and inputs it into the processor. Further, after the code block (or code block stream) is received by the transceiver, the code block (or code block stream) may need to undergo other processing before being input to the processor.
  • the above-mentioned processor may be a processor specially used to execute these methods, or may be a processor that executes computer instructions in a memory to execute these methods, such as a general-purpose processor.
  • the above-mentioned memory can be a non-transitory (non-transitory) memory, such as a read-only memory (Read Only Memory, ROM), which can be integrated with the processor on the same chip, or can be set on different chips respectively.
  • ROM read-only memory
  • the embodiment does not limit the type of the memory and the setting manner of the memory and the processor.
  • the memory is located outside the communication device.
  • the memory is located within the communication device.
  • the processor and the memory may also be integrated into one device, that is, the processor and the memory may also be integrated together.
  • the communication apparatus further includes a transceiver for receiving and/or transmitting signals.
  • the transceiver may be used to receive a stream of code blocks or the like.
  • the present application provides a communication device, the communication device includes a logic circuit and an interface, and the logic circuit is coupled to the interface; wherein, the interface is used to obtain a code block stream (or, it can also be referred to as is the input code block stream), the logic circuit is used to determine the bit pattern to be identified, and compare the bit pattern to be identified with the template bit pattern to obtain inconsistent bit numbers; when the inconsistent bit number is less than or equal to the first In the case of a threshold, the first code block is identified as a first boundary code block.
  • the present application provides a computer-readable storage medium, the computer-readable storage medium is used to store a computer program, which, when running on a computer, enables the first aspect or any possible implementation of the first aspect The method shown is executed.
  • the present application provides a computer program product, the computer program product comprising a computer program or computer code, when it is run on a computer, the above-mentioned first aspect or any possible implementation of the first aspect is shown. method is executed.
  • the present application provides a computer program, when the computer program runs on a computer, the method shown in the first aspect or any possible implementation manner of the first aspect is executed.
  • FIG. 1 is a schematic diagram of a communication system based on a flexible Ethernet protocol provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of an MTN network architecture provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of another MTN network architecture provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the relationship between a first channel and a second channel provided by an embodiment of the present application
  • 5a is a different code type definition of a 64B/66B code block provided by an embodiment of the present application.
  • 5b and 5c are schematic structural diagrams of a code group provided by an embodiment of the present application.
  • FIG. 5d is a schematic diagram of an encapsulation process of a code group provided by an embodiment of the present application.
  • 6a and 6b are schematic diagrams of a template bit pattern provided by an embodiment of the present application.
  • FIGS. 7a to 7c are schematic diagrams of a template bit pattern provided by an embodiment of the present application.
  • 8a is a schematic diagram of a comparison between a template bit pattern and a to-be-identified bit pattern provided by an embodiment of the present application;
  • 8b is a schematic structural diagram of a template bit pattern provided by an embodiment of the present application.
  • 8c is a schematic structural diagram of a to-be-identified bit pattern provided by an embodiment of the present application.
  • FIG. 9 is a schematic flowchart of a code block identification method provided by an embodiment of the present application.
  • 10a is a schematic flowchart of a code block identification method provided by an embodiment of the present application.
  • 10b is a schematic diagram of a module for identifying an S code block provided by an embodiment of the present application.
  • FIG. 11 is a schematic flowchart of a code block identification method provided by an embodiment of the present application.
  • FIG. 13 and 14 are schematic flowcharts of another code block identification method provided by an embodiment of the present application.
  • FIG. 15 to FIG. 17 are schematic structural diagrams of a communication device provided by an embodiment of the present application.
  • At least one (item) means one or more
  • plural means two or more
  • at least two (item) means two or three and three
  • “and/or” is used to describe the relationship of related objects, indicating that there can be three kinds of relationships, for example, "A and/or B” can mean: only A exists, only B exists, and both A and B exist three A case where A and B can be singular or plural.
  • the character “/” generally indicates that the associated objects are an “or” relationship.
  • At least one of the following” or similar expressions refers to any combination of these items. For example, at least one (a) of a, b or c, can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c" ".
  • FlexE optical internet forum
  • FlexE flexible ethernet
  • a bonding group can be composed of one or more physical layer devices (which can also be considered as physical link interfaces, which can be denoted as PHYs).
  • PHYs physical link interfaces
  • the bandwidth resource corresponding to a bonding group is the sum of the bandwidth resources corresponding to the PHYs in the bonding group. Therefore, , Based on the bundled group, FlexE can meet the larger transmission rate and transmission bandwidth.
  • FIG. 1 exemplarily shows a schematic diagram of a communication system based on a flexible Ethernet protocol
  • FIG. 1 is an example of a bonding group including 4 PHYs.
  • FlexE divides the bandwidth resources of each PHY into multiple time slots by means of time division multiplexing (TDM) to achieve hard isolation of transmission pipeline bandwidth.
  • the flexible Ethernet protocol client (FlexE Client) transmits service flows on behalf of the time slot (one time slot or multiple time slots) specified on the binding group.
  • a binding group can carry multiple flexible Ethernet protocol clients, one flexible Ethernet
  • the protocol client corresponds to a service flow (typically, it can be called medium access control (MAC) Client), and the flexible Ethernet protocol functional layer (also called FlexEshim) layer provides flexible Ethernet protocol client to MAC Client. Data adaptation and transformation.
  • MAC medium access control
  • FlexEshim flexible Ethernet protocol functional layer
  • FlexE can support functions such as bonding, sub-rate, channelization, etc. by bonding multiple PHYs.
  • FlexE can bind multiple 100-bit Ethernet (gigabit ethernet, GE) PHY ports, and divide each 100GE port into 20 time slots with 5G particles in the time domain. FlexE can support different Ethernet ports.
  • MAC rate services For example, to support 200G MAC services in a 2 ⁇ 100GE bonding group, that is, FlexE binds multiple Ethernet ports into a bonding group (group) to support MAC services with a rate greater than that of a single Ethernet port, that is, FlexE supports the bonding function .
  • Another example is to support the transmission of 50G MAC services in 100GE bundled groups, that is, by allocating time slots for services to support MAC services with a rate smaller than the bandwidth of the bundled group or smaller than the bandwidth of a single Ethernet port, that is, FlexE supports the sub-rate function.
  • Another example is to support simultaneous transmission of one 150G and two 25G MAC services in a 2 ⁇ 100GE bundle, that is, to support simultaneous transmission of multiple MAC services in a bundle by allocating time slots for services, that is, FlexE supports channelization.
  • FlexE can transmit multiple service flows in parallel through the bundling group, and the service data of the same service flow can be carried on one PHY in the bundling group, or can be carried on different PHYs in the bundling group.
  • the service data of the same service flow can be transmitted to the opposite end through one PHY in the bundling group, or can be transmitted to the opposite end through multiple PHYs in the bundling group.
  • the bandwidth resource of a PHY is usually divided into multiple time slots.
  • the code block stream corresponding to the service can be allocated to the corresponding time slot according to the time slot configuration table. It can be understood that the bandwidth resource of one PHY shown here is usually divided into multiple time slots, and the time slot can be understood as the second time slot.
  • binding group shown in this application may also be called a link group, etc.
  • service flow shown in this application may also be called a data flow, etc., the names of which are not limited in this application.
  • service flow shown here can also be understood as the client signal and the like shown below.
  • the MTN is a new generation of transport network technology system defined by the International Telecommunication Union (telecommunication standardization sector of itu, ITU-T) based on the design logic of FlexE for 5G and other new service requirements.
  • the MTN may include an MTN path layer (MTN path layer) and an MTN section layer (MTN section layer).
  • the MTN channel layer includes an MTN channel adaptation layer (MTN path adaptation), an MTN channel termination layer (MTN path trail termination), an MTN channel connection layer (MTN path connection), and the like.
  • the MTN section layer includes the MTN section layer adaptation layer (MTN section adaptation) and the MTN section layer termination layer (MTN section trail termination).
  • the MTN segment layer may further include an adaptation layer.
  • MTN channel adaptation layer MTN channel termination layer, MTN channel connection layer or MTN segment layer termination layer may also have other names.
  • the MTN channel adaptation layer may also be called the MTN channel adaptation function module. etc., which are not limited in this application. It can be understood that, for the description about the bundling group in the MTN, reference may be made to the description about the bundling group in the FlexE, which will not be described in detail here.
  • the service stream obtained by the sender may pass through the MAC, enter the MTN domain MTN channel adaptation layer and be adapted into the form of 64B/66B code block stream.
  • 64B The channel layer operations, administration, and maintenance (OAM) information is inserted into the /66B code block stream, and the OAM information includes the bit interleavedparity (BIP) result.
  • the sending end can perform channel forwarding through the MTN path connection layer (MTN path connection), that is, the corresponding relationship between the ingress and egress ports is determined at the MTN path connection layer, thereby determining the egress port.
  • MTN path connection MTN path connection layer
  • the MTN section layer adaptation layer (MTN section adaptation) is the adaptation function from the channel layer to the section layer.
  • the service flows of each MAC such as the form of 64B/66B code blocks
  • a 64B/66B code block stream is formed.
  • the one-way 64B/66B code block stream enters the physical layer for transmission through the MTN section trail termination layer (MTN section trail termination), the adaptation layer (adaptation), and the like.
  • the 64B/66B code block stream may also be subjected to scrambling, channel distribution, alignment marker (alignment marker, AM) insertion functions, and the like.
  • the flow direction of the 64B/66B code block stream received by the receiving end is opposite to the flow direction of the 64B/66B code block stream sent by the transmitting end.
  • the 64B/66B code block stream received by the receiving end may sequentially pass through, for example, the MTN segment layer, the MTN channel layer, and the like.
  • the segment layer of MTN is functionally similar to the OIF FlexE shim.
  • the current version of the MTN segment layer reuses compatible FlexE, and the segment layer frame format of the current version of MTN retains the FlexE frame format.
  • MAC coordination sublayer
  • RS reconciliation sublayer
  • PCS encode/decode physical coding sublayer encoding/decoding
  • the client signal (Client) in Figure 3 forms a code group stream after passing through the MTN fg adaptation layer.
  • the code group stream passes through the MTN fg termination layer, the code group stream can be inserted into OAM information or the like (or can also be understood as being inserted into overhead information).
  • the sender determines the correspondence between the ingress and egress ports at the MTN fg connection layer, thereby determining the egress port.
  • the code group stream can be transmitted in the first channel; then at the MTN channel layer, such as the MTN channel adaptation layer, one or more first channels can be multiplexed. One or more first time slots divided by the second channel.
  • overhead information such as OAM can be inserted into one second channel, and at the MTN segment layer adaptation layer, one or more second channels are multiplexed and divided into one or more second time slots by the bundling group . That is, at the MTN segment layer, one second channel can be mapped to one or more second time slots.
  • the code group is encapsulated in the form of code blocks
  • the code group stream passes through the MTN channel layer and the MTN segment layer, what the MTN channel layer and the MTN segment layer perceive is the code block stream.
  • the block stream passes through the physical layer and is sent onto the link.
  • the receiving end may demultiplex the second channel from one or more second time slots in the bundling group at the MTN segment layer adaptation layer. and the MTN channel adaptation layer demultiplexes the first channel from one or more first time slots in the second channel. Thereby, the receiving end can recover the client signal flow from the first channel at the MTN fg layer. It is understandable that since the flow direction of the client signal stream obtained by the receiving end is opposite to the flow direction of the client signal stream sent by the sender end, for the specific way that the receiving end obtains the client signal stream, the sending end can also send the description of the code block stream. More details.
  • slicing packet network (SPN) or MTN provides a hard pipeline based on n ⁇ 5Gbps bandwidth, where n is a positive integer.
  • n is a positive integer.
  • the 5Gbps pipeline bandwidth granularity is still too large.
  • the present application also provides a small particle pipeline.
  • the method provided in the present application can further divide the 5Gbps time slot, for example, divide the 5Gbps time slot into 480 10Mbps time slots.
  • one 10 Mbps may correspond to one client signal, or a plurality of 10 Mbps may correspond to one client signal, etc., which is not limited in this application.
  • the 5Gbps shown here can also be understood as the second time slot.
  • the second time slot may be divided into a plurality of first time slots.
  • the second time slot may be divided into 480 first time slots.
  • the first time slot can include not only 10 Mbps, but also 100 Mbps, 7.5 Mbps, 5 Mbps or 2.5 Mbps, etc.
  • the second time slot can include not only 5 Gbps, but also 10 Gbps, 25 Gbps, etc., which is not limited in this application .
  • the bandwidth of each time slot shown in the present application may still have deviations in specific implementation. Therefore, the present application does not limit the specific value of the bandwidth of the first time slot or the second time slot. Exemplarily, when the bandwidth of the first time slot is 10 Mbps, in a specific implementation, the bandwidth of the first time slot may also be 10.1 Mbps or 10.2 Mbps, or the like.
  • the bundling group, the first time slot and the second time slot shown in this application will be described in detail below.
  • a bundled group may be formed by bundling one or more PHYs, and the bandwidth of the bundled group is the sum of the bandwidths of the one or more PHYs. Further, the bundling group may be divided into X second time slots.
  • the second channel may include N second time slots of the X second slots, and the second channel may be divided into Y first time slots.
  • the first channel may include M first time slots among the Y first time slots. Wherein, N is less than or equal to X, M is less than or equal to Y, and M, N, X and Y are all integers greater than or equal to 1.
  • the first channel includes M first time slots
  • the M first time slots are included in the second channel
  • the second channel includes N second time slots
  • the N second time slots The timeslots are contained in bundled groups that include one or more PHY links.
  • the second channel is divided into Y first time slots
  • the above M first time slots are included in the Y first time slots
  • the bundling group is divided into X second time slots
  • the above N second time slots The time slots are included in the X second time slots.
  • the bandwidth of the first time slot in this application may be 10 Mbps ⁇ K, where K is an integer greater than or equal to 1, and K is less than or equal to 2048.
  • the above-mentioned first channel may be understood as a channel for transmitting code groups, and the above-mentioned second channel may be understood as a channel for transmitting code blocks.
  • M first time slots among the Y first time slots divided by the second channel may be multiplexed.
  • the time slot granularity of the first channel shown in this application is smaller, and the transport network technology is smaller and more flexible than the time slot granularity of MTN.
  • the first channel can be used to transmit dedicated line services and the like.
  • the first channel may be used to transmit one or more different client signals, or the like. It can be understood that the first channel can be used to transmit the code group shown in this application (eg, the first code group, etc.), and the code group can be transparently transmitted to the MTN network.
  • one PHY in the bonding group may include three second channels, and the second time slots included in the second channels are included in the bonding group.
  • One of the second channels may include three first channels, for example, the M first time slots included in the first channel are included in the second channel.
  • the first channel may also be referred to as fgBU channel (or MTN fg channel), flexible small particle channel (or small particle channel) or low-order channel, etc.
  • the second channel may also be referred to as large particle channel or high-order channel etc., the names of which are not limited in this application.
  • P1 B/P2 B code block A coding method, also called P1 B/P2 B bit block, or P1 B/P2 B block, or P1 B/P2 B-coded blocks, or may also be referred to as P1 B/P2 B bitstreams, or may also be referred to as P1/P2 (or P1b/P2b) bit blocks, etc.
  • P1 represents the number of payload bits in the code block (or bit block);
  • P2 represents the total number of bits in the code block,
  • P2-P1 represents the number of synchronization header bits in the code block, P1 and P2 are positive integers, and P2 is greater than P1.
  • the above P1 B/P2 B code block may be an 8 B/10 B code block, a 64 B/66 B code block, a 128 B/130 B code block, or a 256 B/258 B code block, etc.
  • the specific values of the above P1 and P2 are not limited.
  • the 64 B/66 B code block shown below can also be replaced by a 64 B/66 B bit block, or a 64/66 code block, or a 64/66 bit block, or a 64 B/66 B code block, or 64b/66b bit block, or 64 B/66 B bit block stream, or 64 B/66 B encoded block, etc.
  • Fig. 5a shows different code pattern definitions for a 64B/66B code block.
  • the 2 bits "10" or "01" in the header are synchronization header bits
  • the last 64 bits are payload bits, which can be used to carry payload data and the like.
  • Each row in Figure 5a represents a code pattern definition, wherein D0-D7 represent data bytes, C0-C7 represent control bytes, S0 represent the beginning of a MAC frame, and T0-T7 represent the end of a MAC frame.
  • the corresponding code block when the synchronization header bit is 0b10, the corresponding code block may be called a control code block.
  • the control code block is the control code pattern defined in the above P1 B/P2 B code block.
  • the synchronization header of the control code block may be "10"
  • the control code block may further include a control block type field.
  • control code block can be the start code block.
  • control block type field of the control code block defined in 64B/66B is 0xFF
  • the control code block can be the end code block. It is understandable that only an end code block is shown exemplarily here, and the control block type field of the end code block in the code block shown in FIG. 5a may also be 0x87, 0x99, etc., which will not be described in detail here.
  • the control block type field of the second boundary code block shown below in this application may not only be 0xFF, but also 0x87, 0x99, 0xAA, 0xB4, 0xCC, 0xD2 or 0xE1, etc. The type field is not limited.
  • control code block when the control block type field of the control code block defined in 64 B/66 B is 0x4B, the control code block may be a sequence (sequence ordered set, O) code block, or may also be called a signal (signal ordered set, O) code blocks, etc.
  • sequence code block may represent the link state
  • signal code block may represent information of a special signal. This application does not limit the difference between the sequence code block and the signal code block.
  • the sequence code block or the signal code block will be represented by an O code block.
  • the control code block when the control block type field of the control code block defined in 64B/66B is 0x1E, the control code block can be an idle code block or an error code block. As for whether the control code block is an idle code block or an error code block, it can be determined according to the value of the first control byte after the control block type field. For example, when the first control byte is 0xIE, the control code block is an error code block; when the first control byte is 0x00, the control code block can be an idle code block.
  • Boundary code blocks can be used to identify the start or end of a data code block.
  • the boundary code block may include the first boundary code block and/or the second boundary code block.
  • a preamble and/or a start of frame delimiter (SFD) in a message can be encoded as a start code block.
  • an end code block may be added after the last data code block during encoding (or, the end code block may also be used to carry data, etc.). That is, the start code block and the end code block shown here can be used to define at least one data code block. Exemplarily, the start code block and the end code block may be used to define 195 data code blocks. Alternatively, the start code block and end code block may be used to define 33 data code blocks or the like.
  • the descriptions of the start code block and the end code block shown here are only examples.
  • the first boundary code block may be the start code block of the first code group, and the end code block of the first code group may be the third boundary code block (ie, the end code block).
  • the second boundary code block may be the end code block of the second code group, and the start code block of the second code group may be the fourth boundary code block, etc. This application does not limit the start code block of the second code group .
  • the client signal shown below may be in the form of a message.
  • the MAC frame (that is, MAC frame) flow shown below may also be referred to as a message flow, etc., which is not limited in this application.
  • a code group may include a start code block, one or more data code blocks, and an end code block.
  • the start part of the code group is a start code block
  • the end part may be an end code block, or the end part may be other control code blocks and the like.
  • FIG. 5b is a schematic structural diagram of a code group shown in this application.
  • the code group may include a start code block and an end code block, and 33 data code blocks. Since the end code block shown in Figure 5b is 0xFF, the 0th control byte (D0 byte in Figure 5a) to the 6th control byte (D6 byte in Figure 5a) of the end code block is Can be used to carry data. Thus, the load portion shown in FIG. 5b can carry 33 data code blocks.
  • the code group may include a start code block and an end code block, and also include one or more 64B/65B data code blocks encoded according to the 64B/66B data code blocks. It can be understood that the 64B/65B data block is included in the payload portion of the block. In other words, the 64B/65B data code block included in the load part of the code group can be obtained by removing the 1-bit synchronization header from the 64B/66B data code block. As for removing the 0th bit or the 1st bit of the 64B/66B data code block, this application does not limit it.
  • FIG. 5c is a schematic structural diagram of another code group shown in this application.
  • the first row (that is, corresponding to the start code block in Figure 5a) is the start code block in the code group
  • the 197th row (that is, corresponding to the end code block in Figure 5a) is the code block in the code group.
  • the end code block, the 198th line is the other control code blocks located after the end code block in the code block (the 198th line is not shown in Fig. 5c).
  • the first 7 bytes of line 2 are used to carry overhead (OH) information.
  • From the 8th byte of the second row to the 196th row is the 64B/65B data code block, which is used to carry data information.
  • the load part of the code group can be encoded according to 195 data code blocks.
  • the length of the code group may be a preset length, for example, the length of a data code block in a code group may be 1560 bytes.
  • a 64B/66B code block stream is formed, and the 64B/66B code block stream is 64B/65B compressed (remove the 1-bit synchronization header) Then, a 64B/65B code block stream is formed.
  • the 64B/65B code block stream may be mapped into a first time slot according to a group of 8 64B/65B code blocks.
  • the present application shows that the first time slot may include 8 64B/65B. Therefore, in combination with the structure of the fgBU shown in FIG. 5c, one fgBU can carry 24 first time slots. And 20 fgBUs can form a complete multiplexing cycle, and a multiplexing cycle can include 480 time slots. In this application, since the first time slot can be used to carry one client signal, one fgBU can also carry up to 24 client signals.
  • code group shown in the present application may also be called a flexible granularity basic unit (finer granularity basic unit, fgBU), a code block set or a code block cluster, etc., the name of which is not limited in this application.
  • fgBU flexible granularity basic unit
  • lengths of the data code blocks included in the code group shown here are only examples, and in a specific implementation, the lengths of the data code blocks included in the code group may also be other values.
  • the description of the code group shown in this application is applicable to the first code group shown below, where the first code group starts with a first code block, and the first code block may be an S code block.
  • Bit pattern to be identified consists of part or all of the bits of one or more code blocks.
  • the to-be-identified bit pattern may be composed of at least two bits of the first code block.
  • the bit pattern to be identified includes a first bit pattern, where the first bit pattern is a bit pattern formed by the 0th bit to the 9th bit of the first code block.
  • the first bit pattern is a bit pattern formed by the 0th bit to the 65th bit of the first code block.
  • the to-be-identified bit pattern consists of at least two bits of the first code block and at least two bits of the second code block.
  • the bit pattern to be identified includes a first bit pattern and a second bit pattern
  • the second bit pattern may be a bit pattern formed by bits 0 to 9 of the second code block, and the like.
  • the to-be-identified bit pattern consists of at least two bits of the first code block and at least two bits of the third code block.
  • the bit pattern to be identified includes a first bit pattern and a third bit pattern
  • the third bit pattern may be a bit pattern formed by the 0th bit and the 1st bit of the third code block, and the like.
  • the bit pattern to be identified consists of at least two bits of the first code block, at least two bits of the second code block, and at least two bits of the third code block.
  • first bit pattern, the second bit pattern and the third bit pattern shown above are only examples, and in a specific implementation, the first bit pattern may also be the 0th bit to the 17th bit of the first code block Bit pattern composed of bits, etc.
  • the second bit pattern may also be a bit pattern formed by the 0th bit to the 65th bit of the second code block, etc., which is not limited in this embodiment of the present application.
  • the to-be-identified bit pattern can be obtained through a detection window, for example, the detection window can be used to detect whether the first code block is the first boundary code block.
  • Template bit pattern the bit sequence expected to appear when judging whether the first code block is the first boundary code block.
  • the template bit pattern can be understood as: when used to determine whether the first code block is the first boundary code block, the order of bits appearing in the expected detection window.
  • the template bit pattern includes a first template bit pattern, and the first template bit pattern is used to identify the first bit pattern.
  • the position of the first template bit pattern in the template bit pattern is in a one-to-one correspondence with the position of the first bit pattern in the to-be-identified bit pattern.
  • Fig. 8a For the correspondence between the to-be-identified bit pattern and the template bit pattern, reference may also be made to the description of Fig. 8a shown below.
  • the first template bit pattern may be the template bit pattern corresponding to the start code block
  • the second template bit pattern may be the template bit pattern corresponding to the end code block.
  • first template bit pattern and the second template bit pattern reference may be made to the various embodiments shown below.
  • the first template bit pattern may also be the template bit pattern corresponding to the end code block
  • the second template bit pattern may be the template bit pattern corresponding to the data code block
  • the third template bit pattern may be corresponding to the start code block.
  • Template bit pattern may also be a template bit pattern corresponding to any one of an idle code block, an error code block, or an O code block, or the like.
  • the communication apparatus can identify whether the first code block is the end code block by using the second code block before the first code block or the third code block after the first code block. In this case, the first boundary code block is the end code block.
  • the first template bit pattern is the template bit pattern corresponding to the end code block
  • the second template bit pattern is the template bit pattern corresponding to the data code block
  • the third template bit pattern is the start code block, idle code block, and error code.
  • the first template bit pattern shown below can be referred to as the template bit pattern corresponding to the start code block
  • the second template bit pattern is the end code block
  • the third template bit pattern is a specific description of the template bit pattern corresponding to the data code block, which will not be described in detail below.
  • bit pattern (bit pattern) shown in this application may also be called a bit pattern, bit string (bit string), bit sequence (bit sequence (bit sequence) or bit bit pattern, etc., and this application does not limit its name.
  • the template bit pattern (bit pattern) shown in this application may also be referred to as a preset bit pattern, or a preset template, or a preset template, etc., and this application does not limit its name.
  • the to-be-identified bit pattern shown in this application may also be called a to-be-verified bit pattern, or a target bit pattern, etc., and this application does not limit its name.
  • the template bit pattern includes a first template bit pattern
  • the first template bit pattern may be a template bit pattern corresponding to the first boundary code block.
  • the first boundary code block may be an S code block.
  • the first template bit pattern may include template bit patterns corresponding to the 0th bit to the 9th bit of the S code block. That is, the first template bit pattern consists of the synchronization header of the S code block and the control block type field.
  • the first template bit pattern may also include the 0th bit to the 9th bit of the S code block, and the first control byte (such as the D1 byte in FIG. 5a) to the seventh control word.
  • the template bit pattern corresponding to any byte in the section (such as the D7 byte in Figure 5a).
  • the first template bit pattern may be composed of the 0th bit to the 65th bit of the S code block.
  • the first template bit pattern may further include template bit patterns corresponding to the second bit to the ninth bit of the S code block.
  • the first template bit pattern may also be constituted by the control block type field of the S code block, and so on.
  • the template bit pattern includes a first template bit pattern and a second template bit pattern.
  • the second template bit pattern may be a template bit pattern corresponding to any of the following code blocks: a second boundary code block (such as a T7 code block), an idle (idle) code block, a sequence (sequence ordered set, O) code block, a signal (signal ordered set, O) code block, error (error) code block.
  • a second boundary code block such as a T7 code block
  • an idle (idle) code block such as a T7 code block
  • a sequence ordered set, O code block
  • signal signal ordered set, O
  • error error
  • the template bit pattern may include bits 0 to 9 of the T code block, and bits corresponding to the 0th to 9th bits of the S code block.
  • Template bit pattern can be composed of the synchronization header and the control block type field of the T code block, and the synchronization header and the control block type field of the S code block.
  • the first template bit pattern may also include any one of the synchronization header of the S code block or the control block type field
  • the second template bit pattern may also include the synchronization header of the T code block or any of the control block type fields. any of the components, etc. Therefore, the template bit pattern may include the control block type field of the T code block, and the template bit pattern corresponding to the synchronization header and the control block type field of the S code block.
  • the template bit pattern may include the control block type field of the T code block and the template bit pattern corresponding to the control block type field of the S code block.
  • the template bit pattern may include the synchronization header and the control block type field of the T code block, and the template bit pattern corresponding to the control block type field of the S code block.
  • the template bit pattern may include the synchronization header of the T code block, and the template bit pattern corresponding to the synchronization header of the S code block and the control block type field.
  • the template bit pattern may include template bit patterns corresponding to the synchronization header of the T code block and the synchronization header of the S code block. It can be understood that for this description, other code blocks shown below are also applicable, and will not be described in detail below.
  • the template bit pattern may include the synchronization header and block type field of the O code block, and the template bit pattern corresponding to the synchronization header and block type field of the S code block.
  • the template bit pattern may include the synchronization header and block type field of the idle code block, and the template bit pattern corresponding to the synchronization header and block type field of the S code block.
  • the template bit pattern shown in (3) in FIG. 7a can also be understood as the synchronization header and block type field of the error code block, and the template bit pattern corresponding to the synchronization header and block type field of the S code block.
  • the first template bit pattern shown in this application may also be composed of the synchronization header of the S code block, the control block type field of the S code block, and the control bytes of the S code block.
  • the values of the 0th byte to the 7th byte of the error code block are respectively 0x1E.
  • the values of the 0th byte to the 7th byte of the idle code block are 0x00 respectively. Therefore, the second template bit pattern shown in this application may also include control bytes of error code blocks or idle code blocks, and the like.
  • the template bit pattern includes a first template bit pattern and a third template bit pattern.
  • the third template bit pattern may be a template bit pattern corresponding to the data code block.
  • the template bit pattern may include the synchronization header and the block type field of the S code block, and the template bit pattern corresponding to the synchronization header of the data code block.
  • the template bit pattern may include the synchronization header and block type field of the S code block, and the synchronization header of the data code block and the template bit pattern corresponding to the first byte.
  • 0x89 shown in FIG. 7b is the value of the first byte used to carry the overhead information shown in FIG. 5b or FIG. 5c.
  • the 0x89 may also be other values, etc., which is not limited in this embodiment of the present application.
  • the 0xAA shown in FIG. 7b may be understood as the value of the second byte used to carry the overhead information, and the 0xAA may also be other values, which are not limited in this embodiment of the present application.
  • the template bit pattern may include the synchronization header and block type field of the S code block, and the synchronization header, the first byte and the second byte of the data code block.
  • the corresponding template bit pattern may include the synchronization header and block type field of the S code block, and the synchronization header, the first byte and the second byte of the data code block.
  • the template bit pattern may further include a synchronization header and a block type field of the S code block, and a template bit pattern corresponding to the synchronization header of the data code block.
  • the template bit pattern includes a first template bit pattern, a second template bit pattern and a third template bit pattern.
  • the template bit pattern includes the synchronization header and block type field of the T code block, the synchronization header and the block type field of the S code block, and the corresponding synchronization header of the data code block. Template bit pattern.
  • the template bit pattern includes the synchronization header and block type field of the O code block, the synchronization header and block type field of the S code block, and the synchronization header of the data code block corresponding to Template bit pattern.
  • the template bit pattern includes the synchronization header and block type fields of the idle code block (or error code block), the synchronization header and block type fields of the S code block, and the data code block.
  • the template bit pattern corresponding to the sync header of .
  • the template bit pattern shown in this application is only an example, and in a specific implementation, the template bit pattern may also have more expressions, which is not limited in this application.
  • the comparison result between the template bit pattern and the to-be-identified bit pattern (ie, the number of inconsistent bits) will be described below with reference to FIG. 8a.
  • the embodiment of the present application takes the 0th bit to the ninth bit of the first code block as an example, which should not be construed as a limitation on the embodiment of the present application.
  • the bit pattern to be identified is the template bit pattern corresponding to the 0th bit to the 65th bit of the first code block
  • the bit pattern to be identified can be compared with the template bit pattern shown in FIG. 6b, etc., I won't go into details here.
  • the 0th bit and the 1st bit of the first code block are 01, and the 2nd to 9th bits of the first code block are 0x78, by comparing with the template bit pattern, it can be obtained:
  • the number of inconsistent bits is 1.
  • the structure of the template bit pattern shown above is only an example, and the structure of the template bit pattern may also be other structures, which are not limited in this application.
  • the template bit pattern shown in (1) in FIG. 8b is the structure shown above. In this case, the structure of the bit pattern to be identified may be as shown in (1) in FIG. 8c.
  • the template bit pattern shown in (2) in FIG. 8b is another structure of the template bit pattern shown in this application. In this case, the structure of the bit pattern to be identified may be as shown in (2) in FIG. 8c.
  • the first bit pattern in the bit pattern to be identified corresponds to the first template bit pattern
  • the second bit pattern corresponds to the second template bit pattern
  • the third bit pattern corresponds to the second template bit pattern.
  • the first bit pattern shown in this application corresponds to the first template bit pattern, which means that the 0th bit of the first code block corresponds to the 0th bit of the first template bit pattern, and the The first bit corresponds to the first bit of the first template bit pattern, the second bit of the first code block corresponds to the second bit of the second template bit pattern, and so on.
  • the 0th bit and the 1st bit of the first bit pattern are respectively 10, then the 10 can be combined with the 0th bit and the 0th bit in the first template bit pattern.
  • the first bit is 10 for comparison.
  • the 2nd to 9th bits of the first bit pattern are 0x79, and the binary is 0111 1001, then the 2nd to 9th bits, that is, 0111 1001, need to be the same as the 2nd bit in the first template bit pattern. 0111 1000 comparison to the 9th bit.
  • the first channel (also referred to as a flexible small particle channel or a low-order channel, etc.) provided in this application can transparently transmit the MTN network.
  • the first channel is mapped to the second channel (also referred to as a large particle channel or a high-order channel or an MTN channel, etc.) by means of time slot multiplexing. Since the second channel is based on the Ethernet physical port, the speed of the second channel at any two nodes has a rate difference of +/-100ppm. Therefore, in order to enable the first channel to be transparently transmitted to the second channel, the code group shown in this application needs to be format encapsulated, so that the first channel can reuse the rate adaptation method of the second channel.
  • the present application provides a code group, and the code group may include an S code block, a plurality of D code blocks and a T code block. It can be understood that, for the specific description of the code group, reference may be made to the above description, which will not be described in detail here.
  • each fgBU is first identified from the fgBU sequence stream, and then the first time slot corresponding to each fgBU is extracted.
  • the process of identifying the S code block at the same time may also be called fgBU framing. If an abnormality occurs during the framing process, the multiple first time slots corresponding to the fgBU (such as the 24 first time slots shown above) cannot be extracted, causing the fgBUs to be discarded, and causing the fgBUs to include many
  • Each D code block is marked as an error code block. Furthermore, multiple time slots or multiple client signals corresponding to the fgBU cannot be received correctly, resulting in poor system fault tolerance.
  • the present application provides a code block identification method and apparatus, which can improve the situation that the S code block cannot be identified due to occasional code errors. As well as improving the situation where the entire code group is discarded because the S code block cannot be identified due to occasional bit errors. Meanwhile, the method provided by the present application can also effectively improve the fault tolerance of the system.
  • the code block identification method provided by the present application can be applied to a communication device, and the communication device can be a wired device, a switch, a router, a network card, a packet transport network (PTN), (agile transport network, ATN), a sliced packet network (slicing packet network, SPN), etc., the present application does not limit the specific form of the communication device.
  • the communication apparatus may include a receiving end for receiving a code block stream; or, the communication apparatus may also be understood as a receiving end for receiving a code group, or the like.
  • FIG. 9 is a schematic flowchart of a code block identification method provided by an embodiment of the present application. As shown in FIG. 9 , the method includes:
  • a communication device may receive a stream of code blocks and then obtain a first code block from the stream of code blocks.
  • the communication device shown here obtains the code block stream, which can be understood as: the communication device receives the code block stream from the physical layer; or the communication device obtains the code block stream from other devices; or the communication device obtains the code block stream from the MTN
  • the segment layer or the MTN channel layer obtains the code block stream, etc. This embodiment of the present application does not limit how the communication apparatus acquires the code block stream.
  • the communication apparatus may obtain the first code block from the received code block stream, and then obtain the 0th bit to the ninth bit of the first code block from the first code block, and so on, the first code block.
  • the 0th to 9th bits of the code block are the bit patterns to be verified.
  • the communication device may receive the code block stream at the MTN segment layer, and then determine the bit pattern to be identified at the MTN channel layer.
  • the communication device may receive the code block stream through the transceiver, and then determine the to-be-identified bit pattern and the like at the MTN segment layer, which is not limited in this embodiment of the present application.
  • the communication apparatus may determine the to-be-identified bit pattern when receiving the code block stream.
  • the communication apparatus may determine the bit pattern to be identified.
  • the communication device can execute the method shown in FIG. 9 , and after the communication device identifies the first boundary code block from the code block stream, it can obtain a code block stream starting with the first boundary code block. For example, after identifying the S code block from the code block stream, the communication device can obtain a plurality of D code blocks following the S code block, and then obtain a client signal and the like.
  • the communication apparatus can obtain a plurality of client signals corresponding to the first time slots from the first code group.
  • One first time slot may correspond to one client signal, or multiple first time slots may correspond to one client signal. It can be understood that, for the specific description of the code group, reference may be made to FIG. 5 a to FIG. 5 d , which will not be described in detail here.
  • the method shown in FIG. 9 is not only applicable to the scenario where the communication device needs to demultiplex the first channel from the second channel, that is, the scenario where the communication device needs to identify each fgBU from the fgBU sequence stream;
  • the scenarios in which the S code block is identified from the 64B/66B code block stream, etc., are not limited to the scenarios to which the methods provided in the embodiments of the present application are applicable.
  • the template bit pattern includes a first template bit pattern
  • the first template bit pattern is a template bit pattern corresponding to the first boundary code block.
  • the first template bit pattern corresponds to the first bit pattern, that is, the position of the first template bit pattern in the template bit pattern corresponds to the position of the first bit pattern in the to-be-identified bit pattern.
  • the first template bit pattern can be used to identify the first bit pattern.
  • the template bit pattern may include a first template bit pattern, and may also include a second template bit pattern and/or a third template bit pattern. Exemplarily, reference may be made to FIG. 6a, FIG. 6b, FIG. 7a to FIG. 7c, etc. for the template bit pattern.
  • FIG. 6a, FIG. 6b, FIG. 7a to FIG. 7c, etc. for the template bit pattern.
  • the code block stream further includes a second code block
  • the bit pattern to be identified further includes a second bit pattern
  • the second bit pattern is a bit pattern corresponding to the second code block.
  • the second template bit pattern corresponds to the second bit pattern, that is, the second template bit pattern can be used to identify the second bit pattern.
  • the code block stream further includes a third code block
  • the bit pattern to be identified further includes a third bit pattern
  • the third bit pattern is a bit pattern corresponding to the third code block.
  • the third template bit pattern corresponds to the third bit pattern, that is, the third template bit pattern can be used to identify the third bit pattern.
  • the first threshold may be 1, that is, when the number of inconsistent bits is less than or equal to 1 bit, the communication device may identify (or determine) that the first code block is the first boundary code block (eg, S code block).
  • the first threshold may be 2, that is, when the number of inconsistent bits is less than or equal to 2 bits, the communication apparatus may determine that the first code block is the first boundary code block.
  • the first threshold may also take other values, etc., which is not limited in this embodiment of the present application.
  • step 904 may include: in the case that the number of bits that are inconsistent between the bit pattern to be identified and the template bit pattern is greater than or equal to 1, and the number of inconsistent bits is less than or equal to the first threshold, identifying the first code block as the first code block. A boundary code block.
  • the bit pattern to be identified and the template bit pattern may have inconsistent bit numbers, and the inconsistent bit number is less than or equal to the first threshold.
  • the communication device can still identify The first code block is the first boundary code block.
  • step 904 may include: in the case that the first template bit pattern is inconsistent with the first bit pattern, and the number of inconsistent bits between the bit pattern to be identified and the template bit pattern is less than or equal to a first threshold, identifying the first code
  • the block is the first boundary code block.
  • the fact that the first template bit pattern is inconsistent with the first bit pattern means that the values of the first template bit pattern and the first bit pattern at corresponding positions are not completely consistent. In other words, even if the first template bit pattern is not completely consistent with the first bit pattern, it can be determined that the first code block is an S code block.
  • the synchronization header of each code block has a 2-bit Hamming distance protection, and two-bit errors occur continuously, such as 01 jumping to 10, the probability is small; on the other hand, there are 4 bits between the control block type fields For the Hamming distance protection, a one-bit or two-bit error in the 8 bits in the control block type field will not cause the S code block to be misidentified as other control code blocks, such as O code blocks or T code blocks. Therefore, in this embodiment of the present application, even if the values of the first bit pattern and the first template bit pattern at corresponding positions are not completely consistent, the first code block can also be identified as an S code block. It can be understood that the description of the Hamming distance protection of the synchronization header and the control block type field is applicable to the first code block, the second code block or the third code block, etc. shown in this application.
  • step 904 may further include: in the case that the first template bit pattern is consistent with the first bit pattern, and the number of inconsistent bits between the bit pattern to be identified and the template bit pattern is less than or equal to the first threshold, identifying the first template bit pattern.
  • the code block is the first boundary code block. That is to say, when the first template bit pattern is consistent with the first bit pattern, but the second bit pattern is inconsistent with the second template bit pattern, but the number of inconsistent bits is less than or equal to the first threshold, the communication device can still The first code block is identified as the first boundary code block. Exemplarily, if the synchronization header of the second code block is 0b10, 0b00 or 0b11, it means that there may be occasional bit errors in the synchronization header of the second code block. Therefore, the first code block can still be identified as the first boundary code. piece.
  • step 904 may further include: determining a second bit pattern, and comparing the second bit pattern with the second template bit pattern; when the number of inconsistent bits between the to-be-identified bit pattern and the template bit pattern is less than or equal to the first threshold, and In a case where the number of bits that do not match between the second bit pattern and the second template bit pattern is less than or equal to the second threshold, the first code block is identified as the first boundary code block.
  • the second threshold may be less than or equal to the first threshold.
  • the second threshold may be 1 or the like, which is not limited in this embodiment of the present application.
  • the communication device may also compare the second bit pattern with the second template bit pattern, so that when the number of inconsistent bits between the to-be-identified bit pattern and the template bit pattern is less than or equal to the first threshold, and in this In a case where the number of bits that do not match between the second bit pattern and the second template bit pattern is less than or equal to the second threshold, the first code block is identified as the first boundary code block.
  • the communication device may compare the to-be-identified bit pattern (eg, the first bit pattern) with the template bit pattern (eg, the first template bit pattern), and the second bit pattern with the second template bit pattern.
  • the first code block is identified as the first boundary code block. It should be noted that the number of bits that are inconsistent between the second bit pattern and the second template bit pattern is not included in the above-mentioned first threshold.
  • step 904 may further include: determining a second bit pattern, comparing the second bit pattern and the second template bit pattern; when the number of inconsistent bits between the to-be-identified bit pattern and the template bit pattern is less than or equal to the first threshold and if the second bit pattern matches the second template bit pattern, the first code block is identified as the first boundary code block.
  • the method provided by the embodiments of the present application can effectively improve the determination that the first code block is not the first boundary code block when the number of bits inconsistent between the first code block and the first boundary code block (such as the S code block) is not 0 bits.
  • the first boundary code block such as the S code block
  • the communication device can demultiplex a plurality of first time slots corresponding to the code group starting with the S code block, so as to obtain the client signals corresponding to the plurality of first time slots. It is simple and can effectively ensure the reliability of the code group being identified.
  • FIG. 10a is a schematic flowchart of a code block identification method provided by an embodiment of the present application. As shown in Figure 10a, the method includes:
  • the sender obtains a client signal (client).
  • Step 1001 may include: the sending end receives the client signal from the panel-side interface; or, the sending end generates the client signal, and so on.
  • the panel-side interface shown here can be understood as a user-side interface (user network interface, UNI) or the like.
  • the sender performs service mapping and encapsulation on the client signal to obtain an fgBU sequence stream.
  • the transmitting end after acquiring the client signal, can form an fgBU with a preset length through the MTN fg adaptation layer. Then the sender can map the fgBU to the first channel at the MTN fg termination layer.
  • the sending end maps the fgBU sequence stream to the second channel.
  • the fgBU sequence flow shown here refers to the fgBU transmitted by the sender before being mapped to the second channel.
  • the sending end may map the fgBU sequence flow to the second channel at the MTN channel layer.
  • the transmitting end may multiplex one or more first time slots divided by the second channel at the MTN channel adaptation layer, that is, the first channel may include one or more first time slots.
  • the method shown in FIG. 10a will be described below by taking the first channel including M first time slots as an example.
  • the transmitting end maps the second channel to one or more second time slots.
  • the transmitting end may map the second channel to one or more second time slots at the MTN segment layer.
  • the transmitting end may map the second channel to one or more second time slots at the MTN segment layer adaptation layer, thereby multiplexing the bundling group.
  • the sender needs to interleave the service streams of each MAC (ie, in the form of 64B/66B code blocks) to form a 64B/66B code block stream.
  • the transmitting end may map each code block in the second channel to one or more second time slots.
  • the transmitting end sends a 64B/66B code block stream.
  • the 64B/66B code block stream may enter the physical layer through the MTN segment layer termination layer, the adaptation layer, etc. for transmission.
  • the receiving end receives the 64B/66B code block stream.
  • the receiving end may obtain the 64B/66B code block stream from the physical layer.
  • the receiving end demultiplexes the second channel from the N second time slots in the bundling group, and obtains the fgBU code block stream in the N second time slots.
  • the fgBU code block stream shown here refers to the form of the 64B/66B code block that is still received by the receiving end.
  • the receiving end identifies the S code block.
  • the receiving end decapsulates the fgBU.
  • the receiving end After identifying the S code block from the code block stream, the receiving end can identify the fgBU starting with the S code block according to the S code block. Exemplarily, the receiving end can obtain 195 data code blocks and one T code block in the fgBU. Exemplarily, after recognizing the S code block, the receiving end may demultiplex the first channel from the M first time slots in the second channel at the MTN channel layer, so as to obtain the fgBU starting with the S code block.
  • the receiving end shown here demultiplexes the first channel from the M first time slots in the second channel, which can also be understood as: the receiving end recovers the first time slot from the M first time slots of the second channel. a channel to obtain the fgBU in the first channel.
  • the receiving end extracts the client signal.
  • the client signal corresponding to each time slot in the M first time slots can be obtained.
  • the receiving end may also perform operations such as forwarding or terminating the service flow, which is not limited in this embodiment of the present application.
  • the receiving end identifying the S code block can be understood as being executed by the processor of the receiving end, or, it can also be understood as being implemented in the MTN channel adaptation layer in the MTN network of the receiving end (only an example), or, It may also be understood that it is executed by a function, module, or unit in the receiving end, etc., which is not limited in this embodiment of the present application.
  • the functional module for identifying the S-code block at the receiving end may include: a template matching module, a template storage module, and a verification window module.
  • the template storage module stores the template required to identify the first code block as the S code block. That is, the template storage module is used to store the template bit patterns shown in the embodiments of the present application.
  • the check window module can be used to extract corresponding bits from the first code block, the second code block or the third code block to form a to-be-identified bit pattern.
  • the template matching module is used for comparing the bit pattern (ie the bit pattern to be identified) in the inspection window with the template bit pattern.
  • the receiving end can identify the first code block that meets the expectation of the comparison result as the S code block. With the determination of the S code block, the receiving end can complete the fgBU framing. Thus, the time slot data and the like encapsulated by the fgBU are acquired according to the starting position of the fgBU.
  • each module shown in FIG. 10b is only an example, which is not limited in this embodiment of the present application.
  • the second code block and the third code block may be code blocks adjacent to the first code block, respectively. Therefore, for ease of description, the following will take the first code block as the i-th code block, the second code block as the i-1-th code block, and the third code block as the i+1-th code block as examples to illustrate the embodiments of the present application. Provides the code block identification method.
  • FIG. 11 is a schematic flowchart of a code block identification method provided by an embodiment of the present application. As shown in FIG. 11 , the method includes:
  • the receiving end recovers the code block stream from the N 5 Gbps.
  • the receiving end acquires the i-th code block from the code block stream.
  • the receiving end may acquire a code block (ie, the i-th code block) from the code block stream at a fixed period.
  • the receiving end may acquire the i-th code block from the code block stream according to the preset length of the code group. For example, when the code group includes 197 code blocks, the receiving end may obtain one code block (ie, the i-th code block) every 197 code blocks according to the length of the code group.
  • the receiving end may also obtain the i-th code block from the code block stream according to the synchronization header of the known code block. For example, if the receiving end has already learned that the synchronization header of a certain code block is 0b10, the certain code block can be the i-th code block. It is known that the previous code block or the next code block of the certain code block may also be the i-th code block or the like.
  • the receiving end shown above obtains the i th code block from the code block stream, which can also be understood as: the receiving end starts to identify the i code block; or, the receiving end searches for the i th code block from the code block stream. Wait.
  • the embodiment of the present application does not limit the manner in which the receiving end obtains the i-th code block.
  • the receiving end determines whether the synchronization header of the i-th code block is 0b10, and if so, executes step 1105; otherwise, executes step 1104.
  • the receiving end determines that the ith code block is not an S code block, that is, the ith code block cannot be identified as an S code block.
  • the receiving end can stop searching for the code block.
  • the receiving end may also start searching for the next code block, etc., which is not limited in this embodiment of the present application.
  • the receiving end obtains the second to ninth bits of the i-th code block, and obtains the bit pattern to be identified.
  • the receiving end can obtain the second to ninth bits of the i-th code block through the detection window module.
  • the receiving end compares the to-be-identified bit pattern with the template bit pattern to obtain inconsistent bit numbers. And it is judged whether the number of inconsistent bits is less than or equal to K bits, if yes, go to step 1107; otherwise, go to step 1108.
  • the receiving end may compare the bit pattern to be identified with the template bit pattern at corresponding positions.
  • the template bit pattern may be the bit pattern of the S code block.
  • the template bit pattern may be the template bit pattern corresponding to the 2nd bit to the 9th bit of the S code block.
  • the template bit pattern may also be a template bit pattern corresponding to the 0th bit to the 65th bit of the S code block.
  • the receiving end needs to compare the 2nd to 9th bits of the i-th code block with the 2nd to 9th bits of the S code block in order. Bit to 9th bit comparison. It can be understood that, for the description of the template bit pattern, the various embodiments shown below are also applicable.
  • the receiving end may also acquire more bits of the i-th code block, such as acquiring the 2nd to 65th bits of the i-th code block; or, acquire the second bit of the i-th code block to the 17th bit.
  • the receiving end may also not perform the foregoing step 1103, but directly obtain the 0th to 9th bits of the i-th code block, etc., which is not limited in this embodiment of the present application.
  • the number of inconsistent bits is greater than K bits, and the receiving end determines that the i th block cannot be identified as an S code block.
  • the receiving end obtains the i-th code block, and identifies the S-code block for the i-th code block. Therefore, even if the bit pattern of the ith code block is not completely consistent with the bit pattern of the S code block, as long as the number of bits that are inconsistent between the bit pattern to be identified and the template bit pattern at the corresponding position is less than or equal to K bits, the ith code block is still Can be identified as an S-code block.
  • the method is not only convenient and simple to implement, but also effectively improves the fault tolerance of the system.
  • Fig. 12a is a schematic flowchart of a code block identification method provided by an embodiment of the present application. As shown in Fig. 12a, the code block identification method includes:
  • the receiving end recovers the code block stream from the N 5 Gbps.
  • the receiving end obtains the i th code block and the i-1 th code block from the code block stream.
  • the receiving end may obtain two adjacent code blocks from the code block stream, where the adjacent two code blocks are the i-1 th code block and the i th code block, respectively.
  • the receiving end may obtain a code block, that is, the ith code block, from the code block stream. Then, the previous code block of the ith code block, that is, the i-1 th code block, is obtained.
  • the receiving end may also acquire the i th code block and the i-1 th code block according to the code block that has been identified as not the S code block.
  • reference may be made to the method shown in FIG. 12b , for example, for this implementation, reference may be made to step 1213 in FIG. 12b and so on.
  • the receiving end determines the to-be-identified bit pattern according to the first P bits of the i th code block and the first Q bits of the i-1 th code block.
  • the receiving end may acquire the first P bits of the i-th code block and the first Q bits of the i-1-th code block.
  • the receiving end may have identified the i-1 th code block.
  • the receiving end has obtained the bit pattern of the i-1 th code block.
  • the receiving end can obtain the first P bits of the i-th code block. Therefore, according to the first P bits of the i-th code block and the first Q bits of the i-1-th code block, a to-be-identified bit pattern is formed.
  • the P is an integer greater than or equal to 2
  • the Q is an integer greater than or equal to 2.
  • the 0th to 9th bits in the to-be-identified bit pattern may be the first 10 bits of the i-1th code block in sequence, and the 10th to 19th bits in the to-be-identified bit pattern The bits may be sequentially the first 10 bits of the i-th code block.
  • the receiving end compares the to-be-identified bit pattern with the template bit pattern to obtain inconsistent bit numbers. And it is judged whether the number of inconsistent bits is less than or equal to K bits, if yes, go to step 1205; otherwise, go to step 1206.
  • the template bit pattern may be as shown in FIG. 7a.
  • the number of inconsistent bits is greater than K bits, and the receiving end determines that the ith block cannot be identified as an S code block.
  • the method provided by the embodiment of the present application can further improve the fault tolerance of the system.
  • the receiving end recovers the code block stream from the N 5Gbps.
  • the receiving end acquires the i-th code block from the code block stream.
  • the receiving end determines whether the synchronization header of the i-th code block is 0b10, and if so, executes step 1215; otherwise, executes step 1214.
  • the receiving end determines that the ith code block is not an S code block, that is, the ith code block cannot be identified as an S code block.
  • the receiving end may also save at least two bits of the ith code block.
  • the receiving end may save the synchronization header of the i-th code block.
  • the receiving end may also store the 0th bit to the 9th bit of the i-th code block.
  • the receiving end may also store the 0th bit to the 66th bit of the i-th code block, and so on.
  • beneficial information can also be provided for the receiving end to subsequently identify the i+1-th code block and the like. It can be understood that, with regard to the description of saving the i-th code block, other embodiments shown in this application are also applicable.
  • the receiving end obtains the second to ninth bits of the i-th code block, and obtains the bit pattern to be identified.
  • the receiving end compares the to-be-identified bit pattern with the template bit pattern to obtain inconsistent bit numbers. And it is judged whether the number of inconsistent bits is less than or equal to K bits, if yes, go to step 1217; otherwise, go to step 1218.
  • the template bit pattern may be as shown in FIG. 6a or 6b.
  • the receiving end obtains the 0th bit and the 1st bit of the i-1th code block.
  • the receiving end may also acquire the 0th bit to the 9th bit of the i-1th code block, etc., which is not limited in this embodiment of the present application.
  • the receiving end determines that the ith code block is not the S code block.
  • the synchronization header of the i-1 th code block when the synchronization header of the i-1 th code block is 0b01, it means that the i-1 th code block is a data code block, and the first code block cannot be an S code block.
  • the i-1 th code block is not a data code block, for example, the i-1 th code block is an error code block, a T code block, or an O code block, etc., it means that the ith code block can be an S code block.
  • step 1217 and step 1216 or step 1215 and the like may also perform step 1215 and step 1217 at the same time, which is not limited in this embodiment of the present application.
  • the receiving end determines that the ith code block is the S code block.
  • the receiving end determines that the ith code block is not the S code block.
  • the receiving end may also store the second to ninth bits of the i-1th code block, or the second to ninth bits of the i-th code block, and so on.
  • the receiving end can determine whether the i-th code block can be identified as an S-code block by comparing the bit pattern of the i-th code block with the template bit pattern. Further, by judging whether the i-1 th code block is a control code block, the accuracy and reliability of the i th code block being identified as the S code block can be further improved, and the fault tolerance of the system can also be ensured.
  • FIG. 13 is a schematic flowchart of a code block identification method provided by an embodiment of the present application. As shown in FIG. 13 , the method includes:
  • the receiving end recovers the code block stream from the N 5 Gbps.
  • the receiving end obtains the i-th code block and the i+1-th code block from the code block stream.
  • step 1202 for the specific description of acquiring the i-th code block and the i+1-th code block by the receiving end, reference may be made to the description of step 1202 shown above, which will not be described in detail here.
  • the receiving end determines the to-be-identified bit pattern according to the first P bits of the i-th code block and the first Q bits of the i+1-th code block.
  • the receiving end compares the to-be-identified bit pattern with the template bit pattern to obtain inconsistent bit numbers. And it is judged whether the number of inconsistent bits is less than or equal to K bits, if so, go to step 1305; otherwise, go to step 1306.
  • the template bit pattern may be as shown in FIG. 7b.
  • the number of inconsistent bits is greater than K bits, and the receiving end determines that the i th block cannot be identified as an S code block.
  • FIG. 13 It can be understood that, for the specific description of FIG. 13 , reference may be made to the description in FIG. 11 , FIG. 12 a or FIG. 12 b , etc., which will not be described in detail here.
  • FIG. 14 is a schematic flowchart of a code block identification method provided by an embodiment of the present application. As shown in FIG. 14 , the method includes:
  • the receiving end recovers the code block stream from the N 5 Gbps.
  • the receiving end obtains the i-1 th code block, the i th code block, and the i+1 th code block from the code block stream.
  • step 1202 for the specific description of the receiving end acquiring the i-1 th code block, the i th code block and the i+1 th code block, reference may be made to the description of step 1202 and the like shown above, which will not be described in detail here.
  • the receiving end determines the to-be-identified bit pattern according to the first R bits of the -1 th code block, the first P bits of the i th code block, and the first Q bits of the i+1 th code block.
  • the receiving end compares the to-be-identified bit pattern with the template bit pattern to obtain inconsistent bit numbers. And it is judged whether the number of inconsistent bits is less than or equal to K bits, if yes, go to step 1405; otherwise, go to step 1406.
  • the template bit pattern may be as shown in FIG. 7c. It is understandable that P, Q, or R shown in the embodiments of the present application are only examples, and the specific values thereof are not limited in the embodiments of the present application.
  • the number of inconsistent bits is greater than K bits, and the receiving end determines that the i th block cannot be identified as an S code block.
  • the receiving end obtains the i-th code block and two code blocks adjacent to the i-th code block, so as to combine the template bit pattern to determine whether the i-th code block is an S code block, which effectively improves the The accuracy of judging that the ith code block is the S code block improves the fault tolerance of the system.
  • FIG. 15 is a schematic structural diagram of a communication device provided by an embodiment of the present application, and the communication device can be used to execute the method in the above-mentioned embodiment as shown in FIG. 9, FIG. 10a, FIG. 11, FIG. 12a, FIG. 12b, FIG. 13, or FIG. method shown.
  • the communication device may be a switch of any form (or referred to as a switch device, a switch chip, etc.), a router or a network card, etc., and the specific form of the communication device is not made in this embodiment of the present application.
  • the communication device includes: a processing unit 1501 and a transceiver unit 1502 .
  • a transceiver unit 1502 configured to obtain a code block stream, where the code block stream includes a first code block;
  • the processing unit 1501 is configured to determine the bit pattern to be identified, and compare the bit pattern to be identified with the template bit pattern to obtain inconsistent bit numbers; in the case that the inconsistent bit number is less than or equal to a first threshold, identify the first code
  • the block is the first boundary code block.
  • the processing unit 1501 is specifically configured to identify that the first code block is the first code block when the number of inconsistent bits is greater than or equal to 1, and the number of inconsistent bits is less than or equal to the first threshold Boundary code block.
  • the second threshold may be 2 or 1, etc., which is not limited in this embodiment of the present application.
  • the processing unit 1501 is specifically configured to, when the first bit pattern is inconsistent with the first template bit pattern, and the number of bits that are inconsistent between the to-be-identified bit pattern and the template bit pattern is less than or equal to the first threshold case, the first code block is identified as the first boundary code block.
  • the processing unit 1501 is specifically configured to determine a second bit pattern, where the second bit pattern is a bit pattern corresponding to the second code block; compare the second bit pattern with the second template bit pattern; When the number of inconsistent bits is less than or equal to the first threshold, and the number of inconsistent bits between the second bit pattern and the second template bit pattern is less than or equal to the second threshold, the first code block is identified as the first boundary code block.
  • the processing unit 1501 is specifically configured to determine the second bit pattern, and compare the second bit pattern with the second template bit pattern, if the number of bits inconsistent between the to-be-identified bit pattern and the template bit pattern is less than or is equal to the first threshold, and when the second bit pattern is inconsistent with the second template bit pattern, the first code block is identified as the first boundary code block.
  • the processing unit 1501 is specifically configured to determine the first code group from the code block stream according to the first code block, where the first code group starts with the first code block.
  • first bit pattern the second bit pattern, the third bit pattern, the to-be-identified bit pattern, the template bit pattern, the first code block, the second code block, the third code block, and the first boundary code block, etc.
  • the transceiver unit 1502 may be used to perform step 901 in FIG. 9
  • the processing unit 1501 may be used to perform steps 902 to 904 in FIG. 9 .
  • the transceiver unit 1502 can also be used to perform step 1006 in FIG. 10a, and the processing unit 1501 can also be used to perform steps 1007 to 1010 in FIG. 10a.
  • processing unit 1501 may also be configured to perform steps 1101 to 1108 in FIG. 11 .
  • each functional module or unit in each embodiment of the present application may be integrated in the A processor may also exist physically alone, or two or more modules or units may be integrated into one module or unit.
  • the above-mentioned integrated modules or units may be implemented in the form of hardware, or may be implemented in the form of software function modules.
  • the processing unit 1501 can be one or more processors
  • the transceiver unit 1502 can be a transceiver, or the transceiver unit 1502 can also be a sending unit and a receiving unit, and the sending unit can be a transmitter , the receiving unit may be a receiver, and the transmitting unit and the receiving unit are integrated into one device, such as a transceiver.
  • the processor and the transceiver may be coupled, etc., and the connection manner of the processor and the transceiver is not limited in the embodiment of the present application.
  • the communication device 160 includes one or more processors 1620 and a transceiver 1610 .
  • the processor 1620 and the transceiver 1610 may be configured to execute the above-mentioned method executed by the communication apparatus or the receiving end.
  • the transceiver 1610 may be configured to receive the code block stream
  • the processor 1620 may be configured to identify the first code block in the code block stream, and the like.
  • first bit pattern the second bit pattern, the third bit pattern, the to-be-identified bit pattern, the template bit pattern, the first code block, the second code block, the third code block, and the first boundary code block, etc.
  • transceiver and/or the processor reference may be made to the various embodiments shown in FIG. 15 , or, reference may also be made to FIG. 9 , FIG. 10 a , FIG. 11 , FIG. 13 or the method embodiments shown in FIG. 14 will not be described in detail here.
  • the transceiver may include a receiver for performing the function (or operation) of receiving and a transmitter for performing the function (or operation) of transmitting ). And transceivers are used to communicate with other devices/devices over the transmission medium.
  • the communication device 160 may further include one or more memories 1630 for storing program instructions and/or data.
  • Memory 1630 and processor 1620 are coupled.
  • the coupling in the embodiments of the present application is an indirect coupling or communication connection between devices, units or modules, which may be in electrical, mechanical or other forms, and is used for information exchange between devices, units or modules.
  • Processor 1620 may cooperate with memory 1630.
  • Processor 1620 may execute program instructions stored in memory 1630 .
  • at least one of the above-mentioned one or more memories may be included in the processor.
  • the specific connection medium between the transceiver 1610, the processor 1620, and the memory 1630 is not limited in the embodiments of the present application.
  • the memory 1630, the processor 1620, and the transceiver 1610 are connected through a bus 1640 in FIG. 16.
  • the bus is represented by a thick line in FIG. 16, and the connection between other components is only for schematic illustration. , is not limited.
  • the bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of presentation, only one thick line is shown in FIG. 16, but it does not mean that there is only one bus or one type of bus.
  • the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc.
  • a general purpose processor may be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in conjunction with the embodiments of the present application may be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor, or the like.
  • the memory may include, but is not limited to, a non-volatile memory such as a hard disk drive (HDD) or a solid-state drive (SSD), random access memory (RAM), Erasable programmable read-only memory (erasable programmable ROM, EPROM), read-only memory (read-only memory, ROM) or portable read-only memory (compact disc read-only memory, CD-ROM) and so on.
  • a memory is any storage medium that can be used to carry or store program codes in the form of instructions or data structures, and can be read and/or written by a computer (such as the communication devices shown in this application, etc.), but is not limited thereto.
  • the memory in this embodiment of the present application may also be a circuit or any other device capable of implementing a storage function, for storing program instructions and/or data.
  • the communication device shown in the embodiment of the present application may also have more components and the like than those shown in FIG. 16 , which is not limited in the embodiment of the present application.
  • the method performed by the processor and the transceiver shown above is only an example, and for the specific steps performed by the processor and the transceiver, reference may be made to the method described above.
  • the communication device shown in the embodiment of the present application may also have more components and the like than those shown in FIG. 16 , which is not limited in the embodiment of the present application.
  • the processing unit 1501 may be one or more A logic circuit
  • the transceiver unit 1502 may be an input/output interface, also called a communication interface, or an interface circuit, or an interface, and so on.
  • the transceiver unit 1502 may also be a sending unit and a receiving unit, the sending unit may be an output interface, and the receiving unit may be an input interface, the sending unit and the receiving unit are integrated into one unit, such as an input and output interface. As shown in FIG.
  • the communication device shown in FIG. 17 includes a logic circuit 1701 and an interface 1702 . That is, the above-mentioned processing unit 1501 can be implemented by the logic circuit 1701 , and the transceiver unit 1502 can be implemented by the interface 1702 .
  • the logic circuit 1701 may be a chip, a processing circuit, an integrated circuit, or a system on chip (SoC) chip, etc.
  • the interface 1702 may be a communication interface, an input-output interface, or the like.
  • the logic circuit and the interface may also be coupled to each other. The specific connection manner of the logic circuit and the interface is not limited in this embodiment of the present application.
  • the logic circuit and the interface may be used to perform the functions or operations performed by the above-mentioned communication apparatus or the receiving end.
  • the interface 1702 is used to input a code block stream, where the code block stream includes a first code block and the like.
  • the logic circuit 1701 is used to determine the to-be-identified bit pattern, and compare the to-be-identified bit pattern and the template bit pattern to obtain an inconsistent number of bits; when the inconsistent number of bits is less than or equal to a first threshold, identify the first code
  • the block is the first boundary code block.
  • first bit pattern the second bit pattern, the third bit pattern, the to-be-identified bit pattern, the template bit pattern, the first code block, the second code block, the third code block, and the first boundary code block, etc.
  • the present application also provides a computer program for implementing the operations and/or processing performed by the communication device or the receiving end in the method provided by the present application.
  • the present application also provides a computer-readable storage medium, where computer codes are stored in the computer-readable storage medium, and when the computer codes are executed on the computer, the computer executes the method performed by the communication device or the receiving end in the method provided by the present application. manipulation and/or processing.
  • the present application also provides a computer program product, the computer program product includes computer code or computer program, when the computer code or computer program runs on a computer, the operation performed by the communication device or the receiving end in the method provided by the present application is made. and/or processing is performed.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may also be electrical, mechanical or other forms of connection.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the technical effects of the solutions provided by the embodiments of the present application.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium.
  • a computer-readable storage medium includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned readable storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc. that can store program codes medium.

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Abstract

本申请公开了一种码块识别方法及装置，该方法包括：获取码块流，该码块流中包括第一码块；然后，确定待识别比特图样，以及对比该待识别比特图样与模板比特图样，获得不一致的比特数；在该不一致的比特数小于或等于第一阈值的情况下，识别第一码块是第一边界码块。其中，待识别比特图样包括第一比特图样，该第一比特图样为第一码块对应的比特图样；模板比特图样包括第一模板比特图样，该第一模板比特图样为第一边界码块对应的模板比特图样。本申请提供的方法，可以有效改善由于偶发误码导致开始码块无法被识别的情况。

Description

一种码块识别方法及装置
本申请要求于2020年11月30日提交中国专利局、申请号为202011381360.2、申请名称为“一种码块识别方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种码块识别方法及装置。
背景技术
一般的，发送端获取到客户信号之后，会将该客户信号以码块的形式发送出去。示例性的，该客户信号会以开始码块、数据码块以及结束码块的形式(也可以称为码块流)被发送出去。
接收端接收到该码块流之后，如果想要从该码块流中获取到客户信号，就需要从该码块流中识别出开始码块。
因此，如何识别S码块亟待解决。
发明内容
本申请提供一种码块识别方法及装置，可以有效改善由于偶发误码导致开始码块无法被识别的情况，提高了系统的容错性。
第一方面，本申请实施例提供一种码块识别方法，所述方法包括：获取码块流，所述码块流中包括第一码块；确定待识别比特图样，所述待识别比特图样包括第一比特图样，所述第一比特图样为所述第一码块对应的比特图样；对比所述待识别比特图样与模板比特图样，获得不一致的比特数，所述模板比特图样包括第一模板比特图样，所述第一模板比特图样为第一边界码块对应的模板比特图样；在所述不一致的比特数小于或等于第一阈值的情况下，识别所述第一码块是所述第一边界码块。
本申请实施例中，第一比特图样与第一模板比特图样对应，即第一比特图样在待识别比特图样中的位置对应于第一模板比特图样在模板比特图样中的位置。或者，也可以理解为：第一模板比特图样用于识别第一比特图样。同时，第一比特图样中的比特位置与第一模板比特图样中的比特位置对应。示例性的，第一比特图样中的第0个比特对应于第一模板比特图样中的第0个比特，第一比特图样中的第1个比特对应于第一模板比特图样中的第1个比特，第一比特图样中的第2个比特对应于第一模板比特图样中的第2个比特，以此类推。可理解，对于第一比特图样与第一模板比特图样的说明，同样适用于本申请示出的第二比特图样与第二模板比特图样，第三比特图样与第三模板比特图样，下文不再详述。
本申请实施例提供的方法，可以有效改善第一码块与第一边界码块(如S码块)不一致的比特数不为0比特时，确定第一码块不为第一边界码块的情况。从而，改善了由于偶发误码导致第一码块无法被识别为第一边界码块的情况，提高了系统的容错性。
在一种可能的实现方式中，所述第一码块为P1 B/P2 B码块，所述P1为所述第一码块的净荷比特数，所述P2为所述第一码块的总比特数，P2-P1表示所述第一码块的同步头比特数， 所述P1和所述P2分别为正整数，且所述P2大于所述P1。
在一种可能的实现方式中，所述第一比特图样包括所述第一码块的第0个比特至第9个比特构成的图样，所述第一码块的起始比特为所述第0个比特。
本申请实施例中，通过获取第一码块的第0个比特至第9个比特，识别该第一码块是否为第一边界码块，不仅实施方便简单，而且还能够保证第一码块被识别为第一边界码块的可靠性。
当然，本申请实施例中，第一比特图样还可以包括第一码块的第0个比特至第65个比特构成的图样等，本申请实施例对于第一比特图样的具体结构不作限定。
在一种可能的实现方式中，所述第一码块的第0个比特和所述第一码块的第1个比特为所述第一码块的同步头，所述第一码块的第2个比特至所述第一码块的第9个比特为所述第一码块的控制块类型域。
可理解，第一码块的第2个比特至第9个比特还可能为该第一码块的数据字节。示例性的，当第一码块就不是第一边界码块，而是数据码块时，该第2个比特至第9个比特就是数据码块的第一个数据字节。
在一种可能的实现方式中，所述在所述不一致的比特数小于或等于第一阈值的情况下，识别所述第一码块是所述第一边界码块，包括：
在所述待识别比特图样与所述模板比特图样有不一致的比特，且所述不一致的比特数小于或等于所述第一阈值的情况下，识别所述第一码块是所述第一边界码块。
也就是说，本申请实施例中，待识别比特图样与模板比特图样的不一致的比特数大于或等于1，且该不一致的比特数小于或等于第一阈值的情况下，通信装置仍可以识别第一码块是第一边界码块。
在一种可能的实现方式中，在所述不一致的比特数小于或等于第一阈值的情况下，识别所述第一码块是所述第一边界码块，包括：在所述第一比特图样与所述第一模板比特图样不一致，且所述不一致的比特数小于或等于所述第一阈值的情况下，识别所述第一码块是所述第一边界码块。
一般的，第一码块的同步头为0b10，控制块类型域为0x78时，该第一码块才是第一边界码块。然而，本申请实施例中，即使第一码块的同步头不为0b10，和/或，第一码块的控制块类型域不为0x78，但是不一致的比特数小于或等于第一阈值的情况下，该第一码块仍可以被识别为第一边界码块。
在一种可能的实现方式中，所述码块流还包括第二码块，所述待识别比特图样还包括第二比特图样，所述第二比特图样为所述第二码块对应的比特图样；所述模板比特图样还包括第二模板比特图样，所述第二模板比特图样与所述第二比特图样对应。
在一种可能的实现方式中，所述第二模板比特图样为以下任一项码块对应的模板比特图样：第二边界码块、空闲码块、序列码块、信号码块、错误码块。
本申请实施例中，第二码块可以为第一码块之前的码块。示例性的，该第二码块可以为与第一码块相邻的，且位于第一码块之前的码块。
在一种可能的实现方式中，所述第二比特图样包括所述第二码块的第0个比特至第9个比特构成的图样，所述第二码块的起始比特为所述第0个比特。
本申请实施例中，第二码块的第0个比特和第1个比特可以为该第二码块的同步头。该第二码块的第2个比特至第9个比特可以为该第二码块的控制块类型域。
在一种可能的实现方式中，所述码块流还包括第三码块，所述待识别比特图样还包括第 三比特图样，所述第三比特图样为所述第三码块对应的比特图样；所述模板比特图样还包括第三模板比特图样，所述第三模板比特图样与所述第三比特图样对应。
在一种可能的实现方式中，所述第三模板比特图样为数据码块对应的模板比特图样。
本申请实施例中，第三码块可以为第一码块之后的码块。示例性的，该第三码块可以为与第一码块相邻的，且位于第一码块之后的码块。
在一种可能的实现方式中，所述在所述不一致的比特数小于或等于第一阈值的情况下，识别所述第一码块是所述第一边界码块，包括：在所述第一比特图样与所述第一模板比特图样一致，且所述不一致的比特数小于或等于所述第一阈值的情况下，识别所述第一码块是所述第一边界码块。
在一种可能的实现方式中，所述在所述不一致的比特数小于或等于第一阈值的情况下，识别所述第一码块是所述第一边界码块，包括：确定第二比特图样，所述第二比特图样为第二码块对应的比特图样；对比所述第二比特图样与第二模板比特图样；在所述不一致的比特数小于或等于所述第一阈值，且所述第二比特图样与所述第二模板比特图样的不一致的比特数小于或等于第二阈值的情况下，识别所述第一码块是所述第一边界码块。
本申请实施例中，在待识别比特图样与模板比特图样的不一致的比特数小于或等于第一阈值的情况下，以及在该第二比特图样与第二模板比特图样的不一致的比特数小于或等于第二阈值的情况下，通信装置可以识别第一码块是第一边界码块。
示例性的，通信装置可以对比待识别比特图样和模板比特图样，如对比第一比特图样与第一模板比特图样，获得该第一比特图样与第一模板比特图样不一致的比特数。以及该通信装置还可以对比第二比特图样与第二模板比特图样，获得该第二比特图样与第二模板比特图样不一致的比特数。在第一比特图样与第一模板比特图样不一致的比特数小于或等于第一阈值的情况下，以及在第二比特图样与第二模板比特图样不一致的比特数小于或等于第二阈值的情况下，识别第一码块是第一边界码块。例如，通信装置可以先对待识别比特图样(如第一比特图样)与模板比特图样(如第一模板比特图样)进行对比，当待识别比特图样与模板比特图样的不一致的比特数小于或等于第一阈值的情况下，该通信装置再对第二比特图样与第二模板比特图样进行对比。从而，在第二比特图样与第二模板比特图样的不一致的比特数小于或等于第二阈值的情况下，识别第一码块是第一边界码块。
这里所示的实施例中，第二比特图样与第二模板比特图样的不一致的比特数不包含于上述第一阈值中。
示例性的，第二阈值可以为0或1等，本申请实施例对此不作限定。
在一种可能的实现方式中，所述在所述不一致的比特数小于或等于第一阈值的情况下，识别所述第一码块是所述第一边界码块，包括：确定第二比特图样，所述第二比特图样为第二码块对应的比特图样；对比所述第二比特图样与第二模板比特图样；在所述不一致的比特数小于或等于第一阈值，且所述第二比特图样与所述第二模板比特图样一致的情况下，识别所述第一码块是所述第一边界码块。
本申请实施例中，通过判断该第二比特图样是否为控制码块，进一步确认第一码块是否为第一边界码块，从而进一步提高了第一码块被识别为第一边界码块的准确性和可靠性，保证了系统的容错性。可理解，关于第二比特图样与第二模板比特图样的说明，可以参考上述关于第二阈值对应的实施例的说明，这里不再详述。
在一种可能的实现方式中，所述在所述不一致的比特数小于或等于第一阈值的情况下，识别所述第一码块是所述第一边界码块，包括：确定第三比特图样，所述第三比特图样为第 三码块对应的比特图样；对比所述第三比特图样与第三模板比特图样；在所述不一致的比特数小于或等于所述第一阈值，且所述第三比特图样与所述第三模板比特图样的不一致的比特数小于或等于第二阈值的情况下，识别所述第一码块是所述第一边界码块。
可理解，对于第三码块的说明可以参考上述对第二码块的说明，这里不再详述。示例性的，第三码块可以是数据码块。
在一种可能的实现方式中，所述识别所述第一码块是所述第一边界码块之后，所述方法还包括：根据所述第一码块从所述码块流中确定第一码组，所述第一码组以所述第一码块开始。
在一种可能的实现方式中，所述第一码组包括195个数据码块和一个结束码块。
本申请实施例中，通过对S码块的识别，使得通信装置能够解复用出以S码块为开始的码组对应的多个第一时隙，从而获得该多个第一时隙对应的客户信号，不仅实施简单，而且还能够有效保证码组被识别的可靠性。
在一种可能的实现方式中，所述第一码组承载T个客户信号，所述T为正整数。
本申请实施例中，第一码组可以承载T个客户信号。然而，在具体实现中，该第一码组也可能没有承载客户信号等，本申请实施例对此不作限定。
在一种可能的实现方式中，T＝24。
第二方面，本申请提供一种通信装置，用于执行第一方面或第一方面的任意可能的实现方式中的方法。该通信装置包括具有执行第一方面或第一方面的任意可能的实现方式中的方法的相应单元。
例如，该通信装置可以包括收发单元和处理单元。
第三方面，本申请提供一种通信装置，该通信装置包括处理器，用于执行上述第一方面或第一方面的任意可能的实现方式所示的方法。
在执行上述方法的过程中，上述方法中有关接收码块(或码块流)等的过程，可以理解为由处理器接收输入的码块(或码块流)的过程。处理器接收输入的码块(或码块流)时，收发器接收码块(或码块流)，并将其输入处理器。更进一步的，在收发器收到该码块(或码块流)之后，该码块(或码块流)可能需要进行其他的处理，然后才输入处理器。
对于处理器所涉及的发射、发送和接收等操作，如果没有特殊说明，或者，如果未与其在相关描述中的实际作用或者内在逻辑相抵触，则均可以更加一般性的理解为处理器输出和接收、输入等操作，而不是直接由射频电路和天线所进行的发射、发送和接收操作。
在实现过程中，上述处理器可以是专门用于执行这些方法的处理器，也可以是执行存储器中的计算机指令来执行这些方法的处理器，例如通用处理器。上述存储器可以为非瞬时性(non-transitory)存储器，例如只读存储器(Read Only Memory，ROM)，其可以与处理器集成在同一块芯片上，也可以分别设置在不同的芯片上，本申请实施例对存储器的类型以及存储器与处理器的设置方式不做限定。
在一种可能的实现方式中，存储器位于所述通信装置之外。
在一种可能的实现方式中，存储器位于所述通信装置之内。
本申请实施例中，处理器和存储器还可能集成于一个器件中，即处理器和存储器还可以被集成在一起。
在一种可能的实现方式中，所述通信装置还包括收发器，所述收发器，用于接收信号和/或发送信号。
示例性的，该收发器可以用于接收码块流等。
第四方面，本申请提供一种通信装置，所述通信装置包括逻辑电路和接口，所述逻辑电路和所述接口耦合；其中，所述接口，用于获取码块流(或者，也可以称为输入码块流)，所述逻辑电路，用于确定待识别比特图样，以及对比所述待识别比特图样和模板比特图样，获得不一致的比特数；在所述不一致的比特数小于或等于第一阈值的情况下，识别所述第一码块是第一边界码块。
可理解，对于逻辑电路的具体实现方式，还可以参考下文示出的装置实施例等，这里不再详述。对于第一码块、待识别比特图样、模板比特图样等的说明，可以参考本申请的其他实施例等，这里不作详述。
第五方面，本申请提供一种计算机可读存储介质，该计算机可读存储介质用于存储计算机程序，当其在计算机上运行时，使得上述第一方面或第一方面的任意可能的实现方式所示的方法被执行。
示例性的，当上述计算机程序在通信装置(如接收端)上运行时，上述第一方面或第一方面的任意可能的实现方式所示的方法被执行。
第六方面，本申请提供一种计算机程序产品，该计算机程序产品包括计算机程序或计算机代码，当其在计算机上运行时，使得上述第一方面或第一方面的任意可能的实现方式所示的方法被执行。
第七方面，本申请提供一种计算机程序，该计算机程序在计算机上运行时，上述第一方面或第一方面的任意可能的实现方式所示的方法被执行。
附图说明
图1是本申请实施例提供的一种基于灵活以太网协议的通信系统示意图；
图2是本申请实施例提供的一种MTN网络架构示意图；
图3是本申请实施例提供的另一种MTN网络架构示意图；
图4是本申请实施例提供的一种第一通道和第二通道的关系示意图；
图5a是本申请实施例提供的一种64B/66B码块的不同码型定义；
图5b和图5c是本申请实施例提供的一种码组的结构示意图；
图5d是本申请实施例提供的一种码组的封装过程示意图；
图6a和图6b是本申请实施例提供的一种模板比特图样示意图；
图7a至图7c是本申请实施例提供的一种模板比特图样示意图；
图8a是本申请实施例提供的一种模板比特图样与待识别比特图样的对比示意图；
图8b是本申请实施例提供的一种模板比特图样的结构示意图；
图8c是本申请实施例提供的一种待识别比特图样的结构示意图；
图9是本申请实施例提供的一种码块识别方法的流程示意图；
图10a是本申请实施例提供的一种码块识别方法的流程示意图；
图10b是本申请实施例提供的一种识别S码块的模块示意图；
图11是本申请实施例提供的一种码块识别方法的流程示意图；
图12a和图12b是本申请实施例提供的另一种码块识别方法的流程示意图；
图13和图14是本申请实施例提供的又一种码块识别方法的流程示意图；
图15至图17是本申请实施例提供的一种通信装置的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地描述。
本申请的说明书、权利要求书及附图中的术语“第一”和“第二”等仅用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们的任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备等，没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元等，或可选地还包括对于这些过程、方法、产品或设备等固有的其它步骤或单元。
在本文中提及的“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员可以显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
在本申请中，“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上，“至少两个(项)”是指两个或三个及三个以上，“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”。
以下详细介绍本申请涉及的术语。
1、灵活以太网(flexible ethernet，FlexE)
光互联网论坛(optical internet forum，OIF)发布了灵活以太网(flexible ethernet，FlexE)，FlexE是一种支持不同以太网媒体访问控制(media access contro，MAC)层速率的通用技术。FlexE引入了灵活以太网捆绑组(也可称为FlexEgroup或简称为捆绑组)的概念。捆绑组可以由一个或多个物理层装置(也可以认为物理链路接口，可记为PHY)捆绑组成，一个捆绑组对应的带宽资源为该捆绑组中的PHY对应的带宽资源之和，因此，基于捆绑组，FlexE能够满足更大的传输速率和传输带宽。
图1示例性示出了一种基于灵活以太网协议的通信系统示意图，图1是以一个捆绑组包括4个PHY为例。FlexE通过时分复用(time division multiplexing，TDM)方式将每个PHY的带宽资源划分为多个时隙，实现传输管道带宽的硬隔离。灵活以太网协议客户(FlexE Client)代表在捆绑组上指定的时隙(一个时隙或多个时隙)传输业务流，一个捆绑组上可承载多个灵活以太网协议客户，一个灵活以太网协议客户对应一个业务流(典型的，可以称为媒体访问控制(medium access control，MAC)Client)，灵活以太网协议功能层(也可以称为FlexEshim)层提供灵活以太网协议客户到MAC Client的数据适配和转换。
FlexE通过将多个PHY绑定可支持例如绑定、子速率、通道化等功能。示例性的，FlexE可以将多个100比特以太网(gigabit ethernet，GE)PHY端口绑定，将每个100GE端口在时域上以5G为颗粒划分为20个时隙，FlexE可支持不同以太网MAC速率的业务。例如在2×100GE捆绑组中支持200G的MAC业务，也就是FlexE将多个以太网端口绑定为一个捆绑组(group)以支持速率大于单个以太网端口的MAC业务，即FlexE支持绑定功能。又例如支持在100GE捆绑组中传输50G的MAC业务，也就是通过为业务分配时隙支持速率小于捆绑组带宽或者小于单个以太网端口带宽的MAC业务，即FlexE支持子速率功能。又例如在2 ×100GE捆绑组中支持同时传输一个150G和两个25G的MAC业务，也就是通过为业务分配时隙支持在捆绑组中同时传输多个MAC业务，即FlexE支持通道化功能。
可见，FlexE通过捆绑组可以并行地传输多个业务流，同一业务流的业务数据可以承载在捆绑组中的一个PHY，也可以承载在捆绑组中的不同PHY。换句话说，同一业务流的业务数据可以通过捆绑组中的一个PHY传输至对端，也可以通过捆绑组中的多个PHY传输至对端。一个PHY的带宽资源通常会被划分为多个时隙，实际使用时，可以将业务所对应的码块流按照时隙配置表分配到相应时隙上。可理解，这里所示一个PHY的带宽资源通常会被划分为多个时隙，该时隙可以理解为第二时隙。
可理解，本申请示出的捆绑组还可以称为链路组等，以及本申请示出的业务流也可以称为数据流等，本申请对其名称不作限定。可理解，这里所示的业务流也可以理解为下文示出的客户信号等。
2、城域传输网络(metro transport network，MTN)
MTN是国际电信联盟(telecommunication standardization sector of itu，ITU-T)针对5G等新业务需求在沿用FlexE设计逻辑的基础上定义了的新一代传送网技术体系。示例性的，如图2所示，MTN可以包括MTN通道层(MTN path layer)和MTN段层(MTN sectionlayer)。其中，MTN通道层包括MTN通道适配层(MTN path adaptation)、MTN通道终结层(MTN path trail termination)、MTN通道连接层(MTN path connection)等。MTN段层包括MTN段层适配层(MTN section adaptation)和MTN段层终结层(MTN section trail termination)。可选的，MTN段层还可以包括适配层(adaptation)。
可理解，上述MTN通道适配层、MTN通道终结层、MTN通道连接层或MTN段层终结层等，还可能存在其他名称，例如，MTN通道适配层还可以称为MTN通道适配功能模块等，本申请对此不作限定。可理解，对于MTN中关于捆绑组的描述，可参考关于FlexE中关于捆绑组的描述，这里不再详述。
示例性的，发送端获取到的业务流可以经过MAC，进入MTN域MTN通道适配层适配成64B/66B码块流的形式，该64B/66B码块流进入MTN通道终结层后，64B/66B码块流中会被插入通道层操作管理和维护(operations，administration，and maintenance，OAM)信息，该OAM信息中包括比特交织奇偶校验(bit interleavedparity，BIP)结果。接着，发送端可以通过MTN通道连接层(MTN path connection)进行通道转发，即在该MTN通道连接层确定出入端口的对应关系，从而确定出端口。MTN段层适配层(MTN section adaptation)是通道层到段层的适配功能，在该MTN段层适配层各路MAC的业务流(如64B/66B码块的形式)会进行交织，形成一路64B/66B码块流。然后，该一路64B/66B码块流经过MTN段层终结层(MTN section trail termination)、适配层(adaptation)等进入物理层进行传输等。示例性的，该64B/66B码块流还可以经过扰码、通道分布、对齐标记(alignment marker，AM)插入功能等。
相反，接收端接收到64B/66B码块流后，接收端接收的64B/66B码块流的流向与发送端发送64B/66B码块流的流向相反。例如接收端接收到的64B/66B码块流可以依次经过例如MTN段层、MTN通道层等。
从协议栈的角度粗略地看，MTN的段层从功能上来讲与OIF FlexE shim类似。MTN段层当前版本重用兼容FlexE，MTN当前版本的段层帧格式保留了FlexE帧格式。可理解，对于MAC、协调子层(reconciliation sublayer，RS)、物理编码子层编码/反编码(PCS encode/decode)等的具体描述，可参考IEEE802.3的以太网模型。
3、MTN灵活颗粒(finer granularity，fg)层
如图3中的客户信号(Client)经过MTN fg适配层后形成码组流。该码组流经过MTN fg终结层时，该码组流可以被插入OAM信息等(或者也可以理解为被插入开销信息)。然后，发送端在MTN fg连接层确定出入端口的对应关系，从而确定出端口。示例性的，在MTN fg层，如MTN fg终结层，码组流可以在第一通道中被传输；然后在MTN通道层，如MTN通道适配层，一路或多路第一通道可以复用第二通道划分出的一个或多个第一时隙。在MTN通道终结层，一路第二通道中可以被插入OAM等开销信息，以及在MTN段层适配层，一路或多路第二通道复用捆绑组划分出的一个或多个第二时隙。即在MTN段层，一路第二通道可以映射至一个或多个第二时隙。可理解，对于MTN通道层和MTN段层的具体描述可以参考图2，这里不再详述。
本申请中，由于码组是以码块的形式封装的，因此，在码组流经过MTN通道层和MTN段层时，MTN通道层和MTN段层感知到的就是码块流，随后，码块流经过物理层，被发送到链路上。
接收端在接收到码块流后，可以MTN段层适配层从捆绑组中的一个或多个第二时隙中解复用出第二通道。以及MTN通道适配层从第二通道中的一个或多个第一时隙中解复用出第一通道。由此接收端可以在MTN fg层从第一通道中恢复出客户信号流。可理解，由于接收端获取到客户信号流的流向与发送端发送客户信号流的流向相反，因此对于接收端获取到客户信号流的具体方式，还可以发送端发送码块流的描述，这里不再详述。
4、第一时隙
由上文可知，切片分组网(slicing packet network，SPN)或MTN等提供了基于n×5Gbps带宽的硬管道，n为正整数。然而，对于某些业务来说，5Gbps的管道带宽粒度依旧过大。为了解决管道带宽粒度过大的问题，本申请还提供了一种小颗粒管道。如图4所示，在5Gbps管道的基础上，本申请提供的方法可以对该5Gbps进行进一步的时隙化切分，如将5Gbps的时隙切分为480个10Mbps。该情况下，一个10Mbps可以对应一个客户信号，或者，多个10Mbps可以对应一个客户信号等，本申请对此不作限定。这里所示的5Gbps还可以理解为第二时隙。换句话说，第二时隙可以被划分为多个第一时隙。如上所示，第二时隙可以被划分为480个第一时隙。可理解，该第一时隙不仅可以包括10Mbps，还可以包括100Mbps、7.5Mbps、5Mbps或2.5Mbps等，以及第二时隙不仅包括5Gbps，还可以包括10Gbps、25Gbps等，本申请对此不作限定。可理解，本申请示出的各个时隙的带宽，在具体实现中，可能还会存在偏差，因此，对于第一时隙或第二时隙的带宽的具体取值，本申请不作限定。示例性的，第一时隙的带宽为10Mbps时，在具体实现中，该第一时隙的带宽还可以为10.1Mbps或10.2Mbps等。
以下将对本申请示出的捆绑组、第一时隙以及第二时隙进行详细说明。
本申请中捆绑组可以由一个或多个PHY捆绑而成，且该捆绑组的带宽为该一个或多个PHY的带宽之和。进一步的，该捆绑组可以被划分为X个第二时隙。第二通道可以包括该X个第二隙中的N个第二时隙，且该第二通道可以被划分为Y个第一时隙。第一通道可以包括该Y个第一时隙中的M个第一时隙。其中，N小于或等于X，M小于或等于Y，且M、N、X和Y均为大于或等于1的整数。
换句话说，本申请中，第一通道包括M个第一时隙，该M个第一时隙包含于第二通道中，该第二通道包括N个第二时隙，该N个第二时隙包含于捆绑组中，该捆绑组中包括一个或多个PHY链路。其中，第二通道被划分为Y个第一时隙，上述M个第一时隙包含于该Y个第一时隙中，捆绑组被划分为X个第二时隙，上述N个第二时隙包含于该X个第二时隙 中。可选的，本申请中的第一时隙的带宽可以为10Mbps×K，该K为大于或等于1的整数，且K小于或等于2048。
上述第一通道可以理解为用于传输码组的通道，上述第二通道可以理解为用于传输码块的通道。第一通道在传输码组时，可以复用第二通道被划分出的Y个第一时隙中的M个第一时隙。换句话说，本申请示出的第一通道的时隙粒度更小，该传送网络技术相较于MTN的时隙粒度更小，更灵活。例如，该第一通道可以用于传输专线业务等。又例如，该第一通道可以用于传输一个或多个不同的客户信号等。可理解，该第一通道可以用于传输本申请示出的码组(如第一码组等)，该码组可以被透传于MTN网络。
示例性的，如图4所示，捆绑组中的一个PHY可以包括三个第二通道，该第二通道中包括的第二时隙包含于捆绑组中。其中一个第二通道可以包括三个第一通道，如第一通道中包括的M个第一时隙包含于第二通道中。可理解，图4仅为示例，不应将其理解为对本申请的限定。
本申请中，第一通道还可以称为fgBU通道(或MTN fg通道)、灵活小颗粒通道(或小颗粒通道)或低阶通道等，第二通道还可以称为大颗粒通道或高阶通道等，本申请对其名称不作限定。
5、码块(block)
P1 B/P2 B码块：一种编码方式，也可以称为P1 B/P2 B比特块(bit block)，或者也可以称为P1 B/P2 B块，或者也可以称为P1 B/P2 B编码块，或者也可以称为P1 B/P2 B比特流，或者也可以称为P1/P2(或P1b/P2b)比特块等。其中，P1表示码块(或比特块)中的净荷比特数；P2表示码块的总比特数，P2-P1表示码块中的同步头比特数，P1、P2为正整数，且P2大于P1。示例性的，上述P1 B/P2 B码块可以为8 B/10 B码块、64 B/66 B码块、128 B/130 B码块或256 B/258 B码块等，本申请对上述P1和P2的具体取值不作限定。
下文将以64 B/66 B码块为例示出本申请提供的方法。可理解，下文示出的64 B/66 B码块也可以替换为64 B/66 B比特块，或者64/66码块，或者64/66比特块，或者64 b/66 b码块，或者64b/66b比特块，或者64 B/66 B比特块流，或者64 B/66 B编码块等。
作为示例，图5a示出的是一种64B/66B码块的不同码型定义。如图5a所示，首部的2个比特“10”或“01”为同步头比特，后64比特即为净荷比特，可以用于承载净荷数据等。图5a中每一行代表一种码型定义，其中，D0～D7代表数据字节，C0～C7代表控制字节，S0代表MAC帧的开始，T0～T7代表MAC帧的结束。
图5a示出的不同码块中，当同步头比特为0b10时，对应的码块可以称为控制码块。控制码块即为上述P1 B/P2 B码块中定义的控制码型。示例性的，控制码块的同步头可以为“10”，以及该控制码块还可以包括控制块类型域(controlblock type field)。
例如，64 B/66 B中定义的控制码块的控制块类型域为0x78时，该控制码块可以为开始码块。
又例如，64 B/66 B中定义的控制码块的控制块类型域为0xFF时，该控制码块可以为结束码块。可理解，这里仅示例性的示出了一种结束码块，在图5a示出的码块中结束码块的控制块类型域还可以为0x87、0x99等，这里不再详述。本申请下文示出的第二边界码块的控制块类型域不仅可以为0xFF，还可以为0x87、0x99、0xAA、0xB4、0xCC、0xD2或0xE1等，本申请对于第二边界码块的控制块类型域不作限定。
又例如，64 B/66 B中定义的控制码块的控制块类型域为0x4B时，该控制码块可以为序列(sequenceordered set，O)码块，或者也可以称为信号(signal ordered set，O)码块等。示 例性的，该序列码块可以表示链路状态，该信号码块可以表示特殊信号的信息。本申请对于该序列码块和该信号码块的区别不作限定。下文将以O码块表示该序列码块或该信号码块。
又例如，64 B/66 B中定义的控制码块的控制块类型域为0x1E时，该控制码块可以为空闲(idle)码块或错误(error)码块。至于该控制码块具体为空闲码块还是错误码块，可以根据控制块类型域之后的第一个控制字节的取值确定。例如，当第一个控制字节为0xIE时，该控制码块为错误码块；当第一个控制字节为0x00时，该控制码块可以为空闲码块。
6、边界码块
边界码块可以用于标识数据码块的开始或结束。本申请中，边界码块可以包括第一边界码块和/或第二边界码块。
一般的，报文中的前导(preamble)和/或帧起始定界符(startofframedelimiter，SFD)可以被编码为开始码块。以及为标识报文的结束，在编码时可能会在最后一个数据码块之后增加一个结束码块(或者，结束码块中也可以用于承载数据等)。即这里所示的开始码块和结束码块可以用于界定至少一个数据码块。示例性的，开始码块和结束码块可以用于界定195个数据码块。或者，开始码块和结束码块可以用于界定33个数据码块等。这里所示的开始码块和结束码块的描述仅为示例。例如，第一边界码块可以为第一码组的开始码块，至于该第一码组的结束码块可以为第三边界码块(即结束码块)。又例如，第二边界码块可以为第二码组的结束码块，该第二码组的开始码块可以为第四边界码块等，本申请对于第二码组的开始码块不作限定。
示例性的，下文示出的客户信号可以是报文的形式。例如，下文示出的MAC帧(即MAC frame)流也可以称为报文流等，本申请对此不作限定。
7、码组(block group)
以下将示例性说明本申请示出的码组的结构。
第一种，码组可以包括一个开始码块、一个或多个数据码块和一个结束码块。示例性的，该码组的开始部分是开始码块，结尾部分可以是结束码块，或者，结尾部分可以是其他控制码块等。
示例性的，图5b是本申请示出的一种码组的结构示意图。该码组可以包括一个开始码块和一个结束码块，以及33个数据码块。由于图5b示出的结束码块为0xFF，因此该结束码块第0个控制字节(如图5a中的D0字节)至第6个控制字节(如图5a中的D6字节)可以用于承载数据。由此，图5b示出的负载部分可以承载33个数据码块。
第二种，码组可以包括一个开始码块和一个结束码块，以及还包括根据64B/66B数据码块编码得到的一个或多个64B/65B数据码块。可理解，该64B/65B数据码块包含于码组的负载(payload)部分。换句话说，码组的负载部分包括的64B/65B数据码块可以由64B/66B数据码块去掉1比特同步头获得。至于去掉64B/66B数据码块的第0个比特还是第1个比特，本申请不作限定。
示例性的，图5c是本申请示出的另一种码组的结构示意图。如图5c所示，第一行(即对应图5a中的开始码块)为该码组中的开始码块，第197行(即对应图5a中的结束码块)为该码组中的结束码块，第198行为该码块中位于结束码块之后的其他控制码块(图5c中未示出第198行)。第2行的前7个字节用于承载开销(overhead，OH)信息。从第2行的第8个字节开始到第196行即为64B/65B数据码块，用于承载数据信息。根据65与64之间的关系，码组的负载部分可以根据195个数据码块编码得到。图5c示出的负载部分为1560字节，1560字节＝1560*8比特＝192个64B/65B。同时，195个64B/66B数据码块，一共有195*64＝12480 比特＝192*65。因此，图5c示出的码组可以理解为包括一个S码块、195个D码块以及一个T码块。
本申请中，码组的长度可以为预设长度，如一个码组中的数据码块的长度可以为1560个字节。
如图5d所示，客户信号(例如MAC frame流)在经过64B/66B编码后，形成64B/66B码块流，64B/66B码块流在完成64B/65B压缩(去掉1比特的同步头)后，形成64B/65B码块流。该64B/65B码块流可以按照每8个64B/65B码块为一组映射至一个第一时隙中。
也就是说，本申请示出第一时隙可以包括8个64B/65B。由此，结合图5c所示的fgBU的结构，一个fgBU可以承载24个第一时隙。以及20个fgBU可以构成一个完整的复用周期，一个复用周期内可以包括480个时隙。本申请中，由于第一时隙可以用于承载一个客户信号，因此一个fgBU可以最多还可以承载24个客户信号。
可理解，本申请示出的码组还可以称为灵活颗粒基础单元(finer granularity basicunit，fgBU)、码块集或码块簇等，本申请对其名称不作限定。
可理解，这里所示的码组中包括的数据码块的长度仅为示例，在具体实现中，该码组包括的数据码块的长度还可以为其他值等。
可理解，本申请示出的码组的说明适用于下文示出的第一码组，该第一码组以第一码块开始，该第一码块可以为S码块。
8、待识别比特图样和模板比特图样
待识别比特图样：由一个或多个码块的部分或全部比特构成。
可选的，该待识别比特图样可以由第一码块的至少两个比特构成。例如，待识别比特图样包括第一比特图样，该第一比特图样为第一码块的第0个比特至第9个比特构成的比特图样。又例如，第一比特图样为第一码块的第0个比特至第65个比特构成的比特图样。
可选的，待识别比特图样由第一码块的至少两个比特，以及第二码块的至少两个比特构成。例如，待识别比特图样包括第一比特图样和第二比特图样，该第二比特图样可以为第二码块的第0个比特至第9个比特构成的比特图样等。
可选的，待识别比特图样由第一码块的至少两个比特，以及第三码块的至少两个比特构成。例如，待识别比特图样包括第一比特图样和第三比特图样，该第三比特图样可以为第三码块的第0个比特和第1个比特构成的比特图样等。
可选的，待识别比特图样由第一码块的至少两个比特、第二码块的至少两个比特以及第三码块的至少两个比特构成。
可理解，以上示出的第一比特图样、第二比特图样以及第三比特图样仅为示例，在具体实现中，第一比特图样还可以为第一码块的第0个比特至第17个比特构成的比特图样等。或者，第二比特图样还可以为第二码块的第0个比特至第65个比特构成的比特图样等，本申请实施例对此不作限定。
本申请中，可以通过检测窗口获取待识别比特图样，如该检测窗口可以用于检测第一码块是否为第一边界码块。
模板比特图样：用于判断第一码块是否为第一边界码块时所期望出现的比特顺序。如模板比特图样可以理解为：用于判断第一码块是否为第一边界码块时，所期望检测窗口内出现的比特顺序。示例性的，模板比特图样包括第一模板比特图样，该第一模板比特图样用于识别第一比特图样。换句话说，该第一模板比特图样在模板比特图样中的位置与第一比特图样在待识别比特图样中的位置是一一对应的。对于待识别比特图样与模板比特图样的对应关系 还可以参考下文示出的图8a的说明。
示例性的，第一模板比特图样可以为开始码块对应的模板比特图样，第二模板比特图样可以为结束码块对应的模板比特图样。该情况下，对于第一模板比特图样和第二模板比特图样的说明，可以参考下文示出的各个实施例。
然而，本申请中第一模板比特图样还可以为结束码块对应的模板比特图样，第二模板比特图样可以为数据码块对应的模板比特图样，第三模板比特图样可以为开始码块对应的模板比特图样。或者，第三模板比特图样还可以为空闲码块、错误码块或O码块中的任一项对应的模板比特图样等。换句话说，通信装置可以利用第一码块之前的第二码块识或该第一码块之后的第三码块来识别第一码块是否为结束码块。该情况下，第一边界码块即为结束码块。可理解，关于第一模板比特图样为结束码块对应的模板比特图样、第二模板比特图样为数据码块对应的模板比特图样，第三模板比特图样为开始码块、空闲码块、错误码块或O码块中的任一项对应的模板比特图样的具体说明，可以参考下文示出的第一模板比特图样为开始码块对应的模板比特图样，第二模板比特图样为结束码块、空闲码块、错误码块或O码块中的任一项对应的模板比特图样，第三模板比特图样为数据码块对应的模板比特图样的具体说明，下文不作详述。
可理解，本申请示出的比特图样(bit pattern)还可以称为比特图案、比特串(bit string)、比特序列(bit sequence)或比特位模式等，本申请对其名称不作限定。同时，本申请示出的模板比特图样(bit pattern)，还可以称为预设比特图样，或预设模板，或预置模板等，本申请对其名称不作限定。以及本申请示出的待识别比特图样还可以称为待验证比特图样，或目标比特图样等，本申请对其名称也不作限定。
以下结合附图说明本申请示出的模板比特图样。
在一种可能的实现方式中，模板比特图样包括第一模板比特图样，该第一模板比特图样可以为第一边界码块对应的模板比特图样。示例性的，该第一边界码块可以为S码块。
可选的，如图6a所示，该第一模板比特图样可以包括该S码块的第0个比特至第9个比特对应的模板比特图样。即第一模板比特图样由S码块的同步头和控制块类型域构成。
可选的，该第一模板比特图样还可以包括S码块的第0个比特至第9个比特，以及第一个控制字节(如图5a中的D1字节)至第七个控制字节(如图5a中的D7字节)中的任一个字节对应的模板比特图样。如图6b所示，该第一模板比特图样可以由S码块的第0个比特至第65个比特构成。
可选的，第一模板比特图样还可以包括S码块的第2个比特至第9个比特对应的模板比特图样。第一模板比特图样还可以由S码块的控制块类型域构成等。
在另一种可能的实现方式中，模板比特图样包括第一模板比特图样和第二模板比特图样。该第二模板比特图样可以为以下任一项码块对应的模板比特图样：第二边界码块(如T7码块)、空闲(idle)码块、序列(sequenceordered set，O)码块、信号(signal ordered set，O)码块、错误(error)码块。对于第一模板比特图样的说明可以参考图6a和图6b，这里不再详述。
可选的，如图7a中的(1)所示，模板比特图样可以包括T码块的第0个比特至第9个比特，以及S码块的第0个比特至第9个比特对应的模板比特图样。如模板比特图样可以由T码块的同步头和控制块类型域，以及S码块的同步头和控制块类型域构成。
可理解，第一模板比特图样还可以由S码块的同步头或控制块类型域中的任一项，以及 第二模板比特图样还可以包括T码块的同步头或控制块类型域中的任一项构成等。由此，模板比特图样可以包括T码块的控制块类型域，以及S码块的同步头和控制块类型域对应的模板比特图样。或者，模板比特图样可以包括T码块的控制块类型域，以及S码块的控制块类型域对应的模板比特图样。或者，模板比特图样可以包括T码块的同步头和控制块类型域，以及S码块的控制块类型域对应的模板比特图样。或者，模板比特图样可以包括T码块的同步头，以及S码块的同步头和控制块类型域对应的模板比特图样。或者，模板比特图样可以包括T码块的同步头和S码块的同步头对应的模板比特图样。可理解，对于该说明，下文示出的其他码块同样适用，下文不再详述。
可选的，如图7a中的(2)所示，模板比特图样可以包括O码块的同步头和块类型域，以及S码块的同步头和块类型域对应的模板比特图样。
可选的，如图7a中的(3)所示，模板比特图样可以包括空闲码块的同步头和块类型域，以及S码块的同步头和块类型域对应的模板比特图样。或者，图7a中的(3)示出的模板比特图样还可以理解为错误码块的同步头和块类型域，以及S码块的同步头和块类型域对应的模板比特图样。
可理解，本申请示出的第一模板比特图样还可以由S码块的同步头、S码块的控制块类型域以及S码块的控制字节构成。如图5a所示，错误码块的第0个字节至第7个字节的取值分别为0x1E。而空闲码块的第0个字节至第7个字节的取值分别为0x00。因此本申请示出的第二模板比特图样中还可以包括错误码块或空闲码块的控制字节等。
在又一种可能的实现方式中，模板比特图样包括第一模板比特图样和第三模板比特图样。该第三模板比特图样可以为数据码块对应的模板比特图样。
可选的，模板比特图样可以包括S码块的同步头和块类型域，以及数据码块的同步头对应的模板比特图样。
可选的，如图7b中的(1)所示，模板比特图样可以包括S码块的同步头和块类型域，以及数据码块的同步头和第一个字节对应的模板比特图样。可理解，图7b示出的0x89即为图5b或图5c示出的用于承载开销信息的第一个字节的取值。该0x89还可以为其他值等，本申请实施例对此不作限定。图7b示出的0xAA可以理解为用于承载开销信息的第二个字节的取值，该0xAA还可以为其他值等，本申请实施例对此不作限定。
可选的，如图7b中的(2)所示，模板比特图样可以包括S码块的同步头和块类型域，以及数据码块的同步头、第一个字节和第二个字节对应的模板比特图样。
可选的，模板比特图样还可以包括S码块的同步头和块类型域，以及数据码块的同步头对应的模板比特图样。
在又一种可能的实现方式中，模板比特图样包括第一模板比特图样、第二模板比特图样和第三模板比特图样。
可理解，对于第一模板比特图样、第二模板比特图样以及第三模板比特图样的具体说明，可以参考上文，这里不再详述。
示例性的，如图7c中的(1)所示，模板比特图样包括T码块的同步头和块类型域、S码块的同步头和块类型域，以及数据码块的同步头对应的模板比特图样。
示例性的，如图7c中的(2)所示，模板比特图样包括O码块的同步头和块类型域、S码块的同步头和块类型域，以及数据码块的同步头对应的模板比特图样。
示例性的，如图7c中的(3)所示，模板比特图样包括idle码块(或error码块)的同步头和块类型域、S码块的同步头和块类型域以及数据码块的同步头对应的模板比特图样。
可理解，本申请示出的模板比特图样仅为示例，在具体实现中，模板比特图样还可以具有更多的表现形式，本申请对此不作限定。
如以图6a示出的模板比特图样为例，以下结合图8a说明模板比特图样与待识别比特图样的对比结果(即不一致的比特数)。本申请实施例是以第一码块的第0个比特至第9个比特为例，但是不应将其理解为对本申请实施例的限定。示例性的，当待识别比特图样为第一码块的第0个比特至第65个比特对应的模板比特图样时，该待识别比特图样可以与图6b示出的模板比特图样进行对比等，这里不再赘述。
如图8a中的(1)所示，当第一码块的第0个比特和第1个比特为10(即第一码块的同步头为10)，以及第一码块的第2个比特至第9个比特为0x78时，通过与模板比特图样对比，可以获得不一致的比特数为0。
如图8a中的(2)所示，当第一码块的第0个比特和第1个比特为10，而第一码块的第2个比特至第9个比特为0x79时，通过与模板比特图样对比，可以获得不一致的比特数为1。
如图8a中的(3)所示，当第一码块的第0个比特和第1个比特为10，而第一码块的第2个比特至第9个比特为0x7A时，通过与模板比特图样对比，可以获得不一致的比特数为1。
示例性的，当第一码块的第0个比特和第1个比特为01，而第一码块的第2个比特至第9个比特为0x78时，通过与模板比特图样对比，可以获得不一致的比特数为1。
可理解，以上示出的模板比特图样的结构仅为示例，该模板比特图样的结构还可以为其他结构等，本申请对此不作限定。示例性的，图8b中的(1)示出的模板比特图样为上文示出的结构，该情况下，待识别比特图样的结构可以如图8c中的(1)所示。图8b中的(2)示出的模板比特图样是本申请示出的另一种模板比特图样的结构。该情况下，待识别比特图样的结构可以如图8c中的(2)所示。
需要说明的是，不管模板比特图样的结构如何发生变化，只要待识别比特图样中的第一比特图样与第一模板比特图样对应，第二比特图样与第二模板比特图样对应，第三比特图样与第三模板比特图样对应，都落入本申请的保护范围。
可理解，本申请示出的第一比特图样与第一模板比特图样对应，指的是第一码块的第0个比特与第一模板比特图样的第0个比特对应，第一码块的第1个比特与第一模板比特图样的第1个比特对应，第一码块的第2个比特与第二模板比特图样的第2个比特对应，以此类推。示例性的，如图8a中的(2)所示，第一比特图样的第0个比特和第1个比特分别为10，则该10可以与第一模板比特图样中的第0个比特和第1个比特10进行对比。第一比特图样的第2个比特至第9个比特为0x79，二进制为0111 1001，则该第2个比特至第9个比特，即0111 1001需要与第一模板比特图样中的第2个比特至第9个比特的0111 1000对比。
可理解，这里关于对应的说明，下文示出的各个实施例同样适用，下文对于第一比特图样与第一模板比特图样的对应关系，第二比特图样与第二模板比特图样的对应关系，以及第三比特图样与第三模板比特图样的对应关系，不再赘述。
本申请提供的第一通道(又可以称为灵活小颗粒通道或低阶通道等)可以透传MTN网络。同时，该第一通道通过时隙复用的方式，映射至第二通道(又可以称为大颗粒通道或高阶通道或MTN通道等)。由于第二通道是基于以太网物理端口的，所以第二通道在任意两个节点的速率都存在+/-100ppm的速率差。因此，为了使得第一通道能够透传于第二通道，本申请示出的码组需要进行格式封装，使得第一通道可以复用第二通道的速率适配方式。基于 此，本申请提供一种码组，该码组可以包括一个S码块，多个D码块和一个T码块。可理解，对于码组的具体说明，可以参考上文描述，这里不再详述。
本申请中，当通信装置接收到码块流之后，需要从相应的第二时隙中恢复出fgBU序列流。然后从fgBU序列流中先识别每一个fgBU，再提取每个fgBU对应的第一时隙。由此，通过识别S码块，就可以识别fgBU。同时识别S码块的过程，也可以称为fgBU定帧。如果定帧过程中出现异常，就会导致fgBU对应的多个第一时隙(如上文示出的24个第一时隙)均无法被提取，导致fgBU均被丢弃，以及导致fgBU包括的多个D码块均被标记为错误码块。进而，导致fgBU对应的多个时隙或多个客户信号均无法被正确接收，造成系统容错性差。
鉴于此，本申请提供一种码块识别方法及装置，可以改善S码块因为偶发的误码而无法被识别的情况。以及改善由于S码块由于偶发的误码而无法识别，导致整个码组被丢弃的情况。同时，本申请提供的方法，还能够有效提高系统容错性。
本申请提供的码块识别方法可以应用于通信装置，该通信装置可以为有线设备、交换机、路由器、网卡、分组传送网(packet transport network，PTN)、(agile transport network，ATN)、切片分组网(slicing packet network，SPN)等，本申请对于该通信装置的具体形态不作限定。示例性的，该通信装置可以包括用于接收码块流的接收端；或者，该通信装置也可以理解为用于接收码组的接收端等。
图9是本申请实施例提供的一种码块识别方法的流程示意图，如图9所示，该方法包括：
901、获取码块流，该码块流包括第一码块。
例如，通信装置可以接收码块流，然后从码块流中获取第一码块。可理解，这里所示的通信装置获取码块流，可以理解为：该通信装置接收来自物理层的码块流；或者，该通信装置从其他装置获取码块流；或者，该通信装置从MTN段层或MTN通道层获取码块流等。本申请实施例对于该通信装置如何获取码块流不作限定。
902、确定待识别比特图样，该待识别比特图样包括第一比特图样，该第一比特图样为第一码块对应的比特图样。
对于待识别比特图样的具体说明，可以参考上文，这里不再详述。
示例性的，通信装置可以从接收到的码块流中获取第一码块，然后从该第一码块中获得该第一码块的第0个比特至第9个比特等，该第一码块的第0个比特至第9个比特即为待验证比特图样。
可理解，通信装置可以在MTN段层接收该码块流，然后在MTN通道层确定待识别比特图样。或者，通信装置可以通过收发器接收码块流，然后在MTN段层确定待识别比特图样等，本申请实施例对此不作限定。
在一种可能的实现方式中，通信装置可以在接收到该码块流时，确定待识别比特图样。示例性的，通信装置在MTN段层接收到码块流时，可以确定待识别比特图样。然后，该通信装置可以执行图9所示的方法，以及该通信装置从码块流中识别出第一边界码块之后，便可以获得以该第一边界码块为开始的码块流。例如，通信装置从码块流中识别出S码块之后，便可以获得该S码块之后的多个D码块，然后获得客户信号等。
在另一种可能的实现方式中，通信装置需要在MTN通道层从第二通道中解复用出第一通道的情况下，该通信装置可以从码块流中确定待识别比特图样。例如，通信装置可以在MTN通道适配层确定待识别比特图样。然后，该通信装置可以执行图9所示的方法，以及该通信装置从码块流中识别出第一边界码块之后，便可以获得以该第一边界码块为开始的码组。例 如，通信装置从码块流中识别出S码块之后，便可以获得以S码块为开始的第一码组，以及从该第一码组中获得T个客户信号，该T为正整数。例如T＝24。也就是说，通信装置可以从第一码组中获得多个第一时隙对应的客户信号。其中，一个第一时隙可以对应一个客户信号，或者，多个第一时隙可以对应一个客户信号。可理解，对于码组的具体说明，可以参考图5a至图5d，这里不再详述。
换句话说，图9所示的方法不仅适用于通信装置需要从第二通道解复用第一通道的场景，即通信装置需要从fgBU序列流中识别每一个fgBU的场景；而且，还适用于从64B/66B码块流中识别S码块的场景等，对于本申请实施例提供的方法所适用的场景不作限定。
903、对比待识别比特图样与模板比特图样，获得不一致的比特数，该模板比特图样包括第一模板比特图样，该第一模板比特图样为第一边界码块对应的模板比特图样。
本申请实施例中，该第一模板比特图样与第一比特图样对应，即第一模板比特图样在模板比特图样中的位置对应于第一比特图样在待识别比特图样中的位置。换句话说，该第一模板比特图样可以用于识别第一比特图样。
对于模板比特图样，以及待识别比特图样与模板比特图样的对应关系，可以参考上文，这里不再详述。如上文所示，模板比特图样可以包括第一模板比特图样，还可以包括第二模板比特图样和/或第三模板比特图样。示例性的，模板比特图样可以参考图6a、图6b、图7a至图7c等。待识别比特图样与模板比特图样的对应关系可以参考图8a和图8b等。
示例性的，码块流中还包括第二码块，待识别比特图样还包括第二比特图样，该第二比特图样为第二码块对应的比特图样。对于该第二比特图样的说明可以参考上文对第一比特图样的说明等，这里不再赘述。由此，第二模板比特图样与第二比特图样对应，即第二模板比特图样可以用于识别第二比特图样。
示例性的，码块流中还包括第三码块，待识别比特图样还包括第三比特图样，该第三比特图样为第三码块对应的比特图样。对于该第三比特图样的说明可以参考上文对第一比特图样的说明等，这里不再赘述。由此，第三模板比特图样与第三比特图样对应，即第三模板比特图样可以用于识别第三比特图样。
904、在不一致的比特数小于或等于第一阈值的情况下，识别第一码块是第一边界码块。
本申请实施例中，该第一阈值可以为1，即上述不一致的比特数小于或等于1比特的情况下，通信装置可以识别(或确定)第一码块是第一边界码块(如S码块)。或者，第一阈值可以为2，即上述不一致的比特数小于或等于2比特的情况下，通信装置可以确定第一码块是第一边界码块。或者，该第一阈值还可以取其他值等，本申请实施例不作限定。
可选的，步骤904可以包括：在待识别比特图样与模板比特图样不一致的比特数大于或等于1，且该不一致的比特数小于或等于第一阈值的情况下，识别第一码块是第一边界码块。
换句话说，本申请实施例提供的方法中，待识别比特图样与模板比特图样可以有不一致的比特数，而且该不一致的比特数小于或等于第一阈值，该情况下，通信装置仍可以识别第一码块是第一边界码块。该情况下，对于第一模板比特图样、第二模板比特图样以及第三模板比特图样的具体说明，可以参考上文的描述，这里不再详述。
可选的，步骤904可以包括：在第一模板比特图样与第一比特图样不一致，且待识别比特图样与模板比特图样的不一致的比特数小于或等于第一阈值的情况下，识别第一码块是第一边界码块。第一模板比特图样与第一比特图样不一致，指的是第一模板比特图样与第一比特图样在对应位置上的取值不是完全一致的。换句话说，即使第一模板比特图样与第一比特图样不能完全一致，也可以确定第一码块是S码块。这是因为：一方面，每个码块的同步头 有2比特的汉明距保护，连续发生两比特错误，如01跳转10概率小；另一方面，控制块类型域之间有4比特的汉明距保护，控制块类型域中的8个比特发生一个比特或两个比特的错误不会导致S码块被误识别为其他控制码块，如O码块或T码块等。因此，本申请实施例中，即使第一比特图样与第一模板比特图样在对应位置上的取值不是完全一致，第一码块也可以被识别为S码块。可理解，对于该同步头和控制块类型域的汉明距保护的说明，适用于本申请示出的第一码块、第二码块或第三码块等。
可选的，步骤904还可以包括：在第一模板比特图样与第一比特图样一致，且待识别比特图样与模板比特图样的不一致的比特数小于或等于第一阈值的情况下，识别第一码块是第一边界码块。也就是说，当第一模板比特图样与第一比特图样一致，但是在第二比特图样与第二模板比特图样不一致，但是不一致的比特数小于或等于第一阈值的情况下，通信装置仍可以识别第一码块是第一边界码块。示例性的，第二码块的同步头为0b10、0b00或0b11，则说明该第二码块的同步头可能存在偶发误码，由此，第一码块仍可以被识别为第一边界码块。
可选的，步骤904还可以包括：确定第二比特图样，对比第二比特图样和第二模板比特图样；在待识别比特图样与模板比特图样的不一致的比特数小于或等于第一阈值，且第二比特图样与第二模板比特图样的不一致的比特数小于或等于第二阈值的情况下，识别第一码块是第一边界码块。
本申请实施例中，该第二阈值可以小于或等于第一阈值。示例性的，该第二阈值可以为1等，本申请实施例对此不作限定。本申请实施例中，通信装置还可以对比第二比特图样与第二模板比特图样，从而在待识别比特图样与模板比特图样的不一致的比特数小于或等于第一阈值的情况下，以及在该第二比特图样与第二模板比特图样的不一致的比特数小于或等于第二阈值的情况下，识别第一码块是第一边界码块。
换句话说，通信装置可以对待识别比特图样(如第一比特图样)与模板比特图样(如第一模板比特图样)进行对比，以及对第二比特图样与第二模板比特图样进行对比。从而，当待识别比特图样与模板比特图样的不一致的比特数小于或等于第一阈值的情况下，以及在第二比特图样与第二模板比特图样的不一致的比特数小于或等于第二阈值的情况下，识别第一码块是第一边界码块。需要说明的是，第二比特图样与第二模板比特图样的不一致的比特数不包含于上述第一阈值中。
可选的，步骤904还可以包括：确定第二比特图样，对比第二比特图样和第二模板比特图样；在待识别比特图样与模板比特图样的不一致的比特数小于或等于第一阈值的情况下，以及在第二比特图样与第二模板比特图样一致的情况下，识别第一码块是第一边界码块。
可理解，对于第二比特图样和第二模板比特图样的说明可以参考本申请的其他实施例，这里不再详述。
本申请实施例提供的方法，可以有效改善第一码块与第一边界码块(如S码块)不一致的比特数不为0比特时，确定第一码块不为第一边界码块的情况。从而，改善了由于偶发误码导致第一码块无法被识别为第一边界码块的情况，提高了系统的容错性。示例性的，通过改善上述情况，而有效改善由于无法识别S码块而丢弃整个码组的情况。通过对S码块的识别，使得通信装置能够解复用出以S码块为开始的码组对应的多个第一时隙，从而获得该多个第一时隙对应的客户信号，不仅实施简单，而且还能够有效保证码组被识别的可靠性。
结合上文示出的各个方法，以下将以发送端和接收端为例详细对本申请实施例提供的码 块识别方法进行说明。
图10a是本申请实施例提供的一种码块识别方法的流程示意图。如图10a所示，该方法包括：
1001、发送端获取客户信号(client)。
步骤1001可以包括：发送端从面板侧接口接收客户信号；或者，发送端生成客户信号等。可理解，这里所示的面板侧接口可以理解为用户侧接口(user network interface，UNI)等。
1002、发送端对客户信号进行业务映射封装，获得fgBU序列流。
如以图3为例，发送端在获取到客户信号之后，可以通过MTN fg适配层形成预设长度的fgBU。然后发送端可以在MTN fg终结层将fgBU映射至第一通道。
1003、发送端将fgBU序列流映射至第二通道。
这里所示的fgBU序列流指的是在未映射至第二通道之前，发送端传输的是fgBU。示例性的，发送端可以在MTN通道层将fgBU序列流映射至第二通道。结合图3，发送端可以在MTN通道适配层复用第二通道划分出的一个或多个第一时隙，即该第一通道可以包括一个或多个第一时隙。示例性的，下文将以第一通道包括M个第一时隙为例说明图10a所示的方法。
1004、发送端将第二通道映射至一个或多个第二时隙。
示例性的，发送端可以在MTN段层将第二通道映射至一个或多个第二时隙。如以图3为例，发送端可以在MTN段层适配层将第二通道映射至一个或多个第二时隙，从而复用捆绑组。例如，发送端在MTN段层适配层，需要将各路MAC的业务流(即64B/66B码块的形式)进行交织，从而形成一路64B/66B码块流。该情况下，发送端可以将第二通道中的各个码块映射至一个或多个第二时隙。
示例性的，下文将以第二通道包括N个第二时隙为例说明图10a所示的方法。
1005、发送端发送64B/66B码块流。
示例性的，该64B/66B码块流可以MTN段层终结层、适配层等进入物理层进行传输。
1006、接收端接收64B/66B码块流。
示例性的，接收端可以从物理层获得该64B/66B码块流。
1007、接收端从捆绑组中的N个第二时隙中解复用第二通道，获得该N个第二时隙中的fgBU码块流。
可理解，这里示出的fgBU码块流指的是接收端接收到的仍然是64B/66B码块的形式。
1008、接收端识别S码块。
对于接收端识别S码块的方法可以参考图9，以及下文示出的方法实施例等，这里不再详述。
1009、接收端解封装fgBU。
接收端从码块流中识别出S码块之后，可以根据该S码块识别以S码块为开始的fgBU。示例性的，接收端可以获得该fgBU中的195个数据码块以及一个T码块。示例性的，接收端识别出S码块之后，可以在MTN通道层从第二通道中的M个第一时隙中解复用第一通道，从而获得以S码块为开始的fgBU。
可理解，这里所示的接收端从第二通道中的M个第一时隙中解复用第一通道，也可以理解为：接收端从第二通道的M个第一时隙中恢复第一通道，从而获得该第一通道中的fgBU。
1010、接收端提取客户信号。
示例性的，接收端从第二通道中的M个第一时隙中解复用第一通道之后，便可以获得该M个第一时隙中每个时隙对应的客户信号。
可理解，接收端提取出客户信号之后，还可以对业务流进行转发或者终结操作等，本申请实施例对此不作限定。
上述步骤1008，接收端识别S码块可以理解为是由接收端的处理器执行，或者，也可以理解为是在接收端的MTN网络中的MTN通道适配层中实现(仅为示例)，或者，也可以理解为是由接收端中的功能或模块或单元执行等，本申请实施例对此不作限定。
作为示例，如图10b所示，接收端识别S码块的功能模块可以包括：模板匹配模块，模板存储模块，检验窗口模块。该模板存储模块中保存着识别第一码块为S码块所需要的模板。即该模板存储模块用于存储本申请实施例示出的模板比特图样。检验窗口模块可以用于从第一码块、第二码块或第三码块中提取相应比特，组成待识别比特图样。该模板匹配模块用于将检验窗口内的比特图样(即待识别比特图样)与模板比特图样比较。
由此，接收端可以将符合比较结果预期的第一码块识别为S码块。随着S码块的确定，接收端就可以完成fgBU定帧。从而根据fgBU开始的位置获取该fgBU所封装的时隙数据等。
可理解，图10b所示的各个模块仅为示例，本申请实施例对此不作限定。
为更详细地理解上述方法，以下将提供码块识别方法的具体实施例。可理解，以下各个实施例的执行主语可以理解为是64B/66B码块流的接收端。
在本申请实施例中，第二码块和第三码块可以分别为与第一码块相邻的码块。因此，为便于描述，以下将以第一码块为第i码块，第二码块为第i-1码块，第三码块为第i+1码块为例，说明本申请实施例提供的码块识别方法。
实施例一、
图11是本申请实施例提供的一种码块识别方法的流程示意图，如图11所示，该方法包括：
1101、接收端从N个5Gbps中恢复出码块流。
可理解，对于接收端如何从N个5Gbps中恢复出码块流，可以参考上文，这里不再详述。
1102、接收端从码块流中获取第i码块。
在一种可能的实现方式中，接收端可以以固定的周期从码块流中获取一个码块(即第i码块)。
在另一种可能的实现方式中，接收端可以根据码组的预设长度从码块流中获取第i码块。例如，码组包括197个码块时，该接收端可以根据该码组的长度，每197个码块获取一个码块(即第i码块)。
在又一种可能的实现方式中，接收端还可以根据已知码块的同步头等从码块流中获取第i码块。例如，接收端已经获知某个码块的同步头为0b10，则该某个码块即可以为第i码块。获知，该某个码块的前一个码块或下一个码块等也可以为第i码块等。
可理解，上述示出的接收端从码块流中获取第i码块，也可以理解为：接收端开始对对i码块进行识别；或者，接收端从码块流中搜索第i码块等。
可理解，本申请实施例对于接收端以何种方式获取第i码块不作限定。
1103、接收端判断第i码块的同步头是否为0b10，如果是，则执行步骤1105；否则，执行步骤1104。
1104、接收端确定第i码块不为S码块，即第i码块无法被识别为S码块。
可理解，在第i码块无法被识别为S码块的情况下，该接收端可以停止搜索码块。或者，接收端还可以开始下一个码块的搜索等，本申请实施例对此不作限定。
1105、接收端获取第i码块的第2个比特至第9个比特，得到待识别比特图样。
结合图10b所示的识别S码块的模块示意图，接收端可以通过检测窗口模块获取第i码块的第2个比特至第9个比特。
1106、接收端将待识别比特图样与模板比特图样进行对比，获得不一致的比特数。并判断不一致的比特数是否小于或等于K比特，如果是，则执行步骤1107；否则，执行步骤1108。
可理解，接收端可以将待识别比特图样与模板比特图样在对应位置上进行对比。以及该模板比特图样可以为S码块的比特图样。例如，模板比特图样可以为S码块的第2个比特至第9个比特对应的模板比特图样。又例如，模板比特图样还可以为S码块的第0个比特至第65个比特对应的模板比特图样。但是在对比时，由于接收端获取的是第i码块的第2比特至第9比特，因此，接收端需要将第i码块的第2比特至第9比特依次与S码块的第2比特至第9比特对比。可理解，对于模板比特图样的说明，下文示出的各个实施例同样适用。
本申请实施例中，接收端还可以获取第i码块的更多比特，如获取第i码块的第2个比特至第65个比特等；或者，获取第i码块的第2个比特至第17个比特。
可选的，接收端还可以不执行上述步骤1103，而是直接获取第i码块的第0个比特至第9个比特等，本申请实施例对此不作限定。
1107、不一致的比特数小于或等于K比特(如K＝2)，接收端确定第i码块为S码块。
1108、不一致的比特数大于K比特，接收端确定第i不能被识别为S码块。
可理解，对于接收端识别出S码块，从第二通道中解复用第一通道的具体实现，可以参考上文，这里不再详述。
本申请实施例中，接收端通过获取第i码块，对该第i码块进行S码块的识别。从而，即使是第i码块的比特图样与S码块的比特图样不完全一致，只要待识别比特图样与模板比特图样在对应位置不一致的比特数小于或等于K比特，该第i码块仍可以被识别为S码块。该方法不仅实施方便简单，而且有效提高了系统的容错性。
实施例二、
图12a是本申请实施例提供的一种码块识别方法的流程示意图，如图12a所示，该码块识别方法包括：
1201、接收端从N个5Gbps中恢复出码块流。
1202、接收端从码块流中获取第i码块和第i-1码块。
在一种可能的实现方式中，接收端可以从码块流中获取相邻的两个码块，该相邻的两个码块分别为第i-1码块和第i码块。
在另一种可能的实现方式中，接收端可以从码块流中获取一个码块，即第i码块。然后再获取该第i码块的上一个码块，即第i-1码块。
在又一种可能的实现方式中，接收端还可以根据已被识别为不是S码块的码块获取第i码块和第i-1码块。对于该种实现方式可以参考图12b所示的方法，示例性的，对于该实现方式可以适应性参考图12b中的步骤1213等。
1203、接收端根据第i码块的前P个比特与第i-1码块的前Q个比特确定待识别比特图样。
示例性的，接收端获取第i码块和第i-1码块后，可以获取第i码块的前P个比特，以及第i-1码块的前Q个比特。又或者，接收端也可能已对第i-1码块进行识别，该情况下，接收端已经获得了第i-1码块的比特图样。由此，接收端便可以获取第i码块的前P个比特。从而， 根据该第i码块的前P个比特以及第i-1码块的前Q个比特，组成待识别比特图样。该P为大于或等于2的整数，该Q为大于或等于2的整数。
例如，P＝Q＝10时，待识别比特图样内的第0比特至第9比特可以依次为第i-1码块的前10个比特，该待识别比特图样内的第10比特至第19比特可以依次为第i码块的前10个比特。
1204、接收端将待识别比特图样与模板比特图样进行对比，获得不一致的比特数。并判断不一致的比特数是否小于或等于K比特，如果是，则执行步骤1205；否则，执行步骤1206。
示例性的，模板比特图样可以如图7a所示。
1205、不一致的比特数小于或等于K比特(例如K＝2)，接收端确定第i码块为S码块。
1206、不一致的比特数大于K比特，接收端确定第i不能被识别为S码块。
本申请实施例提供的方法，可以进一步提高系统的容错性。
实施例三、
1211、接收端从N个5Gbps中恢复出码块流。
1212、接收端从码块流中获取第i码块。
1213、接收端判断第i码块的同步头是否为0b10，如果是，则执行步骤1215；否则，执行步骤1214。
1214、接收端确定第i码块不为S码块，即第i码块无法被识别为S码块。
该接收端在识别第i码块不为S码块的情况下，还可以保存该第i码块的至少两个比特。示例性的，接收端可以保存该第i码块的同步头。或者，该接收端还可以保存该第i码块的第0个比特至第9个比特。或者，该接收端还可以保存该第i码块的第0个比特至第66个比特等。通过保存该第i码块的至少两个比特，一方面，可使得接收端后续需要使用该第i码块的至少两个比特时，直接获取保存的第i码块的至少两个比特。另一方面，通过保存该第i码块的至少两个比特，还可以为接收端后续识别第i+1码块等提供有益信息。可理解，关于保存第i码块的说明，本申请示出的其他实施例，同样适用。
1215、接收端获取第i码块的第2个比特至第9个比特，得到待识别比特图样。
1216、接收端将待识别比特图样与模板比特图样进行对比，获得不一致的比特数。并判断不一致的比特数是否小于或等于K比特，如果是，则执行步骤1217；否则，执行步骤1218。
示例性的，模板比特图样可以如图6a或图6b所示。
1217、接收端获取第i-1码块的第0个比特和第1个比特。
示例性的，该接收端还可以获取该第i-1码块的第0个比特至第9个比特等，本申请实施例对此不作限定。
1218、接收端确定第i码块不为S码块。
1219、根据该第i-1码块的第0个比特和第1个比特，判断该第i-1码块的同步头是否为0b01；如果否，则执行步骤1220；如果是，执行步骤1221。
可理解，本申请实施例中，当第i-1码块的同步头为0b01时，则说明该第i-1码块是数据码块，则第一码块不可能为S码块。而当第i-1码块不为数据码块，如第i-1码块为错误码块、T码块或O码块等，则说明第i码块可以为S码块。
可理解，本申请实施例对于步骤1217与步骤1216或步骤1215等的先后顺序不作限定。例如，接收端还可以同时执行步骤1215和步骤1217等，本申请实施例对此不作限定。
1220、接收端确定第i码块为S码块。
1221、接收端确定第i码块不为S码块。
可理解，该情况下，接收端还可以保存第i-1码块的第2个比特至第9个比特，或者第i码块的第2个比特至第9个比特等。
本申请实施例中，接收端通过将第i码块的比特图样与模板比特图样进行对比，就可以确定该第i码块是否可以被识别为S码块。进一步地，通过判断第i-1码块是否为控制码块，可以进一步提高第i码块被识别为S码块的准确度和可靠性，同时还能够保证系统的容错性。
可理解，本申请实施例示出的方法同样适用于第i码块和第i+1码块的实施例，为避免赘述，下文不再详细说明。
实施例四、
图13是本申请实施例提供的一种码块识别方法的流程示意图，如图13所示，该方法包括：
1301、接收端从N个5Gbps中恢复出码块流。
1302、接收端从码块流中获取第i码块和第i+1码块。
可理解，对于接收端获取第i码块和第i+1码块的具体说明，可以参考上文示出的步骤1202的说明，这里不再详述。
1303、接收端根据第i码块的前P个比特与第i+1码块的前Q个比特确定待识别比特图样。
1304、接收端将待识别比特图样与模板比特图样进行对比，获得不一致的比特数。并判断不一致的比特数是否小于或等于K比特，如果是，则执行步骤1305；否则，执行步骤1306。
示例性的，模板比特图样可以如图7b所示。
1305、不一致的比特数小于或等于K比特(例如K＝2)，接收端确定第i码块为S码块。
1306、不一致的比特数大于K比特，接收端确定第i不能被识别为S码块。
可理解，对于图13的具体描述可以参考图11、图12a或图12b中的描述等，这里不再详述。
实施例五、
图14是本申请实施例提供的一种码块识别方法的流程示意图，如图14所示，该方法包括：
1401、接收端从N个5Gbps中恢复出码块流。
1402、接收端从码块流中获取第i-1码块、第i码块和第i+1码块。
可理解，对于接收端获取第i-1码块、第i码块和第i+1码块的具体说明，可以参考上文示出的步骤1202等的说明，这里不再详述。
1403、接收端根据第-1码块的前R个比特、第i码块的前P个比特与第i+1码块的前Q个比特确定待识别比特图样。
1404、接收端将待识别比特图样与模板比特图样进行对比，获得不一致的比特数。并判断不一致的比特数是否小于或等于K比特，如果是，则执行步骤1405；否则，执行步骤1406。
示例性的，当R＝P＝Q＝10时，该模板比特图样可以如图7c所示。可理解，本申请实施例示出的P、Q或R仅为示例，对于其具体取值，本申请实施例不作限定。
1405、不一致的比特数小于或等于K比特(例如K＝2)，接收端确定第i码块为S码块。
1406、不一致的比特数大于K比特，接收端确定第i不能被识别为S码块。
本申请实施例中，接收端通过获取第i码块，以及与第i码块相邻的两个码块，从而结合 模板比特图样对第i码块是否为S码块进行判断，有效提高了判断第i码块为S码块的准确性，同时提高了系统的容错性。
可理解，以上所示的各个实施例中，其中一个实施例中未详尽描述的实现方式，可以参考另一个实施例的描述，这里不作详述。或者，本文中描述的各个实施例可以为独立的方案，也可以根据内在逻辑进行组合，这些方案都落入本申请的保护范围中。换句话说，以上所示的各个实施例相互之间可以结合。
以下将介绍本申请实施例提供的通信装置。
图15是本申请实施例提供的一种通信装置的结构示意图，该通信装置可以用于执行上述方法实施例中如图9、图10a、图11、图12a、图12b、图13或图14所示的方法。示例性的，该通信装置可以为任意形态的交换机(或者称为交换设备、交换芯片等)、路由器或网卡等等，本申请实施例对于该通信装置的具体形态不作的。如图15所示，该通信装置包括：处理单元1501和收发单元1502。
收发单元1502，用于获取码块流，该码块流中包括第一码块；
处理单元1501，用于确定待识别比特图样，以及对比该待识别比特图样和模板比特图样，获得不一致的比特数；在该不一致的比特数小于或等于第一阈值的情况下，识别第一码块是第一边界码块。
在一种可能的实现方式中，处理单元1501，具体用于在不一致的比特数大于或等于1，且该不一致的比特数小于或等于第一阈值的情况下，识别第一码块是第一边界码块。
示例性的，第二阈值可以为2或1等，本申请实施例对此不作限定。
在一种可能的实现方式中，处理单元1501，具体用于在第一比特图样与第一模板比特图样不一致，且待识别比特图样与模板比特图样的不一致的比特数小于或等于第一阈值的情况下，识别第一码块是第一边界码块。
在一种可能的实现方式中，处理单元1501，具体用于确定第二比特图样，该第二比特图样为第二码块对应的比特图样；对比第二比特图样与第二模板比特图样；在不一致的比特数小于或等于第一阈值，且第二比特图样与第二模板比特图样的不一致的比特数小于或等于第二阈值的情况下，识别第一码块是第一边界码块。
在一种可能的实现方式中，处理单元1501，具体用于确定第二比特图样，对比第二比特图样与第二模板比特图样，在待识别比特图样与模板比特图样的不一致的比特数小于或等于第一阈值，且在第二比特图样与第二模板比特图样不一致，识别第一码块是第一边界码块。
在一种可能的实现方式中，处理单元1501，具体用于根据第一码块从码块流中确定第一码组，该第一码组以第一码块开始。
可理解，关于第一比特图样、第二比特图样、第三比特图样、待识别比特图样、模板比特图样、第一码块、第二码块、第三码块以及第一边界码块等的描述，可以参考前述各个实施例等，这里不再详述。
示例性的，收发单元1502可以用于执行图9中的步骤901，处理单元1501可以用于执行图9中的步骤902至步骤904。
示例性的，收发单元1502还可以用于执行图10a中的步骤1006，处理单元1501还可以用于执行图10a中的步骤1007至步骤1010。
示例性的，处理单元1501还可以用于执行图11中的步骤1101至步骤1108。
可理解，对于收发单元和处理单元的其他功能或步骤等，可以参考上述方法实施例，这 里不再一一列举。
本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，另外，在本申请各个实施例中的各功能模块或单元可以集成在一个处理器中，也可以是单独物理存在，也可以两个或两个以上模块或单元集成在一个模块或单元中。上述集成的模块或单元既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
以上介绍了本申请实施例的通信装置，以下介绍所述通信装置可能的产品形态。应理解，但凡具备上述图15所述的通信装置的功能的任何形态的产品，都落入本申请实施例的保护范围。还应理解，以下介绍仅为举例，不限制本申请实施例的通信装置的产品形态仅限于此。
在一种可能的实现方式中，当图15所示的通信装置是任意形态的交换机、路由器或网卡等；或者是任意形态的交换机、路由器或网卡等中的装置，或者是与任意形态的交换机、路由器或网卡等匹配使用的装置时，处理单元1501可以是一个或多个处理器，收发单元1502可以是收发器，或者收发单元1502还可以是发送单元和接收单元，发送单元可以是发送器，接收单元可以是接收器，该发送单元和接收单元集成于一个器件，例如收发器。本申请实施例中，处理器和收发器可以被耦合等，对于处理器和收发器的连接方式，本申请实施例不作限定。
如图16所示，该通信装置160包括一个或多个处理器1620和收发器1610。
本申请实施例中，该处理器1620和该收发器1610可以用于执行上述通信装置或接收端执行的方法。
示例性的，收发器1610可以用于接收码块流，处理器1620可以用于对码块流中的第一码块进行识别等。
可理解，关于第一比特图样、第二比特图样、第三比特图样、待识别比特图样、模板比特图样、第一码块、第二码块、第三码块以及第一边界码块等的描述，可以参考前述各个实施例等，这里不再详述。
可理解，对于收发器和/或处理器执行的功能或操作等，可以参考图15示出的各个实施例，或者，还可以参考图9、图10a、图11、图12a、图12b、图13或图14所示的方法实施例，这里不再一一详述。
在图16所示的通信装置的各个实现方式中，收发器可以包括接收机和发射机，该接收机用于执行接收的功能(或操作)，该发射机用于执行发射的功能(或操作)。以及收发器用于通过传输介质和其他设备/装置进行通信。
可选的，通信装置160还可以包括一个或多个存储器1630，用于存储程序指令和/或数据。存储器1630和处理器1620耦合。本申请实施例中的耦合是装置、单元或模块之间的间接耦合或通信连接，可以是电性，机械或其它的形式，用于装置、单元或模块之间的信息交互。处理器1620可能和存储器1630协同操作。处理器1620可能执行存储器1630中存储的程序指令。可选的，上述一个或多个存储器中的至少一个可以包括于处理器中。
本申请实施例中不限定上述收发器1610、处理器1620以及存储器1630之间的具体连接介质。本申请实施例在图16中以存储器1630、处理器1620以及收发器1610之间通过总线1640连接，总线在图16中以粗线表示，其它部件之间的连接方式，仅是进行示意性说明，并不引以为限。所述总线可以分为地址总线、数据总线、控制总线等。为便于表示，图16中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
在本申请实施例中，处理器可以是通用处理器、数字信号处理器、专用集成电路、现场 可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等，可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成等。
本申请实施例中，存储器可包括但不限于硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)等非易失性存储器，随机存储记忆体(random access memory，RAM)、可擦除可编程只读存储器(erasable programmable ROM，EPROM)、只读存储器(read-only memory，ROM)或便携式只读存储器(compact disc read-only memory，CD-ROM)等等。存储器是能够用于携带或存储具有指令或数据结构形式的程序代码，并能够由计算机(如本申请示出的通信装置等)读和/或写的任何存储介质，但不限于此。本申请实施例中的存储器还可以是电路或者其它任意能够实现存储功能的装置，用于存储程序指令和/或数据。
可理解，本申请实施例示出的通信装置还可以具有比图16更多的元器件等，本申请实施例对此不作限定。以上所示的处理器和收发器所执行的方法仅为示例，对于该处理器和收发器具体所执行的步骤可参照上文介绍的方法。
可理解，本申请实施例示出的通信装置还可以具有比图16更多的元器件等，本申请实施例对此不作限定。
可理解，以上所示的处理器和收发器所执行的方法仅为示例，对于该处理器和收发器具体所执行的步骤可参照上文介绍的方法。
在另一种可能的实现方式中，当上述通信装置是芯片系统，如交换机(或者称为交换设备、交换芯片等)、路由器、网卡等中的芯片系统时，处理单元1501可以是一个或多个逻辑电路，收发单元1502可以是输入输出接口，又或者称为通信接口，或者接口电路，或接口等等。或者收发单元1502还可以是发送单元和接收单元，发送单元可以是输出接口，接收单元可以是输入接口，该发送单元和接收单元集成于一个单元，例如输入输出接口。如图17所示，图17所示的通信装置包括逻辑电路1701和接口1702。即上述处理单元1501可以用逻辑电路1701实现，收发单元1502可以用接口1702实现。其中，该逻辑电路1701可以为芯片、处理电路、集成电路或片上系统(system on chip，SoC)芯片等，接口1702可以为通信接口、输入输出接口等。本申请实施例中，逻辑电路和接口还可以相互耦合。对于逻辑电路和接口的具体连接方式，本申请实施例不作限定。
本申请实施例中，该逻辑电路和该接口可以用于执行上述通信装置或接收端执行的功能或操作等。
示例性的，接口1702，用于输入码块流，该码块流中包括第一码块等。逻辑电路1701，用于确定待识别比特图样，以及对比该待识别比特图样和模板比特图样，获得不一致的比特数；在该不一致的比特数小于或等于第一阈值的情况下，识别第一码块是第一边界码块。
可理解，关于逻辑电路和接口的具体实现方式，还可以参考上述各个实施例，这里不再一一举例。
可理解，关于第一比特图样、第二比特图样、第三比特图样、待识别比特图样、模板比特图样、第一码块、第二码块、第三码块以及第一边界码块等的描述，可以参考前述各个实施例等，这里不再详述。
此外，本申请还提供一种计算机程序，该计算机程序用于实现本申请提供的方法中由通 信装置或接收端执行的操作和/或处理。
本申请还提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机代码，当计算机代码在计算机上运行时，使得计算机执行本申请提供的方法中由通信装置或接收端执行的操作和/或处理。
本申请还提供一种计算机程序产品，该计算机程序产品包括计算机代码或计算机程序，当该计算机代码或计算机程序在计算机上运行时，使得本申请提供的方法中由通信装置或接收端执行的操作和/或处理被执行。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例提供的方案的技术效果。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个可读存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的可读存储介质包括：U盘、移动硬盘、只读存储器(read-only memory,ROM)、随机存取存储器(random access memory,RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (34)

  1. 一种码块识别方法，其特征在于，所述方法包括：
    获取码块流，所述码块流包括第一码块；
    确定待识别比特图样，所述待识别比特图样包括第一比特图样，所述第一比特图样为所述第一码块对应的比特图样；
    对比所述待识别比特图样与模板比特图样，获得不一致的比特数，所述模板比特图样包括第一模板比特图样，所述第一模板比特图样为第一边界码块对应的模板比特图样；
    在所述不一致的比特数小于或等于第一阈值的情况下，识别所述第一码块是所述第一边界码块。
  2. 根据权利要求1所述的方法，其特征在于，所述第一比特图样包括所述第一码块的第0个比特至第9个比特构成的图样，所述第一码块的起始比特为所述第0个比特。
  3. 根据权利要求2所述的方法，其特征在于，所述第一码块的第0个比特和所述第一码块的第1个比特为所述第一码块的同步头，所述第一码块的第2个比特至所述第一码块的第9个比特为所述第一码块的控制块类型域。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，在所述不一致的比特数小于或等于第一阈值的情况下，识别所述第一码块是所述第一边界码块，包括：
    在所述第一比特图样与所述第一模板比特图样不一致，且所述不一致的比特数小于或等于所述第一阈值的情况下，识别所述第一码块是所述第一边界码块。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述码块流还包括第二码块，所述待识别比特图样还包括第二比特图样，所述第二比特图样为所述第二码块对应的比特图样；
    所述模板比特图样还包括第二模板比特图样，所述第二模板比特图样与所述第二比特图样对应。
  6. 根据权利要求5所述的方法，其特征在于，所述第二模板比特图样为以下任一项码块对应的模板比特图样：
    第二边界码块、空闲码块、序列码块、信号码块、错误码块。
  7. 根据权利要求5或6所述的方法，其特征在于，所述第二比特图样包括所述第二码块的第0个比特至第9个比特构成的图样，所述第二码块的起始比特为所述第0个比特。
  8. 根据权利要求1-7任一项所述的方法，其特征在于，所述码块流还包括第三码块，所述待识别比特图样还包括第三比特图样，所述第三比特图样为所述第三码块对应的比特图样；
    所述模板比特图样还包括第三模板比特图样，所述第三模板比特图样与所述第三比特图样对应。
  9. 根据权利要求8所述的方法，其特征在于，所述第三模板比特图样为数据码块对应的模板比特图样。
  10. 根据权利要求5-9任一项所述的方法，其特征在于，所述在所述不一致的比特数小于或等于第一阈值的情况下，识别所述第一码块是所述第一边界码块，包括：
    在所述第一比特图样与所述第一模板比特图样一致，且所述不一致的比特数小于或等于所述第一阈值的情况下，识别所述第一码块是所述第一边界码块。
  11. 根据权利要求1-4任一项所述的方法，其特征在于，所述在所述不一致的比特数小于或等于第一阈值的情况下，识别所述第一码块是所述第一边界码块，包括：
    确定第二比特图样，所述第二比特图样为第二码块对应的比特图样；
    对比所述第二比特图样与第二模板比特图样；
    在所述不一致的比特数小于或等于所述第一阈值，且所述第二比特图样与所述第二模板比特图样一致的情况下，识别所述第一码块是所述第一边界码块。
  12. 根据权利要求1-11任一项所述的方法，其特征在于，所述识别所述第一码块是所述第一边界码块之后，所述方法还包括：
    根据所述第一码块从所述码块流中确定第一码组，所述第一码组以所述第一码块开始。
  13. 根据权利要求12所述的方法，其特征在于，所述第一码组包括195个数据码块和一个结束码块。
  14. 根据权利要求12或13所述的方法，其特征在于，所述第一码组承载T个客户信号，所述T为正整数。
  15. 根据权利要求14所述的方法，其特征在于，T＝24。
  16. 一种通信装置，其特征在于，包括：
    收发单元，用于获取码块流，所述码块流包括第一码块；
    处理单元，用于确定待识别比特图样，所述待识别比特图样包括第一比特图样，所述第一比特图样为所述第一码块对应的比特图样；
    所述处理单元，还用于对比所述待识别比特图样与模板比特图样，获得不一致的比特数，所述模板比特图样包括第一模板比特图样，所述第一模板比特图样为第一边界码块对应的模板比特图样；
    所述处理单元，还用于在所述不一致的比特数小于或等于第一阈值的情况下，识别所述第一码块是所述第一边界码块。
  17. 根据权利要求16所述的装置，其特征在于，所述第一比特图样包括所述第一码块的第0个比特至第9个比特构成的图样，所述第一码块的起始比特为所述第0个比特。
  18. 根据权利要求17所述的装置，其特征在于，所述第一码块的第0个比特和所述第一码块的第1个比特为所述第一码块的同步头，所述第一码块的第2个比特至所述第一码块的第9个比特为所述第一码块的控制块类型域。
  19. 根据权利要求16-18任一项所述的装置，其特征在于，
    所述处理单元，具体用于在所述第一比特图样与所述第一模板比特图样不一致，且所述不一致的比特数小于或等于所述第一阈值的情况下，识别所述第一码块是所述第一边界码块。
  20. 根据权利要求16-19任一项所述的装置，其特征在于，所述码块流还包括第二码块，所述待识别比特图样还包括第二比特图样，所述第二比特图样为所述第二码块对应的比特图样；
    所述模板比特图样还包括第二模板比特图样，所述第二模板比特图样与所述第二比特图样对应。
  21. 根据权利要求20所述的装置，其特征在于，所述第二模板比特图样为以下任一项码块对应的模板比特图样：
    第二边界码块、空闲码块、序列码块、信号码块、错误码块。
  22. 根据权利要求20或21所述的装置，其特征在于，所述第二比特图样包括所述第二码块的第0个比特至第9个比特构成的图样，所述第二码块的起始比特为所述第0个比特。
  23. 根据权利要求16-22任一项所述的装置，其特征在于，所述码块流还包括第三码块，所述待识别比特图样还包括第三比特图样，所述第三比特图样为所述第三码块对应的比特图 样；
    所述模板比特图样还包括第三模板比特图样，所述第三模板比特图样与所述第三比特图样对应。
  24. 根据权利要求23所述的装置，其特征在于，所述第三模板比特图样为数据码块对应的模板比特图样。
  25. 根据权利要求20-24任一项所述的装置，其特征在于，
    所述处理单元，具体用于在所述第一比特图样与所述第一模板比特图样一致，且所述不一致的比特数小于或等于所述第一阈值的情况下，识别所述第一码块是所述第一边界码块。
  26. 根据权利要求16-19任一项所述的装置，其特征在于，
    所述处理单元，具体用于确定第二比特图样，所述第二比特图样为第二码块对应的比特图样；以及对比所述第二比特图样与第二模板比特图样；在所述不一致的比特数小于或等于所述第一阈值，且所述第二比特图样与所述第二模板比特图样一致的情况下，识别所述第一码块是所述第一边界码块。
  27. 根据权利要求16-26任一项所述的装置，其特征在于，
    所述处理单元，还用于根据所述第一码块从所述码块流中确定第一码组，所述第一码组以所述第一码块开始。
  28. 根据权利要求27所述的装置，其特征在于，所述第一码组包括195个数据码块和一个结束码块。
  29. 根据权利要求27或28所述的装置，其特征在于，所述第一码组承载T个客户信号，所述T为正整数。
  30. 根据权利要求29所述的装置，其特征在于，T＝24。
  31. 一种通信装置，其特征在于，包括处理器和存储器；
    所述存储器用于存储计算机程序；
    所述处理器用于执行所述计算机程序，使得如权利要求1-15任一项所述的方法被执行。
  32. 一种通信装置，其特征在于，包括逻辑电路和接口，所述逻辑电路和所述接口耦合；
    所述接口用于输入待处理的数据，所述逻辑电路按照如权利要求1-15任一项所述的方法对所述待处理的数据进行处理，获得处理后的数据，所述接口用于输出所述处理后的数据。
  33. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质用于存储计算机程序，当所述计算机程序被执行时，如权利要求1-15任一项所述的方法被执行。
  34. 一种计算机程序，其特征在于，所述计算机程序被执行时，如权利要求1-15任一项所述的方法被执行。
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