WO2022111101A1

WO2022111101A1 - Display substrate and driving method therefor, and display device

Info

Publication number: WO2022111101A1
Application number: PCT/CN2021/123630
Authority: WO
Inventors: 袁粲; 李永谦; 袁志东
Original assignee: 京东方科技集团股份有限公司; 合肥京东方卓印科技有限公司
Priority date: 2020-11-25
Filing date: 2021-10-13
Publication date: 2022-06-02
Also published as: US20230080385A1; US11854509B2; CN112435622B; CN112435622A

Abstract

Provided is a display substrate provided with a display area and a peripheral area. The display substrate comprises: multiple sub-pixels, multiple groups of gate scanning signal lines, and multiple groups of data lines which are provided in the display area; each group of gate scanning signal lines comprise at least one gate scanning signal line; each group of data lines comprise n data lines; the multiple sub-pixels are arranged in an array; wherein n≥2; one group of gate scanning signal lines is electrically connected to n rows of sub-pixels; one column of sub-pixels is electrically connected to one group of data lines and comprises multiple groups of sub-pixels; each group of sub-pixels comprises n sub-pixels; and the n sub-pixels are respectively, correspondingly, and electrically connected to n data lines of one group of data lines electrically connected to the column of sub-pixels.

Description

Display substrate and driving method thereof, and display device

This application claims the priority of the Chinese Patent Application No. 202011339522.6 filed on November 25, 2020, the entire contents of which are incorporated herein by reference.

technical field

The present disclosure relates to the field of display technology, and in particular, to a display substrate, a driving method thereof, and a display device.

Background technique

In the field of display technology, GOA (Gate Diver on Array) technology is a technology in which the gate scanning driving circuit is made on one side or both sides of the effective display area on the array substrate. Compared with the traditional gate driving circuit chip, the GOA technology can effectively reduce the area of the frame and realize narrow frame display.

SUMMARY OF THE INVENTION

In one aspect, a display substrate is provided, which has a display area and a peripheral area, and the display substrate includes: a plurality of sub-pixels disposed in the display area, a plurality of groups of gate scanning signal lines and a plurality of groups of data lines; each group of the gate scanning signal lines includes at least one gate scanning signal line, each group of data lines includes n data lines, and the plurality of sub-pixels are arranged in an array; n≥2; wherein, one group of gate scanning signal lines is electrically connected to n rows of sub-pixels; A column of sub-pixels is electrically connected to a group of data lines; a column of sub-pixels includes multiple groups of sub-pixels, each group of sub-pixels includes n sub-pixels, and the n sub-pixels respectively correspond to a group of data lines electrically connected to the column of sub-pixels The n data lines are electrically connected.

In some embodiments, each adjacent n rows of sub-pixels are electrically connected to a group of gate scanning signal lines; in a column of sub-pixels, the n sub-pixels included in each group of sub-pixels are adjacent n sub-pixels, and the n sub-pixels are adjacent to each other. The i-th sub-pixel in the sub-pixels is electrically connected to the i-th data line among the n data lines electrically connected to the sub-pixels in the column; wherein, 1≤i≤n.

In some embodiments, a group of gate scanning signal lines is electrically connected to two adjacent rows of sub-pixels; a column of sub-pixels is electrically connected to two data lines, and the odd-numbered sub-pixels in a column of sub-pixels are electrically connected to the two data lines. One of the data lines is electrically connected, and the even-numbered sub-pixels are electrically connected with another data line.

In some embodiments, each group of gate scan signal lines is disposed between two adjacent rows of sub-pixels to which it is electrically connected.

In some embodiments, each group of gate scanning signal lines includes 2-4 gate scanning signal lines; each gate scanning signal line is electrically connected to corresponding n rows of sub-pixels.

In some embodiments, each sub-pixel includes a pixel driving circuit; a set of gate scanning signal lines are electrically connected to the pixel driving circuits of the N rows of sub-pixels, and a set of data lines are electrically connected to the pixel driving circuits of a column of sub-pixels; The pixel driving circuit includes a data writing sub-circuit; the data writing sub-circuit is electrically connected to a gate scanning signal line in a group of gate scanning signal lines, and a gate scanning signal line in a group of data lines electrically connected to the sub-pixel. A data line is electrically connected; the data writing sub-circuit is configured to, under the control of the gate scanning signal transmitted by the gate scanning signal line, write the data signal received at the data line to the gate scanning signal line. in the pixel driver circuit.

In some embodiments, the display substrate further includes: a plurality of first voltage signal lines, a plurality of second voltage signal lines and a plurality of initialization signal lines disposed in the display area. Each group of gate scanning signal lines includes a first gate scanning signal line, a second gate scanning signal line, a third gate scanning signal line and a fourth gate scanning signal line; the first gate scanning signal line, The second gate scanning signal line, the third gate scanning signal line and the fourth gate scanning signal line are all electrically connected to the corresponding n rows of sub-pixels; the pixel driving circuit of each sub-pixel is connected to a first a voltage signal line, a second voltage signal line, an initialization signal line, the first gate scanning signal line, the second gate scanning signal line, the third gate scanning signal line and the first gate scanning signal line The four-gate scanning signal lines are electrically connected; the sub-pixel further includes a light-emitting device electrically connected to the pixel driving circuit.

In some embodiments, the pixel driving circuit further includes: a first reset subcircuit, a second reset subcircuit, a driving subcircuit, a light emission control subcircuit, and a storage subcircuit. The first reset sub-circuit is electrically connected to the first node, the initialization signal line and the second gate scan signal line; the first reset sub-circuit is configured to Under the control of the second gate scan signal transmitted by the line, the initialization signal received at the initialization signal line is transmitted to the first node; the second reset sub-circuit is connected to a first voltage signal line, a second The node is electrically connected to the fourth gate scanning signal line; the second reset sub-circuit is configured to, under the control of the fourth gate scanning signal transmitted by the fourth gate scanning signal line, The first voltage signal received at the first voltage signal line is transmitted to the second node.

One gate scanning signal line electrically connected to the data writing sub-circuit is the first gate scanning signal line, and the data writing sub-circuit is also electrically connected to the third node; the data writing sub-circuit is electrically connected to the third node; is configured to transmit the data signal received at the data line to the third node under the control of the first gate scan signal transmitted by the first gate scan signal line. The driving sub-circuit is electrically connected to the second node, the third node, the fourth node and the second gate scanning signal line; the driving sub-circuit is configured to be connected to the second gate Under the control of the second gate scan signal transmitted by the scan signal line, the first voltage signal at the second node is transmitted to the fourth node, and the data signal at the third node is transmitted to the fourth node. the fourth node, and under the voltage control of the fourth node, a driving current is generated and transmitted to the third node.

The storage sub-circuit is electrically connected to the first node and the fourth node; the storage sub-circuit is configured to store the voltage of the fourth node and the voltage of the first node, and store the voltage of the fourth node and the voltage of the first node at the Under the action of the voltage of the first node, the potential of the fourth node is changed. The light-emitting control sub-circuit is electrically connected to the first node, the third node and the third gate scan signal line; the light-emitting control sub-circuit is configured to scan the signal at the third gate The driving current received at the third node is transmitted to the first node under the control of the third gate scan signal transmitted by the line. The light emitting device is electrically connected to the first node and a second voltage signal line; the light emitting device is configured to emit light under the control of a drive current received at the first node.

In some embodiments, the first reset sub-circuit includes a first transistor; a control electrode of the first transistor is electrically connected to the second gate scan signal line, and a first electrode of the first transistor is connected to the second gate scan signal line. The initialization signal line is electrically connected, and the second electrode of the first transistor is connected to the first node. The second reset sub-circuit includes a second transistor; the control electrode of the second transistor is electrically connected to the fourth gate scanning signal line, and the first electrode of the second transistor is connected to the first voltage signal line electrically connected, and the second electrode of the second transistor is electrically connected to the second node.

The data writing sub-circuit includes a third transistor; the control electrode of the third transistor is electrically connected to the first gate scanning signal line, and the first electrode of the third transistor is electrically connected to the data line, The second electrode of the third transistor is electrically connected to the third node. The driving sub-circuit includes a fourth transistor and a fifth transistor; the control electrode of the fourth transistor is electrically connected to the fourth node, the first electrode of the fourth transistor is electrically connected to the second node, and the The second electrode of the fourth transistor is electrically connected to the third node; the control electrode of the fifth transistor is electrically connected to the second gate scanning signal line, and the first electrode of the fifth transistor is electrically connected to the second gate scanning signal line. The second node is electrically connected, and the second electrode of the fifth transistor is electrically connected to the fourth node.

The storage subcircuit includes a storage capacitor; a first pole of the storage capacitor is electrically connected to the third node, and a second pole of the storage capacitor is electrically connected to the first node. The light-emitting control sub-circuit includes a sixth transistor; the control electrode of the sixth transistor is electrically connected to the third gate scanning signal line, and the first electrode of the sixth transistor is electrically connected to the third node, The second electrode of the sixth transistor is electrically connected to the first node. The first pole of the light emitting device is electrically connected to the first node, and the second pole of the light emitting device is electrically connected to the second voltage signal line.

In some embodiments, the display substrate further includes: at least one gate driving circuit disposed in the peripheral region; wherein each gate driving circuit includes a plurality of shift registers, each shift register is associated with a set of gate scanning signals At least one gate scan signal line among the lines is electrically connected.

In some embodiments, when each group of gate scanning signal lines includes a first gate scanning signal line, a second gate scanning signal line, a third gate scanning signal line and a fourth gate scanning signal line Next, the at least one gate drive circuit includes four gate drive circuits, each gate drive circuit includes a plurality of shift registers, one shift register of each gate drive circuit and a group of gate scanning signal lines One of the gate scan signal lines is electrically connected. Alternatively, the at least one gate drive circuit includes three gate drive circuits, each gate drive circuit includes a plurality of shift registers; one shift of one gate drive circuit in the three gate drive circuits The register is electrically connected to two gate scanning signal lines in the group of gate scanning signal lines; among the other two gate driving circuits among the three gate driving circuits, one of each gate driving circuit The shift register is electrically connected to one of the other two gate scanning signal lines in a group of gate scanning signal lines.

In some embodiments, the display substrate further includes a plurality of data selectors disposed in the frame area; each data selector is electrically connected to n data lines electrically connected to a column of sub-pixels.

In another aspect, a display device is provided, including the display substrate according to any one of the above.

In some embodiments, the display device further includes a source driver electrically connected to the plurality of data lines in the display substrate.

In another aspect, a method for driving a display substrate is provided, and the driving method is used for driving the display substrate according to any one of the above; wherein, each group of n rows of sub-pixels electrically connected to the gate scanning signal lines is one driver unit. The driving method of the display substrate includes: each group of gate scanning signal lines transmits the gate scanning signal to n rows of sub-pixels included in a driving unit to which it is electrically connected; and n rows of sub-pixels included in each driving unit Under the control of the gate scanning signal, they work simultaneously; multiple groups of gate scanning signal lines sequentially control the sub-pixels of the plurality of driving units to work.

Description of drawings

In order to illustrate the technical solutions in the present disclosure more clearly, the following briefly introduces the accompanying drawings that need to be used in some embodiments of the present disclosure. Obviously, the accompanying drawings in the following description are only the appendixes of some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can also be obtained from these drawings. In addition, the accompanying drawings in the following description may be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present disclosure, the actual flow of the method, the actual timing of signals, and the like.

FIG. 1 is a block diagram of a display device according to some embodiments;

FIG. 2 is a structural diagram of a display substrate according to some embodiments of the prior art;

FIG. 3 is another structural diagram of a display substrate according to some embodiments of the prior art;

4 is a structural diagram of a display substrate according to some embodiments of the present disclosure;

FIG. 5 is another structural diagram of a display substrate according to some embodiments of the present disclosure;

6 is another structural diagram of a display substrate according to some embodiments of the present disclosure;

7 is still another structural diagram of a display substrate according to some embodiments of the present disclosure;

8 is a structural diagram of electrical connection between gate scanning signal lines and pixel driving circuits in a display substrate according to some embodiments of the present disclosure;

9A is another structural diagram of the electrical connection between the gate scanning signal line and the pixel driving circuit in the display substrate according to some embodiments of the present disclosure;

9B is another structural diagram of the electrical connection between the gate scanning signal line and the pixel driving circuit in the display substrate according to some embodiments of the present disclosure;

10 is a driving signal diagram of a pixel driving circuit in a display substrate according to some embodiments of the present disclosure.

Detailed ways

The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided by the present disclosure fall within the protection scope of the present disclosure.

Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms such as the third person singular "comprises" and the present participle "comprising" are used It is interpreted as the meaning of openness and inclusion, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" example)" or "some examples" and the like are intended to indicate that a particular feature, structure, material or characteristic related to the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

Hereinafter, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

In describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited by the content herein.

The use of "adapted to" or "configured to" herein means open and inclusive language that does not preclude devices adapted or configured to perform additional tasks or steps.

Additionally, the use of "based on" is meant to be open and inclusive, as a process, step, calculation or other action "based on" one or more of the stated conditions or values may in practice be based on additional conditions or beyond the stated values.

As shown in FIG. 1 , some embodiments of the present disclosure provide a display device 1000, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a car computer, a wearable The display device and the like can be, for example, a watch. The embodiments of the present disclosure do not specifically limit the specific form of the above-mentioned display device.

In some examples, the display device may be a liquid crystal display device (Liquid Crystal Display, LCD for short); the display device may also be an electroluminescence display device or a photoluminescence display device. In the case where the display device is an electroluminescence display device, the electroluminescence display device may be an organic electroluminescence display device (Organic Light-Emitting Diode, OLED for short) or a quantum dot electroluminescence display device (Quantum Dot Light Emitting). Diodes, referred to as QLED). When the display device is a photoluminescence display device, the photoluminescence display device may be a quantum dot photoluminescence display device.

The display device includes a display substrate 01 . Exemplarily, the display substrate may be a liquid crystal display substrate or an OLED (organic light emitting diode, organic light emitting diode) display substrate.

As shown in FIGS. 2 to 7 , the display substrate 01 includes a display area AA (Active Area, AA area for short; also called an active display area) and a peripheral area BB on at least one side of the display area AA. For example, the peripheral area BB is arranged in a circle around the display area AA.

The display substrate 01 includes a plurality of sub-pixels 10, a plurality of gate scanning signal lines G and a plurality of data lines D arranged in the display area AA, and a plurality of sub-pixels 10, a plurality of gate scanning signal lines G and a plurality of data lines D are arranged On the base substrate 001, the plurality of gate scanning signal lines G include a plurality of scanning timing signal lines and a plurality of light-emitting timing signal lines. Exemplarily, a plurality of gate scanning signal lines G extend along a horizontal direction X, a plurality of data lines D extend along a vertical direction Y, and the plurality of sub-pixels 10 are arranged in an array, for example, the plurality of sub-pixels 10 are arranged in N rows. M columns, at this time, the sub-pixels 10 arranged in a row along the horizontal direction X are called a row of sub-pixels, and the sub-pixels 10 arranged in a row along the vertical direction Y are called a column of sub-pixels.

In the related art, as shown in FIG. 2 , one row of sub-pixels 10 can be coupled to one or more gate scanning signal lines G, and one column of sub-pixels can be coupled to one data signal line D. All the coupled gate scanning signal lines are called a group of gate scanning signal lines (each gate scanning signal line in parentheses in the figure is a group of gate scanning signal lines), that is, a group of gate scanning signal lines The signal lines are coupled to one row of sub-pixels 10, so that when a plurality of sub-pixels 10 are arranged in N rows and M columns, the display substrate 01 includes N groups of gate scanning signal lines G(1)-G(N) and M data lines Lines D(1) to D(M).

In some embodiments, the display substrate 01 further includes at least one gate driving circuit 20 disposed in the peripheral region BB, and the gate driving circuit 20 is integrated in the display substrate 01 by means of GOA (Gate Driver on Array). The gate driving circuit 20 is electrically connected to the plurality of gate scanning signal lines G, and is configured to implement a shift register function, and transmit the plurality of gate scanning signals to the plurality of gate scanning signal lines line by line in one frame period , to drive the plurality of gate scanning signal lines G.

As shown in FIG. 3 , each gate driving circuit 20 includes a plurality of shift registers RS, the plurality of shift registers RS are cascaded in sequence, and each shift register RS is electrically connected to one or two gate scanning signal lines G , each shift register RS corresponds to a row of sub-pixels 10, and is configured to output one or two gate scanning signals corresponding to the row of sub-pixels 10, so that the display substrate 01 includes N rows of sub-pixels 10, N groups of gates In the case of the polar scanning signal line G, each gate drive circuit 20 includes N shift registers RS. The shift register is composed of a plurality of thin film transistors. In the case where the gate drive circuit includes many shift registers, in order to ensure the stability of the characteristics of the thin film transistor, so that the gate drive circuit can normally realize its function, it is necessary to set aside enough The space is used for arranging structures such as thin film transistors included in the gate driving circuit, which results in a larger area of the frame area, which is not conducive to the realization of the ultra-narrow frame of the display substrate.

Based on this, as shown in FIG. 4 and FIG. 6 , the present disclosure provides a display substrate 01 . In the display substrate 01 , a plurality of gate scanning signal lines G and a plurality of data lines D are respectively divided into a plurality of groups, namely The display substrate 01 includes a plurality of groups of gate scanning signal lines and a plurality of groups of data lines, each gate scanning signal line in a bracket in FIG. 4 and FIG. 6 is a group of gate scanning signal lines G(k), a bracket in Each data line of is a group of data lines D-(k), where k is any positive integer between 1 and the maximum value of the group number of gate scanning signal lines. Each group of gate scanning signal lines includes at least one gate scanning signal line, and each group of data lines includes n data lines, where n≥2.

A group of gate scanning signal lines G(k) are electrically connected to the sub-pixels 10 in n rows. That is, a group of gate scanning signal lines G(k) is electrically connected to at least two rows of sub-pixels 10 . Exemplarily, a group of gate scanning signal lines G(k) may be electrically connected to two rows of sub-pixels 10, three rows of sub-pixels 10, or four rows of sub-pixels 10. The n rows of sub-pixels 10 are electrically connected to each other. The positional relationship of the pixels 10 is not limited. For example, a group of gate scanning signal lines G(k) is electrically connected to the adjacent n rows of sub-pixels 10, and may also be electrically connected to n rows of sub-pixels 10 arranged at intervals.

A column of sub-pixels 10 is electrically connected to a set of data lines D-(k); that is, a column of sub-pixels 10 is electrically connected to at least two data lines D. Exemplarily, a column of sub-pixels 10 may be electrically connected with two data lines D, or with three data lines D, or with four data lines D, and a group of data lines D- (k) is, for example, adjacent n data lines D.

A column of sub-pixels 10 includes a plurality of groups of sub-pixels, each group of sub-pixels includes n sub-pixels, and the n sub-pixels respectively correspond to n data lines of a group of data lines D-(k) electrically connected to the column of sub-pixels. connect.

The n sub-pixels included in each group of sub-pixels are electrically connected to the same group of gate scanning signal lines G(k), and the n sub-pixels are electrically connected to n of a group of data lines D-(k) to which the column of sub-pixels is electrically connected The data lines are electrically connected in one-to-one correspondence.

Exemplarily, as shown in FIG. 4 , when n is 2, each group of data lines includes 2 data lines, for example, the first group of data lines D-(1) includes data line D(1) and data line D (2), a group of gate scanning signal lines G(k) is electrically connected to 2 rows of sub-pixels 10, for example, the first group of gate scanning signal lines G(1) is connected to the first row of sub-pixels 10 and the second row of sub-pixels 10 Electrical connections. A column of sub-pixels 10 is electrically connected to a group of data lines D-(k); a column of sub-pixels includes multiple groups of sub-pixels, each group of sub-pixels includes 2 sub-pixels, and the two sub-pixels are connected to the same group of gate scanning signal lines G ( k) Electrical connection, the two sub-pixels are respectively electrically connected to two data lines of a group of data lines D-(k) electrically connected to the column of sub-pixels. In this case, the display substrate includes N/2 groups of gate scanning signal lines.

Or, as shown in FIG. 6 , when n is 3, each group of data lines includes 3 data lines, for example, the first group of data lines D-(1) includes data lines D(1), data lines D(2 ) and the data line D(3), a group of gate scanning signal lines G(k) are electrically connected to 3 rows of sub-pixels 10, for example, the first group of gate scanning signal lines G(1) are connected to the first row of sub-pixels 10, The sub-pixels 10 in the second row and the sub-pixels 10 in the third row are electrically connected. A column of sub-pixels 10 is electrically connected to a group of data lines D-(k); a column of sub-pixels includes multiple groups of sub-pixels, each group of sub-pixels includes 3 sub-pixels, and the 3 sub-pixels are connected to the same group of gate scanning signal lines G ( k) Electrical connection, the three sub-pixels are respectively electrically connected to the three data lines of a group of data lines D-(k) electrically connected to the sub-pixels in the column. In this case, the display substrate includes N/3 sets of gate scanning signal lines.

In this way, every n rows of sub-pixels 10 are turned on under the control of the same group of gate scanning signal lines G(k), and a plurality of data lines D write data signals into the corresponding sub-pixels 10, so that n rows of sub-pixels 10 work simultaneously, In one frame period, multiple groups of gate scanning signal lines sequentially control the corresponding n rows of sub-pixels to work, so as to light up all sub-pixels and realize picture display.

In the display substrate provided by some embodiments of the present disclosure, a set of gate scanning signal lines G(k) is electrically connected to n rows of sub-pixels, and a set of gate scanning signal lines G(k) simultaneously controls n rows of sub-pixels At the same time, each column of sub-pixels is electrically connected to a group of data lines D-(k), so that each sub-pixel is written with the corresponding data signal, so that on the premise of ensuring the normal display of the display screen, by making a group of gate scanning signals The line G(k) simultaneously controls n rows of sub-pixels, which can reduce the number of gate scanning signal lines, thereby reducing the number of shift registers electrically connected to the gate scanning signal lines. For example, in the case where a plurality of sub-pixels are arranged in N rows and M columns, using the method of coupling a group of gate scanning signal lines G(k) to a row of sub-pixels in the related art, N groups of gate scanning signal lines are required, so that the gate scanning signal lines G(k) The total number of polar scanning signal lines is relatively large. Using the connection methods provided by some embodiments of the present disclosure, N rows of sub-pixels require N/n groups of gate scanning signal lines, so that the total number of gate scanning signal lines is reduced. The number of shift registers included in the gate driving circuit is reduced, which is beneficial to narrowing the frame of the display substrate, thereby increasing the screen ratio of the display substrate and improving the display effect.

In some embodiments, as shown in FIGS. 4 to 7 , each adjacent n rows of sub-pixels are electrically connected to a group of gate scanning signal lines G(k). In a row of sub-pixels 10, the n sub-pixels 10 included in each group of sub-pixels 10 are adjacent n sub-pixels 10, and the i-th sub-pixel 10 in the n sub-pixels 10 is electrically connected to the N sub-pixels 10 in the row of sub-pixels 10. The i-th data line among the data lines is electrically connected; wherein, 1≤i≤n.

Exemplarily, as shown in FIG. 6 and FIG. 7 , when n is 3, each group of data lines D-(k) includes 3 data lines D, and each adjacent 3 rows of sub-pixels 10 is a driving unit, A group of gate scanning signal lines G(k) are electrically connected to the adjacent three rows of sub-pixels 10 . A column of sub-pixels 10 is electrically connected to three data lines D; a column of sub-pixels 10 includes multiple groups of sub-pixels 10, each group of sub-pixels 10 includes three adjacent sub-pixels 10, and the first pixel of the three sub-pixels 10 is connected to The first data line D among the three data lines D is electrically connected, the second sub-pixel 10 is electrically connected to the second data line D, and the third sub-pixel 10 is electrically connected to the third data line D.

With this arrangement, the distance between a group of gate scanning signal lines G(k) and the n-row sub-pixels 10 to which they are electrically connected is relatively uniform, and the connecting lines between the gate scanning signal lines and the n-row sub-pixels 10 are shorter , so that the resistance is too large due to the long connection line, and the voltage drop and signal loss during the signal transmission process are avoided.

In some embodiments, as shown in FIG. 4 and FIG. 5 , a group of gate scanning signal lines G(k) is electrically connected to two adjacent rows of sub-pixels 10 . A column of sub-pixels 10 is electrically connected to two data lines D, an odd-numbered sub-pixel 10 in a column of sub-pixels 10 is electrically connected to one of the two data lines D, and an even-numbered sub-pixel 10 is electrically connected to the other data line D Electrical connection.

Every two adjacent rows of sub-pixels 10 are controlled by the same set of gate scanning signal lines G(k), and each sub-pixel 10 in a column of sub-pixels 10 is electrically connected to two data lines DD alternately in odd-even rows. The number of gate scanning signal lines G in the substrate is halved, so that the number of shift registers included in the gate driving circuit is halved, which is beneficial to narrow the frame of the display substrate.

In some examples, as shown in FIGS. 4 and 5 , each group of gate scanning signal lines G(k) is disposed between two adjacent rows of sub-pixels 10 to which it is electrically connected.

Each group of gate scanning signal lines G(k) is disposed between two adjacent rows of sub-pixels 10 to which it is electrically connected, so that the distances between each group of gate scanning signal lines G(k) and the two rows of sub-pixels 10 are equal or approximately equal, the length of the gate scanning signal line and the connecting line between the sub-pixels 10 is the same, which can ensure that the gate scanning signals received by the two rows of sub-pixels 10 are basically the same, and improve the stability of the brightness of the sub-pixels 10 during operation. sex.

In some embodiments, each group of gate scanning signal lines G(k) includes one gate scanning signal line G, and the gate scanning signal line is electrically connected to the corresponding N rows of sub-pixels 10 . In other embodiments, each group of gate scanning signal lines G(k) includes 2˜4 gate scanning signal lines G; each gate scanning signal line G is electrically connected to corresponding N rows of sub-pixels 10 .

In some embodiments, the connection relationship between the at least one gate driving circuit 20 disposed in the peripheral region BB and the plurality of gate scanning signal lines G is: each gate driving circuit 20 includes a plurality of shift registers RS, Each shift register RS is electrically connected to at least one gate scanning signal line G among a group of gate scanning signal lines G(k).

In some examples, in the case where each group of gate scanning signal lines G(k) includes one gate scanning signal line G, the display substrate 01 includes one gate driving circuit 20 , and the gate driving circuit 20 includes a plurality of gate driving circuits 20 . Shift registers RS, each of which is electrically connected to one gate scanning signal line G. In the case where a plurality of sub-pixels 10 are arranged in N rows and M columns, the display substrate includes N/n groups of gate scanning signal lines, and the gate driving circuit includes N/n shift registers RS, each of which corresponds to n rows sub-pixel 10.

In other examples, when each group of gate scanning signal lines G(k) includes 2 to 4 gate scanning signal lines G, exemplarily, as shown in FIGS. 4 to 7 , each group of gate The scan signal line G(k) includes a first gate scan signal line, a second gate scan signal line G2, a third gate scan signal line G3, and a fourth gate scan signal line G4. The fourth gate scanning signal line G4 is the light-emitting timing signal line E.

In this case, as a possible design, as shown in FIG. 5 , the display substrate 01 includes four gate drive circuits 20 , each gate drive circuit 20 includes a plurality of shift registers RS, and each gate drive circuit 20 includes a plurality of shift registers RS. One shift register RS of the driving circuit 20 is electrically connected to one gate scanning signal line G among a group of gate scanning signal lines G(k).

Exemplarily, the above four gate driving circuits 20 are a first gate driving circuit 201, a second gate driving circuit 202, a third gate driving circuit 203 and a fourth gate driving circuit 204, respectively. A shift register RS of the driving circuit 201 is electrically connected to the first gate scanning signal line G1 in a group of gate scanning signal lines G(k). The shift register RS outputs the first gate scanning signal and transmits it to The first gate scans the signal line G1. A shift register RS of the second gate driving circuit 202 is electrically connected to the second gate scanning signal line G2 in a group of gate scanning signal lines G(k), and the shift register RS outputs the second gate scanning signal , and transmitted to the second gate scanning signal line G2. A shift register RS of the third gate driving circuit 203 is electrically connected to the third gate scanning signal line G3 in a group of gate scanning signal lines G(k), and the shift register RS outputs the third gate scanning signal , and transmitted to the third gate scanning signal line G3. A shift register RS of the fourth gate driving circuit 204 is electrically connected to the fourth gate scanning signal line G4 in a group of gate scanning signal lines G(k), and the shift register RS outputs the fourth gate scanning signal , and transmitted to the fourth gate scanning signal line G4. For example, the timing diagrams of the first gate scan signal, the second gate scan signal, the third gate scan signal and the fourth gate scan signal in one frame period can be referred to G1, G2, G3, EM in FIG. 10 Timing diagram corresponding to /G4. When a plurality of sub-pixels 10 are arranged in N rows and M columns, the display substrate 01 includes N/n groups of gate scanning signal lines, and each gate driving circuit includes N/n shift registers, each of which corresponds to There are n rows of sub-pixels 10 .

Among the above four gate driving circuits, as an example, the first gate driving circuit 201 and the second gate driving circuit 202 are located on one side of the display area AA, the third gate driving circuit 203 and the fourth gate driving circuit The circuit 204 is located on the other side of the display area AA.

As another possible design, as shown in FIG. 7 , the display substrate 01 includes three gate driving circuits 20 , and each gate driving circuit 20 includes a plurality of shift registers RS. One shift register of one gate driving circuit of the three gate driving circuits 20 is electrically connected with two gate scanning signal lines G in a group of gate scanning signal lines G(k); the three gate driving circuits In the other two gate driving circuits in , one shift register of each gate driving circuit is electrically connected to one of the other two gate scanning signal lines G in a group of gate scanning signal lines G(k) .

Exemplarily, as shown in FIG. 7 , the above-mentioned four gate driving circuits 20 are respectively a first gate driving circuit 201 , a second gate driving circuit 202 and a third gate driving circuit 203 . One shift register RS of 201 is electrically connected to the first gate scanning signal line G1 and the fourth gate scanning signal line G4 in a group of gate scanning signal lines G(k), for example, the first gate driving circuit 201 One of the shift registers RS can output two identical signals. In some embodiments, one shift register RS of the first gate driving circuit 201 and the first gate of a group of gate scanning signal lines G(k) The gate scanning signal line G1 is directly electrically connected, and the shift register RS is electrically connected with the fourth gate scanning signal line G4 through the inverter 2a, that is, the first gate driving circuit 201 includes a plurality of signal output units 2A, one shift register RS. The bit register and an inverter form a signal output unit 2A, so that through the phase inversion of the inverter, the fourth gate scanning signal received by the fourth gate scanning signal line G4 and the first gate scanning signal line The phase of the first gate scan signal received by G1 is opposite. For the timing diagram of the first gate scan signal and the fourth gate scan signal in one frame period, please refer to the timing diagram corresponding to G1 and EM/G4 in FIG. 10 .

A shift register RS of the second gate driving circuit 202 is electrically connected to the third gate scanning signal line G3 in a group of gate scanning signal lines G(k), and the shift register RS outputs the third gate scanning signal , and transmitted to the third gate scanning signal line G3. A shift register RS of the third gate driving circuit 203 is electrically connected to the second gate scanning signal line G2 in a group of gate scanning signal lines G(k), and the shift register RS outputs the second gate scanning signal , and transmitted to the second gate scanning signal line G2. For the timing diagram of the second gate scanning signal and the third gate scanning signal in one frame period, please refer to the timing diagram corresponding to G2 and G3 in FIG. 10 .

When a plurality of sub-pixels 10 are arranged in N rows and M columns, the display substrate 01 includes N/n groups of gate scanning signal lines, and each gate driving circuit includes N/n shift registers, each of which corresponds to There are n rows of sub-pixels 10 .

Among the above four gate driving circuits, as an example, the first gate driving circuit 201 is located on one side of the display area AA, and the second gate driving circuit 202 and the third gate driving circuit 203 are located on the other side of the display area AA. side.

As shown in FIGS. 8 , 9A and 9B , in some embodiments, each sub-pixel 10 includes a pixel driving circuit 100 ; a set of gate scanning signal lines G(k) and the pixel driving of the n rows of sub-pixels 10 The circuit 100 is electrically connected, and a group of data lines D-(k) is electrically connected to the pixel driving circuit 100 of a column of sub-pixels 10 .

The pixel driving circuit 100 includes a data writing sub-circuit 103 .

The data writing sub-circuit 103 is electrically connected to a gate scanning signal line G in a group of gate scanning signal lines G(k) and a data line in a group of data lines D-(k) to which the sub-pixel 10 is electrically connected D is electrically connected; the data writing sub-circuit 103 is configured to write the data signal received at the data line into the pixel driving circuit 100 under the control of the gate scanning signal transmitted by the gate scanning signal line.

When the display substrate is a liquid crystal display substrate, as shown in FIG. 8 , the sub-pixel 10 further includes a liquid crystal capacitor 107 that is electrically connected to the pixel driving circuit 100 . In addition to the data writing sub-circuit 103 , the pixel driving circuit 100 also includes a storage sub-circuit 106 . One set of gate scanning signal lines G(k) includes one gate scanning signal line G. As shown in FIG.

The data writing sub-circuit 103 is also electrically connected to the storage sub-circuit 106 and the liquid crystal capacitor 107, and the data writing sub-circuit 103 is configured to be controlled by the gate scanning signal transmitted by the gate scanning signal line, to write the data at the data line. The received data signal is written into the storage sub-circuit 106 and the liquid crystal capacitor 107 .

The storage sub-circuit 106 is also electrically connected to the constant voltage terminal and the liquid crystal capacitor 107 , and the storage sub-circuit 106 is configured to store data signals and keep the potential of the connection terminal of the storage sub-circuit 106 and the liquid crystal capacitor 107 stable. The constant voltage terminal is, for example, a ground signal terminal GND, a low voltage signal terminal, and the like.

The liquid crystal capacitor 107 is also electrically connected to the constant voltage terminal, and the liquid crystal capacitor 107 is configured to form an electric field under the action of the data signal.

In some embodiments, as shown in FIG. 8 , the data writing sub-circuit 103 includes a switching transistor (the third transistor T3 ), the storage sub-circuit 106 includes a storage capacitor Cst, and the liquid crystal capacitor 107 includes oppositely disposed pixel electrodes and common electrodes, and a liquid crystal layer disposed between the pixel electrode and the common electrode.

The control electrode of the switching transistor is electrically connected to the data line D, the first electrode of the switching transistor is electrically connected to the gate scanning signal line G, the second electrode of the switching transistor is electrically connected to the first electrode of the storage capacitor Cst, and the pixel electrode of the liquid crystal capacitor 107 electrical connection. The first pole of the storage capacitor Cst is electrically connected to the connection node. Under the action of the pixel voltage provided by the switching transistor, the liquid crystal capacitor 107 forms an electric field between the pixel electrode and the common electrode, and the electric field can control the deflection of the liquid crystal molecules in the liquid crystal layer to control the state of light passing through the sub-pixel 10 area, Thus, the display substrate realizes image display.

In some implementations, as shown in FIGS. 9A and 9B , when the display substrate 01 is the OLED display substrate 01 , the display substrate 01 further includes: a plurality of first voltage signal lines VDD, a plurality of The second voltage signal line VSS and a plurality of initialization signal lines VINI. Exemplarily, the plurality of first voltage signal lines VDD and the plurality of second voltage signal lines VSS extend in the vertical direction Y, the plurality of initialization signal lines VINI extend in the horizontal direction X, and the initialization signal lines VINI are configured to transmit initialization signals .

Each group of gate scanning signal lines G(k) includes a first gate scanning signal line G1, a second gate scanning signal line G2, a third gate scanning signal line G3 and a fourth gate scanning signal line G4; The gate scanning signal line G1 , the second gate scanning signal line G2 , the third gate scanning signal line G3 and the fourth gate scanning signal line G4 are all electrically connected to the corresponding N rows of sub-pixels 10 .

As shown in FIGS. 9A and 9B , the pixel driving circuit 100 of each sub-pixel 10 is connected to a first voltage signal line VDD, a second voltage signal line VSS, an initialization signal line VINI, a first gate scanning signal line G1, The second gate scanning signal line G2, the third gate scanning signal line G3, and the fourth gate scanning signal line G4 are electrically connected.

The subpixel 10 also includes a light emitting device 108 electrically connected to the pixel driver circuit 100 . The light emitting device 108 is, for example, an organic light emitting diode. Under the driving action of the pixel driving circuit 100 , the light emitting device 108 emits light, so that the display substrate 01 realizes a display screen.

In some examples, as shown in FIGS. 9A and 9B , in addition to the data writing subcircuit 103, the pixel driving circuit 100 further includes: a first reset subcircuit 101, a second reset subcircuit 102, a driving subcircuit 104, Lighting control sub-circuit 105 and storage sub-circuit 106 .

The first reset sub-circuit 101 is electrically connected to the first node N1, the initialization signal line VINI and the second gate scanning signal line G2; Under the control of the two-gate scan signal, the initialization signal received at the initialization signal line VINI is transmitted to the first node N1.

Exemplarily, the first reset sub-circuit 101 includes a first transistor T1; the control electrode of the first transistor T1 is electrically connected to the second gate scanning signal line G2, and the first electrode of the first transistor T1 is electrically connected to the initialization signal line VINI. , the second pole of the first transistor T1 is connected to the first node N1.

The second reset sub-circuit 102 is electrically connected to a first voltage signal line VDD, the second node N2 and the fourth gate scanning signal line G4; the second reset sub-circuit 102 is configured to scan the fourth gate signal line G4 on the Under the control of the transmitted fourth gate scan signal, the first voltage signal received at the first voltage signal line VDD is transmitted to the second node N2.

Exemplarily, the second reset sub-circuit 102 includes a second transistor T2; the control electrode of the second transistor T2 is electrically connected to the fourth gate scanning signal line G4, and the first electrode of the second transistor T2 is connected to the first voltage signal line VDD. Electrically connected, the second pole of the second transistor T2 is electrically connected to the second node N2.

A gate scanning signal line G electrically connected to the data writing sub-circuit 103 is the first gate scanning signal line G1, and the data writing sub-circuit 103 is also electrically connected to the third node N3; the data writing sub-circuit 103 is configured In order to transmit the data signal received at the data line to the third node N3 under the control of the first gate scan signal transmitted by the first gate scan signal line G1.

Exemplarily, the data writing sub-circuit 103 includes a third transistor T3; the control electrode of the third transistor T3 is electrically connected to the first gate scanning signal line G1, the first electrode of the third transistor T3 is electrically connected to the data line, and the first electrode of the third transistor T3 is electrically connected to the data line. The second pole of the three transistors T3 is electrically connected to the third node N3.

The driving sub-circuit 104 is electrically connected to the second node N2, the third node N3, the fourth node N4 and the second gate scanning signal line G2; the driving sub-circuit 104 is configured to Under the control of the second gate scan signal, the first voltage signal at the second node N2 is transmitted to the fourth node N4, and the data signal at the third node N3 is transmitted to the fourth node N4, and at the fourth node N4 Under the voltage control of the node N4, the driving current is generated and transmitted to the third node N3.

Exemplarily, the driving sub-circuit 104 includes a fourth transistor T4 and a fifth transistor T5; the control electrode of the fourth transistor T4 is electrically connected to the fourth node N4, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, The second pole of the fourth transistor T4 is electrically connected to the third node N3; the control pole of the fifth transistor T5 is electrically connected to the second gate scanning signal line G2, and the first pole of the fifth transistor T5 is electrically connected to the second node N2 , the second pole of the fifth transistor T5 is electrically connected to the fourth node N4.

The storage sub-circuit 106 is electrically connected to the first node N1 and the fourth node N4; the storage sub-circuit 106 is configured to store the voltage of the fourth node N4 and the voltage of the first node N1, and the function of the voltage of the first node N1 Next, the potential of the fourth node N4 is changed.

Exemplarily, the storage sub-circuit 106 includes a storage capacitor Cst; the first pole of the storage capacitor Cst is electrically connected to the third node N3, and the second pole of the storage capacitor Cst is electrically connected to the first node N1.

The light-emitting control sub-circuit 105 is electrically connected to the first node N1, the third node N3 and the third gate scanning signal line G3; the light-emitting control sub-circuit 105 is configured to Under the control of the gate scan signal, the driving current received at the third node N3 is transmitted to the first node N1.

Exemplarily, the light-emitting control sub-circuit 105 includes a sixth transistor T6; the control electrode of the sixth transistor T6 is electrically connected to the third gate scanning signal line G3, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, The second pole of the sixth transistor T6 is electrically connected to the first node N1.

The light emitting device 108 is electrically connected to the first node N1 and a second voltage signal line VSS; the light emitting device 108 is configured to emit light under the control of the driving current received at the first node N1. For example, the first pole of the light emitting device 108 is electrically connected to the first node N1, and the second pole of the light emitting device 108 is electrically connected to the second voltage signal line VSS.

In some embodiments, in the pixel driving circuit 100 provided by the present disclosure, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all P-type The transistors are either N-type transistors.

In the embodiments of the present disclosure, the specific implementation manner of the pixel driving circuit 100 is not limited to the manner described above, and it can be any implementation manner, such as a conventional connection manner well known to those skilled in the art, and only needs to ensure that the corresponding function. The above example of the present disclosure provides a structural example of a 6T1C pixel driving circuit 100. It can be understood that the pixel driving circuit 100 may also be a 3T1C or 7T1C structure, and the above examples do not limit the protection scope of the present disclosure. In practical applications, the skilled person can choose to use or not apply one or more of the above circuits according to the situation, and the various combinations and modifications of the above circuits do not depart from the principles of the present disclosure, and will not be repeated here.

Taking the pixel driving circuit 100 shown in FIG. 9A as an example, and the transistors included in the pixel driving circuit 100 are all N-type transistors as an example, the driving process of the pixel driving circuit 100 in each sub-pixel 10 described above is described below: As shown in FIG. 10 As shown, the driving process is: for one sub-pixel 10, one frame period includes a reset phase S1, a data writing and compensation phase S2, and a light-emitting phase S3.

During reset phase S1:

The level of the first gate scan signal transmitted by the first gate scan signal line G1 is low level, the level of the second gate scan signal transmitted by the second gate scan signal line G2 is high level, and the level of the third gate scan signal transmitted by the second gate scan signal line G2 is high level. The level of the third gate scan signal transmitted by the gate scan signal line G3 is a low level, and the level of the fourth gate scan signal transmitted by the fourth gate scan signal line G4 is a high level.

Under the control of the second gate scan signal, the first reset sub-circuit 101 transmits the initialization signal received at the initialization signal line VINI to the first node N1 to reset the potential of the first node N1. The first node N1 is electrically connected to the storage sub-circuit 106 and the light-emitting device 108, and at this time, the storage sub-circuit 106 and the light-emitting device 108 are reset simultaneously.

The second reset sub-circuit 102 transmits the first voltage signal received at the first voltage signal line VDD to the second node N2 under the control of the fourth gate scan signal.

The driving sub-circuit 104 transmits the first voltage signal at the second node N2 to the fourth node N4 under the control of the second gate scan signal. Therefore, the potentials of the second node N2 and the fourth node N4 are both the potentials of the first voltage signal.

The first reset sub-circuit 101 includes a first transistor T1, the second reset sub-circuit 102 includes a second transistor T2, the data writing sub-circuit 103 includes a third transistor T3, and the driving sub-circuit 104 includes a fourth transistor T4 and a fifth transistor T5, when the storage sub-circuit 106 includes the storage capacitor Cst, and the light-emitting control sub-circuit 105 includes the sixth transistor T6, in the reset stage S1:

The first transistor T1 is turned on under the control of the second gate scan signal, and transmits the initialization signal to the first node N1, so as to reset the potential of the second pole of the storage capacitor Cst and the anode of the light emitting device 108, and the storage capacitor Cst The potential of the second pole is the potential V _ini of the initialization signal.

The second transistor T2 is turned on under the control of the fourth gate scan signal, and transmits the first voltage signal to the second node N2, so that the potential of the second node N2 is the potential V _dd of the first voltage signal.

The fifth transistor T5 is turned on under the control of the second gate scan signal, and transmits the first voltage signal at the second node N2 to the fourth node N4, so that the potential of the fourth node N4 is the potential of the first voltage signal V _dd , the storage capacitor Cst stores the first voltage signal, and the potential of the first pole of the storage capacitor Cst is the potential V _dd of the first voltage signal.

The fourth transistor T4 is turned on under the control of the voltage of the fourth node N4. Both the third transistor T3 and the fifth transistor T5 are turned off.

In the data writing and compensation phase S2:

The level of the first gate scan signal transmitted by the first gate scan signal line G1 is high level, the level of the second gate scan signal transmitted by the second gate scan signal line G2 is high level, and the level of the third gate scan signal transmitted by the second gate scan signal line G2 is high level. The level of the third gate scan signal transmitted by the gate scan signal line G3 is a low level, and the level of the fourth gate scan signal transmitted by the fourth gate scan signal line G4 is a low level. The data lines transmit data signals with set voltages.

The data writing sub-circuit 103 transmits the data signal received at the data line to the third node N3 under the control of the first gate scan signal.

Under the control of the second gate scan signal, the driving sub-circuit 104 transmits the data signal received at the third node N3 to the fourth node N4, and under the control of the voltage of the fourth node N4, the driving sub-circuit 104, Discharge to the third node N3 until the compensation for the threshold voltage of the driving transistor in the driving sub-circuit 104 is completed, and the discharging is stopped.

Under the control of the second gate scan signal, the first reset sub-circuit 101 continues to transmit the initialization signal received at the initialization signal line VINI to the first node N1 to reset the potential of the first node N1. The first node N1 is electrically connected to the storage sub-circuit 106 and the light-emitting device 108 , and at this time, the storage sub-circuit 106 and the light-emitting device 108 continue to be reset.

The first reset sub-circuit 101 includes a first transistor T1, the second reset sub-circuit 102 includes a second transistor T2, the data writing sub-circuit 103 includes a third transistor T3, and the driving sub-circuit 104 includes a fourth transistor T4 and a fifth transistor T5, when the storage sub-circuit 106 includes a storage capacitor Cst, and the light-emitting control sub-circuit 105 includes the sixth transistor T6, in the data writing and compensation stage S2:

The third transistor T3 is turned on under the control of the first gate scan signal, and transmits the data signal received at the data line to the third node N3. At this time, the potential of the third node N3 is the potential of the data signal. V _data .

The fourth transistor T4 is turned on under the control of the voltage of the fourth node N4, the fifth transistor T5 is turned on under the control of the second gate scan signal, and the fourth transistor T4 and the fifth transistor T5 connect the voltage at the third node N3. The data signal is transmitted to the fourth node N4, and the potential of the fourth node N4 starts to be changed, until the potential of the fourth node N4 becomes the sum of the potential of the third node N3 and the threshold voltage of the fourth transistor T4, that is, the fourth node N4 The potential of V _N4 =V _N3 +V _th =V _data +V _th . At this time, the fourth transistor T4 is turned off.

The storage capacitor Cst stores the potential of the fourth node N4, and the potential of the first pole of the storage capacitor Cst is V _data +V _th , thereby completing the writing of the data signal and the storage of the threshold voltage of the fourth transistor T4.

The first transistor T1 is turned on under the control of the second gate scan signal, and continues to transmit the initialization signal received at the initialization signal line VINI to the first node N1, so that the storage capacitor Cst stores the initialization signal, and the second The potential of the pole is the potential V _ini of the initialization signal.

Both the second transistor T2 and the sixth transistor T6 are turned off.

In the luminous phase S3:

The level of the first gate scan signal transmitted by the first gate scan signal line G1 is low level, the level of the second gate scan signal transmitted by the second gate scan signal line G2 is low level, and the level of the third gate scan signal transmitted by the second gate scan signal line G2 is low level. The level of the third gate scan signal transmitted by the gate scan signal line G3 is a high level, and the level of the fourth gate scan signal transmitted by the fourth gate scan signal line G4 is a high level. The data lines transmit data signals with set voltages.

Under the control of the third gate scan signal transmitted by the third gate scan signal line G3, the light emission control sub-circuit 105 transmits the initialization signal received at the first node N1 to the third node N3, so that the driving sub-circuit 104 Under the control of the voltage of the third node N3, the voltage of the fourth node N4 and the voltage of the second node N2, a driving current is generated, and the light emission control sub-circuit 105 transmits the driving current to the light emitting device 108, so that the light emitting device 108 emits light.

The first reset sub-circuit 101 includes a first transistor T1, the second reset sub-circuit 102 includes a second transistor T2, the data writing sub-circuit 103 includes a third transistor T3, and the driving sub-circuit 104 includes a fourth transistor T4 and a fifth transistor T5, when the storage sub-circuit 106 includes the storage capacitor Cst, and the light-emitting control sub-circuit 105 includes the sixth transistor T6, in the light-emitting stage S3:

The second transistor T2 is turned on under the control of the fourth gate scan signal, and transmits the first voltage signal received at the first voltage signal line VDD to the second node N2, so that the potential of the second node N2 is the first voltage voltage of the signal.

The fifth transistor T5 is turned on under the control of the third gate scan signal, and transmits the initialization signal at the first node N1 to the third node N3, and the potential of the third node N3 changes from the potential of the data signal to the potential of the initialization signal , so that the gate-source voltage difference of the fourth transistor T4 is greater than its threshold voltage, the fourth transistor T4 is turned on, and the voltage of the fourth transistor T4 at the third node N3, the voltage of the fourth node N4 and the voltage of the second node N2 Under the control, a driving current is generated, and the fifth transistor T5 transmits the driving current to the light emitting device 108, so that the light emitting device 108 emits light.

During the light-emitting process of the light-emitting device 108, the potential of the first node N1 is equal to the potential _Voled of the anode of the light-emitting device 108, and the voltage variation of the first node N1 is ΔV _N1 = _Voled -V _ini , so that the storage capacitor Cst has a The voltage variation of the second pole is also ΔV _N1 . Under the bootstrap action of the capacitor, the voltage variation of the second pole of the storage capacitor Cst is ΔV _N1 , so the potential of the fourth node N4 is V _N4 =V _data +V _th +ΔV _N1 , that is, the potential of the control electrode (gate) of the fourth transistor T4 is V _N4 =V _data +V _th +ΔV _N1 . The potential of the first electrode (source) of the fourth transistor T4 is V _oled .

Therefore, the driving current generated by the fourth transistor T4 (ie, the current I _oled input to the light emitting device 108 ) is:

Wherein, W/L is the channel width to length ratio of the third transistor T3; μ is the carrier mobility; C _ox is the channel capacitance per unit area of the fourth transistor T4; V _gs is the gate-source voltage of the fourth transistor T4 difference; V _th is the threshold voltage of the fourth transistor T4.

It can be seen that the magnitude of the current I _oled input to the light-emitting device 108 is related to the voltage V _data of the written data signal and the initialization signal, and has nothing to do with the threshold voltage V _th of the fourth transistor T4, so the driving current generated by the fourth transistor T4 The size of t is not affected by the threshold voltage, which avoids the difference in the threshold voltage of the fourth transistor T4 caused by the fabrication process from affecting the driving current, thereby affecting the display effect.

The driving process of the above-mentioned pixel driving circuit 100 is the driving process of the pixel driving circuit 100 in one sub-pixel 10 in one frame period. For the pixel driving circuit shown in FIG. 9A and FIG. 9B , the same group of gate scanning signal lines G ( k) The driving processes of the pixel driving circuits 100 of the N rows of sub-pixels 10 that are electrically connected are all the same, and they all go through the reset stage S1, the data writing and compensation stage S2 and the light-emitting stage S3 at the same time. For each sub-pixel 10, in the data The data signal written in the writing and compensating stage S2 depends on the size of the data signal transmitted by the signal line to which it is electrically connected, so as to emit light corresponding to the brightness and realize gray scale display. For example, referring to FIG. 9A and FIG. 10 , for the first group of sub-pixels in the first column of sub-pixels, the first group of sub-pixels includes two sub-pixels, both of which are electrically connected to a group of gate scanning signal lines, and are respectively It is electrically connected to the data line D1 and the data line D2, and the driving process of the pixel driving circuit 100 in the two sub-pixels is consistent. In the data writing and compensation stage S2, the first sub-pixel is written to the data signal transmitted by the data line D1. The voltage V _data1 , the second sub-pixel is written to the voltage V _data2 of the data signal transmitted by the data line D2.

In some embodiments, as shown in FIGS. 5 and 7 , the display device 1000 further includes a source driver 40 electrically connected to the plurality of data lines D of the display substrate 01 , and the source driver 40 is configured to output data signals to The display substrate 01 is controlled to realize display.

The source driver 40 includes a plurality of output ports, and each output port is electrically connected to a data line D, that is to say, the number of output ports of the source driver 40 is consistent with the number of data lines D, so that each output port is The corresponding data signal is output and transmitted to the corresponding data line.

As a possible design, the display substrate 01 further includes a plurality of data selectors 30 disposed in the frame area BB; each data selector 30 is electrically connected to n data lines D electrically connected to a column of sub-pixels 10 . Each data selector is also coupled to one output port of the source driver 40 .

As shown in FIG. 5 , the display substrate 01 further includes a plurality of data selectors 30 disposed in the frame area BB. Each data selector 30 is electrically connected to two data lines D electrically connected to a column of sub-pixels 10, and is also electrically connected to a source One output port of the pole driver 40 is coupled. Therefore, the display substrate 01 includes 2M data lines, the 2M data lines are M groups of data lines, and the display substrate 01 includes M data selectors 30 .

In this case, in one frame period, when a group of gate scanning signal lines scans n rows of sub-pixels, the data signal output from one output port of the source driver 40 includes n different voltages, and the n voltages Corresponding to the n sub-pixels coupled to the n data lines coupled to the output port respectively, for the driving process of the pixel driving circuit shown in FIG. 9A and FIG. 10, it is assumed that the data selector is not set. The duration of the writing and compensation stage S2 is T. In the case of setting the data selector, the duration of the data writing and compensation stage S2 is extended to n times of T. In each T, the data selector sequentially selects The voltage of the data signal is transmitted to the corresponding data line, so that the specific voltage of the data signal is written into the corresponding sub-pixel.

In the above display device, a column of sub-pixels 10 is electrically connected to n data lines D, that is, for a plurality of sub-pixels 10 arranged in N rows and M columns, a total of n*M data lines D are required. The selectors, exemplarily, are provided with M data selectors, so that the number of the corresponding output ports of the source driver 40 is consistent with the number of data selectors, and both are M, which can reduce the number of output ports of the source driver 40. The number of the output ports of the source driver 40 is too large to avoid the problem of increased cost.

The present disclosure also provides a method for driving a display substrate 01 , wherein, as shown in FIG. 5 , in the above-mentioned display substrate 01 , the sub-pixels 10 in n rows electrically connected to each group of gate scanning signal lines G(k) are One driving unit 100', the display substrate 01 includes N/n driving units 100'.

The driving method of the display substrate 01 includes:

Each group of gate scanning signal lines G(k) transmits the gate scanning signal to n rows of sub-pixels 10 included in one driving unit 100' to which it is electrically connected.

The n rows of sub-pixels 10 included in each driving unit 100' work simultaneously under the control of the gate scan signal.

The operation of the sub-pixel 10 means that when the display substrate 01 is the liquid crystal display substrate 01, the sub-pixel 10 performs data signal writing under the control of the gate scanning signal, and forms an electric field according to the data signal, so that the The liquid crystal molecules in the liquid crystal layer are deflected under the action of the electric field to control the light to pass through the sub-pixel 10 area.

When the display substrate 01 is an OLED display substrate 01, the sub-pixels 10 perform reset, data signal writing and threshold voltage compensation under the control of the gate scan signal to generate a driving current and control the light-emitting device to emit light.

The plurality of groups of gate scanning signal lines sequentially control the operation of the sub-pixels 10 of the plurality of driving units 100'.

Therefore, according to the sequence of the plurality of groups of gate scanning signal lines, the sub-pixels 10 of the plurality of driving units 100' work in sequence, and the sub-pixels 10 in each driving unit 100' work simultaneously.

In the case where each group of gate scanning signal lines G(k) transmits the gate scanning signal to the n rows of sub-pixels 10 included in one driving unit to which it is electrically connected are adjacent n rows of sub-pixels 10, the above display The driving method of the substrate 01 is different from the row-by-row scanning method in the related art, which can be understood as scanning by n rows. The sub-pixels 10 in the light-emitting diodes emit light sequentially from top to bottom. When n is 2, every 2 rows of sub-pixels 10 is a driving unit, the sub-pixels 10 in the plurality of driving units emit light sequentially, and the sub-pixels 10 in each driving unit 100' emit light simultaneously.

In each sub-pixel 10, the driving process of the pixel driving circuit 100 can be referred to the foregoing description, and details are not repeated here.

In some embodiments, since each group of gate scanning signal lines G(k) is electrically connected to n rows of sub-pixels 10, under the premise that the number of sub-pixels 10 included in the display substrate 01 remains unchanged, for example, a plurality of sub-pixels 10 are arranged N rows and M columns are formed. Compared with the row-by-row scanning method in the related art, the total driving duration of each row of sub-pixels 10 in one frame period is, for example, T1. The voltage change frequency of the data signal is P. In the manner of scanning by n lines provided by some embodiments of the present disclosure, the duration of one frame period is unchanged, and the total driving duration of each driving unit in one frame period is, for example, n*T1, The total driving duration becomes n times as long as the original total driving duration, so the voltage change frequency of the data signal output from the source driver 40 also becomes 1/n of the original.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any person skilled in the art who is familiar with the technical scope of the present disclosure, thinks of changes or replacements, should cover within the scope of protection of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

A display substrate has a display area and a peripheral area, the display substrate includes: a plurality of sub-pixels arranged in the display area, a plurality of groups of gate scanning signal lines and a plurality of groups of data lines; each group of the gate scanning signal lines includes at least one gate Scanning signal lines, each group of data lines includes n data lines, the plurality of sub-pixels are arranged in an array; n≥2; wherein,

A group of gate scanning signal lines are electrically connected with the n rows of sub-pixels;

A column of sub-pixels is electrically connected to a set of data lines;

A column of sub-pixels includes multiple groups of sub-pixels, each group of sub-pixels includes n sub-pixels, and the n sub-pixels are respectively electrically connected to n data lines of a group of data lines electrically connected to the column of sub-pixels.
The display substrate according to claim 1, wherein each adjacent n rows of sub-pixels are electrically connected to a group of gate scanning signal lines;

In a column of sub-pixels, the n sub-pixels included in each group of sub-pixels are adjacent n sub-pixels, and the i-th sub-pixel in the n sub-pixels is electrically connected to the i-th sub-pixel in the n data lines electrically connected to the sub-pixels in the column. The data lines are electrically connected; wherein, 1≤i≤n.
The display substrate according to claim 1 or 2, wherein,

A group of gate scanning signal lines are electrically connected to two adjacent rows of sub-pixels;

A column of sub-pixels is electrically connected to two data lines, the odd-numbered sub-pixels in a column of sub-pixels are electrically connected to one of the two data lines, and the even-numbered sub-pixels are electrically connected to the other data line.
The display substrate according to claim 3, wherein each group of gate scanning signal lines is disposed between two adjacent rows of sub-pixels to which it is electrically connected.
The display substrate according to any one of claims 1 to 4, wherein each group of gate scanning signal lines includes 2 to 4 gate scanning signal lines; and each gate scanning signal line is associated with corresponding N rows of Pixel electrical connections.
The display substrate according to any one of claims 1 to 5, wherein each sub-pixel includes a pixel driving circuit; a group of gate scanning signal lines are electrically connected to the pixel driving circuits of the n-row sub-pixels, and a group of data The line is electrically connected to the pixel driving circuit of a column of sub-pixels;

The pixel driving circuit includes a data writing sub-circuit;

The data writing sub-circuit is electrically connected to a gate scanning signal line in a group of gate scanning signal lines and a data line in a group of data lines electrically connected to the sub-pixel; the data writing sub-circuit is electrically connected to The circuit is configured to write the data signal received at the data line into the pixel driving circuit under the control of the gate scan signal transmitted by the gate scan signal line.
The display substrate according to claim 6, further comprising: a plurality of first voltage signal lines, a plurality of second voltage signal lines and a plurality of initialization signal lines disposed in the display area;

Each group of gate scanning signal lines includes a first gate scanning signal line, a second gate scanning signal line, a third gate scanning signal line and a fourth gate scanning signal line; the first gate scanning signal line, the second gate scanning signal line, the third gate scanning signal line and the fourth gate scanning signal line are all electrically connected to corresponding N rows of sub-pixels;

The pixel driving circuit of each sub-pixel is connected with a first voltage signal line, a second voltage signal line, an initialization signal line, the first gate scanning signal line, the second gate scanning signal line, the The three gate scanning signal lines are electrically connected to the fourth gate scanning signal line;

The sub-pixel further includes a light emitting device electrically connected to the pixel driving circuit.
The display substrate according to claim 7, wherein the pixel driving circuit further comprises: a first reset sub-circuit, a second reset sub-circuit, a driving sub-circuit, a light-emitting control sub-circuit and a storage sub-circuit;

The first reset sub-circuit is electrically connected to the first node, the initialization signal line and the second gate scan signal line; the first reset sub-circuit is configured to Under the control of the second gate scan signal transmitted by the line, transmit the initialization signal received at the initialization signal line to the first node;

The second reset sub-circuit is electrically connected to a first voltage signal line, the second node and the fourth gate scan signal line; the second reset sub-circuit is configured to scan on the fourth gate Under the control of the fourth gate scan signal transmitted by the signal line, transmit the first voltage signal received at the first voltage signal line to the second node;

One gate scanning signal line electrically connected to the data writing sub-circuit is the first gate scanning signal line, and the data writing sub-circuit is also electrically connected to the third node; the data writing sub-circuit is electrically connected to the third node; is configured to, under the control of the first gate scan signal transmitted by the first gate scan signal line, transmit the data signal received at the data line to the third node;

The driving sub-circuit is electrically connected to the second node, the third node, the fourth node and the second gate scanning signal line; the driving sub-circuit is configured to be connected to the second gate Under the control of the second gate scan signal transmitted by the scan signal line, the first voltage signal at the second node is transmitted to the fourth node, and the data signal at the third node is transmitted to the fourth node. the fourth node, and under the voltage control of the fourth node, a driving current is generated and transmitted to the third node;

The storage sub-circuit is electrically connected to the first node and the fourth node; the storage sub-circuit is configured to store the voltage of the fourth node and the voltage of the first node, and store the voltage of the fourth node and the voltage of the first node at the Under the action of the voltage of the first node, the potential of the fourth node is changed;

The light-emitting control sub-circuit is electrically connected to the first node, the third node and the third gate scan signal line; the light-emitting control sub-circuit is configured to scan the signal at the third gate transmitting the driving current received at the third node to the first node under the control of the third gate scan signal transmitted by the line;

The light emitting device is electrically connected to the first node and a second voltage signal line; the light emitting device is configured to emit light under the control of a drive current received at the first node.
The display substrate of claim 8, wherein,

The first reset sub-circuit includes a first transistor; the control electrode of the first transistor is electrically connected to the second gate scanning signal line, and the first electrode of the first transistor is electrically connected to the initialization signal line , the second pole of the first transistor is connected to the first node;

The second reset sub-circuit includes a second transistor; the control electrode of the second transistor is electrically connected to the fourth gate scan signal line, and the first electrode of the second transistor is connected to the first voltage signal line electrically connected, the second pole of the second transistor is electrically connected to the second node;

The data writing sub-circuit includes a third transistor; the control electrode of the third transistor is electrically connected to the first gate scanning signal line, and the first electrode of the third transistor is electrically connected to the data line, the second pole of the third transistor is electrically connected to the third node;

The driving sub-circuit includes a fourth transistor and a fifth transistor; the control electrode of the fourth transistor is electrically connected to the fourth node, the first electrode of the fourth transistor is electrically connected to the second node, and the The second electrode of the fourth transistor is electrically connected to the third node; the control electrode of the fifth transistor is electrically connected to the second gate scanning signal line, and the first electrode of the fifth transistor is electrically connected to the second gate scanning signal line. The second node is electrically connected, and the second pole of the fifth transistor is electrically connected to the fourth node;

The storage subcircuit includes a storage capacitor; a first pole of the storage capacitor is electrically connected to the third node, and a second pole of the storage capacitor is electrically connected to the first node;

The light-emitting control sub-circuit includes a sixth transistor; the control electrode of the sixth transistor is electrically connected to the third gate scanning signal line, and the first electrode of the sixth transistor is electrically connected to the third node, the second pole of the sixth transistor is electrically connected to the first node;

The first pole of the light emitting device is electrically connected to the first node, and the second pole of the light emitting device is electrically connected to the second voltage signal line.
The display substrate according to any one of claims 1 to 9, further comprising: at least one gate driving circuit disposed in the peripheral region; wherein,

Each gate driving circuit includes a plurality of shift registers, and each shift register is electrically connected to at least one gate scanning signal line in a group of gate scanning signal lines.
The display substrate of claim 10, wherein each group of gate scanning signal lines comprises a first gate scanning signal line, a second gate scanning signal line, a third gate scanning signal line and a fourth gate In the case of extremely scan signal lines,

The at least one gate drive circuit includes four gate drive circuits, each gate drive circuit includes a plurality of shift registers, and one shift register of each gate drive circuit is connected to a set of gate scanning signal lines. A gate scanning signal line is electrically connected;

Alternatively, the at least one gate drive circuit includes three gate drive circuits, and each gate drive circuit includes a plurality of shift registers;

One shift register of one gate driving circuit in the three gate driving circuits is electrically connected with two gate scanning signal lines in the group of gate scanning signal lines; the three gate driving circuits In the other two gate driving circuits, one shift register of each gate driving circuit is electrically connected to one of the other two gate scanning signal lines in a group of gate scanning signal lines.
The display substrate according to any one of claims 1 to 11, further comprising:

A plurality of data selectors are arranged in the frame area; each data selector is electrically connected to n data lines electrically connected to a column of sub-pixels.
A display device comprising the display substrate according to any one of claims 1 to 12.
The display device of claim 13, further comprising: a source driver electrically connected to the plurality of data lines in the display substrate.
A driving method of a display substrate, the driving method is used for driving the display substrate according to any one of claims 1 to 10; wherein,

The n rows of sub-pixels electrically connected to each group of gate scanning signal lines are a driving unit;

The driving method of the display substrate includes:

Each group of gate scanning signal lines transmits the gate scanning signal to n rows of sub-pixels included in one driving unit to which it is electrically connected;

The n rows of sub-pixels included in each driving unit work simultaneously under the control of the gate scanning signal;

The plurality of groups of gate scanning signal lines sequentially control the sub-pixels of the plurality of driving units to work.