WO2022110327A1

WO2022110327A1 - Neuronal network unit

Info

Publication number: WO2022110327A1
Application number: PCT/CN2020/135749
Authority: WO
Inventors: 孔繁生; 周华
Original assignee: 光华临港工程应用技术研发(上海)有限公司
Priority date: 2020-11-30
Filing date: 2020-12-11
Publication date: 2022-06-02
Also published as: CN112465128B; CN112465128A

Abstract

A neuronal network unit, comprising: an inhibitory read control transistor (T21) and an excitatory read control transistor (T22) which are provided in parallel, and a write control transistor (T1) provided to be opposite the two transistors (T21, T22) in a stacked manner longitudinally; the source electrode of the write control transistor (T1) and the source electrodes of the read control transistors (T21, T22) are arranged facing away from each other; the drain electrode of the write control transistor (T1) is electrically connected to a first end of a magnetic tunnel junction (MTJ); the drain electrode of the inhibitory read control transistor (T21) is electrically connected to a second end of the magnetic tunnel junction (MTJ) by means of a weight signal line (W); and the drain electrode of the excitatory read control transistor (T22) is electrically connected to the second end of the magnetic tunnel junction (MTJ) by means of the weight signal line (W). By arranging the transistors of the neuronal network unit in a vertically stacked manner, the total area of a chip is reduced, and the two transistors share a magnetic tunnel junction (MTJ), so that in cases where an excitation signal and a suppression signal are opposite, the levels are completely consistent and are counteracted, improving the accuracy of a deep learning algorithm.

Description

neural network unit

technical field

The invention relates to the field of artificial intelligence, in particular to a neural network unit.

Background technique

FIG. 1 is a schematic diagram of a typical neuron network architecture and a corresponding circuit, including N×M synaptic weight components. The corresponding circuit includes N×M cell arrays, and each cell includes a non-volatile memory (NVM, Non-volatile memory) composed of two symmetrically arranged transistors and corresponding variable resistors. FIG. 2 shows the operation mode of the above-mentioned neuron network in the working process, and the weight of each point is W=G ⁺ -G ^- .

It can be seen from the above figure that a complete neuron network circuit chip requires a large number of transistors to form an array, so how to reduce the total area of the neuron network chip is an important problem faced in the prior art.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a neuron network unit, which can reduce the circuit area.

In order to solve the above problems, the present invention provides a neuron network unit, comprising: an inhibitory read control transistor and an excitatory read control transistor arranged in parallel; a write control transistor vertically stacked on top of the above two transistors; the write control transistor The control transistor is arranged opposite to the source of the read control transistor; the drain of the write control transistor is electrically connected to the first end of a magnetic tunnel junction; the drain of the inhibitive read control transistor is connected to the The second end of the magnetic tunnel junction is electrically connected; the drain of the excitatory read control transistor is electrically connected to the second end of the magnetic tunnel junction through a weighted signal line. .

By stacking the transistors of the neuron network unit on top of each other, the invention reduces the total chip area, reduces the physical distance between the write control transistor and the read control transistor, and reduces the parasitic effect and signal caused by the long connection. noise, and clock delays. In addition, multiple transistors share a magnetic tunnel junction, so that when the excitation signal and the inhibitory signal are opposite, the levels are exactly the same and canceled, which improves the accuracy of the deep learning algorithm.

Description of drawings

Figure 1 shows a typical neural network architecture and a corresponding circuit diagram in the prior art.

FIG. 2 is a schematic diagram of the operation mode of the neuron network shown in FIG. 1 in the working process.

FIG. 3 is a schematic structural diagram of a neuron network unit according to a specific embodiment of the invention.

Detailed ways

The specific embodiments of the neuron network unit provided by the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 3 is a schematic structural diagram of a neuron network unit according to this specific embodiment, including a write control transistor T1, an inhibitory read control transistor T21 and an excitatory read control transistor T22, the write control transistor T1 is in the The top and source up and the inhibitory read control transistor T21 and the excitatory read control transistor T22 are in the bottom and source down. The write control transistor T1, the inhibitory read control transistor T21, and the excitatory read control transistor T22 all include a source S+/-, a drain D+/-, and a vertical channel between the source and the drain, the gate G+/- is arranged around the vertical channel. In this embodiment, an inhibitory read control transistor and an excitatory read control transistor are taken as examples to disclose the plurality of transistors arranged in parallel. In other specific embodiments, multiple inhibitory read control transistors T21 and excitatory read control transistors T22 may also be provided, and different transistors are controlled by software to be gated to realize feedback of multiple neurons.

The drain of the write control transistor is electrically connected to the first end of a storage medium unit. In this specific embodiment, the storage medium unit is a magnetic tunnel junction MTJ, that is, the drain of the write control transistor is electrically connected to the first end of a magnetic tunnel junction MTJ. In other specific implementation manners, the medium storage unit may also be a phase-change storage unit, a magnetoresistive storage unit, or other medium structures that store data through resistance modal changes.

The drains of the inhibitory read control transistor T21 and the excitatory read control transistor T22 are electrically connected to the second terminal of the magnetic tunnel junction MTJ through the same weight line W. The first end of the magnetic tunnel junction includes a first ferromagnetic sheet 01 , and the second end includes a second ferromagnetic sheet 02 . The magnetic tunnel junction MTJ further includes an insulating interlayer 03 between the first ferromagnetic sheet 01 and the second ferromagnetic sheet 02 . The thickness of the insulating interlayer 03 is about 0.1 nm˜2.0 nm.

In the resistance characteristics of the above-mentioned magnetic tunnel junction MTJ, when stimulated by a specific external electrical signal, the resistance changes due to the characteristics of its own material, thereby playing the role of storing information. As the volume of the magnetic memory layer is reduced, the spin-polarized current that needs to be injected for writing or switching operations is also smaller. Therefore, this writing method enables device miniaturization and current reduction at the same time. In the prior art, characteristics such as writing current (~50μA), power consumption, writing speed (~10ns), and cell area (~50F ² ) are still far from ideal figures. The basic reason is that the carriers carrying the spin current in the STT (Spin Transfer Torque) flip mechanism are electrons, and the mass of electrons is very light, only 1/1840 of that of protons. Anyone who has studied the most basic physics knows that force or torque is proportional to mass, so even if current can carry spin current and generate torque on magnetic moment, the efficiency will not be too high. Because of the low turnover efficiency, the writing speed is slow, the current is large, and the power consumption is also large. And because to provide a larger current, a larger CMOS is required, which is larger than the MTJ, which becomes the bottleneck of miniaturization. In quantum mechanics, spin interacts with the angular momentum of atomic orbitals, but the source of this force or torque is the nucleus. The larger the atomic number, the greater the spin-orbit interaction. In some special substances, such as topological insulators, there are also abnormally large spin-orbit interactions on the surface. The spin-orbit torque (SOT, Spin Orbit Torque) effect is used to flip the magnetic moment of the free layer in the MTJ, which is the above-mentioned SOT MRAM.

When the above neuron network is working, the write control transistor T1 can be used to control the state of the magnetic tunnel junction MTJ in the above neuron network after being turned on: the write control transistor T1 is turned on and a sufficiently large current is applied to the magnetic tunnel junction MTJ through it, The state of the magnetic tunnel junction MTJ can be rewritten to play the role of logic configuration; the control transistor T1 is turned on and the level used for reading is applied to the magnetic tunnel junction MTJ through it, then the output current of the weight line W is related to the magnetic tunnel junction. The resistance of the MTJ is related and plays an output role. On the other hand, the inhibitory read control transistor T21 or the excitatory read control transistor T22 is turned on by software to enter the working state. When the excitatory read control transistor T22 enters the working state, the state of the magnetic tunnel junction MTJ is configured as the excitatory logic G ⁺ , then the output current of the weight line W is the excitatory logic I=∑G ⁺ V(t); otherwise, When the inhibitory read control transistor T21 enters the working state, the states of all the magnetic tunnel junctions MTJ in the array are configured as the inhibitory logic G ⁻ , and the output current of the weight line W is the inhibitory logic I=∑G ⁻ V( t). The software records these two values separately in the background and performs operations to obtain the final result. In addition, the two transistors share a magnetic tunnel junction, so that when the excitation signal and the inhibitory signal are opposite, the levels are exactly the same and canceled, which improves the accuracy of the deep learning algorithm.

The above technical solution The above technical solution optimizes the stacking of two transistors, and involves the stacking of the two transistors, thereby reducing the overall area of the circuit.

The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can also be made, and these improvements and modifications should also be regarded as It is the protection scope of the present invention.

Claims

A neuron network unit, characterized in that it includes:

Multiple read control transistors arranged in parallel;

a write control transistor vertically stacked on top of the above-mentioned plurality of transistors;

The write control transistor and the source of the read control transistor are arranged opposite to each other;

The drain of the write control transistor is electrically connected to the first end of a storage medium unit;

The drain of the read control transistor is electrically connected to the second end of the storage medium unit through a weighted signal line;

The drain of the excitatory read control transistor is electrically connected to the second terminal of the magnetic tunnel junction through a weighted signal line.
The neuron network unit according to claim 1, wherein the plurality of transistors arranged in parallel include an inhibitory read control transistor and an excitatory read control transistor.
The neuron network unit according to claim 1, wherein the medium storage unit is selected from any one of a magnetic tunnel junction, a phase-change storage unit, and a magnetoresistive storage unit.
The neuron network unit of claim 3, wherein the first end of the magnetic tunnel junction includes a first ferromagnetic sheet, and the second end includes a second ferromagnetic sheet.
The neuron network unit according to claim 4, wherein the magnetic tunnel junction further comprises an insulating interlayer between the first ferromagnetic sheet and the second ferromagnetic sheet.
The neuron network unit according to claim 5, wherein the thickness of the insulating interlayer is about 0.1 nm˜2.0 nm.
The neuron network unit according to claim 1, wherein the write control transistor and the plurality of read control transistors include a source electrode, a drain electrode, and a vertical channel between the source electrode and the drain electrode, and the gate electrode A pole is disposed around the vertical channel.