WO2022105733A1 - 堆叠式光学感测封装体 - Google Patents

堆叠式光学感测封装体 Download PDF

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Publication number
WO2022105733A1
WO2022105733A1 PCT/CN2021/130847 CN2021130847W WO2022105733A1 WO 2022105733 A1 WO2022105733 A1 WO 2022105733A1 CN 2021130847 W CN2021130847 W CN 2021130847W WO 2022105733 A1 WO2022105733 A1 WO 2022105733A1
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WIPO (PCT)
Prior art keywords
light
optical sensing
sensing package
window
photosensitive chip
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PCT/CN2021/130847
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English (en)
French (fr)
Inventor
周正三
范成至
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神盾股份有限公司
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Publication of WO2022105733A1 publication Critical patent/WO2022105733A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
    • G01S17/06—Systems determining position data of a target
    • G01S17/08—Systems determining position data of a target for measuring distance only
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/481—Constructional features, e.g. arrangements of optical elements

Definitions

  • the present invention relates to a stacked optical sensing package, and in particular, to a stacked optical sensing package in which light-emitting elements are stacked on a photosensitive chip.
  • optical depth sensors eg, Time Of Flight (TOF) sensors
  • TOF Time Of Flight
  • 3D imaging three-dimensional (3D) imaging
  • proximity functions such as detection or camera focus.
  • the optical depth sensor emits near-infrared light into the scene, and uses the light's time-of-flight information to measure the distance to objects in the scene.
  • TOF Time Of Flight
  • 3D imaging three-dimensional (3D) imaging
  • proximity functions such as detection or camera focus.
  • the optical depth sensor emits near-infrared light into the scene, and uses the light's time-of-flight information to measure the distance to objects in the scene.
  • the advantages of optical depth sensors are that the depth information calculation is small, the anti-interference is strong, and the measurement range is long, so it has gradually been favored.
  • the core components of the optical depth sensor include: a light source, such as an infrared vertical cavity surface emitting laser (Vertical Cavity Surface Emitting Laser, VCSEL); a light sensor, such as a Single Photon Avalanche Diode (SPAD) ; and Time to Digital Converter (TDC).
  • a light source such as an infrared vertical cavity surface emitting laser (Vertical Cavity Surface Emitting Laser, VCSEL); a light sensor, such as a Single Photon Avalanche Diode (SPAD) ; and Time to Digital Converter (TDC).
  • VCSEL in the optical depth sensor transmits a pulse wave to the scene, the SPAD receives the pulse wave reflected from the object to be measured, the TDC records the time interval between the transmitted pulse and the received pulse, and the depth information of the object to be measured can be calculated by the time of flight .
  • FIG. 1 shows a schematic diagram of a conventional TOF optical sensing module 300 .
  • the TOF optical sensing module 300 includes a cap 310 , a light emitting unit 320 , a sensor chip 330 and a substrate 350 , such as a printed circuit board.
  • the light emitting unit 320 and the sensor chip 330 are disposed on the substrate 350 through an adhesive material.
  • the light emitting unit 320 and the sensor chip 330 are electrically connected to the substrate 350 .
  • At least one reference pixel 331 and at least one sensing pixel 341 are formed on the sensor chip 330 .
  • the cap 310 has an emission window 314 and a reception window 312 and is disposed above the substrate 350 to accommodate the light emitting unit 320 and the sensor chip 330 on the substrate 350 in a chamber 315 of the cap 310 .
  • the light emitting unit 320 emits the measuring light L1 to reach the object (not shown) through the emission window 314 , and the sensing pixel 341 receives the sensing light L3 reflected by the object through the receiving window 312 .
  • the reference light L2 is generated and travels toward the reference pixel 331 . By calculating the time difference between the sensing pixel 341 and the reference pixel 331 receiving the light, it can be converted into distance information.
  • the single light-emitting unit 320 and the single sensor chip 330 are arranged side by side on the substrate 350 by a conventional pick and place method, and then the wires 351 are bonded to sense the The pixel 341 , the reference pixel 331 and the light emitting unit 320 are electrically connected to the substrate 350 so that electrical connection points can be subsequently pulled out from one side of the substrate 350 to a circuit board (not shown). Then, the bonding wire 351 is fixed by using the encapsulant 352 . Next, the cap 310 is assembled on the substrate 350 .
  • the sensing pixels 341 , the reference pixels 331 and the light emitting units 320 are arranged in a pick-and-place manner, it is easy to generate placement errors (eg, several tens of micrometers) during production. Furthermore, when assembling the cap 310 , the alignment of the receiving window 312 with the corresponding sensing pixel 341 and the emitting window 314 with the corresponding light emitting unit 320 also has production problems in assembly accuracy. In addition, this packaging method cannot be used in Chip Scale Package (CSP) or Wafer Level Chip Scale Package (WLCSP), so it cannot effectively mass produce and reduce the package size.
  • CSP Chip Scale Package
  • WLCSP Wafer Level Chip Scale Package
  • an object of the present invention is to provide a stacked optical sensing package, which can be completed by a CSP or WLCSP process, thereby effectively mass-producing and reducing the volume of the package.
  • the present invention provides a stacked optical sensing package, at least comprising: a photosensitive chip having a photosensitive area; a light-emitting element disposed on an upper surface of the photosensitive chip; and a cover , which is arranged on the photosensitive chip and has a receiving window and an emission window.
  • the light-emitting element emits measuring light, a part of the measuring light irradiates a target through the emission window and reflects from the target to output sensing light, and the light sensing area receives the sensing light through the receiving window to generate a sensing electrical signal.
  • the CSP or WLCSP process can be used, the photosensitive chip is used as the packaging substrate, the light-emitting element is stacked on the photosensitive chip, and then the process of electrical connection, packaging and cutting is performed to achieve mass production and reduce the package volume. Purpose.
  • FIG. 1 shows a schematic diagram of a conventional optical sensing module.
  • FIG. 2 shows a schematic diagram of an optical sensing package according to a preferred embodiment of the present invention.
  • FIG. 3 is a schematic diagram illustrating a modification of the optical sensing package of FIG. 2 .
  • FIG. 4A is a schematic diagram showing another modification of the optical sensing package of FIG. 2 .
  • FIG. 4B is a schematic diagram illustrating a variation of the optical sensing package of FIG. 4A .
  • 5A and 5B respectively show schematic diagrams of other modifications of the optical sensing package of FIGS. 2 and 4A .
  • 6A and 6B respectively show schematic diagrams of other modifications of the optical sensing package of FIGS. 2 and 4A .
  • the embodiments of the present invention mainly use the WLCSP or CSP process to complete the optical sensing package, use the wafer-level batch manufacturing process to mass-produce and reduce costs, and greatly improve the light-emitting element and photosensitive through integrated optical manufacturing.
  • the accuracy of chip arrangement (even down to micron-level accuracy).
  • Die Bond die bonding
  • gluing or surface mount technology Surface Mount Technology, SMT
  • SMT surface Mount Technology
  • FIG. 2 shows a schematic diagram of an optical sensing package according to a preferred embodiment of the present invention.
  • the present embodiment provides a stacked optical sensing package 100 , which is a packaged package and at least includes a photosensitive chip 10 , a light-emitting element 20 and a cover 30 .
  • the stacked optical sensing package 100 may further include a light-emitting driving module (not shown) for controlling the operation of the light-emitting element 20 .
  • the light-emitting driving module can be integrated with the photosensitive chip 10 , or can be separated from the photosensitive chip 10 and the light-emitting element 20 and electrically connected together by wires, so it is not particularly limited here.
  • the photosensitive chip 10 has a photosensitive area 11 .
  • the light-emitting element 20 is disposed on an upper surface 10T of the photosensitive chip 10 . That is, the light emitting element 20 is stacked on the photosensitive chip 10 .
  • the cover body 30 is disposed on the photosensitive chip 10 , and has a receiving window 31 and an emission window 32 as a light confinement structure, so that the light-emitting element 20 emits the measurement light L1 to travel outward from the emission window 32 .
  • a part of the measuring light L1 is irradiated on a target F through the emission window 32 and reflected from the target F to output the sensing light L3 .
  • the light sensing area 11 receives the sensing light L3 through the receiving window 31 to generate a sensing electrical signal.
  • the light-emitting element 20 and the photosensitive chip 10 of this embodiment transmit and receive light through the above-mentioned light confinement structure, so that the photosensitive chip 10 generates a sensing electrical signal.
  • the CSP or WLCSP process can be used to manufacture a plurality of optical sensing packages 100 on a chip or a wafer, and then dicing to form a plurality of optical sensing packages 100 , so that the plane size of the optical sensing packages 100 is It is close to the plane size of the upper surface 10T of the photosensitive chip 10 , so that mass production can be performed, and the volume of the optical sensing package 100 can be effectively reduced.
  • the photosensitive chip 10 has: a photosensitive structure, such as a photodiode, an avalanche diode (Avalanche Photo Diode, APD), etc.; an optional micro-optical lens group (not shown) is located above the photosensitive structure, wherein the micro The optical lens group may include optical elements such as microlenses, filter layers, light apertures, etc.; and a sensing circuit for processing electrical signals from the photosensitive structure.
  • a photosensitive structure such as a photodiode, an avalanche diode (Avalanche Photo Diode, APD), etc.
  • an optional micro-optical lens group (not shown) is located above the photosensitive structure, wherein the micro
  • the optical lens group may include optical elements such as microlenses, filter layers, light apertures, etc.
  • a sensing circuit for processing electrical signals from the photosensitive structure.
  • the photosensitive chip 10 can be fabricated by, for example, a complementary metal-oxide semiconductor (Complementary Metal-Oxide Semiconductor, CMOS) process, such as a front side illumination (FSI) or a back side illumination (BSI) process, or or other semiconductor processes, the present invention is not limited to this.
  • CMOS complementary metal-oxide semiconductor
  • FSI front side illumination
  • BSI back side illumination
  • the material of the photosensitive chip 10 may include semiconductor materials, such as silicon, germanium, gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium alloy, phosphorus arsenide Gallium alloy, arsenic aluminum indium alloy, arsenic aluminum gallium alloy, arsenic indium gallium alloy, phosphorus indium gallium alloy, phosphorus indium arsenic gallium alloy, or a combination of the above materials.
  • the photosensitive chip may also include one or more electrical components (eg, integrated circuits).
  • Integrated circuits may be analog or digital circuits, which may be implemented as active elements, passive elements, conductive and dielectric layers, etc. formed within a chip and electrically connected according to the electrical design and function of the chip.
  • the light-emitting element 20 may be a VCSEL or a light-emitting diode (Light-Emitting Diode, LED), such as an infrared LED.
  • the light-emitting element 20 can be electrically connected to a part of the plurality of electrical contacts 12 on the upper surface 10T of the photosensitive chip 10 by using Metal Solder SMT (not shown in the figure) or metal wire bonding. More specifically, the light-emitting element 20 is electrically connected to the electrical contacts 12 (eg, bonding pads) through at least a plurality of connecting wires 40 and interconnecting wires in the photosensitive chip 10 .
  • the cover body 30 can be formed on the photosensitive chip 10 by using wafer-level photolithography (WLP), compression molding or screen printing, which partially covers the light-emitting element 20, In addition, by covering the connecting wires 40 , the covering body 30 can isolate the photosensitive chip 10 from the light emitting element 20 , forming a surrounding structure and providing the function of fixing and protecting the light emitting element 20 .
  • the cover body 30 may be formed of an opaque organic material.
  • the cover body 30 may be formed of a light-transmitting organic material, and an opaque light blocking layer (not shown in the figure) is formed on the upper surface 30T of the cover body 30 to further block light.
  • the material of the light blocking layer can be any metal material or non-metal material that can prevent light penetration.
  • the cover 30 is formed from a single layer or multiple layers of material used by WLP or screen printing techniques. The cover body 30 can further limit the angle of light emission and light reception, and also prevent stray light from entering the photosensitive chip 10 .
  • Another part of the electrical contacts 12 are the sensing pixels that are electrically connected to the light sensing area 11. In this embodiment, the electrical contacts 12 are electrically connected to an external printed circuit board or a flexible circuit board (not shown) by wire bonding.
  • the optical sensing package 100 may further include a first optical device 36 and a second optical device 37, respectively. It is arranged on the receiving window 31 and the transmitting window 32 .
  • the first optical device 36 and the second optical device 37 include but are not limited to light-transmitting elements or optical devices with special optical functions, such as curved mirrors, lenses with functions such as astigmatism or light-gathering, and diffractive optical elements (Diffraction Optical Elements). , DOE), filter elements of specific wavelengths, other optical elements, or a combination of multiple optical functions, etc.
  • At least one photolithography (Photo Lithography) process is used to fabricate a Fresnel lens with at least one order depth on the transparent layer in the receiving window 31 or the transmitting window 32, which can detect the sensing light L3.
  • the measurement light L1 is optically processed for focusing or beam expansion.
  • the receiving window 31 and the transmitting window 32 are cavities. For the sake of simplicity, the following FIGS. 3 to 6B will take a cavity as an example for description.
  • FIG. 3 to 6A and 6B are schematic diagrams showing several variations of the optical sensing package of FIG. 2 . Elements with the same reference numerals as in FIG. 2 have the same functions, and will not be repeated here.
  • FIG. 3 this example is similar to FIG. 2 , the difference is that a plurality of conductive filling holes 15 (or conductive plugs) are formed in the photosensitive chip 10 , so that the electrical contacts 12 can be electrically connected to the conductive filling holes 15 .
  • the input and output contacts 16 of the lower surface 10B of the photosensitive chip 10 (shown schematically by arrows).
  • the conductive via 15 is a Through Silicon Via (TSV).
  • TSV Through Silicon Via
  • the contacts include solder pads or solder balls, which may be in Ball Grid Array (BGA) or Land Grid Array (LGA) packages.
  • BGA Ball Grid Array
  • LGA Land Grid Array
  • RDL redistribution layer
  • this example is similar to FIG. 2 , in which a plurality of redistributed wires 33 are mainly used to replace the connecting wires 40 provided by the bonding method in FIG. 2 .
  • the light-emitting element 20 is electrically connected to the electrical contacts 12 at least through redistributed wires 33 (providing horizontal and vertical conductive paths).
  • the engraving process is different from the wire bonding method shown in Figure 2, and is more suitable for wafer-level fabrication and integration.
  • Using the redistributed wires 33 can avoid the limitation of the wire arc height required for wire bonding, and help to further reduce the volume of the optical sensing package.
  • the light-emitting element 20 can be thinned to 100 microns or even thinner, and then placed on the photosensitive chip 10 , then the redistributed wires 33 and the cover 30 are arranged, and then cut to complete the optical sensing package 100 .
  • FIGS. 3 and 4A can be changed to obtain the optical sensing package 100 of FIG. 4B , wherein the light-emitting element 20 at least passes through the plurality of redistributed wires 33 , the electrical contacts 12 and the conductive fillers.
  • the hole 15 is electrically connected to the input and output contacts 16, which has the effect of integrating TSV and redistributed wires.
  • this example is similar to FIG. 2 except that the first optical device 36 and the second optical device 37 are attached to the upper surface 30T of the cover body 30 to cover the receiving window 31 and the transmitting window 32 respectively. , provides the function of optical processing and protects the photosensitive chip 10 and the light-emitting element 20 .
  • a carrier plate (not shown in the figure) having a plurality of first optical devices 36 and second optical devices 37 arranged in an array can be attached to the cover body 30, and then a cutting process can be performed to form Optical sensing package 100 .
  • FIG. 5B this example is similar to FIG. 4A and FIG. 5A , wherein the first optical device 36 and the second optical device 37 are attached to the cover body 30 to cover the receiving window 31 and the transmitting window 32 respectively, providing a structure similar to that shown in FIG. 4A . Integration effect with Figure 5A.
  • the cover body 30 is a protective cover made of plastic material by injection molding, and the first optical device 36 and the second optical device 37 are first attached to the cover
  • the body 30 corresponds to the lower surface 30B of the receiving window 31 and the transmitting window 32 , and the protective cover is pasted on the photosensitive chip 10 , and the electrical contacts 12 are located outside the protective cover.
  • the cover body 30 may no longer be in direct contact with the light-emitting element 20 , but there is a gap G between the cover body 30 and the light-emitting element 20 .
  • the above-mentioned assembly method can also be performed in a wafer-level or chip-level manner. It can be understood that, in another embodiment, the connecting wire 40 may be covered by an encapsulant (not shown).
  • this example is similar to the integrated modification example of FIG. 4A and FIG. 6A , in which after the cover body 30 is formed, the enclosing structure 34 of the optical sensing package body 100 is injection-molded with a plastic material as a protective cover, The first optical device 36 and the second optical device 37 are attached to the lower surface 34B of the enclosure structure 34 to cover the receiving window 31 and the emission window 32 respectively, and then the protective cover is pasted on the cover body 30 to realize WLP and Assembly integration. It can be understood that, in another embodiment, the surrounding structure 34 can also be pasted on the photosensitive chip 10 .

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Abstract

一种堆叠式光学感测封装体，至少包含：一感光芯片，具有一光感测区；一发光元件，设置于感光芯片的一上表面上；及一覆盖体，设置于感光芯片上，并且具有一接收窗及一发射窗。发光元件发射测量光，测量光的一部分通过发射窗照射在一目标物并从目标物反射输出感测光，光感测区通过接收窗接收感测光而产生一感测电信号。

Description

堆叠式光学感测封装体 技术领域
本发明是有关于一种堆叠式光学感测封装体，且特别是有关于一种将发光元件堆叠在感光芯片上的堆叠式光学感测封装体。
背景技术
现今的智能电话、平板计算机或其他手持装置搭配有光学模块，例如光学深度感测器(例如飞行时间(Time Of Flight，TOF)感测器)，来达成手势检测、三维(3D)成像、近接检测或相机对焦等功能。操作时，光学深度感测器向场景中发射近红外光，利用光的飞行时间信息，测量场景中物体的距离。光学深度感测器的优点是深度信息计算量小，抗干扰性强，测量范围远，因此已经渐渐受到青睐。
光学深度感测器的核心组件包含：光源，例如是红外线垂直共振腔面射激光(Vertical Cavity Surface Emitting Laser,VCSEL)；光感测器，例如是单光子雪崩二极管(Single Photon Avalanche Diode,SPAD)；和时间至数字转换器(Time to Digital Converter,TDC)。光学深度感测器中的VCSEL向场景发射脉冲波，SPAD接收从待测物体反射回来的脉冲波，TDC记录发射脉冲和接收脉冲之间的时间间隔，可以利用飞行时间计算待测物体的深度信息。
图1显示一种传统的TOF光学感测模块300的示意图。如图1所示，TOF光学感测模块300包含一帽盖(cap)310、一发光单元320、一感测器芯片330及一基板350，譬如是印刷电路板。基板350上通过粘胶材料设置发光单元320及感测器芯片330。发光单元320及感测器芯片330电连接至基板350。感测器芯片330上形成有至少一参考像素331及至少一感测像素341。帽盖310具有一发射窗314及一接收窗312，并且设置于基板350的上方，以将基板350上的发光单元320及感测器芯片330容置于帽盖310的一腔室315中。发光单元320发出测量光L1通过发射窗314到达物体(未显示)，感测像素341通过接收窗312接收物体反射的感测光L3。测量光L1被帽盖310反射后产生参考光L2朝参考像素331行进。借由计算感测像素341与参考像素331收到光线的时间差，可以换算成距离信息。
在上述的光学感测模块300中，单一发光单元320与单一感测器芯片330是先通过传统的取放(pick and place)方式并排设置于基板350上，再通过打线351而将感测像素 341、参考像素331及发光单元320电连接至基板350，以便后续可以从基板350的一侧拉出电连接点到电路板(未显示)。然后，使用封装胶352来固定打线351。接着，将帽盖310组装至基板350上。因为用取放方式设置感测像素341、参考像素331及发光单元320，故很容易在生产时产生放置时的误差(例如几十微米)。再者，在组装帽盖310时，接收窗312与对应的感测像素341及发射窗314与对应的发光单元320的对准也都有组装精准度上的生产问题。此外，这种封装方式无法用芯片尺寸封装(Chip Scale Package,CSP)或晶圆级芯片尺寸封装(Wafer Level Chip Scale Package,WLCSP)，因此无法有效大量生产及缩小封装体积。
发明内容
因此，本发明的一个目的是提供一种堆叠式光学感测封装体，可以用CSP或WLCSP的工艺来完成光学感测封装体，进而有效大量生产，缩小封装体的体积。
为达上述目的，本发明提供一种堆叠式光学感测封装体，至少包含：一感光芯片，具有一光感测区；一发光元件，设置于感光芯片的一上表面上；及一覆盖体，设置于感光芯片上，并且具有一接收窗及一发射窗。发光元件发射测量光，测量光的一部分通过发射窗照射在一目标物并从目标物反射输出感测光，光感测区通过接收窗接收感测光而产生一感测电信号。
利用上述的实施例，可以采用CSP或WLCSP工艺，以感光芯片当作封装基板，将发光元件堆叠于感光芯片的上面，再进行电连接封装及切割的工艺，以达到大量生产及缩小封装体积的目的。
为让本发明的上述内容能更明显易懂，下文特举较佳实施例，并配合所附图式，作详细说明如下。
附图说明
图1显示一种传统的光学感测模块的示意图。
图2显示依据本发明较佳实施例的光学感测封装体的示意图。
图3显示图2的光学感测封装体的一变化例的示意图。
图4A显示图2的光学感测封装体的另一变化例的示意图。
图4B显示图4A的光学感测封装体的一变化例的示意图。
图5A与图5B分别显示图2与图4A的光学感测封装体的其他变化例的示意图。
图6A与图6B分别显示图2与图4A的光学感测封装体的其他变化例的示意图。
附图说明：
F:目标物
G:间隙
L1:测量光
L2:参考光
L3:感测光
10:感光芯片
10B:下表面
10T:上表面
11:光感测区
12:电气接点
15:导电填孔
16:输入输出接点
20:发光元件
30:覆盖体
30B:下表面
30T:上表面
31:接收窗
32:发射窗
33:重布导线
34:围挡结构
34B:下表面
36:第一光学器件
37:第二光学器件
40:连接线
100:光学感测封装体
300:光学感测模块
310:帽盖
312:接收窗
314:发射窗
315:腔室
320:发光单元
330:感测器芯片
331:参考像素
341:感测像素
350:基板
351:打线
352:封装胶
具体实施方式
本发明的实施例主要是采用WLCSP或CSP工艺来完成光学感测封装体，利用晶圆级的批量制造工艺，来大量生产并降低成本，并且通过整合性的光学制造，大幅改进发光元件与感光芯片排列的精准度(甚至到微米级精度)。利用晶粒键合(Die Bond)、胶合或是表面安装技术(Surface Mount Technology,SMT)将发光元件(例如发光芯片)放置于具有感光芯片的晶圆或芯片的上面，进行电连接以及封装的工艺，再进行切割，以达到大量生产、缩小封装体积的目的，并且实现收发光或飞行时间感测的效果。由于本领域技术人员可以从以下实施例轻易理解如何进行WLCSP或CSP工艺，故于此省略其详细图式说明。
图2显示依据本发明较佳实施例的光学感测封装体的示意图。如图2所示，本实施例提供一种堆叠式光学感测封装体100，其为一个封装完成的封装体，并且至少包含一感光芯片10、一发光元件20及一覆盖体30。于另一实施例中，堆叠式光学感测封装体100可以还包含一发光驱动模块(未显示)，用于控制发光元件20的操作。可以理解的，发光驱动模块可以与感光芯片10整合成一体，也可以与感光芯片10及发光元件20分开，借由导线而电连接在一起，故于此不作特别限制。
感光芯片10具有一光感测区11。发光元件20设置于感光芯片10的一上表面10T上。亦即，发光元件20堆叠于感光芯片10上。覆盖体30设置于感光芯片10上，并且具有一接收窗31及一发射窗32作为光限制结构，使发光元件20发射测量光L1从发射窗32往外行进。测量光L1的一部分通过发射窗32照射在一目标物F并从目标物F反射输出感测光L3，光感测区11通过接收窗31接收感测光L3而产生一感测电信号。因 此，本实施例的发光元件20与感光芯片10通过上述光限制结构来进行光线发射及接收，使感光芯片10产生感测电信号。依据上述结构，可以用CSP或WLCSP工艺来制造多个光学感测封装体100于芯片或晶圆上，然后进行切割形成多个光学感测封装体100，使得光学感测封装体100的平面尺寸接近感光芯片10的上表面10T的平面尺寸，如此可以进行大量生产，并有效缩小光学感测封装体100的体积。
于一实施例中，感光芯片10具有：光敏结构，例如光电二极管、雪崩二极管(Avalanche Photo Diode,APD)等等；可选的微光学镜组(未显示)，位于光敏结构的上方，其中微光学镜组可以包含微透镜、滤光层、光孔等光学元件；以及感测电路，用于处理来自于光敏结构的电信号。感光芯片10的制造可以是使用例如互补式金属氧化物半导体(Complementary Metal-Oxide Semiconductor,CMOS)工艺，例如采用前面照度(Front Side Illumination,FSI)或背面照度(Back Side Illumination,BSI)工艺，抑或者其他的半导体工艺，本发明并不以此为限。感光芯片10的材料可以包含半导体材料，半导体材料例如硅、锗、氮化镓、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、硅锗合金、磷砷镓合金、砷铝铟合金、砷铝镓合金、砷铟镓合金、磷铟镓合金、磷砷铟镓合金或上述材料的组合。感光芯片上可以还包括一个或多个电气元件(如集成电路)。集成电路可以是类比或数字电路，类比或数字电路可以被实现为在芯片内形成并且根据芯片的电气设计与功能而达成电连接的主动元件、被动元件、导电层和介电层等等。此外，发光元件20可以是VCSEL或发光二极管(Light-Emitting Diode,LED)，例如红外线LED。
于本实施例中，可利用金属焊料(Metal Solder)SMT(图中未示)或金属打线方式将发光元件20电连接至感光芯片10的上表面10T的多个电气接点12的一部分。更具体地，发光元件20至少通过多条连接线40以及感光芯片10中的内连线而电连接至电气接点12(例如焊垫)。可以利用晶圆级光刻技术(Wafer-Level Photolithography,WLP)、热压成型(Compression Molding)或网印(Screen printing)方式于感光芯片10上形成覆盖体30，其局部包覆发光元件20，且包覆连接线40，覆盖体30可以将感光芯片10与发光元件20阻隔开，形成围挡结构并且提供固定及保护发光元件20的功能。于一例子中，覆盖体30可以是由不透光的有机材料所形成。于另一例子中，覆盖体30可以是由透光有机材料形成，再于覆盖体30的上表面30T上形成一不透光的阻光层(图中未示)，用于更进一步阻挡光线穿透，阻光层的材料可以是任何能阻止光线穿透的金属材料或非金属材料。于又另一例子中，覆盖体30为WLP或网印技术所使用的单层或多层材料所形成。覆盖体30可以进一步限制发光与收光的角度，也避免杂散光进入感光芯片10。电气接点12的另 一部分是电连接至光感测区11的感测像素。于本实施例中，电气接点12通过打线方式电连接至外部印刷电路板或软性电路板(未显示)。
于本实施例中，接收窗31及发射窗32的一者或两者中填有透明层，且光学感测封装体100可以还包含一第一光学器件36及一第二光学器件37，分别设置于接收窗31及发射窗32上。第一光学器件36及第二光学器件37包含但不限于透光元件或者具有特殊光学功能的光学器件，例如是曲面镜、具有例如散光或聚光功能的镜头、绕射光学元件(Diffraction Optical Element，DOE)、特定波长的滤光元件、其他光学元件、抑或多个光学功能的结合的器件等等。于一例子中，利用至少一道光刻(Photo Lithography)工艺，在接收窗31或发射窗32中的透明层上制作至少一阶深度的菲涅尔透镜(Fresnel Lens)，可以对感测光L3或测量光L1做聚焦或扩束的光学处理。于另一实施中，接收窗31及发射窗32为空腔。为简化起见，以下的图3至图6B，将以空腔作为例子来说明。
图3至图6A与图6B显示图2的光学感测封装体的数个变化例的示意图。与图2具有相同元件符号的元件具有相同功能，在此不再赘述。如图3所示，本例类似于图2，差异点在于感光芯片10中形成有多个导电填孔15(或称导电柱塞)，使得电气接点12可以通过导电填孔15而电连接至感光芯片10的一下表面10B的输入输出接点16(以箭头示意表示)。于本例中，导电填孔15为一硅穿孔(Through Silicon Via,TSV)。接点的实施方式有很多，于此不特别限制。于一例中，接点包含焊垫或焊球，可以采用球栅网格阵列封装(Ball Grid Array,BGA)或平面网格阵列封装(Land Grid Array,LGA)。于另一例中，也可以在光学感测封装体100的背面配置有额外的重新分布层(ReDistribution Layer,RDL)(图中未示)来将封装的焊垫或焊球做重新分布，以配合所欲安装的电子装置的输入输出接点用。
如图4A所示，本例类似于图2，其中主要是使用多条重布导线33来取代图2的打线方式设置的连接线40。另外，发光元件20至少通过重布导线33(提供水平及铅直方向的导电路径)而电连接至电气接点12，重布导线33可以借由金属镀膜、电镀、或网印等工艺再配合光刻工艺制作，有别于图2的打线方式，更适合于晶圆级的制作跟整合。利用重布导线33可以免去打线所需要的打线弧高的限制，并有助于更进一步缩小光学感测封装体的体积。实际制作时，可以将发光元件20磨薄到100微米或甚至更薄，再放置到感光芯片10上，然后布置重布导线33及覆盖体30，再进行切割，完成光学感测封装体100。
可以理解的，可以依据图3与图4A的部分结构予以变化，以获得图4B的光学感测 封装体100，其中发光元件20至少通过所述多条重布导线33、电气接点12及导电填孔15而电连接至输入输出接点16，具有TSV与重布导线的整合效果。
如图5A所示，本例类似于图2，差异点在于第一光学器件36与第二光学器件37两者贴合至覆盖体30的上表面30T，以分别覆盖接收窗31与发射窗32，提供光学处理的功能并且保护感光芯片10与发光元件20。以晶圆级工艺制作时，可以将具有阵列排列的多个第一光学器件36与第二光学器件37的载板(图中未示)贴合至覆盖体30上后，进行切割工艺以形成光学感测封装体100。
如图5B所示，本例类似于图4A与图5A，其中第一光学器件36与第二光学器件37贴合至覆盖体30，以分别覆盖接收窗31与发射窗32，提供类似图4A与图5A的整合效果。
如图6A所示，本例类似于图5A，差异点在于覆盖体30是由塑胶材料通过射出成型所制成的保护盖，先将第一光学器件36与第二光学器件37贴合至覆盖体30对应于接收窗31与发射窗32的一下表面30B，再将保护盖粘贴至感光芯片10上，并使电气接点12位于保护盖的外部。另外，覆盖体30可以不再与发光元件20有直接接触，而是覆盖体30与发光元件20之间有隔开的间隙G。上述组装方式，亦可通过晶圆级或芯片级的方式进行。可以理解的，于另一实施例中，连接线40可以由封装胶(未显示)包覆住。
如图6B所示，本例类似于图4A与图6A的整合变化例，其中在形成覆盖体30以后，利用塑胶材料射出成型的光学感测封装体100的围挡结构34当作保护盖，将第一光学器件36与第二光学器件37贴合至围挡结构34的下表面34B，而分别覆盖接收窗31与该发射窗32，再将保护盖粘贴至覆盖体30上，实现WLP与组装的整合。可以理解的，于另一实施例中，围挡结构34也可以粘贴至感光芯片10上。
值得注意的是，上述所有实施例，都可以适当的交互组合、替换或修改，以提供多样化的效果。
在较佳实施例的详细说明中所提出的具体实施例仅用以方便说明本发明的技术内容，而非将本发明狭义地限制于上述实施例，在不超出本发明的精神及权利要求保护范围的情况下，所做的种种变化实施，皆属于本发明的范围。

Claims (15)

  1. 一种堆叠式光学感测封装体(100)，其特征在于，至少包含：
    一感光芯片(10)，具有一光感测区(11)；
    一发光元件(20)，设置于所述感光芯片(10)的一上表面(10T)上；及
    一覆盖体(30)，设置于所述感光芯片(10)上，并且具有一接收窗(31)及一发射窗(32)，其中所述发光元件(20)发射测量光(L1)，所述测量光(L1)的一部分通过所述发射窗(32)照射在一目标物(F)并从所述目标物(F)反射输出感测光(L3)，所述光感测区(11)通过所述接收窗(31)接收所述感测光(L3)而产生一感测电信号。
  2. 根据权利要求1所述的堆叠式光学感测封装体(100)，其特征在于，所述覆盖体(30)局部包覆所述发光元件(20)，并具有所述发射窗(32)及所述接收窗(31)。
  3. 根据权利要求1所述的堆叠式光学感测封装体(100)，其特征在于，所述发光元件(20)至少通过多条连接线(40)而电连接至所述感光芯片(10)的所述上表面(10T)的多个电气接点(12)的一部分，且所述覆盖体(30)包覆所述多条连接线(40)。
  4. 根据权利要求3所述的堆叠式光学感测封装体(100)，其特征在于，所述多个电气接点(12)至少通过多个导电填孔(15)而电连接至所述感光芯片(10)的一下表面(10B)的多个输入输出接点(16)。
  5. 根据权利要求1所述的堆叠式光学感测封装体(100)，其特征在于，所述发光元件(20)至少通过多条重布导线(33)而电连接至所述感光芯片(10)的所述上表面(10T)的多个电气接点(12)的一部分，且所述覆盖体(30)包覆所述多条重布导线(33)。
  6. 根据权利要求5所述的堆叠式光学感测封装体(100)，其特征在于，所述多个电气接点(12)至少通过所述多条重布导线(33)、多个导电填孔(15)而电连接至所述感光芯片(10)的一下表面(10B)的多个输入输出接点(16)。
  7. 根据权利要求1所述的堆叠式光学感测封装体(100)，其特征在于，还包含：
    一第一光学器件(36)与一第二光学器件(37)，两者贴合至所述覆盖体(30)，以分别覆盖所述接收窗(31)与所述发射窗(32)。
  8. 根据权利要求7所述的堆叠式光学感测封装体(100)，其特征在于，所述覆盖体(30)局部包覆所述发光元件(20)，且所述第一光学器件(36)与所述第二光学器件(37)贴合至所述覆盖体(30)的一上表面(34T)。
  9. 根据权利要求7所述的堆叠式光学感测封装体(100)，其特征在于，所述第一光学器件(36)与所述第二光学器件(37)贴合至所述覆盖体(30)的一下表面(30B)。
  10. 根据权利要求7所述的堆叠式光学感测封装体(100)，其特征在于，所述覆盖体(30)粘贴至所述感光芯片(10)，且所述覆盖体(30)与所述发光元件(20)之间有隔开的间隙(G)。
  11. 根据权利要求1所述的堆叠式光学感测封装体(100)，其特征在于，所述接收窗(31)或所述发射窗(32)中填有透明层。
  12. 根据权利要求11所述的堆叠式光学感测封装体(100)，其特征在于，所述透明层上形成有菲涅尔透镜。
  13. 根据权利要求1所述的堆叠式光学感测封装体(100)，其特征在于，所述接收窗(31)及所述发射窗(32)中填有透明层，且所述堆叠式光学感测封装体(100)还包含一第一光学器件(36)及一第二光学器件(37)，分别位于所述接收窗(31)的所述透明层及所述发射窗(32)的所述透明层上。
  14. 根据权利要求1所述的堆叠式光学感测封装体(100)，其特征在于，还包含一发光驱动模块，用于控制所述发光元件(20)的操作。
  15. 根据权利要求1所述的堆叠式光学感测封装体(100)，其特征在于，所述覆盖体(30)局部包覆所述发光元件(20)，并具有所述发射窗(32)及所述接收窗(31)，其中所述发光元件(20)至少通过多条重布导线(33)及多个电气接点(12)而电连接至所述感光芯片(10)的所述上表面(10T)的多个电气接点(12)的一部分，且所述覆盖体(30)包覆所述多条重布导线(33)，且所述堆叠式光学感测封装体(100)还包含：
    一围挡结构(34)，设置于所述覆盖体(30)上；以及
    一第一光学器件(36)与一第二光学器件(37)，两者贴合至所述围挡结构(34)，以分别覆盖所述接收窗(31)与所述发射窗(32)。
PCT/CN2021/130847 2020-11-19 2021-11-16 堆叠式光学感测封装体 WO2022105733A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102447002A (zh) * 2010-10-07 2012-05-09 苏炎坤 堆叠型光电感测装置
TWM445768U (zh) * 2012-07-27 2013-01-21 Txc Corp 疊設式光感測晶片封裝結構
CN104766847A (zh) * 2014-01-07 2015-07-08 财团法人工业技术研究院 导通孔结构、封装结构以及光感测元件封装
CN107430187A (zh) * 2014-12-02 2017-12-01 新加坡恒立私人有限公司 深度传感器模块和深度感测方法
US20180292568A1 (en) * 2017-04-11 2018-10-11 Dapa, Inc. Optical proximity sensor with a self-integrated barrier

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102447002A (zh) * 2010-10-07 2012-05-09 苏炎坤 堆叠型光电感测装置
TWM445768U (zh) * 2012-07-27 2013-01-21 Txc Corp 疊設式光感測晶片封裝結構
CN104766847A (zh) * 2014-01-07 2015-07-08 财团法人工业技术研究院 导通孔结构、封装结构以及光感测元件封装
CN107430187A (zh) * 2014-12-02 2017-12-01 新加坡恒立私人有限公司 深度传感器模块和深度感测方法
US20180292568A1 (en) * 2017-04-11 2018-10-11 Dapa, Inc. Optical proximity sensor with a self-integrated barrier

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