WO2022104074A1 - Transfert de substrat par épitaxie - Google Patents

Transfert de substrat par épitaxie Download PDF

Info

Publication number
WO2022104074A1
WO2022104074A1 PCT/US2021/059161 US2021059161W WO2022104074A1 WO 2022104074 A1 WO2022104074 A1 WO 2022104074A1 US 2021059161 W US2021059161 W US 2021059161W WO 2022104074 A1 WO2022104074 A1 WO 2022104074A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
mask
gan
repeating units
epitaxy
Prior art date
Application number
PCT/US2021/059161
Other languages
English (en)
Inventor
Jia Wang
Ya-Hong Xie
Hiroshi Amano
Original Assignee
The Regents Of The University Of California
National University Corporation Tokai National Higher Education And Research System
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Regents Of The University Of California, National University Corporation Tokai National Higher Education And Research System filed Critical The Regents Of The University Of California
Publication of WO2022104074A1 publication Critical patent/WO2022104074A1/fr

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/0242Crystalline insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02576N-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02579P-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639Preparation of substrate for selective deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639Preparation of substrate for selective deposition
    • H01L21/02642Mask materials other than SiO2 or SiN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647Lateral overgrowth
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate

Definitions

  • the technical field relates to a method of epitaxy-enabled substrate transfer, and in particular, relates to methods used to transfer a selective-area doping structure from a substrate to another substrate via epitaxy.
  • etch and regrowth the excess crystal defectivity at the regrown interface introduced during dry etch causes problems such as type conversion and large leakage current along regrowth interface.
  • ion implantation can only reach rather limited doping depth and the annealing heat treatment for damage recovery by ion implantation are complicated. Few reports of the successful activation of ion-implanted magnesium to date require extreme condition of high temperature and ultra-high pressure.
  • an article of manufacture or product includes a substrate comprising Group-Ill -nitride material (e.g., GaN), wherein a selective-area doping profile is constructed one side of the substrate, wherein the doping profile comprises repeating units each of which features sharp lateral p-n junctions or n'-n + homojunctions with significant and adjustable junction length and uniform widths.
  • the selective-area doping profile is produced by, in one embodiment, selective-area epitaxial growths carried out by metalorganic vapor phase epitaxy (MOVPE) and halide vapor phase epitaxy (HVPE), successively.
  • MOVPE metalorganic vapor phase epitaxy
  • HVPE halide vapor phase epitaxy
  • the mask pattern is stripe-like (or hexagonal in another embodiment), and the epitaxial growth is used to thicken the GaN film performed via HVPE.
  • the final article of manufacture is made using a foreign or parent substrate that is separated during the manufacturing process to liberate a transfer substrate that includes the repeating units therein.
  • the selective-area epitaxial growth of the repeating units e.g., islands
  • MOVPE MOVPE
  • HVPE HVPE was used to coalesce the islands and also to grow a thickened GaN film (to generate the transfer substrate).
  • the method is slightly different in that the selective-area epitaxial growth is carried out by MOVPE through coalescence of the repeating units.
  • the mask pattern is stripe-like, HVPE is used for epitaxial growth to form the thicken GaN film.
  • the method is slightly different in that the mask pattern is hexagon-like.
  • the selective area epitaxial growths are MOVPE and HVPE successively, and the epitaxial growth to thicken GaN film is performed via HVPE.
  • a method of epitaxy-enabled substrate transfer to form an article of manufacture includes the operations of: performing a plurality of selective-area epitaxy operations of a single crystalline material on a mask- patterned substrate, wherein each of the plurality of selective-area epitaxy operations create repeating units along the surface of the mask-patterned substrate having discrete doping profiles on the mask-patterned substrate; epitaxially growing a transfer substrate on the repeating units; and separating the transfer substrate from the mask-patterned substrate, wherein the repeating units having discrete doping profiles on the mask-patterned substrate are transferred to the transfer substrate.
  • the article of manufacture (or product) comprises a transfer substrate comprising a single crystalline material, polycrystalline material, or amorphous material, wherein the repeating units formed thereon have discrete doping profiles that are located on one side of the virtual or transfer substrate.
  • an article of manufacture includes a poly crystalline gallium nitride substrate having a first side and a second side, the first side of the poly crystalline gallium nitride substrate comprising a plurality of single-crystalline gallium nitride repeating units having discrete doping profiles forming a plurality of lateral p-n junctions across the surface of the first side of the polycrystalline gallium nitride substrate.
  • the article of manufacture may include a vertical MOSFET having a planar gate structure formed on the first side between adjacent single-crystalline gallium nitride repeating units and further comprising a pair of source contacts disposed on the first side over the adjacent single-crystalline gallium nitride repeating units and a drain contact disclosed on the second side of the substrate.
  • VJFETs vertical junction field effect transistors
  • junction barrier Schottky diodes junction barrier Schottky diodes
  • super-junction MOSFETs transistors, power electronics, sensors, p-GaN, etc.
  • FIG. 1 is a cross-sectional schematic illustration of mask-paterned substrate.
  • FIG. 2 is a top-view schematic illustration of one example of mask paterns, wherein the white stripe illustrates the window regions, and the textured stripe illustrates mask regions.
  • FIG. 3 is a cross-sectional schematic illustration of ELOG of an array of GaN islands via MOVPE with in-situ doping operations, wherein the doping sequence is n + /n7p- type successively.
  • FIG. 4 is a cross-sectional schematic illustration of selective area epitaxy and film thickening via HVPE, wherein GaN stripes coalesce into a continuous film before the thickness of film increases incrementally.
  • FIG. 5 is a cross-sectional schematic illustration of separation of the thickened GaN film from mask-paterned foreign substrate to create the transfer substrate having the repeating units formed thereon.
  • FIG. 6 is a cross-sectional schematic illustration of the as-separated GaN substrate, wherein a selective-area doping profile is constructed at one side thereof with a reversed polarity from that which was originally grown during selective area epitaxial growth(s). Furthermore, a periodic ridge-like structure or protrusion is also preserved on the surface of GaN substrate, characteristic of complete separation of GaN film from the foreign substrate.
  • FIG. 7 is a top-view schematic illustration of a product of GaN substrate such as that illustrated in FIG. 6 which is grown and separated from the stripe mask-paterned foreign substrate, wherein a selective-area doping profile is constructed at the surface, wherein p- GaN, n + -GaN and n'-GaN is grown by selective-area MOVPE and n-GaN is grown by selective-area HVPE.
  • FIG. 8 is a top-view scanning electron microscopic image of a product of GaN substrate which is grown and separated from the stripe mask-paterned foreign substrate, wherein a selective-area doping profile is constructed at the surface, wherein p-GaN and n- GaN display different brightness as p-GaN appears as bright white stripe.
  • FIGS. 9A-9E schematically illustrate the botom-up epitaxial layer transfer process to form the final GaN substrate product.
  • FIG. 9A mask paterning on the parent substrate.
  • FIG. 9B Ist-stage epitaxial lateral overgrowth with intentional doping of GaN stripe array, and the enlarged view reveals the half-core-shell p-n doping profile in each GaN stripe.
  • FIG. 9C 2nd-stage epitaxial lateral overgrowth and botom-up generation of alternative host substrate.
  • FIG. 9D separation of the host substrate from the parent substrate assisted by thermal stress and minor external mechanical force.
  • FIG. 9E the Hipped-over substrate features flat surface regardless of growth morphology on the opposite side, and the integrated active layer has repeating p-n doping pattern (shown in the enlarged view) whose strike-like backbone is copied from the pattern of mask on the parent substrate as depicted in FIG. 9A.
  • FIG. 10A Top-view (+c-plane) OM image of the GaN stripe array (pitch size: 60 pm) on the mask-patterned parent substrate after MOVPE stage, scale bar: 1 mm.
  • FIG. 10B Angled-view SEM image (scale bar: 1 mm) showing the surface (-c plane) and cross-section (m-plane) of the as-separated (AS)-GaN substrate which has fully integrated the active layer featuring repeating doping profiles (periodicity: 60 pm).
  • the inset shows a magnified cross-sectional view SEM image of a repeating unit of the active layer (scale bar: 15 pm).
  • FIG. 10C Top-view (+c-plane) OM image of the GaN stripe array (pitch size: 36 pm) on the mask-patterned parent substrate after MOVPE stage, scale bar: 1 mm.
  • FIG. 10D Cross-sectional view (m-plane) of a single GaN stripe on the mask- patterned parent substrate, scale bar: 20 pm.
  • FIG. 11 A GaN root structure buried inside the space enclosed by the mask layers on the parent substrate, scale bar: 5 pm.
  • FIG. 1 IB Mask layers on the parent substrate after the GaN layer was fully detached, scale bar: 5 pm.
  • FIG. 11C Cross-section view of the ridge-like surface protrusion on the AS-GaN substrate surface which previously was the GaN root in FIG. 11 A, scale bar: 5 pm.
  • FIGS. 12A-12C show a set of photographs showing (FIG. 12A) 2.5mm*4mm*0.45mm, (FIG. 12B)10 mmxl0mm*0.40mm, and (FIG. 12C) 16mm> ⁇ 16mm> ⁇ 0.26mm GaN substrates with integrated active layer that were fully released from the diced mask-patterned sapphire substrates (thickness: 0.42 mm) of equal size.
  • Upper left image the top-view (-c plane) OM image of the AS-face of the active layer- integrated GaN substrate, where the periodic dark lines are the ridge-like surface protrusions and a few cloudy patterns indicate poly crystalline GaN deposited on the opposite side during HVPE stage.
  • Lower left image the corresponding mirror-symmetrical AS-face (+c plane) of the mask-patterned parent substrate, where the periodic dark lines indicate the corresponding openings in the mask layer.
  • the area range of the above two OM images is 1 mm* 1mm.
  • FIGS. 13A-13F Cross-section view (m-plane) of the dopant, carrier, and elemental mappings of a repeating unit in the active layer:
  • FIG. 13 A scanning non-linear dielectric microscopic mapping showing the polarity (n/p) of the charged dopant species in each doping region.
  • FIG. 13B scanning microwave microscopic mapping showing the absolute carrier (n/p) concentration in each doping region.
  • FIG. 13C -
  • FIG. 13F NanoSIMS mapping showing the elemental distribution of Mg, Si and O atoms, respectively.
  • FIGS. 14A-14C illustrate NanoSIMS mapping results of distribution of H and C, and the line scanning results of H, C, O and Si. Cs + primary ion beams were used for the detection of C', O', and Si' secondary ions.
  • FIGS. 14B-14C The line scanning results of H, C, O, and Si along the direction 1 (horizontal - FIG. 14B) and the direction 2 (vertical - FIG. 14C) indicated in the top right NanoSIMS mapping image (30 pmx30 pm) (FIG. 14A), respectively. The scanning length is 30 pm.
  • the detection limit (DL) of H, C, O elements are high due to the microscale sampling length and small atomic mass, so the concentration of H, C, O could not be detected.
  • Si has relatively lower detection limit (2-3 *10 18 cm' 3 ) and the concentration of Si in the MOVPE-grown region is detected whereas that in the HVPE-grown region is below the detection limit.
  • FIGS. 15A-15C The line scanning results of Mg. O' primary ion beams were used for the detection of Mg + secondary ions.
  • the scanning length is 30 pm.
  • Different levels of Mg incorporation in the M-P regions grown along c-plane and a-plane are observed.
  • the concentration of Mg above the detection limit (DL) of 2*10 17 cm' 3 in the H-P regions due to diffusion can be quantitatively revealed.
  • FIGS. 16A Top view (-c plane) scanning electron microscopic image (scale bar: 100 pm) of the AS-GaN substrate. Smooth surface morphology with periodic ridges can be observed and the repeating lateral p-n junctions are revealed due to dopant contrast of secondary electrons. The corresponding cross-sectional schematic is drawn above the SEM image.
  • FIG. 16B Top view (-c plane) fluorescence microscopic image (scale bar: 200 pm) of the as-polished GaN substrate surface on which the ridges were removed. The natural color of the emitted visible fluorescent light from different doping regions can be clearly distinguished. The corresponding cross-sectional schematic is drawn above the FM image.
  • FIG. 17A Cross-sectional schematic illustration of the structure of a normally-off planar-gate vertical MOSFET fabricated on the GaN substrate.
  • FIG. 17B The angled-view SEM image (scale bar: 50 pm) showing the doping regions and the trench used for device isolation and pad support before deposition of oxide, metal and polyimide filling.
  • the M-N, M-P, H-N and H-P doping regions in a repeating unit are marked.
  • FIG. 17C Top-view (-c plane) of the fluorescence microscopic image (scale bar: 36 pm) of the MOSFET fabricated on the GaN substrate, where the relative position of metal source, gate and pad (pitch black) against p-type (blue) and n-type (light and dark green) regions can be distinguished. Gate pad and source pad were deposited on the polyimide-filled trenches, respectively.
  • FIG. 17D The IDS-VDS characteristics of the MOSFET where VG ranged from 0V to 10V.
  • FIG. 17E The IDS-VGS characteristics of the MOSFET where VDS was 0.5 V, plotted in semilogarithmic scale.
  • FIG. 17F The IDS-VGS characteristics and the field-effect mobility
  • FIG. 18 is a cross-sectional schematic illustration of ELOG of an array of GaN islands via MOVPE with in-situ doping operations, wherein the doping sequence is n + /n7p- type successively, and during the process of p-type doping the stripes coalescence with neighboring stripes, forming a continuous film.
  • FIG. 19 is a cross-sectional schematic illustration of the as-separated GaN substrate, wherein a selective-area doping profile constructed in this way at one of its sides consists of GaN solely grown by MOVPE.
  • FIG. 20 is a cross-sectional scanning electron microscopic image of the as- separated GaN substrate showing one of the repeating units and ridge-like structure, corresponding to Fig. 10, wherein the p-GaN layer appears as bright white color due to secondary electron yield-related dopant contrast.
  • FIG. 21 A is a top-view schematic illustration of another example of mask patterns, wherein the white stripe illustrates the window region, and the textured hexagon illustrates mask region.
  • FIG. 21B is a corresponding top-view schematic illustration of a product of GaN substrate which is grown and separated from the hexagonal mask-patterned foreign substrate, wherein a selective-area doping profile is constructed at the surface, wherein p-GaN, n + -GaN and n'-GaN is grown by selective-area MOVPE and n-GaN is grown by selective-area HVPE.
  • FIG. 22 is a cross-sectional schematic illustration of the GaN substrate with flattened surface after removal of the periodic ridge-like structure via chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • FIGS. 23A-23C illustrate the preferred orientations of the masks for the stripe (FIG. 23B) and hexagonal (FIG. 23C) embodiments.
  • a method of epitaxy-enabled substrate transfer that forms an article of manufacture 2 (e.g., a product) includes the use of hybrid of halide vapor phase epitaxy (HVPE) and metalorganic vapor phase epitaxy (MOVPE) with in-situ doping of a single crystalline material on a substrate 12.
  • In-situ doping refers to a process whereby dopant species (e.g., atoms, molecules) are introduced during the growth phase of the semiconductor material.
  • the single crystalline material is preferably a Group III-V semiconductor compound (with respect to the periodic table Groups).
  • An example of one such single crystalline material is gallium nitride (GaN).
  • Additional examples include aluminum nitride (AIN), indium nitride (InN), or alloys or combinations thereof.
  • the single crystalline material may also include other families of semiconductor materials, oxides, or even metals. Examples of additional single crystalline materials include gallium oxide, silicon carbide, silicon, diamond, zinc oxide, and zinc selenide.
  • HVPE is capable of growing thick GaN epi-film which can serve as freestanding substrate after separation (i.e., a transfer substrate), while MOVPE features better growth and doping accuracy to satisfy the need for producing active layers of electronic devices.
  • the hybrid growth starts with a well-known selective-area epitaxy method called epitaxial lateral overgrowth (ELOG).
  • ELOG epitaxial lateral overgrowth
  • a mask 10 is first patterned onto a substrate 12 (also referred to herein as the foreign or mask-patterned substrate) such as sapphire with an array of openings called windows 14, while the areas above the mask are called wings 16.
  • Additional materials for the substrate 12 include silicon, diamond, silicon carbide, gallium oxide, zinc oxide, glass, quartz, zinc selenide, graphene, or combinations thereof.
  • the mask-patterned substrate 12 is a material that has at least one element selected from the group consisting of: nitrogen, arsenic, and phosphorous and at least one element selected from the group consisting of boron, gallium, aluminum, and indium.
  • the mask- patterned substrate 12 is crystalline and has a compatible crystalline symmetry (e.g., lattice symmetry and lattice constant) with a single crystalline material comprising a III-V semiconductor compound or alloy thereof.
  • each window 14 in one embodiment, is preferentially a long narrow stripe (seen in FIG. 2) and explained further below.
  • a good material for the mask 10 should possess excellent selectivity so that GaN cannot nucleate onto it.
  • Silicon nitride (SiN x ) and silicon dioxide (SiCh) are often used for the ELOG of GaN and can be used for the mask 10.
  • Additional mask 10 materials include tungsten, tungsten nitride, zirconium oxide, hafnium oxide, yttrium oxide, graphene or combinations thereof.
  • FIG. 3 shows an example of how in-situ doping is operated along with the ELOG of an array of GaN islands.
  • GaN nucleation within each window 14 forms an initial layer (which is n" in the final article of manufacture 2) on which a n + layer is formed which moves laterally over the mask 10 to form an island.
  • Another n" layer is formed over the n + layer and adds height and lateral progression of the islands.
  • This is followed by a p layer that forms the final layer of the islands or repeating units 20 formed along the surface of the substrate 12.
  • these layers are all grown using MOVPE.
  • the doping sequence may vary depending on the target device structure, the principle is to adjust one or more of the flow rate of dopant source, growth temperature, and growth pressure during the lateral growth of GaN.
  • GaN “islands” characteristic of a core-shell structure in which regions of different dopant-type and/or different levels of doping concentration can be manufactured from the inner core to the outer layers.
  • Typical n- type dopants include silane (SiFL).
  • a typical p-type dopant is CP2Mg. These islands form repeating units 20 having discrete doping profiles on the surface of the substrate 12 with the masks 10. There may be large numbers of these repeating units 20 that are formed using a single substrate 12.
  • repeating units 20 there may be several hundreds or even thousands of such repeating units 20 are used to form laterally-patterned p-n junctions.
  • the lateral width and vertical thickness of each region within the repeating units 20 can be easily controlled by properly adjusting the growth time and lateral/vertical growth rate at every stage.
  • the dopant concentration in the repeating units 20 may vary but is generally within the range of about 10 15 to 10 21 atoms per cubic centimeter. [0053] It should be noted that the growth anisotropy also dictates the shape of the GaN repeating units 20.
  • the cross-sectional shape of GaN island that forms the repeating unit 20 may vary, of which the sidewall facet is either vertical forming a cross-sectional rectangular shape or inclined forming a cross-sectional trapezoidal shape.
  • the growth front should preferably maintain to be substantially vertical (perpendicular to the face of the substrate 12) during the lateral growth so as to produce lateral junctions 22 with uniform width at all depths, like depicted in FIG. 4.
  • semi-polar plane of GaN (inclined sidewall) tends to incorporate much more impurities such as oxygen and less dopant species such as magnesium during growth.
  • a vertical sidewall facet throughout ELOG process is highly preferred over inclined sidewall facet.
  • the orientation of mask window 14 is preferred to be [1100] relative to the substrate 12 to ensure the formation of a substantially vertical sidewall. See e g., FIGS. 23A-23C.
  • HVPE growth then follows.
  • the main purpose of HVPE is to grow thick GaN film 24 so that the separated epi-film can become “free-standing.”
  • HVPE growth of GaN film 24 also serves an important role to complete the coalescence of the GaN repeating units 20 by adding a selective-area epitaxy stage as an initial period, as shown in FIG. 4.
  • HVPE is capable of achieving near-perfect morphology after island coalescence compared to MOVPE, while the latter typically suffers from an inverted-V-shape void at the bottom of coalescence front near the hetero-interface.
  • the p-n junction 22 formed between HVPE-regrown n-GaN and MOVPE-grown p-GaN is sharp. Sharp in this context is meant to indicate an abrupt change in the doping profile between the junction.
  • the article of manufacture 2 includes a transfer substrate 26 that is made from a single crystalline material (e.g., GaN), wherein the repeating units 20 having discrete doping profiles are located on one side of the transfer substrate 26. It should be appreciated, however, that the transfer substrate 26 may also include a poly crystalline material or an amorphous material that contains repeating units 20.
  • the repeating units 20 have discrete doping profiles and, in one embodiment, form sharp p-n junctions 22.
  • the entire grown-in selective-area repeating units 20 with their respective doping structure previously obtained by selective-area growth(s) is preserved, transferred and constructed at one side of the GaN transfer substrate 26.
  • a selective-area doping profile constructed at one side of the GaN substrate features laterally- aligned p-n junctions 22 and n'-n + junctions 22 with uniform width (FIGS. 7 and 8) and significant vertical junction length (e.g., over 10 pm) which are tailored to the special needs of high-performance electronic devices.
  • the as-separated GaN transfer substrate 26 has mirror-like surface on the side wherein said doping profile of the repeating units 20 are constructed.
  • this ridge-like structure or surface protrusion 28 can be useful in photolithography alignment in that it helps to accurately position each repeating unit 20 of doping profile in the optical microscope imaging.
  • this ridge-like structure or surface protrusion 28 can also be easily removed by chemical mechanical polishing (CMP) or other planarization techniques and ultra-flatness of the surface of the GaN transfer substrate 26 thus can be obtained (FIG. 22).
  • FIGS. 9A-9E illustrate a schematic representation of the process used to create the article of manufacture 2 (e.g., a product) includes the use of HVPE and MOVPE with in-situ doping of a single crystalline material on a substrate 12.
  • FIG. 9A illustrates the patterning of the mask 10 onto the mask-patterned substrate 12.
  • FIG. 9B shows the Ist-stage epitaxial lateral overgrowth with intentional doping of GaN stripe array using MOVPE, and the enlarged view reveals the half-core-shell p-n doping profile in each repeating unit 20 in the form of a GaN stripe.
  • FIG. 9C shows the 2nd-stage epitaxial lateral overgrowth and bottom-up generation of the GaN film 24 used to form the transfer substrate 26 (using HVPE).
  • FIG. 9D illustrates the separation of the transfer substrate 26 from the parent substrate 12 assisted by thermal stress and minor external mechanical force.
  • FIG. 9E shows the Hipped-over transfer substrate 26 that features a flat surface regardless of growth morphology on the opposite side, and the integrated active layer has repeating p-n lateral junctions 22 (doping pattern shown in the enlarged view) whose stripe-like backbone is copied from the pattern of mask 10 on the parent substrate 12 as depicted in FIG. 9A.
  • the GaN repeating units 20 e.g., stripe arrays with different pitch size (36 pm and 60 pm) were achieved, as shown in FIG. 10A and 10C, respectively.
  • the inter-gaps to be filled via HVPE growth
  • the 2nd-stage epitaxial lateral overgrowth and the generation of GaN transfer substrate 26 was carried out by HVPE which was capable of achieving void-free island (stripe) coalescence and growing thick epi-film for a freestanding substrate 26.
  • FIGS. 11 A-l 1C offer detailed descriptions of the adjoining part between the GaN active layer and the mask-patterned parent substrate 12.
  • FIGS. 11 A-l 1C offer detailed descriptions of the adjoining part between the GaN active layer and the mask-patterned parent substrate 12.
  • the root-like GaN structure was buried inside the space enclosed by the layers of the mask 10.
  • the bright region indicated the strong chemical- bonded GaN-sapphire (substrate 12) interface.
  • the area ratio of this bonded interface was quite small against the larger GaN-SiN x mask interface containing weak van der Waals bonding or vacuum gap.
  • the GaN transfer substrates 26 of varying dimensions were completely released from the mask-patterned sapphire substrates 12 (thickness: 420 pm) of equal size, as shown in FIGS. 12A, 12B, and 12C, respectively.
  • the largest square size allowed in the 1 inch-diameter growth reactor is 18mmxl8mm. It was found that with the thickness of GaN transfer substrate 26 increased, the degree of transparency decreased due to opaque poly crystalline GaN deposited during HVPE growth. However, the mirror-like surface was invariantly achieved on the integrated active layer side irrespective of large-area poly crystalline GaN and uneven surface on the opposite side.
  • the cross-sectional elemental, dopant and carrier distribution mappings of the repeating unit 20 in the active layer of the final transfer substrate 26 were carried out by NanoSIMS, scanning non-linear dielectric microscopy (SNDM), scanning microwave microscopy (SMM) measurements, respectively.
  • SNDM and SMM are based on scanning probe microscopy techniques like atomic probe microscopy (AFM). Similar to scanning capacitance microscopy (SCM) but featuring higher sensitivity, SNDM collects the localized signals of dC/dv related to charged dopant and carrier concentration, whereas SMM collects the localized scattered micro wave signals of dSn/dVtip related to carrier concentration.
  • the SNDM is capable of recognize p/n polarity and has peak sensitivity in the detection of middle-range carrier concentration ( ⁇ 10 17 cm’ 3 ) which decreases toward both heavy- and light-range directions.
  • the SMM is incapable of recognize p/n polarity but has better quantitative analysis capability since the sensitivity and signal intensity has a good monotonous and linear relation with increasing carrier concentration.
  • the SNDM and SMM employed herein feature the detection range of 10 14 -l O 20 cm’ 3 and 10 14 - 10 21 cm’ 3 , respectively.
  • FIGS. 13A and 13B show the cross-sectional SNDM and SMM mapping results, respectively of the repeating unit 20.
  • the polarity of the doping regions can be concluded from FIG. 13A that each repeating unit 20 of the active layer is characterized by an MOVPE- grown n-type (M-N) core region, surrounded by an MOVPE-grown p-type (M-P) shell region, and an HVPE-grown n-type (H-N) matrix region surrounding the MOVPE-grown square regions and also making up a majority part of GaN transfer substrate 26. Furthermore, a triangular prism-like p-type (H-P) region beneath each discrete MOVPE-grown region was developed during HVPE growth (FIGS.
  • the carrier concentration of each region can be revealed in FIG. 13B. It is seen that both M-N and H-N regions are heavily n- type doped with electron concentration above 10 18 cm' 3 .
  • the M-P region has hole concentration mostly in the range of 5xl0 16 to IxlO 17 cm 3 and the H-P region has a hole concentration mostly around IxlO 16 cm 3 except that in the narrow area adjacent to M-P region the hole concentration experienced a diffusion-induced large gradience from 10 18 cm' 3 to 10 16 cm' 3 within a vertical distance of 5-6 pm.
  • FIGS. 13C-13F show the cross-sectional NanoSIMS mapping results of Si, Mg and O.
  • the quantitative line scanning results of these elements can be found in FIGS. 14A-14C and 15A-15C. It can be confirmed that the dominant n-type dopant species in the M-N and H-N regions are Sica and ON, respectively, since the shape of distributions of Si and O well matches the corresponding M- H and H-N regions in FIGS. 13A and 13B.
  • the p-type dopant species in the M-P and H-P regions is MgGa.
  • the incorporation of Si in the MOVPE-grown region mainly came from the intentional introduction of dopant precursor SiHi. In addition, it was also from the desorption of Si from the SiN x mask 10 during MOVPE growth, and this unintentionally doping source was responsible for the presence of Si in the M-P region. Instead, the incorporation of Si into HVPE-grown region was below the detection limit of NanoSIMS, most probably due to the deposition of poly crystalline GaN which covered the SiNx mask 10 and suppressed the desorption of Si into vapor phase during HVPE growth.
  • the undetectable Si in the HVPE-grown region also accounted for the higher hole concentration in the small part of H-P region adjacent to M-P region than in the M-P region due to the compensating donor effect of Si in p-type GaN.
  • the high electron concentration in the H-N matrix region came from O-an impurity species commonly associated with HVPE (O is a rare impurity for MOVPE).
  • the lightly-doped H-P region further extended the p-n junction 22 length by over 40 pm, showing great promise in the design and application of state-of-the-art power electronics such as superjunction-based transistors should the unintentional [O] in the H-N region were significantly reduced.
  • the top view (-c plane) of the AS-active layer surface with selective-area doping profile was revealed by the SEM image in FIG. 16A.
  • the bright white regions were p-type GaN due to the dopant contrast of secondary electron imaging.
  • the repeating unit 20 can be clearly identified which consists of a pair of regular bright stripes indicating neighboring M-P regions as well as an irregular grey stripe indicating the ridge-like surface protrusion 28.
  • the same sample was subject to a chemical mechanical polish process to remove the ridge-like structures or surface protrusions 28.
  • the top view (-c plane) optical fluorescence microscopic image in FIG. 16B shows the as-polished active layer surface.
  • the microscope was not loaded with any filtering lens when the images were taken in the fluorescence mode so that all the colors in the image faithfully represented the in-situ “true colors” of corresponding visible light emitted from different doping regions in response of the external ultraviolet (UV)-light illumination.
  • the blue luminescence from the GaN:Mg region (identified in FIG. 16B by white lines) was associated with a broad peak centered at 2.94 eV (equivalent of 422 nm) attributed to conduction band electron-Mg acceptor transition in GaN at room temperature.
  • the width and relative position of blue stripe pairs in FIG. 16B exactly match those bright white stripes pairs in FIG. 16A, mutually verifying that these stripe pairs were p-type GaN:Mg regions and confirming that the surface consists of ultra-long repeating laterally-patterned p-n junctions 22.
  • the formed GaN transfer substrate 26 with the integrated active layer containing the repeating units 20 featuring repeating p-n junctions 22 enables or facilitates the fabrication of a series of state-of-the-art electronics and optoelectronics.
  • a normally-off vertical power MOSFET 40 such as that illustrated in FIG. 17A, is an example whose vertical device architecture can also comprehensively evaluate both the active layer and bulk GaN substrate.
  • the cross-sectional schematic of the double-gated n-channel vertical MOSFET 40 is shown in FIG. 17 A. Specifically, the demonstration of p-well due to a simple flip-over process of the as-grown half-core-shell p-n structure allows for a standard planar gate architecture preferred over an otherwise recessed-gate architecture.
  • FIG. 17B shows a top-view fluorescence microscopic image of the fabricated transistors 40 (gate pad, source pad, gate (G), and source (S) are visible).
  • the relative position of the metal contacts (source contact 44, gate contact 46) appearing as pitch black due to complete fluorescence absorption can be distinguished against that of the underlying GaN doping regions in blue- or green-color fluorescence.
  • the metal gate 46 and underlying oxide layer 47 spans over a double-channel consisting of a pair of M-P regions, whereas the source contact pair 44 was deposited on the neighboring M-N regions and adjoined to a large pad on the polyimide-flattened trench.
  • the drain contact 48 was deposited over the entire backside of the n-type GaN transfer substrate 26.
  • the output and transfer characteristic curves of the transistor 40 are shown in FIGS. 17D and 17F, respectively.
  • the extracted field-effect mobility p FE was plotted against VG in FIG. 17E when a small VDS of 0.5V was applied, based on the following equation:
  • the drain current IDS was plotted in both semilogarithmic and linear scales in FIGS. 17E and 17F, respectively.
  • An on/off ratio of over 10 8 and a threshold voltage of 3.8V were achieved, indicating a good normally-off transistor action.
  • the high on/off ratio suggested that leakage paths were effectively suppressed.
  • the low value of threshold voltage was likely explained by a combination of factors including the compensating donors of Si in p-GaN, the plasma treatment to p-GaN surface along SiN x sputtering, and the intrinsic properties of nitrogen-terminated GaN surface.
  • the IDS-VDS curves under a set of VGS in the linear region of the MOSFET were plotted in FIG. 17G with the specific on-resistance RON-VDS curve.
  • the resistance can be further reduced by optimizing the device design, such as shortening the channel length L to commonly- employed sub-micrometer scale to reduce the channel resistance, and narrowing the length of M-N core region (source region) to optimize the effective device area.
  • the good transistor 40 operation confirmed the successful integration of selective-area doped active layer into the native conducting substrate by the bottom-up epitaxial layer transfer process.
  • the method is largely the same as that in the embodiment described above except that the selective-area epitaxy is only performed by MOVPE (and not MOVPE followed by HVPE) while HVPE serves the sole purpose of film thickening.
  • MOVPE selective-area MOVPE
  • the GaN repeating units 20 experience a coalescence (the stripes coalesce with neighboring stripes) into a continuous film during the final stage of in-situ doping, as depicted in FIG. 18.
  • the surface of the as- separated GaN transfer substrate 26 will then solely consist of MOVPE-grown GaN, as shown in FIG. 19.
  • the method is largely the same as that in the first embodiment except that the pattern of the mask 10 is hexagon-like (FIG. 21 A), instead of stripe-like (FIG. 2).
  • the cross-sectional view of the GaN repeating units 20 is the same as that depicted in FIG. 3.
  • the cross- sectional views across each of the six edges of a hexagon, of the sample after selective-area epitaxy via HVPE (selective-area HVPE) and after film separation are the same as those depicted in FIG. 4 and FIG. 5, respectively.
  • the cross-sectional view across each of the six edges of a hexagon, of the as-separated GaN transfer substrate 26 is the same as that depicted in FIG. 6.
  • the top view of the as-separated GaN transfer substrate 26 (FIG. 2 IB) is different than that depicted in FIG. 7, due to the difference between stripe-like mask pattern (FIG. 2) and hexagon-like mask pattern (FIG. 21A).
  • the hexagonal arrangement of selective-area doping profile in this embodiment can further increase the ratio of active device area versus chip area which is highly sought after in the field of applications of electronic devices such as MOSFETs 40.
  • the produced lateral p-n junction 22 has a uniform width at all depths (i.e., vertical separation) as well as significant and adjustable vertical junction length, which in principle are impossible to obtain using ion implantation. Compared to the etch and regrowth method, this approach is free of plasma-induced damages during dry etch. Furthermore, the lateral p-n junction 22 produced by MOVPE-grown p-type GaN and HVPE- regrown n-type GaN has sharp lateral junction interface which means that magnesium does not diffuse out noticeably along lateral direction during the subsequent HVPE regrowth, as evidenced by repeated growth results characterized by scanning electron microscopy and optical fluorescence microscopy.
  • the obtained freestanding GaN transfer substrate 26 is suitable for power electronic devices with vertical architecture, and it is well established that vertical device structure has greater voltage blocking capability as well as current handling capability than its lateral counterpart.
  • the surface of the obtained substrate features has very low density of threading dislocation by virtue of ELOG during which dislocations either thread up or bend and propagate laterally. In principle, very few of laterally- propagating dislocations would bend for a second time and thread down during ELOG when the growth front maintains to be vertical sidewall facet, thereby freeing of dislocation propagating to the bottom surface-the surface of newly-obtained substrate, as evidenced by the surface cathodoluminescence mapping where no dark spot is observed.
  • the typical issue of impurity out-diffusion of impurity atoms such as oxygen from the underlying substrate 12 into epi-film is greatly alleviated due to the non-bonding of GaN with underlying mask 10 in the regions with wings 16.
  • a thin layer of AIN needs to be first deposited onto the substrate 12 before mask patterning in order to prevent meltback etching and AIN deposition on the mask 10.
  • a buffer layer comprising Group-III-nitride material can be deposited first onto the substrate 12 before mask patterning in order to further promote the quality of the Group-III-nitride material grown by subsequent selective area epitaxy, in these circumstances, such special substrate 12 onto which the mask 10 is patterned is usually referred to as Group-III-nitride material template in this field.
  • the produced substrate 12 e.g., GaN
  • the produced substrate 12 is (0001) oriented (nitrogen-polar) which has unparalleled advantages (such as lower contact resistance and higher carrier mobility) in the applications of high electron mobility transistor (HEMT) due to that the polarization-induced two-dimensional electron gas (2DEG) is formed at GaN/AlGaN heterointerface above Al GaN back-barrier layer, instead of below Al GaN topbarrier layer as is the case in gallium-polar GaN.
  • HEMT high electron mobility transistor
  • a mask-patterned 2-inch sapphire substrate 12 was loaded into a MOVPE reactor (VEECO).
  • the mask 10 consists of stacking layers SiNx/SiCh/SiNx which were deposited by LPCVD followed by selective dry etching, finally enclosing a serpentine-like channel.
  • the mask 10 has stripe-like openings 14 along [1100] orientation (m-direction) with three types of pitch size (distance between neighboring openings): 36 um, 60 um, and 100 um.
  • the width of opening 14 in the top SiN x mask 10 is universally 2um. GaN was grown initially inside the channel via geometrically-defined heteroepitaxy.
  • the continuous HVPE growth consisted of two stages: coalescence of islands or repeating units 20 (continued growth of active layer) and film thickening of the GaN film 24 (generation of transfer substrate 26). Each stage featured different V/III ratios and growth temperature ranging from 950°C to 1080°C. After unloading from HVPE reactor, a minor shear stress by a tweezer was applied to separate GaN transfer substrates 26 entirely from the mask-patterned sapphire substrates 12.
  • the AS (as separated)-GaN article of manufacture 2 was subject to a mechanical polishing to flatten the uneven backside and a chemical mechanical polishing process to remove ridge-like structures or surface protrusions 28.
  • the square trenches on the sample surface were created via Ch-based dry etch in an ICP-RIE system (model: SAMCO RIE- 200iP NXT) for isolation where a hard mask consisted of 200 nm Ni was deposited by electron-beam evaporation.
  • the sample was then subject to a hot 25% TMAH solution wet etch for plasma damage recovery where the top hard mask of Ni was maintained for N-face GaN protection.
  • the sample was annealed in an RTA furnace (Yonekura MIR-HP) at 850 °C and 1 hr. for Mg activation.
  • a Ti/Al/Ni/Au (20nm/120nm/20nm/200nm) was then evaporated onto the M-N region on the surface as source contact, followed by RTA annealing (in nitrogen, 5 min at 650 °C) to improve n-type Ohmic contact.
  • a SiN x of ⁇ l-2 nm was deposited via sputtering (ULVAC ACS- 4000) followed by a deposition of amorphous AI2O3 of 50 nm by atomic layer deposition (ALD).
  • Post deposition annealing was carried out by 450 °C for 1 hr. Wet etch by a dilute HF solution was then used to expose openings for source contacts 44.
  • ANi/Au (20nm/100nm) was evaporated onto the oxide as gate metal contacts 46 followed by post-metallization annealing (N2 atmosphere, 1 hr. at 350 °C).
  • N2 atmosphere 1 hr. at 350 °C.
  • polyimide was filled and thermally cured.
  • Ni/Au was evaporated onto the polyimide-flattened trenches for contact pads.
  • Al (thickness ⁇ 180nm) was sputtered (ULVAC ACS-4000) onto the flattened backside of the n-type GaN substrate for drain contact 48.
  • the morphology and dopant contrast were observed by using field-emission scanning electron microscopy (Hitachi SU9000 and Hitachi SU4300) operated at 10 kV.
  • a two-dimensional dopant and carrier mapping were carried out by scanning non-linear dielectric microscopy (SNDM) and scanning microwave microscopy (SMM) for p-n polarity imaging and carrier concentration imaging, respectively.
  • the scanning non-linear dielectric microscope was measured on a common platform (Hitachi High-tech AFM5000 II) along with atomic force microscopy (AFM) measurement (conductive probe, radius curvature: 20-40 nm) and the scanning microwave microscope (SMM) is measured in couple with Keysight Technologies 5600LS (Pt Probe, radius curvature: 10 nm).
  • AFM atomic force microscopy
  • SMM scanning microwave microscope
  • the two- dimensional elemental mapping and one-dimensional line scanning were carried out by CAMECA NanoSIMS 50L.
  • Cs + and O' primary ion beams were used for the detection of C, O, Si (negative secondary ion) and Mg (positive secondary ion), respectively.
  • the fluorescence microscopic imaging was performed on an optical microscope (Nikon LV150A) with mercury lamp illuminator (Nikon intensilight C-HGFI, wavelength 380nm).
  • the electrical measurements of the transistor 40 were performed with a Keysight Agilent B1505A parameter analyzer.

Abstract

Un procédé de transfert de substrat par épitaxie pour former un article de fabrication consiste à exécuter une pluralité d'opérations d'épitaxie à zone sélective d'un matériau monocristallin sur un substrat à dessin de masques, chacune de la pluralité d'opérations d'épitaxie à zone sélective créant des unités de répétition présentant des profils de dopage distincts sur le substrat à dessin de masques. Un substrat de transfert est obtenu par croissance épitaxiale sur les unités de répétition. Le substrat de transfert est ensuite séparé du substrat à dessin de masques, les unités de répétition présentant des profils de dopage distincts sur le substrat à dessin de masques étant transférées au substrat de transfert qui forme l'article de fabrication. Les unités de répétition peuvent former des jonctions p-n serrées ou des homojonctions n--n+ présentant une longueur de jonction considérable et réglable et des largeurs uniformes.
PCT/US2021/059161 2020-11-13 2021-11-12 Transfert de substrat par épitaxie WO2022104074A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202063113388P 2020-11-13 2020-11-13
US63/113,388 2020-11-13

Publications (1)

Publication Number Publication Date
WO2022104074A1 true WO2022104074A1 (fr) 2022-05-19

Family

ID=81602619

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2021/059161 WO2022104074A1 (fr) 2020-11-13 2021-11-12 Transfert de substrat par épitaxie

Country Status (1)

Country Link
WO (1) WO2022104074A1 (fr)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030064535A1 (en) * 2001-09-28 2003-04-03 Kub Francis J. Method of manufacturing a semiconductor device having a thin GaN material directly bonded to an optimized substrate
US20060175613A1 (en) * 2005-02-07 2006-08-10 Ho Lee Method of manufacturing an epitaxial semiconductor substrate and method of manufacturing a semiconductor device
US20070264782A1 (en) * 2004-10-08 2007-11-15 Shenoy Praveen M Method of Making a MOS-Gated Transistor with Reduced Miller Capacitance
US20090194026A1 (en) * 2008-01-31 2009-08-06 Burrows Brian H Processing system for fabricating compound nitride semiconductor devices
US20100001376A1 (en) * 2006-12-26 2010-01-07 Shin-Etsu Handotai Co., Ltd Method for manufacturing nitride semiconductor self-supporting substrate and nitride semiconductor self-supporting substrate
US20100012952A1 (en) * 2004-07-26 2010-01-21 Adam William Saxler Nitride-Based Transistors Having Laterally Grown Active Region and Methods of Fabricating Same
US20120129301A1 (en) * 2010-11-18 2012-05-24 Monolithic 3D Inc. System comprising a semiconductor device and structure
US20170200707A1 (en) * 2009-05-12 2017-07-13 The Board Of Trustees Of The University Of Illinois Printed Assemblies of Ultrathin, Microscale Inorganic Light Emitting Diodes for Deformable and Semitransparent Displays
US20180097081A1 (en) * 2016-09-30 2018-04-05 Hrl Laboratories, Llc Doped Gate Dielectric Materials
US20190088820A1 (en) * 2017-09-15 2019-03-21 Glo Ab Etendue enhancement for light emitting diode subpixels

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030064535A1 (en) * 2001-09-28 2003-04-03 Kub Francis J. Method of manufacturing a semiconductor device having a thin GaN material directly bonded to an optimized substrate
US20100012952A1 (en) * 2004-07-26 2010-01-21 Adam William Saxler Nitride-Based Transistors Having Laterally Grown Active Region and Methods of Fabricating Same
US20070264782A1 (en) * 2004-10-08 2007-11-15 Shenoy Praveen M Method of Making a MOS-Gated Transistor with Reduced Miller Capacitance
US20060175613A1 (en) * 2005-02-07 2006-08-10 Ho Lee Method of manufacturing an epitaxial semiconductor substrate and method of manufacturing a semiconductor device
US20100001376A1 (en) * 2006-12-26 2010-01-07 Shin-Etsu Handotai Co., Ltd Method for manufacturing nitride semiconductor self-supporting substrate and nitride semiconductor self-supporting substrate
US20090194026A1 (en) * 2008-01-31 2009-08-06 Burrows Brian H Processing system for fabricating compound nitride semiconductor devices
US20170200707A1 (en) * 2009-05-12 2017-07-13 The Board Of Trustees Of The University Of Illinois Printed Assemblies of Ultrathin, Microscale Inorganic Light Emitting Diodes for Deformable and Semitransparent Displays
US20120129301A1 (en) * 2010-11-18 2012-05-24 Monolithic 3D Inc. System comprising a semiconductor device and structure
US20180097081A1 (en) * 2016-09-30 2018-04-05 Hrl Laboratories, Llc Doped Gate Dielectric Materials
US20190088820A1 (en) * 2017-09-15 2019-03-21 Glo Ab Etendue enhancement for light emitting diode subpixels

Similar Documents

Publication Publication Date Title
US10418239B2 (en) Epitaxial substrate for semiconductor elements, semiconductor element, and manufacturing method for epitaxial substrates for semiconductor elements
Krost et al. GaN‐based devices on Si
US7365374B2 (en) Gallium nitride material structures including substrates and methods associated with the same
US7339205B2 (en) Gallium nitride materials and methods associated with the same
US6579359B1 (en) Method of crystal growth and resulted structures
US20100065854A1 (en) Growth and manufacture of reduced dislocation density and free-standing aluminum nitride films by hydride vapor phase epitaxy
EP2615628A1 (fr) Procédé de croissance de couche semi-conductrice de nitrure
CN102403201A (zh) 制造氮化物半导体晶体层的方法
KR101615822B1 (ko) 질화물 반도체 소자, 질화물 반도체 웨이퍼, 및 질화물 반도체층의 형성 방법
US10770552B2 (en) Epitaxial substrate for semiconductor elements, semiconductor element, and manufacturing method for epitaxial substrates for semiconductor elements
CA2641016A1 (fr) Substrat semiconducteur semi-isolant a base de nitrure et methode de fabrication, substrat epitaxial semiconducteur a base de niture et transistor a effet de champ
US20230106300A1 (en) GaN VERTICAL-CHANNEL JUNCTION FIELD-EFFECT TRANSISTORS WITH REGROWN p-GaN BY METAL ORGANIC CHEMICAL VAPOR DEPOSITION (MOCVD)
CN112510088A (zh) 沟槽栅增强型GaN基HEMT器件及其制备方法
US20160268134A1 (en) Method for manufacturing semiconductor device
WO2022104074A1 (fr) Transfert de substrat par épitaxie
JP6944569B2 (ja) 半導体素子用エピタキシャル基板および半導体素子
Khan et al. Selective-area growth of GaN and AlGaN nanowires on N-polar GaN templates with 4° miscut by plasma-assisted molecular beam epitaxy
Yu MOCVD growth of novel GaN materials on silicon substrates
CN213459745U (zh) 高电子迁移率晶体管外延结构及高电子迁移率晶体管
Tanaka Heteroepitaxial Thick GaN Layers and Vertical High-Power Devices by Selective Area MOCVD Growth
Sun Growth and characterization of M-plane GaN and (In, Ga) N/GaN multiple quantum wells
Li et al. Correlation of surface morphology and optical properties of GaN by conventional and selective-area MOCVD
WO2024015623A1 (fr) Mosfet à tranchée de gan et procédé de fabrication
CN111101197A (zh) Iii族氮化物半导体及其制造方法
신인수 A study on the low temperature buffer layer for III-nitride electronic device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21892879

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21892879

Country of ref document: EP

Kind code of ref document: A1