WO2022100595A1 - 随机数的产生方法及装置、电子设备和可读存储介质 - Google Patents

随机数的产生方法及装置、电子设备和可读存储介质 Download PDF

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WO2022100595A1
WO2022100595A1 PCT/CN2021/129710 CN2021129710W WO2022100595A1 WO 2022100595 A1 WO2022100595 A1 WO 2022100595A1 CN 2021129710 W CN2021129710 W CN 2021129710W WO 2022100595 A1 WO2022100595 A1 WO 2022100595A1
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random access
access memory
data
write operation
trigger
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PCT/CN2021/129710
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English (en)
French (fr)
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何伟
沈杨书
祝夭龙
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北京灵汐科技有限公司
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Publication of WO2022100595A1 publication Critical patent/WO2022100595A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes

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  • the present application relates to the field of computers, and in particular, to a method and apparatus for generating random numbers, an electronic device, and a readable storage medium.
  • a common method for generating binary random numbers is to continuously output a pulse signal, and when a random number needs to be generated, read the value of the current pulse signal, and use the currently collected value as a random number.
  • this method of generating random numbers needs to continuously output pulse signals within a certain period of time, which leads to problems such as high energy consumption and large resource occupation in the process of generating random numbers.
  • Embodiments of the present application provide a method and device for generating random numbers, an electronic device, and a readable storage medium, so as to solve the problem of generating random numbers by continuously outputting pulse signals in the related art, resulting in high energy consumption and resource consumption in the process of generating random numbers. Occupy big problem.
  • a method for generating random numbers includes: inputting a trigger signal to a random access memory to trigger a write operation to obtain a random number; wherein the write operation has a probability of success; In the case of success, the first data is generated; in the case that the write operation is unsuccessful each time, the second data is generated; the first data and the second data are respectively different data in the binary data.
  • a random number generating device including: a random access memory, configured to receive a trigger signal to trigger a write operation; the write operation has a probability of success; a controller, configured to obtain a random number according to the write operation number, and is used to generate first data every time the write operation is successful, and generate second data every time the write operation is unsuccessful; the first data and the second The data are respectively different data in the binary data.
  • an embodiment of the present application further provides an electronic device, including a processor, a memory, and a program or instruction stored in the memory and executable on the processor, the program or instruction being The processor implements the steps of the method as described in the first aspect when executed.
  • an embodiment of the present application further provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, the method according to the first aspect is implemented. step.
  • a trigger signal can be input to the random access memory to trigger the execution of the write operation, and in the case that the write operation is successful or unsuccessful, the first data and the second data are respectively generated, and the first data and the second data are The data in the binary data, so that the present application can realize the random generation of random numbers according to the first data and the second data, and there is no need to continuously input a trigger signal to the random access memory. Therefore, it solves the problem of generating random numbers by continuously outputting pulse signals in related art The process of generating random numbers consumes a lot of energy and consumes a lot of resources.
  • Fig. 1 is the flow chart of the generation method of the random number of the embodiment of the present application.
  • FIG. 2a is a schematic diagram 1 of a random number generated by a random processor according to an embodiment of the present application
  • 2b is a second schematic diagram of a random number generated by a random processor according to an embodiment of the present application
  • 2c is a schematic diagram 3 of the random number generated by the random processor according to the embodiment of the present application.
  • FIG. 3 is a schematic diagram of the relationship between the input voltage of the trigger signal, the pulse width of the trigger signal and the probability of a successful write operation according to an embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of a random number device according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a readable storage medium according to an embodiment of the present application.
  • first and second are only for the purpose of description, and cannot be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature delimited with “first”, “second” may expressly or implicitly include one or more of that feature. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
  • FIG. 1 is a flowchart of the method for generating random numbers in an embodiment of the present application. As shown in FIG. The steps of the method:
  • step S102 a trigger signal is input to the random access memory to trigger a write operation to obtain a random number.
  • the write operation has a probability of success.
  • step S104 first data is generated when each write operation is successful; and step S106, when each write operation is unsuccessful, second data is generated.
  • the first data and the second data are data in binary data.
  • RAM random access memory
  • step S104 and S106 needs to be performed correspondingly according to whether the write operation is successful; for another example, step S102 may include multiple A random number is finally obtained, and there will be a corresponding step S104 or step S106 for each write operation.
  • a trigger signal can be input to the random access memory to trigger the execution of the write operation, and when the write operation is successful or unsuccessful, the first data and the second data are respectively generated.
  • the first data and the second data are data in binary data, so that the present application can realize random generation of random numbers according to the first data and the second data, and it is not necessary to continuously input a trigger signal to the random access memory. Therefore, it solves the problem in the related art. By continuously outputting pulse signals to generate random numbers, the process of generating random numbers has problems of high energy consumption and large resource occupation.
  • the binary data in this embodiment of the present application refers to a combination of two specific data, for example, it may include 0 and 1, that is, the first data may be 1, and the second data may be 0; One data is 0, and the second data is 1.
  • the above binary data including 0 and 1 is only for illustration, and other binary data combinations are also possible, for example, the binary data is 2 and 1, or 3 and 5, or 4 and 7, and so on.
  • the specific value of the binary data is not limited in this application, and the specific value can be determined according to the actual situation.
  • the random access memory is a non-volatile magnetic random access memory MRAM.
  • a magnetic random access memory can be used as the above random access memory, because the magnetic random access memory can use a pulse signal as a trigger signal to perform a write operation, and the probability of its successful writing is related to the width of the pulse signal.
  • the parameters of the trigger signal have a certain relationship, which is easy to adjust.
  • the method of inputting a trigger signal to the random access memory involved in step S102 in the embodiment of the present application to trigger the execution of the write operation may further include:
  • Step S102-11 setting trigger signal parameters corresponding to the trigger signal.
  • the value of the trigger signal parameter is associated with the success probability of the write operation.
  • step S102-12 a trigger signal is input to the random access memory, and the write operation is triggered based on the trigger signal parameter of the trigger signal.
  • a trigger signal parameter associated with the success probability of the write operation can be set to adjust the success probability of the write operation, that is, to adjust the probability of obtaining the first data from the write operation.
  • the probability and the probability of the second data and then adjust the probability of finally obtaining different random numbers.
  • the trigger signal parameters in the embodiment of the present application include at least one of the following: the pulse width of the trigger signal, the pulse amplitude of the trigger signal , the input voltage of the trigger signal, and the number of times the trigger signal is input in a unit time (ie, the time of each write operation).
  • the pulse width of the trigger signal is 20ns
  • the input voltage is 1.5V
  • the number of times the trigger signal is input per unit time is 10 times.
  • the method in the embodiments of the present application may further include:
  • Step S103 adjusting the value of the trigger signal parameter.
  • the trigger signal parameter in the embodiment of the present application is associated with the success probability of the write operation; for example, the current unit time (that is, the time of each write operation) is 1s, and the number of times the trigger signal is input in the current 1s is 40 times. For more data generated by successful write operations, the number of input trigger signals within 1s can be increased to 60 times, or, in order to reduce the data generated by successful operations, the number of input trigger signals within 1s can be reduced to 20 times. For the pulse width, if the pulse width of the current trigger signal is 20ns, since the value of the pulse width is related to the probability of a successful write operation, if the value of the pulse width is larger, the probability of the success of the write operation is higher.
  • the current pulse width can be adjusted to 30ns, 40ns, etc. On the contrary, if the success probability of the write operation is lower, the current pulse width can be adjusted to 10ns and so on.
  • the success rate of the write operation is 100%, and above or below the pulse width, the success rate of the write operation decreases exponentially.
  • a pulse width of 50 ns with a write success rate of 100% is 60% or less in the case of a pulse width of 40 ns or 60 ns.
  • the value of the trigger signal parameter may be adjusted accordingly according to the actual situation.
  • the processing method is similar, that is, the pulse amplitude of the trigger signal can also be adjusted, and the input voltage of the trigger signal can be adjusted.
  • the corresponding relationship between the pulse duration representation) and the success probability of the write operation is shown in Figure 3.
  • inputting a trigger signal to the random access memory to trigger execution of a write operation, and obtaining a random number includes:
  • Steps 102-21 a trigger signal is input to a random access memory to trigger a write operation, and a random number is determined according to the data generated by the write operation.
  • a write operation may be performed only on the random access memory once, and a random number may be determined according to data generated by the one write operation. For example, if the write operation is successful and the first data is generated, the first data is used as the obtained random number; if the write operation is unsuccessful and the second data is generated, the second data is used as the obtained random number.
  • inputting a trigger signal to the random access memory to trigger execution of a write operation, and obtaining a random number includes:
  • Steps 102-21 Input multiple trigger signals to the random access memory to trigger the execution of multiple write operations, and determine a random number according to multiple data generated by multiple write operations.
  • the data generated by a single write operation is only determined by the success probability of the write operation of the random access memory, but the success probability does not necessarily match the generation probability of the required random number. For example, if the success probability of a single write operation is 70%, and the expected random numbers are both 1 and 0 with a 50% probability, it is difficult to obtain the desired random number through a single write operation.
  • each write operation will obtain data (first data or second data), and then certain operations (such as logical operations) can be performed according to these data to obtain the final required data.
  • the number of random access memories may be one or more.
  • the embodiments of the present application may be implemented by only one random access memory, and may also be implemented by multiple random access memories.
  • the method of inputting a trigger signal to the random access memory in the embodiment of the present application to trigger a write operation to obtain a random number (step S102 ) , which can further include:
  • step S11 multiple trigger signals are input to the random access memory to trigger the execution of multiple write operations.
  • the random access memory has a corresponding success probability of a write operation under each trigger.
  • step S12 a plurality of corresponding data are generated according to the results of the multiple write operations.
  • Step S13 perform the first operation on the data in the plurality of data until a unique random number is obtained.
  • the first operation includes one of the following: an exclusive-OR operation and an exclusive-OR operation.
  • multiple data can be obtained, each data being the first data or the second data, and by performing a logical operation (first operation) on these data, one data can be finally obtained, as the desired random number.
  • the first operation is performed on each pair of pieces of data in the multiple pieces of data until the first operation is performed on all the pieces of data, and the first operation is continued on the results of the first operation. Perform the first operation again on the pairwise results until a unique random number is obtained; when the number of multiple data is an odd number, perform the first operation on the paired data in the multiple data until only one of the multiple data is left untouched. Perform the first operation, and continue to perform the first operation on the pairwise objects in the combination consisting of the result of the first operation and the remaining data until a unique random number is obtained; wherein the result of the first operation is binary data.
  • the success probability of the random access memory having a corresponding write operation under each trigger means: for the same random access memory under different trigger signals, the success probability of each write operation may be the same or different. In practical application scenarios , the success probabilities of write operations corresponding to different trigger signals are basically different.
  • the success probability of each write operation is: 10%, 20%, 40%, 70%, respectively
  • the probability of obtaining 1 is centered by taking the same or the number, that is, the probability that the final random number is 1 tends to be 50 %.
  • the above takes the XOR operation as an example, and the XOR operation is also handled in a similar manner, and the probability that the final random number is 0 also tends to be 50%. Since the random access memory is greatly affected by temperature, the probability of successful writing may not be as expected in the trigger signal when input, or the probability of obtaining 1 may not be evenly distributed (that is, 50%). Through the method in this application, The probability of successful writing under different trigger signals is also different, and finally the probability of obtaining 1 tends to be 50%, thereby greatly reducing the influence of temperature on the random access memory.
  • the specific process for generating random numbers is: after the single random access memory input 8 trigger signals, because the probability of each data is related to the probability of success or failure of the write operation of the random access memory, for example, generating 8 data: 1, 0, 1, 1, 0, 0, 1, 0; among them, the 8 data can be XORed in pairs, for example, the combination of XOR operation is (1 ⁇ 0), (1 ⁇ 1), (0 ⁇ 0), (1 ⁇ 0), the result is: 0, 1, 0, 1, continue to perform XOR operation on the result pairwise, for example: (0 ⁇ 1), ( 0 ⁇ 1), the result is: 0, 0, continue to perform the XOR operation on the result: (0 ⁇ 0), the result is 1, then input 8 trigger signals to a single random memory this time. XOR operation until the unique random number 1 is obtained.
  • 8 data are generated: 1, 0, 1, 1, 0, 0, 1, 0; wherein the 8 data can be paired Perform XOR operation, for example, the combination of XOR operation is (1 ⁇ 0), (1 ⁇ 1), (0 ⁇ 0), (1 ⁇ 0), the result is: 1, 0, 1, 0, right
  • the result is: 1, 1, 1, continue to perform the XOR operation on the result: (1 ⁇ 1), the result is 0, then input 8 trigger signals to a single random access memory this time to perform XOR operation between pairs until a unique random number 0 is obtained.
  • the above 8 trigger signals are only examples, and other numbers of trigger signals, for example, 5, 10, 20, 100, etc., are not limited in this application. According to the actual situation, take the corresponding value.
  • the above-mentioned data for XOR operation or XOR operation may be a combination determined in advance, or may be randomly combined in pairs from the multiple (8 in the above example) data to perform XOR operation, or perform XOR operation. Or operation, that is, in this application, the rules for pairwise combination thereof are not limited.
  • the way of inputting a trigger signal to the random access memory to trigger the execution of a write operation to obtain a random number may further include: :
  • Step S21 respectively inputting one or more trigger signals to the multiple random access memories to trigger the execution of multiple write operations.
  • each of the random access memories has a success probability of a corresponding write operation when triggered by a trigger signal.
  • step S22 a plurality of corresponding data are generated according to the results of the multiple write operations.
  • Step S23 perform the first operation on the data in the plurality of data until a unique random number is obtained.
  • the first operation includes one of the following: an exclusive-OR operation and an exclusive-OR operation.
  • the first operation is performed on each pair of pieces of data in the multiple pieces of data until the first operation is performed on all the pieces of data, and the first operation is continued on the results of the first operation.
  • the first operation is performed again on the pairwise results until a unique random number is obtained;
  • the first operation is performed on the paired data in the multiple data, until only one of the multiple data remains unexecuted the first operation, and continue to perform the first operation on the pairwise objects in the combination consisting of the result of the first operation and the remaining data until a unique random number is obtained; wherein the result of the first operation is binary data.
  • the success probability of its write operation may be the same or different, which may be larger in specific application scenarios.
  • the probabilities are not the same.
  • one random access memory generates multiple data, which is equivalent to multiple identical random access memories generating multiple data, which is equivalent to the special case of the steps S21 to S23, that is, the multiple random access memories generate random numbers.
  • the result of being 1 is similar to the above steps S11 to S13, that is, the probability of obtaining 1 tends to be 50%, and the influence of temperature on the random access memory is greatly reduced.
  • the number of random access memories is 5, and the first operation is an XOR operation as an example, as shown in FIG. 2a, each random access memory inputs a trigger signal, through the After the random access memory generates data, the XOR operation is performed on pairs of data, and the obtained results continue to be XORed in pairs until a unique random number is obtained.
  • each random access memory inputs a trigger signal, and after data is generated by the random access memory, the pairwise data are XORed.
  • the obtained results continue to be XORed in pairs until a unique random number is obtained.
  • FIG. 2a and FIG. 2b are examples for illustration, and in the embodiment of the present application, the number of random access memories may be 8, 15, 50, etc., which may be set according to actual conditions.
  • the data for performing the XOR operation or the XOR operation two by two may be set according to a preset rule.
  • the multiple random access memories are divided into N stages, where the number of random access memories of the i-th stage is 2 i-1 , N is an integer greater than or equal to 2, and i is less than or A positive integer equal to N; except for the first order, the random access memory of each other order is divided into multiple combinations, and each combination includes a first random memory and a second random memory; except for the Nth order, each other Each random access memory in the order corresponds to a combination of the last 1 order.
  • a trigger signal is input to the random access memory to trigger a write operation to obtain a random number (step S102), including:
  • triggering step when the current write operation is successful, send a trigger signal to the first random access memory in the combination corresponding to the random access memory performing the current write operation; when the current write operation is unsuccessful, send a trigger signal to the random access memory corresponding to the current write operation The combination of the second random access memory sends the trigger signal.
  • the multiple random access memories are divided into multiple levels (or multi-layers), wherein the i-th level has 2 i-1 random access memories, and the 2 i-1 random access memories are divided into 2 i-2 There are 2 combinations (except the 1st level, because the 1st level has only one random access memory), each combination is 2 random access memories, and each random access memory (except the Nth level random access memory) corresponds to a combination in the next 1st level.
  • a trigger signal will be sent to different random access memories in its corresponding combination (that is, the combination in the next level), triggering the next level random access memory.
  • the write operation of the memory, and the write operation of the next-level random access memory will trigger the write operation of the next-level random access memory again.
  • the trigger signal is first input to a random access memory of the first stage to trigger the write operation
  • the write operation of one random access memory in each subsequent stage will be triggered in turn, until the write operation is finally triggered in a random access memory of the nth stage. operation, so that the random number can be determined according to the data of the write operation of the random access memory. For example, different random numbers can be obtained according to the data generated when a write operation is triggered in different random access memories of the Nth order.
  • the write operation of different random access memories random access memories of different levels, or random access memories of different groups, or different first random access memories, or different second random access memories, or the first random access memory and the second random access memory
  • the success probability can be different, and the write operation success probability corresponding to different trigger signals can also be different, so that through the conduction of multi-order random access memory, many complex combinations can be realized to obtain random numbers with the required probability.
  • the first stage has 1 random access memory
  • the second stage has 2 random access memories (divided into 1 combination)
  • the third stage has 4 random access memories Memory (divided into 2 combinations)
  • the fourth stage has 8 random access memories (divided into 4 combinations)
  • the trigger signal is input from the first stage, the first stage trigger signal write operation is successful
  • the trigger signal is input to the first random access memory of the unique combination of the second order, and the write operation of the first random access memory of the second order fails.
  • the first combination of the third order (combination according to the figure).
  • the trigger signal is input to the second random access memory in the top-to-bottom direction, and the second random access memory in the first combination of the third stage is also a write operation failure.
  • a trigger signal is input to the second random access memory in the second combination, and the write operation of the second random access memory in the fourth-order second combination is successful, and the final random number (eg, 1) is output after the write operation is successful.
  • the trigger signal may also be directly input from a first random access memory or a second random access memory of the second or third order, and the execution process is similar to the process in the above Figure 2c, Until a certain first random access memory or second random access memory of the fourth stage outputs the final random number.
  • the 4th-order random access memory in the above-mentioned FIG. 2c is only an example, and other methods in the embodiments of the present application may also be other levels of random access memory, such as 5th-order, 8th-order, etc., which can be implemented according to the actual situation. corresponding settings.
  • the success or failure of the write operation of the random access memory in FIG. 2c is determined according to the actual situation.
  • a complex multi-random generator is formed to improve the unpredictability of whether the write operation is successful or not.
  • FIG. 4 is a schematic structural diagram of the apparatus for generating random numbers according to an embodiment of the present application. As shown in FIG. 4 , the apparatus includes:
  • the random access memory 42 is used to receive a trigger signal to trigger a write operation.
  • the write operation has a probability of success.
  • the controller 44 is configured to obtain a random number according to the write operation, and is configured to generate first data when each write operation is successful, and generate second data when each write operation is unsuccessful.
  • the first data and the second data are respectively different data in the binary data.
  • a trigger signal can be input to the random access memory to trigger the execution of a write operation, and when the write operation is successful or unsuccessful, first data and second data are respectively generated, the first data and the The second data is data in binary data, so that the present application can realize random generation of random numbers according to the first data and the second data, and it is not necessary to continuously input a trigger signal to the random access memory.
  • the signal is used to generate random numbers, which leads to the problem of high energy consumption and large resource occupation in the process of generating random numbers.
  • the random access memory is a non-volatile magnetic random access memory MRAM.
  • the random access memory 42 in this embodiment of the present application may further include: a setting unit for setting trigger signal parameters corresponding to the trigger signal, wherein the value of the trigger signal parameter is associated with the success probability of the write operation; the input unit , which is used to input a trigger signal to the random access memory, and trigger the write operation based on the trigger signal parameter of the trigger signal.
  • the trigger signal in this embodiment of the present application is a pulse signal.
  • the trigger signal parameters in the embodiments of the present application include at least one of the following: the pulse width of the trigger signal, the pulse amplitude of the trigger signal, the input voltage of the trigger signal, and the number of times the trigger signal is input per unit time.
  • controller 44 in this embodiment of the present application is further configured to perform the following steps:
  • a trigger signal is input to a random access memory to trigger a write operation, and a random number is determined according to the data generated by the write operation.
  • controller 44 in this embodiment of the present application is further configured to perform the following steps:
  • S1 input multiple trigger signals to the random access memory to trigger the execution of multiple write operations, and determine a random number according to multiple data generated by multiple write operations.
  • the apparatus of the embodiment of the present application may further include: an adjustment module, configured to adjust the value of the trigger signal parameter after triggering the execution of the write operation.
  • controller 44 in this embodiment of the present application is further configured to perform the following steps:
  • the random access memory has a corresponding success probability of a write operation under each trigger.
  • the first operation includes one of the following: an exclusive-OR operation and an exclusive-OR operation.
  • controller 44 in this embodiment of the present application is further configured to perform the following steps:
  • S1 respectively input one or more trigger signals to the multiple random access memories to trigger the execution of multiple write operations.
  • each of the random access memories has a success probability of a corresponding write operation when triggered by a trigger signal.
  • the multiple random access memories are divided into N stages, wherein the number of random access memories of the i-th stage is 2 i-1 , N is an integer greater than or equal to 2, and i is A positive integer less than or equal to N; except for the first order, the random access memory of each other order is divided into multiple combinations, and each combination includes a first random memory and a second random memory; except for the Nth order, Each random access memory in each of the other stages corresponds to a combination of the next stage.
  • the controller 44 in the embodiment of the present application is further configured to perform the following steps:
  • triggering step when the current write operation is successful, send a trigger signal to the first random access memory in the combination corresponding to the random access memory performing the current write operation; when the current write operation is unsuccessful, send a trigger signal to the random access memory corresponding to the current write operation The combination of the second random access memory sends the trigger signal.
  • an embodiment of the present application further provides an electronic device, including a processor, a memory, a program or instruction stored in the memory and executable on the processor, the program or instruction being executed by the processor During execution, each process of the above-mentioned embodiment of the method for generating an adversarial sample is implemented, and the same technical effect can be achieved. In order to avoid repetition, details are not repeated here.
  • the electronic devices in the embodiments of the present application include the aforementioned mobile electronic devices and non-mobile electronic devices.
  • an embodiment of the present application further provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, the above-mentioned method for generating an adversarial sample is implemented
  • a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, the above-mentioned method for generating an adversarial sample is implemented
  • the processor is the processor in the electronic device described in the foregoing embodiments.
  • the readable storage medium includes a computer-readable storage medium, such as a computer read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.
  • modules or steps of the present application can be implemented by a general-purpose computing device, and they can be centralized on a single computing device or distributed in a network composed of multiple computing devices Alternatively, they may be implemented in program code executable by a computing device, such that they may be stored in a storage device and executed by the computing device, and in some cases, in a different order than here
  • the steps shown or described are performed either by fabricating them separately into individual integrated circuit modules, or by fabricating multiple modules or steps of them into a single integrated circuit module.
  • the present application is not limited to any particular combination of hardware and software.

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Abstract

本申请提供一种随机数的产生方法及装置、电子设备和可读存储介质，其中，该方法包括：向随机存储器输入触发信号以触发执行写操作，得到随机数；其中，所述写操作具有成功概率；在每次所述写操作成功的情况下，产生第一数据；在每次所述写操作未成功的情况下，产生第二数据；所述第一数据和所述第二数据分别为二值数据中的不同数据。通过本申请，解决了相关技术中通过持续输出脉冲信号以产生随机数，导致产生随机数的过程能耗大以及资源占用大的问题。

Description

随机数的产生方法及装置、电子设备和可读存储介质 技术领域
本申请涉及计算机领域，具体涉及一种随机数的产生方法及装置、电子设备和可读存储介质。
背景技术
目前，产生二值随机数的常用方式是：持续输出脉冲信号，并在需要产生随机数时，读取当前脉冲信号的数值，将当前采集到的数值作为随机数。但是这种产生随机数的方式需要在一定时间内持续输出脉冲信号，导致其产生随机数的过程能耗大、资源占用大等问题。
发明内容
本申请实施例提供了一种随机数的产生方法及装置、电子设备和可读存储介质，以解决相关技术中通过持续输出脉冲信号以产生随机数，导致产生随机数的过程能耗大以及资源占用大的问题。
为了解决上述技术问题，本申请是这样实现的：
第一方面，提供了一种随机数的产生方法，其包括：向随机存储器输入触发信号以触发执行写操作，得到随机数；其中，所述写操作具有成功概率；在每次所述写操作成功的情况下，产生第一数据；在每次所述写操作未成功的情况下，产生第二数据；所述第一数据和所述第二数据分别为二值数据中的不同数据。
第二方面，提供了一种随机数的产生装置，包括：随机存储器，用于接收触发信号以触发执行写操作；所述写操作具有成功概率；控制器，用于根据所述写操作得到随机数，且用于在每次所述写操作成功的情况下，产生第一数据，在每次所述写操作未成功的情况下，产生第二数据；所述第一数据和所述第二数据分别为二值数据中的不同数据。
第三方面，本申请实施例还提供了一种电子设备，包括处理器，存储器及存储在所述存储器上并可在所述处理器上运行的程序或指令， 所述程序或指令被所述处理器执行时实现如第一方面所述的方法的步骤。
第四方面，本申请实施例还提供了一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如第一方面所述的方法的步骤。
在本申请中，可以通过向随机存储器输入触发信号以触发执行写操作，并在写操作成功或未成功的情况下，分别产生第一数据和第二数据，该第一数据和第二数据为二值数据中的数据，从而本申请可根据第一数据和第二数据实现随机产生随机数，且无需持续向随机存储器输入触发信号，因此，解决了相关技术中通过持续输出脉冲信号以产生随机数，导致产生随机数的过程能耗大以及资源占用大的问题。
附图说明
图1是本申请实施例的随机数的产生方法的流程图；
图2a是本申请实施例的随机处理器产生随机数的示意图一；
图2b是本申请实施例的随机处理器产生随机数的示意图二；
图2c是本申请实施例的随机处理器产生随机数的示意图三；
图3是本申请实施例的触发信号的输入电压、触发信号的脉冲宽度与写操作成功概率之间的关系示意图；
图4是本申请实施例的随机数的装置的结构示意图；
图5是本申请实施例的电子设备的结构示意图；
图6是本申请实施例的可读存储介质的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
在本申请的描述中，需要理解的是，术语“第一”、“第二”仅由于描述目的，且不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。因此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者多个该特征。本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的随机数的产生方法进行详细地说明。
第一方面，本申请实施例提供了一种随机数(尤其是二值随机数)的产生方法，图1是本申请实施例的随机数的产生方法的流程图，如图1所示，该方法的步骤：
步骤S102，向随机存储器输入触发信号以触发执行写操作，得到随机数。
其中，写操作具有成功概率。
步骤S104，在每次写操作成功的情况下，产生第一数据；步骤S106，在每次写操作未成功的情况下，产生第二数据。
其中，第一数据和第二数据为二值数据中的数据。
在向随机存储器(RAM)进行写操作时，不是一定成功，而是有一定的成功概率，而在写操作之前，该写操作是否成功是无法预知的，或者说其结果是“随机”的。因此，若在写操作成功或未成功时分别产生第一数据和第二数据，就相当于随机得到了不同的数据，故根据该数据可实现随机数(尤其是二值随机数)的产生。
其中，以上步骤的编号和描述顺序并不代表其必然的执行顺序，例如，对每次写操作，根据其是否成功需相应进行步骤S104和步骤S106之一；再如，步骤S102中可包括多次写操作，并最终得到随机数，而对每次写操作都会有相应的步骤S104或步骤S106。
通过本申请实施例中的步骤S102至步骤S106，可以通过向随机存储器输入触发信号以触发执行写操作，并在写操作成功或未成功的情况下，分别产生第一数据和第二数据，该第一数据和第二数据为二 值数据中的数据，从而本申请可根据第一数据和第二数据实现随机产生随机数，且无需持续向随机存储器输入触发信号，因此，解决了相关技术中通过持续输出脉冲信号以产生随机数，导致产生随机数的过程能耗大以及资源占用大的问题。
需要说明的是，本申请实施例中的二值数据是指特定的两种数据的组合，如其可包括0和1，即第一数据可以是1，第二数据可以为0；也可以是第一数据为0，第二数据为1。当然，上述二值数据包括0和1仅仅是举例说明，其它的二值数据组合也是可以的，例如二值数据为2和1，或3和5，或4和7等等。在本申请中并不限定二值数据的具体取值情况，具体取值可以根据实际情况进行确定。
在本申请实施例的可选实施方式中，随机存储器为非挥发性的磁性随机存储器MRAM。
作为本申请实施例的一种方式，可采用磁性随机存储器MRAM作为以上随机存储器，这是因为磁性随机存储器可以脉冲信号为触发信号进行写入操作，且其写入成功的概率与脉冲信号的宽度等触发信号参数有一定的关系，便于调节。
在本申请实施例的可选实施方式中，对于本申请实施例中步骤S102涉及到的向随机存储器输入触发信号以触发执行写操作的方式，进一步可以包括：
步骤S102-11，设置与触发信号对应的触发信号参数。
其中，触发信号参数的取值与写操作的成功概率关联。
步骤S102-12，向随机存储器输入触发信号，基于触发信号的触发信号参数触发执行写操作。
通过上述步骤S102-11和步骤S102-12，对每次写操作，可以设置与写操作的成功概率关联的触发信号参数，以调整写操作成功的概率，也就是调整写操作得到第一数据的概率和第二数据的概率，进而调整最终得到不同随机数的概率。
在本申请实施例中以触发信号为脉冲信号(例如针对以上磁性随 机存储器)为例，则本申请实施例中的触发信号参数包括以下至少一项：触发信号的脉冲宽度、触发信号的脉冲振幅、触发信号的输入电压、单位时间(即每次写操作的时间)内输入触发信号的次数。例如，触发信号的脉冲宽度为20ns，输入电压为1.5V，单位时间内输入触发信号的次数为10次等。上述取值仅仅是举例取值，在不同的应用场景中可以根据实际情况进行相应的取值。
基于上述本申请实施例中为了能够调整写操作的成功概率，在触发执行写操作之后，本申请实施例中的方法还可以包括：
步骤S103，对触发信号参数的取值进行调整。
本申请实施例中的触发信号参数与写操作的成功概率相关联；例如，当前单位时间(即每次写操作的时间)为1s，当前1s内输入触发信号的次数为40次，为了能够得到更多写操作成功所产生的数据，可以将1s内输入触发信号的次数提高到60次，或者，为了减少操作成功所产生的数据，可以将1s内输入触发信号的次数降低到20次。对于脉冲宽度，如果当前触发信号的脉冲宽度为20ns，由于脉冲宽度的取值是与写操作成功的概率是关联的，如果是脉冲宽度的取值越大，其写操作的成功概率越高，则为了写操作的成功概率更高，则可以调整当前脉冲宽度为30ns，40ns等等，反之，如果为了写操作的成功概率更低，则可以调整当前脉冲宽度为10ns等等。当然，在其它应用场景中，可以是在一指定脉冲宽度下，其写操作成功率为100％，高于或低于该脉冲宽度，其写操作成功率呈指数倍下降。例如，写操作成功率为100％的脉冲宽度为50ns，则在脉冲宽度或40ns或60ns的情况下，其成功率为60％或者更低。当然，上述仅仅是举例说明，在具体应用场景中，可以根据实际情况对触发信号参数的取值进行相应的调整。
对于触发信号参数中的其它参数，也是类似的处理方式，即也可以调整触发信号的脉冲振幅、调整触发信号的输入电压，其中，对于触发信号的输入电压、触发信号的脉冲宽度(图中用脉冲持续时间表示)、写操作成功概率(图中用切换概率表示)的对应关系，如图3所示。
在本申请实施例的一个可选实施方式中，向随机存储器输入触发信号以触发执行写操作，得到随机数(步骤S102)包括：
步骤102-21，向一个随机存储器输入一个触发信号以触发执行一次写操作，根据该次写操作产生的数据确定随机数。
作为本申请实施例的一种方式，可仅对随机存储器进行一次写操作，并根据该一次写操作产生的数据确定随机数。例如，若该写操作成功而产生第一数据，就以第一数据为所得的随机数；若该写操作未成功而产生第二数据，就以第二数据为所得随机数。
在本申请实施例的另一个可选实施方式中，向随机存储器输入触发信号以触发执行写操作，得到随机数(步骤S102)包括：
步骤102-21，向随机存储器输入多个触发信号以触发执行多次写操作，根据多次写操作产生的多个数据确定随机数。
单次写操作产生的数据仅由随机存储器的写操作成功概率决定，但该成功概率不一定与所需随机数的产生概率匹配。例如，若单次写操作的成功概率为70％，而期望的随机数是1和0的概率均为50％，则很难通过单次写操作得到所需的随机数。
为此，可进行多次写操作，其中每次写操作都会得到数据(第一数据或第二数据)，进而可根据这些数据再进行一定的运算(如逻辑运算)，以得到最终所需的随机数。例如，若单次写操作的成功概率为70％，而期望的随机数是1和0的概率均为50％，则可进行两次写操作，并在两次写操作都成功(得到两个第一数据)时产生1作为随机数，其它均产生0作为随机数，则其得到1的概率为70％*70％＝49％，很接近50％。
在本申请实施例的可选实施方式中，随机存储器的数量可以为一个或多个。
本申请实施例可仅通过一个随机存储器实现，也可通过多个随机存储器实现。
在本申请实施例的可选实施方式中，在随机存储器的数量为一个 的情况下，对于本申请实施例中的向随机存储器输入触发信号以触发执行写操作得到随机数(步骤S102)的方式，进一步可以包括：
步骤S11，向随机存储器输入多个触发信号以触发执行多次写操作。
其中，随机存储器在每一次触发下具有对应的写操作的成功概率。
步骤S12，根据多次写操作的结果产生对应的多个数据。
步骤S13，对多个数据中的数据执行第一操作，直到获得唯一的随机数。
其中，第一操作包括以下之一：异或操作、同或操作。
通过向一个随机存储器多次进行写操作，可得到多个数据，每个数据为第一数据或第二数据，而通过对这些数据进行逻辑运算(第一操作)，可最终得出一个数据，作为所需的随机数。
需要说明的是，在多个数据的数量为偶数时，对多个数据中的两两数据执行第一操作，直到多个数据均被执行第一操作，并继续对第一操作的结果中的两两结果再次执行第一操作直到获得唯一的随机数；在多个数据的数量为奇数时，对多个数据中的两两数据执行第一操作，直到多个数据中只剩一个数据未被执行第一操作，并继续对由第一操作的结果和剩下的数据组成的组合中的两两对象执行第一操作直到获得唯一的随机数；其中，第一操作的结果为二值数据。
此外，随机存储器在每一次触发下具有对应的写操作的成功概率是指：对于同一个随机存储器在不同的触发信号下，每一次的写操作的成功概率可能相同或者不同，在实际应用场景中，不同的触发信号对应的写操作的成功概率基本上是不相同的。
通过上述步骤S11至步骤S13，如果以同或操作，且输入的多个触发信号的数量为8为例，每一次写操作的成功概率分别为10％、20％、30％、40％、50％、60％、70％、70％；其两两组合进行同或操作得到结果为1的概率分别为：(10％*20％+90％*80％)＝74％，(30％*40％+70％*60％)＝54％，(50％*60％+50％*40％)＝50％， (70％*70％+30％*30％)＝58％，对于上述结果两两之间再进行同或操作为：(74％*54％+26％*46％)＝51.9％，(50％*58％+50％*42％)＝50％，再对上述结果进行同或操作：(51.9％*50％+48.1％*50％)＝50％。也就是说，对于最终得到随机数为1的概率50％，而如果是直接对每一次的成功概率求平均数，则为(10％+20％+30％+40％+50％+60％+70％+70％)/8＝43.75％。
在本申请实施例的另一个可选实施方式中，如果以输入的多个触发信号的数量为4为例：每一次写操作的成功概率分别为：10％、20％、40％、70％时，两两做同或最后得到1(写成功)的概率为：第一组为1的概率(10％*20％)+(90％*80％)＝74％，第二组为1的概率(40％*70％+60％*30％)＝46％，两组的结果在同或，74％*46％+28％*54％＝48.08％，而如果是直接对每一次的成功概率求平均数，则为(10％+20％+30％+40％+70％)＝35％。可见，通过本申请实施例的上述方式，相对于这组概率的平均概率而言，通过同或取数的方式，将获得1的概率居中，即，使得最终随机数为1的概率倾向于50％。
需要说明的是，上述是以同或操作为例，对于异或操作也是类似的处理方式，而且对于最终随机数为0的概率也是倾向于50％。由于随机存储器受温度影响大，导致写成功的概率未必如输入时如触发信号中预期的那样，或者，获得为1的概率也未必均衡分布(即为50％)，通过本申请中的方式，在不同的触发信号下写成功的几率也是不同的，最终使得获得1的概率趋向于50％，从而大大降低了由温度给随机存储器带来的影响。
在具体应用场景中，对于具体产生随机数的过程为：上述该单个随机存储器输入8个触发信号后，由于每一个数据的概率是与随机存储器的写操作成功或失败的概率相关的，例如产生了8个数据：1，0，1，1，0，0，1，0；其中，对该8个数据可以两两进行同或操作，例如进行异或操作的组合为(1⊙0)，(1⊙1)，(0⊙0)，(1⊙0)，其结果为：0，1，0，1，对该结果两两继续进行异或操作，例如：(0⊙1)，(0⊙1)，其结果为：0，0，对该结果继续进行异或操作：(0 ⊙0)，其结果为1，则本次向单个随机存储器输入8个触发信号两两之间执行同或操作，直到获得唯一的随机数1。
同样地，对于异或操作，如果该单个随机存储器输入8个触发信号后，产生了8个数据：1，0，1，1，0，0，1，0；其中该8个数据可以两两进行异或操作，例如进行异或操作的组合为(1⊕0)，(1⊕1)，(0⊕0)，(1⊕0)，其结果为：1，0，1，0，对该结果两两继续进行异或操作，例如：(1⊕0)，(1⊕0)，其结果为：1，1，对该结果继续进行异或操作：(1⊕1)，其结果为0，则本次向单个随机存储器输入8个触发信号两两之间执行异或操作，直到获得唯一的随机数0。
需要说明的是，上述8个触发信号仅仅是举例说明，也可以其它数量的触发信号，例如，5，10，20，100等等，在本申请并不限定其具体取值或范围，可以根据实际情况进行相应的取值。而且上述进行异或操作或同或操作的数据可以是事先确定好的组合，也可以是从该多个(上述举例中则是8个)数据中两两随机组合进行同或操作，或进行异或操作，即在本申请中也对此并不限定其两两组合的规则。
在本申请实施例的另一个可选实施方式中，在随机存储器的数量为多个的情况下，向随机存储器输入触发信号以触发执行写操作得到随机数(步骤S102)的方式，进一步可以包括：
步骤S21，向多个随机存储器分别输入一个或多个触发信号以触发执行多次写操作。
其中，在触发信号的触发下每一个所述随机存储器具有对应写操作的成功概率。
步骤S22，根据多次写操作的结果产生对应的多个数据。
步骤S23，对多个数据中的数据执行第一操作，直到获得唯一的随机数。
其中，第一操作包括以下之一：异或操作、同或操作。
作为本申请实施例的另一种方式，也可以是向多个随机存储器多 次进行写操作，得到多个数据，并对这些数据进行逻辑运算(第一操作)，最终得出一个数据，作为所需的随机数。
需要说明的是，在多个数据的数量为偶数时，对多个数据中的两两数据执行第一操作，直到多个数据均被执行第一操作，并继续对第一操作的结果中的两两结果再次执行第一操作直到获得唯一的随机数；在多个的数量为奇数时，对多个数据中的两两数据执行第一操作，直到多个数据中只剩一个数据未被执行第一操作，并继续对由第一操作的结果和剩下的数据组成的组合中的两两对象执行第一操作直到获得唯一的随机数；其中，第一操作的结果为二值数据。
虽然在步骤S21至步骤S23涉及到的是多个随机存储器，但是对于每一个随机存储器在每一次触发信号的触发下，其写操作的成功概率可以是相同或不同的，在具体应用场景中大概率是不相同的。上述步骤S11至步骤S13中一个随机存储器产生多个数据，相当于是多个相同的随机存储器产生多个数据，相当于该步骤S21至步骤S23的特殊情况，即该多个的随机存储器产生随机数为1的结果与上述步骤S11至步骤S13是类似的，即最终使得获得1的概率也是趋向于50％，也大大降低了由温度给随机存储器带来的影响。
对于上述步骤S21至步骤S23，在具体应用场景中以随机存储器的数量为5个，且第一操作为异或操作为例，如图2a所示，每个随机存储器输入一个触发信号，通过该随机存储器产生数据之后，两两数据进行异或操作，得到的结果两两继续进行异或操作，直到得到唯一的随机数。或者，以随机存储器的数量为5个，且第一操作为同或操作为例，如图2b所示，每个随机存储器输入一个触发信号，通过该随机存储器产生数据之后，两两数据进行异或操作，得到的结果两两继续进行异或操作，直到得到唯一的随机数。
需要说明的是，上述图2a和图2b进行是举例说明，在本申请实施例中随机存储器的数量可以是8、15、50等，可以根据实际情况进行相应的设置。另外，两两进行异或操作，或进行同或操作的数据可以是按照预设规则设置的。
在本申请实施例的另一个可选实施方式中，多个随机存储器分成N阶，其中第i阶的随机存储器数量为2 i-1个，N为大于或等于2的整数，i为小于或等于N的正整数；除第1阶外，其它每阶的随机存储器分为多个组合，每个组合包括1个第一随机存储器和1个第二随机存储器；除第N阶外，其它每阶中的每个随机存储器对应后1阶的一个组合。
向随机存储器输入触发信号以触发执行写操作，得到随机数(步骤S102)，包括：
S31，向第1阶的随机存储器输入触发信号以触发执行写操作。
S32，触发步骤：在当前写操作成功时，向执行当前写操作的随机存储器对应的组合中的第一随机存储器发送触发信号；在当前写操作未成功时，向执行当前写操作的随机存储器对应的组合中的第二随机存储器发送触发信号。
S33，在当前随机存储器位于除第N阶外的其它阶时，返回触发步骤；在当前随机存储器位于第N阶时，根据当前写操作产生的数据确定随机数。
本申请实施例中，将多个随机存储器分为多阶(或者说多层)，其中第i阶有2 i-1个随机存储器，且这2 i-1个随机存储器分为2 i-2个组合(除第1阶，因第1阶只有1个随机存储器)，每组合为2个随机存储器，且每个随机存储器(除第N阶的随机存储器)对应后1阶中的一个组合。而且，对每个随机存储器，当其进行写操作时，根据写操作是否成功，会向其对应的组合(即下一阶中的组合)中的不同随机存储器发出触发信号，触发下一阶随机存储器的写操作，而下一阶随机存储器的写操作又会再次触发更下一阶随机存储器的写操作。
由此，只要先将触发信号输入第1阶的1个随机存储器触发写操作，则会依次触发其后每阶中一个随机存储器的写操作，直到最终在第N阶的某个随机存储器触发写操作，从而可根据该随机存储器的写操作的数据确定随机数。例如，可在第N阶不同的随机存储器被触发写操作时，根据其产生的数据得到不同的随机数。
其中，不同的随机存储器(不同阶的随机存储器，或不同组的随机存储器，或不同的第一随机存储器，或不同的第二随机存储器，或第一随机存储器与第二随机存储器)的写操作成功概率可以是不同的，而不同的触发信号对应的写操作成功概率也可以是不同的，从而通过多阶随机存储器的传导，可实现许多复杂的组合，从而得到所需概率的随机数。
对于上述步骤S31至S33，以N的取值为4为例，则第1阶有1个随机存储器，第2阶有2个随机存储器(分为1个组合)，第3阶有4个随机存储器(分为2个组合)，第4阶有8个随机存储器(分为4个组合)，如图2c所示，如果是从第1阶输入触发信号，该第1阶触发信号写操作成功后向第2阶的唯一组合的第一随机存储器输入触发信号，此时该第2阶的第一随机存储器写操作失败，写操作失败后，向第3阶的第一组合(组合按照图中从上到下的方向排号)中的第二随机存储器输入触发信号，此时该第3阶的第一组合中的第二随机存储器也是写操作失败，写操作失败后向第4阶的第二组合中的第二随机存储器输入触发信号，此时第4阶的第二组合中的第二随机存储器写操作成功，写操作成功后输出最终的随机数(例如为1)。
需要说明的是，在上述图2c中，也可以是直接从第2阶或第3阶的某一个第一随机存储器或第二随机存储器输入触发信号，执行过程与上述图2c中的过程类似，直到第4阶的某一个第一随机存储器或第二随机存储器输出最终的随机数。此外，上述图2c中的4阶随机存储器也仅仅是举例说明，在本申请实施例中的其它方式，也可以是其它阶的随机存储器，例如5阶、8阶等等，可以根据实际情况进行相应的设置。另外，图2c中的随机存储器的写操作成功或失败，是根据实际情况确定的。
通过图2c中多个存储器形成多层概率叠加，形成了复杂多随机发生器提升了写操作成功与否的不可预测性。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来 实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对相关技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本申请各个实施例的方法。
第二方面，本申请实施例提供了一种随机数的产生装置，图4是本申请实施例的随机数的产生装置的结构示意图，如图4所示，该装置包括：
随机存储器42，用于接收触发信号以触发执行写操作。
其中，写操作具有成功概率。
控制器44，用于根据写操作得到随机数，且用于在每次写操作成功的情况下，产生第一数据，在每次写操作未成功的情况下，产生第二数据。
其中，第一数据和第二数据分别为二值数据中的不同数据。
通过本申请实施例中的装置，可以通过向随机存储器输入触发信号以触发执行写操作，并在写操作成功或未成功的情况下，分别产生第一数据和第二数据，该第一数据和第二数据为二值数据中的数据，从而本申请可根据第一数据和第二数据实现随机产生随机数，且无需持续向随机存储器输入触发信号，因此，解决了相关技术中通过持续输出脉冲信号以产生随机数，导致产生随机数的过程能耗大以及资源占用大的问题。
可选地，随机存储器为非挥发性的磁性随机存储器MRAM。
可选地，本申请实施例中的随机存储器42进一步可以包括：设置单元，用于设置与触发信号对应的触发信号参数，其中，触发信号参数的取值与写操作的成功概率关联；输入单元，用于向随机存储器输入触发信号，基于触发信号的触发信号参数触发执行写操作。
可选地，本申请实施例中的触发信号为脉冲信号。基于此，本申 请实施例中的触发信号参数包括以下至少一项：触发信号的脉冲宽度、触发信号的脉冲振幅、触发信号的输入电压、单位时间内输入触发信号的次数。
可选地，本申请实施例中的控制器44，还用于执行以下步骤：
S1，向一个随机存储器输入一个触发信号以触发执行一次写操作，根据该次写操作产生的数据确定随机数。
可选地，本申请实施例中的控制器44，还用于执行以下步骤：
S1，向随机存储器输入多个触发信号以触发执行多次写操作，根据多次写操作产生的多个数据确定随机数。
在本申请实施例的可选实施方式中，本申请实施例的装置还可以包括：调整模块，用于在触发执行写操作之后，对触发信号参数的取值进行调整。
可选地，在随机存储器的数量为一个的情况下，本申请实施例中的控制器44，还用于执行以下步骤：
S1，向随机存储器输入多个触发信号以触发执行多次写操作。
其中，随机存储器在每一次触发下具有对应的写操作的成功概率。
S2，根据多次写操作的结果产生对应的多个数据。
S3，对多个数据中的数据执行第一操作，直到获得唯一的随机数。
其中，第一操作包括以下之一：异或操作、同或操作。
可选地，在随机存储器的数量为多个的情况下，本申请实施例中控制器44，还用于执行以下步骤：
S1，向多个随机存储器分别输入一个或多个触发信号以触发执行多次写操作。
其中，在触发信号的触发下每一个所述随机存储器具有对应写操作的成功概率。
S2，根据多次写操作的结果产生对应的多个数据。
S3，对多个数据中的数据执行第一操作，直到获得唯一的随机数。
可选地，在随机存储器的数量为多个的情况下，多个随机存储器分成N阶，其中第i阶的随机存储器数量为2 i-1个，N为大于或等于2的整数，i为小于或等于N的正整数；除第1阶外，其它每阶的随机存储器分为多个组合，每个组合包括1个第一随机存储器和1个第二随机存储器；除第N阶外，其它每阶中的每个随机存储器对应后1阶的一个组合。
本申请实施例中的控制器44，还用于执行以下步骤：
S1，向第1阶的随机存储器输入触发信号以触发执行写操作。
S2，触发步骤：在当前写操作成功时，向执行当前写操作的随机存储器对应的组合中的第一随机存储器发送触发信号；在当前写操作未成功时，向执行当前写操作的随机存储器对应的组合中的第二随机存储器发送触发信号。
S3，在当前随机存储器位于除第N阶外的其它阶时，返回触发步骤；在当前随机存储器位于第N阶时，根据当前写操作产生的数据确定随机数。
第三方面，参照图5，本申请实施例还提供一种电子设备，包括处理器，存储器，存储在存储器上并可在所述处理器上运行的程序或指令，该程序或指令被处理器执行时实现上述对抗样本的生成方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要注意的是，本申请实施例中的电子设备包括上述所述的移动电子设备和非移动电子设备。
第四方面，参照图6，本申请实施例还提供一种可读存储介质，所述可读存储介质上存储有程序或指令，该程序或指令被处理器执行时实现上述对抗样本的生成方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
其中，所述处理器为上述实施例中所述的电子设备中的处理器。所述可读存储介质，包括计算机可读存储介质，如计算机只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access  Memory，RAM)、磁碟或者光盘等。
显然，本领域的技术人员应该明白，上述的本申请的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本申请不限制于任何特定的硬件和软件结合。
以上所述仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (12)

  1. 一种随机数的产生方法，其特征在于，包括：
    向随机存储器输入触发信号以触发执行写操作，得到随机数；
    其中，所述写操作具有成功概率；在每次所述写操作成功的情况下，产生第一数据；在每次所述写操作未成功的情况下，产生第二数据；所述第一数据和所述第二数据分别为二值数据中的不同数据。
  2. 根据权利要求1所述的方法，其特征在于，向随机存储器输入触发信号以触发执行写操作，包括：
    设置与所述触发信号对应的触发信号参数；其中，所述触发信号参数的取值与所述写操作的成功概率关联；
    向所述随机存储器输入所述触发信号，基于所述触发信号的触发信号参数触发执行所述写操作。
  3. 根据权利要求1或2所述的方法，其特征在于，向随机存储器输入触发信号以触发执行写操作，得到随机数包括：
    向一个随机存储器输入一个触发信号以触发执行一次写操作，根据该次写操作产生的数据确定随机数。
  4. 根据权利要求1或2所述的方法，其特征在于，向随机存储器输入触发信号以触发执行写操作，得到随机数包括：
    向随机存储器输入多个触发信号以触发执行多次写操作，根据多次写操作产生的多个数据确定随机数。
  5. 根据权利要求1或2所述的方法，其特征在于，所述随机存储器的数量为一个或多个。
  6. 根据权利要求5所述的方法，其特征在于，所述随机存储器的数量为一个；向随机存储器输入触发信号以触发执行写操作，得到随机数，包括：
    向所述随机存储器输入多个触发信号以触发执行多次写操作；其 中，所述随机存储器在每一次触发下具有对应的写操作的成功概率；
    根据多次写操作的结果产生对应的多个数据；
    对所述多个数据中的数据执行第一操作，直到获得唯一的随机数；其中，所述第一操作包括以下之一：异或操作、同或操作。
  7. 根据权利要求5所述的方法，其特征在于，所述随机存储器的数量为多个；向随机存储器输入触发信号以触发执行写操作，得到随机数，包括：
    向多个所述随机存储器分别输入一个或多个触发信号以触发执行多次写操作；其中，在所述触发信号的触发下每一个所述随机存储器具有对应写操作的成功概率；
    根据多次写操作的结果产生对应的多个数据；
    对所述多个数据中的数据执行第一操作，直到获得唯一的随机数；其中，所述第一操作包括以下之一：异或操作、同或操作。
  8. 根据权利要求5所述的方法，其特征在于，
    所述随机存储器的数量为多个，多个所述随机存储器分成N阶，其中第i阶的随机存储器数量为2 i-1个，N为大于或等于2的整数，i为小于或等于N的正整数；除第1阶外，其它每阶的随机存储器分为多个组合，每个组合包括1个第一随机存储器和1个第二随机存储器；除第N阶外，其它每阶中的每个随机存储器对应后1阶的一个组合；
    向随机存储器输入触发信号以触发执行写操作，得到随机数，包括：
    向第1阶的随机存储器输入触发信号以触发执行写操作；
    触发步骤：在当前写操作成功时，向执行当前写操作的随机存储器对应的组合中的第一随机存储器发送触发信号；在当前写操作未成功时，向执行当前写操作的随机存储器对应的组合中的第二随机存储器发送触发信号；
    在当前随机存储器位于除第N阶外的其它阶时，返回触发步骤；在当前随机存储器位于第N阶时，根据当前写操作产生的数据确定随 机数。
  9. 根据权利要求1或2所述的方法，其特征在于，所述随机存储器为非挥发性的磁性随机存储器MRAM。
  10. 一种随机数的产生装置，其特征在于，包括：
    随机存储器，用于接收触发信号以触发执行写操作；所述写操作具有成功概率；
    控制器，用于根据所述写操作得到随机数，且用于在每次所述写操作成功的情况下，产生第一数据，在每次所述写操作未成功的情况下，产生第二数据；所述第一数据和所述第二数据分别为二值数据中的不同数据。
  11. 一种电子设备，其特征在于，包括处理器，存储器及存储在所述存储器上并可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如权利要求1-9中任一项所述的随机数的产生方法的步骤。
  12. 一种可读存储介质，其特征在于，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如权利要求1-9中任一项所述的随机数的产生方法的步骤。
PCT/CN2021/129710 2020-11-13 2021-11-10 随机数的产生方法及装置、电子设备和可读存储介质 WO2022100595A1 (zh)

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