WO2022100578A1 - 5g系统中ofdm变换方法及相关产品 - Google Patents

5g系统中ofdm变换方法及相关产品 Download PDF

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Publication number
WO2022100578A1
WO2022100578A1 PCT/CN2021/129594 CN2021129594W WO2022100578A1 WO 2022100578 A1 WO2022100578 A1 WO 2022100578A1 CN 2021129594 W CN2021129594 W CN 2021129594W WO 2022100578 A1 WO2022100578 A1 WO 2022100578A1
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num
stage
fft
fftgroup
factors
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PCT/CN2021/129594
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French (fr)
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顾明飞
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展讯半导体(成都)有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm

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  • the present application relates to the technical field of communication processing, and in particular, to an OFDM conversion method in a 5G system and related products.
  • OFDM Orthogonal Frequency Division Multiplexing
  • OFDM transformation needs to be completed, which requires extremely high delay.
  • the existing OFDM transformation has high delay and large resource consumption.
  • the embodiments of the present application disclose an OFDM conversion method and related products in a 5G system, which can reduce the time delay of OFDM, effectively reduce resource consumption, and improve user experience.
  • a first aspect provides an OFDM transformation method in a 5G system, the method comprising the following steps:
  • the first stage operation is performed after zero-filling the value not input in the first stage operation according to the zero value mapping.
  • the stage fetching address is determined according to the address mapping, and the fetching address is The output operation result is written into the address with the fetched data, and the output operation result is subjected to accelerated processing of partial continuous sequence conversion to obtain the OFDM transformation result.
  • a user equipment in a second aspect, includes:
  • the processing unit is used to determine the order stage of the OFDM transformation in the 5G system; the corresponding address mapping is determined according to the stage and the number of factors decomposed by the data; when the first stage is operated, the first stage is operated according to the zero-value mapping. The first stage operation is performed after the zero-filling of the uninput value.
  • the corresponding address mapping is determined according to the stage and the number of factors decomposed by the processed data; the stage fetching address is determined according to the address mapping, and the The data of the fetch address is operated to obtain an output operation result, the output operation result is written into the address with the fetch address, and the output operation result is subjected to accelerated processing of partial continuous sequence conversion to obtain the OFDM transformation result.
  • an electronic device comprising a processor, a memory, a communication interface, and one or more programs, the one or more programs being stored in the memory and configured to be executed by the processor , the program includes instructions for performing the steps in the method of the first aspect.
  • a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program causes a computer to perform the method of the first aspect.
  • a computer program product in a fifth aspect, includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute the first aspect of the embodiments of the present application. some or all of the steps described in .
  • the computer program product may be a software installation package.
  • a chip system in a sixth aspect, includes at least one processor, a memory and an interface circuit, the memory, the transceiver and the at least one processor are interconnected through a line, and the at least one memory stores There is a computer program; the computer program when executed by the processor implements the method of the first aspect.
  • the technical solution provided by this application is to obtain the data of OFDM transformation in the 5G system, and determine the stage of the OFDM transformation in the 5G system; determine the corresponding address mapping according to the stage and the number of factors decomposed by the data; in the first stage operation, According to the zero-value mapping, the first stage operation is performed after zero-filling the value not input in the first stage operation.
  • the corresponding address mapping is determined according to the stage and the number of factors of the decomposition of the processed data; according to the The address mapping determines the fetch address of the stage, performs an operation on the data of the fetch address to obtain the output operation result, writes the output operation result into the address with the fetch address, and performs partial sequential sequential conversion acceleration processing on the output operation result to obtain the OFDM transformation result.
  • the solution of the present application uses the same address structure to read and write data, which effectively reduces the delay. In the actual test, it only delays a few clock beats, so it has the effect of reducing the delay.
  • Retrieving numbers according to the above mapping can greatly improve the address utilization rate, increase the operation speed, reduce the operation resources, and improve the user experience.
  • 1 is a system architecture diagram of an example communication system
  • FIG. 2 is a schematic flowchart of an OFDM conversion method in a 5G system provided by the present application
  • Fig. 3 is the hardware structure schematic diagram of FFT processor
  • Fig. 4 is a schematic diagram of a base 8/4/2 butterfly operation structure
  • Figure 5 is a schematic diagram of a 4-point or 2-point FFT hardware structure
  • FIG. 6 is a schematic structural diagram of a user equipment provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • connection in the embodiments of the present application refers to various connection modes such as direct connection or indirect connection, so as to realize communication between devices, which is not limited in the embodiments of the present application.
  • OFDM transform generally needs to be realized by FFT (Fast Fourier Transform)/IFFT (Inverse Fast Fourier Transform) processor.
  • FFT_size represents the size of the FFT
  • fftidx_max represents the maximum index of the fft
  • fftgroup_max represents the maximum value of the fft group.
  • FIG. 2 provides an OFDM conversion method in a 5G system.
  • the method is implemented in the communication system as shown in FIG. 1. Specifically, the above method can be executed by a terminal in the communication system as shown in FIG. 1. , of course, in an optional solution, it can also be performed by a network device in the communication system as shown in FIG. 1 , and the method includes the following steps:
  • Step S201 obtaining the data of the OFDM transformation in the 5G system
  • Step S202 determine the stage of the OFDM transformation in the 5G system; determine the corresponding address mapping according to the stage and the number of factors of the decomposition of the processing data; during the first stage operation, according to the zero value mapping, the first stage operation is not input. After the value is zero-filled, the first stage operation is performed.
  • the method of the above zero-filling processing may be that the data at the zero-filling position is not read, and the data at the zero-filling position is determined to be zero, and the zero-filling is a position not included in the data in the preset transformation size, for example, the preset transformation The size is 16 and the data is 9, then the position of the last 7 data is regarded as the zero-padding position.
  • zero-filling can also be determined according to the zero-filling mapping relationship, and the mapping relationship can be continuous zero-filling, tree-shaped zero-filling, zero-filling at every interval, and so on.
  • the above-mentioned zero-value mapping may specifically be: which data is 0 is represented by the following parameters, which are specifically described in the following description.
  • the OFDM variation described above may include FFT or IFFT transforms. The specific process is as follows:
  • the data is input to 8 pieces of RAM, and the linear address is mapped to RAM BANK number and BANK address. If the number of data input is less than or equal to FFT_size, if it is less than the value of the FFT points to be calculated, the uninput value will be used as the first stage operation.
  • the zero-filling process obtains data conforming to FFT_size (that is, processing data), that is, the address is judged when the number is fetched, and the value corresponding to the address is directly assigned to 0 when the condition is satisfied, without reading RAM.
  • Which data is 0 is characterized by the following parameters; k0, k0_size, k1, k1_size, map_type.
  • map_type is 0 to indicate continuous 0-value mapping k0 is the first address of the mapping, k0_size is the mapping length, k1 is the first address of the mapping, k1_size is the mapping length; map_type is 1 indicates that it is a comb-shaped mapping type1, and its mapping address and length It is still represented by k0, k1, k0_size, k1_size, but the address of 0 is mapped to 0 for every other address; map_type is 2 to indicate comb mapping type2, and its mapping address and length are still determined by k0, k1, k0_size , represented by k1_size, but its 0 address is mapped to 0 every two addresses;
  • the operation is performed under the external operation enable and configuration parameters (FFT_size, IFFT or FFT operation flag).
  • FFT_size the linear address of the data required for the operation is described above, and the address is converted to the RAM BANK number under the mapping. And BANK address, the 8 numbers are taken for base 8 operation, the operation result is multiplied by the twiddle factor in the non-last stage, and the intermediate result of the operation is written back to the memory.
  • the base 2 or base 4 or base 8 operation will be performed (depending on the specific decomposition of each point).
  • the operation is carried out to the last stage, there is no twiddle factor, and the result will be output after the cache conversion. described below.
  • RAM adopts dual-port memory, which is used for data input and output at the same time.
  • the ROM table is used to store the 7-way twiddle factors required for base-8 operations.
  • Cache and continuous sequence conversion, and further partial continuous sequence conversion on the output operation result is beneficial to the accelerated processing of the subsequent processing unit (digital front end).
  • the sequence here satisfies 4 consecutive addresses.
  • the specific buffering and fetching rules can be as follows: for the rdx2 operation of the last operation processing, the output starts after the third 8-point data is input in each group, and the other results are output after the fourth 8-point data is input in each group.
  • a group of input and output here refers to the input and output of 32 numbers, and the first group and the second group are executed alternately.
  • Step S203 during the subsequent stage operation, determine the stage fetching address according to the address mapping, perform an operation on the data of the fetching address to obtain an output operation result, write the output operation result with the fetching address, and perform part of the output operation result.
  • the accelerated processing of the sequential order transform obtains the OFDM transform result.
  • the above operation may specifically be an intermediate operation of the OFDM transform, for example, an addition and a multiplication operation.
  • the technical solution provided by this application is to obtain the data of OFDM transformation in the 5G system, and determine the stage of the OFDM transformation in the 5G system; determine the corresponding address mapping according to the stage and the number of factors decomposed by the data; in the first stage operation, According to the zero-value mapping, the first stage operation is performed after zero-filling the value not input in the first stage operation.
  • the corresponding address mapping is determined according to the stage and the number of factors of the decomposition of the processed data; according to the The address mapping determines the fetch address of the stage, performs an operation on the data of the fetch address to obtain the output operation result, writes the output operation result into the address with the fetch address, and performs partial sequential conversion on the output operation result for accelerated processing to obtain the OFDM transformation result.
  • the solution of the present application uses the same address structure to read and write data, which effectively reduces the delay. In the actual test, it only delays a few clock beats, so it has the effect of reducing the delay.
  • Retrieving numbers according to the above mapping can greatly improve the address utilization rate, increase the operation speed, reduce the operation resources, and improve the user experience.
  • stage fetching address specifically includes:
  • stage fetching address fftgroup_num, fftidx_num, fftidx_max, and log2_num.
  • the fftgroup_num may specifically be the fft group number, and the fftidx_num may specifically be the fft index number.
  • the value of each point in each stage is as follows:
  • fftgroup_max 1, 8, 64, 256
  • the above-mentioned determination of the stage fetching address according to fftgroup_max, fftidx_num, fftidx_max, and log2_num specifically includes:
  • fft_addr0 fftidx_num+fftgroup_base
  • fft_addrx fft_addr(x-1)+fftidx_max*x;
  • x is an integer of [1,7]
  • fftgroup_base fftgroup_num ⁇ log2_num
  • fft_addr0 fftidx_num+fftgroup_base
  • fft_addr1 fft_addr0+fftidx_max;
  • fft_addr2 fft_addr1+fftidx_max*2;
  • fft_addr3 fft_addr2+fftidx_max*3;
  • fft_addr4 fft_addr3+fftidx_max*4;
  • fft_addr5 fft_addr4+fftidx_max*5;
  • fft_addr6 fft_addr5+fftidx_max*6;
  • fft_addr7 fft_addr6+fftidx_max*7;
  • Twiddle factor address: twf_rom_addr fftidx_num;
  • ⁇ means left shift
  • fftgroup_base fftgroup_num ⁇ log2_num.
  • the counter fftidx_num is calculated in each clock cycle.
  • the fftgroup_num counter is incremented by 1.
  • the stage operation fetches the address. produce end.
  • fft_addr0 indicates the first address of an fft value
  • addr indicates the address
  • 0 indicates that the address number of the value is 0 (starting value).
  • fft_addrx represents the number of the address, which can be any integer between [1,7].
  • the corresponding address mapping is determined according to the stage and the number of factors of the processing data decomposition; the determination of the stage data fetching address according to the address mapping specifically includes:
  • fftgroup_num the fast Fourier transform group value fftgroup_num according to the stage and the number of decomposed factors. If the stage is the last stage, determine fft_addr0 according to the specific bits of the fftgroup_num and the number of factors decomposed; determine the subsequent fft_addrx according to fft_addr0, the The value of x is an integer of [1,7].
  • determining fft_addr0 according to the specific bits of the fftgroup_num and the number of factors decomposed; determining the subsequent fft_addrx according to fft_addr0 specifically includes:
  • fft_addr0 fftgroup_num[2:0] ⁇ 3; wherein, fftgroup_num[2:0] indicates that the 0th, 1st, and 2th of fftgroup_num are selected
  • ⁇ means left shift
  • 3 means the number of bits to move, that is, the value of the 0th, 1st, and 2th bits of fftgroup_num is shifted to the left by 3 bits.
  • fft_addr0 fftgroup_num[3:1] ⁇ 6+fftgroup_num[6:4] ⁇ 3; where, fftgroup_num[3:1] represents the 1st, 2nd, and 3rd of fftgroup_num. bits, fftgroup_num[6:4] represents the 4th, 5th, and 6th bits of fftgroup_num[6:4], and ⁇ represents left shift. It should be noted that the addition operation is performed after the left shift is performed. .
  • fft_addr0 fftgroup_num[9:7] ⁇ 3+fftgroup_num[6:4] ⁇ 6+ftgroup_num[3:1] ⁇ 9.
  • fftgroup_num[9:7] represents the 7th, 8th, and 9th bits of fftgroup_num
  • fftgroup_num[6:4] represents the 4th, 5th, and 6th bits of fftgroup_num[6:4]
  • ⁇ Indicates a left shift
  • fftgroup_num[3:1] indicates the 1st, 2nd, and 3rd bits of fftgroup_num. It should be noted that the addition operation is performed after the left shift is performed.
  • FIG. 3 is a schematic diagram of the hardware structure of a processor of FFT and IFFT in OFDM transformation in an embodiment of the application, as shown in FIG. 4,
  • FIG. 4 is a radix 8/4/2 butterfly in OFDM transformation in an embodiment of the application
  • Fig. 5 is a schematic diagram of the structure of the shape operation.
  • Fig. 5 is a schematic diagram of the hardware structure of one 4-point or two 2-point FFT in the OFDM transform according to the embodiment of the present application.
  • the user equipment includes corresponding hardware and/or software modules for executing each function.
  • the present application can be implemented in hardware or in the form of a combination of hardware and computer software in conjunction with the algorithm steps of each example described in conjunction with the embodiments disclosed herein. Whether a function is performed by hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functionality for each particular application in conjunction with the embodiments, but such implementations should not be considered beyond the scope of this application.
  • the electronic device can be divided into functional modules according to the above method examples.
  • each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware. It should be noted that, the division of modules in this embodiment is schematic, and is only a logical function division, and there may be other division manners in actual implementation.
  • FIG. 6 shows a schematic diagram of a user equipment.
  • the UE 600 may include: an obtaining unit 601 and a processing unit 602.
  • the processing unit 602 may be configured to support the user equipment to perform the above steps S202, S203, etc., and/or other processes for the techniques described herein.
  • the obtaining unit 601 may be used to support the user equipment to perform the above-mentioned step S201, etc., and/or other processes for the techniques described herein.
  • the network device provided in this embodiment is configured to perform step S201 in the above method shown in FIG. 2 , so the same effect as the above implementation method can be achieved.
  • the user equipment may include a processing module, a storage module and a communication module.
  • the processing module may be used to control and manage the actions of the user equipment, for example, may be used to support the electronic device to perform the steps performed by the obtaining unit 601 and the processing unit 602 above.
  • the storage module may be used to support the electronic device to execute stored program codes and data, and the like.
  • the communication module can be used to support the communication between the electronic device and other devices.
  • the processing module may be a processor or a controller. It may implement or execute the various exemplary logical blocks, modules and circuits described in connection with this disclosure.
  • the processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, and the like.
  • the storage module may be a memory.
  • the communication module may specifically be a device that interacts with other electronic devices, such as a radio frequency circuit, a Bluetooth chip, and a Wi-Fi chip.
  • the interface connection relationship between the modules illustrated in the embodiments of the present application is only a schematic illustration, and does not constitute a structural limitation of the user equipment.
  • the user equipment may also adopt different interface connection manners in the foregoing embodiments, or a combination of multiple interface connection manners.
  • FIG. 7 is an electronic device 70 provided by an embodiment of the present application.
  • the electronic device 70 includes a processor 701, a memory 702, and a communication interface 703.
  • the processor 701, the memory 702, and the communication interface 703 pass through a bus connected to each other.
  • the memory 702 includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or A portable read-only memory (compact disc read-only memory, CD-ROM), the memory 702 is used for related computer programs and data.
  • the communication interface 703 is used to receive and transmit data.
  • the processor 701 may be one or more central processing units (central processing units, CPUs). In the case where the processor 701 is a CPU, the CPU may be a single-core CPU or a multi-core CPU.
  • the processor 701 may include one or more processing units, for example, the processing unit may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor ( image signal processor, ISP), controller, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural-network processing unit (neural-network processing unit, NPU), etc. Wherein, different processing units may be independent components, or may be integrated in one or more processors.
  • the user equipment may also include one or more processing units.
  • the controller can generate an operation control signal according to the instruction operation code and the timing signal, and complete the control of fetching and executing instructions.
  • memory may also be provided in the processing unit for storing instructions and data.
  • the memory in the processing unit may be a cache memory. This memory can hold instructions or data that have just been used or recycled by the processing unit. If the processing unit needs to use the instruction or data again, it can be called directly from the memory. In this way, repeated access is avoided, and the waiting time of the processing unit is reduced, thereby improving the efficiency of the user equipment in processing data or executing instructions.
  • the processor 701 may include one or more interfaces.
  • the interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous transceiver (universal) asynchronous receiver/transmitter, UART) interface, mobile industry processor interface (mobile industry processor interface, MIPI), general-purpose input/output (GPIO) interface, SIM card interface and/or USB interface, etc.
  • the USB interface is an interface that conforms to the USB standard specification, and can specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, and the like.
  • the USB interface can be used to connect a charger to charge the user equipment, and can also be used to transfer data between the user equipment and peripheral devices.
  • the USB port can also be used to connect headphones and play audio through the headphones.
  • the processor 701 in the electronic device 70 is configured to read the computer program code stored in the memory 702, and perform the following operations:
  • the data of the OFDM transformation in the 5G system If the data is smaller than the preset transformation size, perform zero-padding processing on the data to obtain the processed data, and determine the order stage of the OFDM transformation in the 5G system; according to the stage and the decomposition of the processed data. The number of factors determines the corresponding address mapping;
  • the electronic device 70 is a network side device, such as a base station.
  • An embodiment of the present application further provides a chip system, the chip system includes at least one processor, a memory, and an interface circuit, the memory, the transceiver, and the at least one processor are interconnected by lines, and the at least one memory
  • a computer program is stored in the computer; when the computer program is executed by the processor, the method flow shown in FIG. 2 is realized.
  • Embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed on a network device, the method flow shown in FIG. 2 is implemented.
  • the embodiment of the present application further provides a computer program product, when the computer program product runs on the terminal, the method flow shown in FIG. 2 is realized.
  • Embodiments of the present application further provide a terminal, including a processor, a memory, a communication interface, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the processor , the program includes instructions for performing the steps in the method of the embodiment shown in FIG. 2 .
  • the electronic device includes corresponding hardware structures and/or software templates for executing each function.
  • the present application can be implemented in hardware or in the form of a combination of hardware and computer software, in combination with the units and algorithm steps of each example described in the embodiments provided herein. Whether a function is performed by hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.
  • the electronic device may be divided into functional units according to the foregoing method examples.
  • each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units. It should be noted that the division of units in the embodiments of the present application is illustrative, and is only a logical function division, and other division methods may be used in actual implementation.
  • the disclosed apparatus may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the above-mentioned units is only a logical function division.
  • multiple units or components may be combined or integrated. to another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical or other forms.
  • the units described above as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the above-mentioned integrated units if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable memory.
  • the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art, or all or part of the technical solution, and the computer software product is stored in a memory.
  • a computer device which may be a personal computer, a server, or a network device, etc.
  • the aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

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Abstract

一种5G系统中OFDM变换方法及相关产品，方法包括如下步骤：获取5G系统中OFDM变换的数据，确定5G系统中OFDM变换的阶数stage；依据stage以及数据的分解的因子个数确定对应的地址映射；在第一stage运算时，依据零值映射对第一stage运算未输入的数值补零处理后执行第一stage运算，在后续stage运算时，依据地址映射确定stage取数地址，对取数地址的数据执行运算得到输出运算结果，将输出运算结果写入取数地址，对输出运算结果进行部分连续序转换的加速处理得到OFDM变换结果。从而具有用户体验度高的优点。

Description

5G系统中OFDM变换方法及相关产品
本申请要求2020年11月10日递交的发明名称为“5G系统中OFDM变换方法及相关产品”的申请号2020112503721的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本申请涉及通信处理技术领域，尤其涉及一种5G系统中OFDM变换方法及相关产品。
背景技术
OFDM(Orthogonal Frequency Division Multiplexing，正交频分复用)系统可以有效对抗干扰，在多径及衰弱信道环境中可以实现超高速数据传输，同时系统中可以对每条链路独立调制。在5G系统中需要完成OFDM变换，其对时延要求极高，现有的OFDM变化的时延较高，资源消耗大。
发明内容
本申请实施例公开了一种5G系统中OFDM变换方法及相关产品，能够降低OFDM的时延，有效降低资源消耗量，提高用户的体验度。
第一方面，提供一种5G系统中OFDM变换方法，所述方法包括如下步骤：
获取5G系统中OFDM变换的数据，确定5G系统中OFDM变换的阶数stage；依据该stage以及该处理数据的分解的因子个数确定对应的地址映射；
在第一stage运算时，依据零值映射对第一stage运算未输入的数值补零处理后执行第一stage运算，在后续stage运算时，依据该地址映射确定stage取数地址，对取数地址的数据执行运算得到输出运算结果，将输出运算结果写入带该取数地址，对输出运算结果进行部分连续序转换的加速处理得到OFDM变换结果。
第二方面，提供一种用户设备，所述用户设备包括：
获取单元，用于获取5G系统中OFDM变换的数据；
处理单元，用于确定5G系统中OFDM变换的阶数stage；依据该stage以及该数据的分解的因子个数确定对应的地址映射；在第一stage运算时，依 据零值映射对第一stage运算未输入的数值补零处理后执行第一stage运算，在后续stage运算时，依据该stage以及该处理数据的分解的因子个数确定对应的地址映射；依据该地址映射确定stage取数地址，对取数地址的数据执行运算得到输出运算结果，将输出运算结果写入带该取数地址，对输出运算结果进行部分连续序转换的加速处理得到OFDM变换结果。
第三方面，提供一种电子设备，包括处理器、存储器、通信接口，以及一个或多个程序，所述一个或多个程序被存储在所述存储器中，并且被配置由所述处理器执行，所述程序包括用于执行第一方面所述的方法中的步骤的指令。
第四方面，提供了一种计算机可读存储介质，存储用于电子数据交换的计算机程序，其中，所述计算机程序使得计算机执行第一方面所述的方法。
第五方面，提供了一种计算机程序产品，其中，上述计算机程序产品包括存储了计算机程序的非瞬时性计算机可读存储介质，上述计算机程序可操作来使计算机执行如本申请实施例第一方面中所描述的部分或全部步骤。该计算机程序产品可以为一个软件安装包。
第六方面，提供了芯片系统，所述芯片系统包括至少一个处理器，存储器和接口电路，所述存储器、所述收发器和所述至少一个处理器通过线路互联，所述至少一个存储器中存储有计算机程序；所述计算机程序被所述处理器执行时实现第一方面所述的方法。
本申请提供的技术方案在获取5G系统中OFDM变换的数据，确定5G系统中OFDM变换的stage；依据该stage以及该数据的分解的因子个数确定对应的地址映射；在第一stage运算时，依据零值映射对第一stage运算未输入的数值补零处理后执行第一stage运算，在后续stage运算时，依据该stage以及该处理数据的分解的因子个数确定对应的地址映射；依据该地址映射确定stage取数地址，对取数地址的数据执行运算得到输出运算结果，将输出运算结果写入带该取数地址，对输出运算结果进行部分连续序转换的加速处理得到OFDM变换结果。本申请的方案采用同址结构进行数据的读取和写入，有效的降低了时延，在实际测试中，其只会延时数个时钟节拍，因此其具有降低时延的作用，另外，依据上述映射取数能够极大的提高地址利用率，提高运算速度，降低运算资源，提高用户体验度。
附图说明
以下对本申请实施例用到的附图进行介绍。
图1是一种示例通信系统的系统架构图；
图2是本申请提供的一种5G系统中OFDM变换方法的流程示意图；
图3是FFT处理器的硬件结构示意图；
图4是基8/4/2蝶形运算结构示意图；
图5是一个4点或2个2点FFT硬件结构示意图；
图6是本申请实施例提供的一种用户设备的结构示意图；
图7是本申请实施例提供的一种电子设备的结构示意图。
具体实施方式
下面结合本申请实施例中的附图对本申请实施例进行描述。
本申请中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，表示前后关联对象是一种“或”的关系。
本申请实施例中出现的“多个”是指两个或两个以上。本申请实施例中出现的第一、第二等描述，仅作示意与区分描述对象之用，没有次序之分，也不表示本申请实施例中对设备个数的特别限定，不能构成对本申请实施例的任何限制。本申请实施例中出现的“连接”是指直接连接或者间接连接等各种连接方式，以实现设备间的通信，本申请实施例对此不做任何限定。
本申请实施例的技术方案可以应用于如图1所示的示例通信系统100，该示例通信系统100包括终端110和网络设备120，终端110与网络设备120通信连接。
OFDM变换一般需要采用FFT(快速傅里叶变换)/IFFT(快速傅里叶逆变换)处理器来实现，FFT/IFFT处理器运算stage(阶数)与其分解因子有关，其分解的因子个数确定其运算阶数，令FFT_size为所要变换的点数，fftidx_max，fftgroup_max,为某一点数及各运算stage(运算阶数)下分解的固定 计数最大值，其取值满足FFT_size＝fftidx_max*fftgroup_max*8。
其中，FFT_size表示，FFT的尺寸，fftidx_max表示，fft的索引最大值，fftgroup_max表示，fft组的最大值。
参阅图2，图2提供了一种5G系统中OFDM变换方法，该方法在如图1所示的通信系统下实现，具体的，上述方法可以由如图1所示的通信系统中的终端执行，当然在一种可选的方案中，也可以由如图1所示的通信系统中的网络设备执行，所述方法包括如下步骤：
步骤S201、获取5G系统中OFDM变换的数据；
步骤S202、确定5G系统中OFDM变换的stage；依据该stage以及该处理数据的分解的因子个数确定对应的地址映射；在第一stage运算时，依据零值映射对第一stage运算未输入的数值补零处理后执行第一stage运算，
上述补零处理的方式可以为，不读取该补零位置的数据，认定该补零位置的数据为零，该补零为预设变换尺寸中该数据不包含的位置，例如，预设变换尺寸为16，数据为9，那么认定后7个数据的位置为补零位置。当然补零也可以根据补零映射关系来确定，该映射关系可以为连续补零，也可以为树状补零、隔位补零等等。
上述零值映射具体可以为：数据哪些为0由下列几个参数表征，具体参加如下描述。上述OFDM变化可以包括FFT或IFFT变换。其具体过程如下：
首先数据输入到8片RAM，线性地址到RAM BANK号及BANK地址映射，数据输入的数量若小于等于FFT_size，如小于所要运算FFT点数值，则在第一个stage运算时将未输入的数值作补零处理得到符合FFT_size的数据(即处理数据)，即在取数时对地址作判断，条件满足时将该地址所对应的数值直接赋值为0，而不用读RAM。数据哪些为0由下列几个参数表征；k0,k0_size,k1,k1_size,map_type。其中，map_type为0指示为连续0值映射k0为映射的首地址，k0_size为映射长度，k1为映射的首地址，k1_size为映射长度；map_type为1指示为梳状映射type1，其映射地址和长度任然由k0,k1,k0_size,k1_size所表征，但是其取0地址为每隔一个地址映射为0；map_type为2指示为梳状映射type2，其映射地址和长度任然由k0,k1,k0_size,k1_size所表征，但是其取0地址为每隔二个地址映射为0；
数据输入完成后，在外部运算使能及配置参数(FFT_size、IFFT或者FFT运算标识)下进行运算动作，运算所需数据的线性地址由上文所述，该地址在映射下转换为RAM BANK号及BANK地址，所取8个数进行基8运算，在非最后一个stage下运算结果和旋转因子相乘，运算中间结果回写存储器。运算进行到最后一个stage时将进行基2或者基4或者基8运算(视各个点数具体分解情况而定)，运算进行最后一级时已无旋转因子作用，结果缓存转换后输出，缓存转换由下文所描述。RAM采用双口存储器，用于数据输入和输出的同时进行。ROM表用于存储基8运算所需的7路旋转因子。
缓存及连续序转换，对输出运算结果进行进一步的部分连续序转换有利于后续处理单元(数字前端)的加速处理，这里的序满足4个地址连续。
具体缓存及取数规则可以为：对于最后运算处理的rdx2运算，在每组输入第三个8点数据后即开始输出结果，其它在每组输入第四个8点数据后输出结果。这里的一组输入输出指32个数的输入输出，第一组和第二组交替执行。
步骤S203、在后续stage运算时，依据该地址映射确定stage取数地址，对取数地址的数据执行运算得到输出运算结果，将输出运算结果写入带该取数地址，对输出运算结果进行部分连续序转换的加速处理得到OFDM变换结果。
上述运算具体可以为，OFDM变换的中间运算，例如，加、乘运算。
本申请提供的技术方案在获取5G系统中OFDM变换的数据，确定5G系统中OFDM变换的stage；依据该stage以及该数据的分解的因子个数确定对应的地址映射；在第一stage运算时，依据零值映射对第一stage运算未输入的数值补零处理后执行第一stage运算，在后续stage运算时，依据该stage以及该处理数据的分解的因子个数确定对应的地址映射；依据该地址映射确定stage取数地址，对取数地址的数据执行运算得到输出运算结果，将输出运算结果写入带该取数地址，对输出运算结果进行部分连续序转换的加速处理得到OFDM变换结果。本申请的方案采用同址结构进行数据的读取和写入，有效的降低了时延，在实际测试中，其只会延时数个时钟节拍，因此其具有降低时延的作用，另外，依据上述映射取数能够极大的提高地址利用率，提高运算速度，降低运算资源，提高用户体验度。
在一种可选的方案中，上述依据该stage以及该处理数据分解的因子个数 确定对应的地址映射；依据该地址映射确定stage取数地址具体包括：
依据该stage以及分解的因子个数确定快速傅里叶变换组值fftgroup_num、快速傅里叶变换索引值fftidx_num、fftidx_num以及log2_num；
若该stage为非最后一个stage，依据fftgroup_num、fftidx_num、fftidx_max、log2_num确定stage取数地址。
fftgroup_num具体可以为，fft组编号，该fftidx_num具体可以为，fft索引编号。各点数在各个stage取值如下：
4096点：
Stage 0，1，2，3
fftgroup_max 1，8，64，512
log2_num 12,9,6,3
fftidx_max 512,64,8,1
2048点：
Stage 0，1，2，3
fftgroup_max 1，8，64，256
log2_num 11,8,5,3
fftidx_max 256,32,4,1
1024点：
Stage 0，1，2，3
fftgroup_max 1，8，64，128
log2_num 10,7,4,3
fftidx_max 128,16,2,1
512点：
Stage 0，1，2
fftgroup_max 1，8，64
log2_num 9,6,3
fftidx_max 64,8,1
256点：
Stage 0，1，2
fftgroup_max 1，8，32
log2_num 8,5,3
fftidx_max 32,4,1
128点：
Stage 0，1，2
fftgroup_max 1，8，16
log2_num 7,4,3
fftidx_max 16,2,1
64点：
Stage 0，1
fftgroup_max 1，8
log2_num 6,3
fftidx_max 8,1
在一种可选的方案中，上述依据fftgroup_max、fftidx_num、fftidx_max、log2_num确定stage取数地址具体包括：
fft_addr0＝fftidx_num+fftgroup_base；
fft_addrx＝fft_addr(x-1)+fftidx_max*x；
其中，x的取值为【1,7】的整数；
fftgroup_base＝fftgroup_num<<log2_num
fft_addr0＝fftidx_num+fftgroup_base；
fft_addr1＝fft_addr0+fftidx_max；
fft_addr2＝fft_addr1+fftidx_max*2；
fft_addr3＝fft_addr2+fftidx_max*3；
fft_addr4＝fft_addr3+fftidx_max*4；
fft_addr5＝fft_addr4+fftidx_max*5；
fft_addr6＝fft_addr5+fftidx_max*6；
fft_addr7＝fft_addr6+fftidx_max*7；
旋转因子地址：twf_rom_addr＝fftidx_num；
其中，<<表示左移。
fftgroup_base＝fftgroup_num<<log2_num。
令计数器fftidx_num，fftgroup_num，在每一个stage开始时清零，
在每一个stage，计数器fftidx_num在每个时钟周期计算，在计数到fftidx_max-1时，fftgroup_num计数器加1，在fftidx_num，fftgroup_num，分别计数到fftidx_max-1，fftgroup_max-1时，该stage运算取数地址产生结束。
上述fft_addr0表示一次fft取值的第一个地址，addr表示地址，0表示取值的地址编号为0(起始值)。fft_addrx表示地址的编号，可以取【1,7】之间任意一个整数。
在一种可选的方案中，所述依据该stage以及该处理数据分解的因子个数确定对应的地址映射；依据该地址映射确定stage取数地址具体包括：
依据该stage以及分解的因子个数确定快速傅里叶变换组值fftgroup_num，若该stage为最后一个stage，依据该fftgroup_num的特定比特位以及分解的因子个数确定fft_addr0；依据fft_addr0确定后续fft_addrx，该x的取值为【1,7】的整数。
在一种可选的方案中，所述依据该fftgroup_num的特定比特位以及分解的因子个数确定fft_addr0；依据fft_addr0确定后续fft_addrx具体包括：
若分解的因子个数为：64、512、4096，
fft_addrx＝fft_addr0+x。
在一种可选的方案中，若分解的因子个数为64，则fft_addr0＝fftgroup_num[2:0]<<3；其中，fftgroup_num[2:0]表示选取fftgroup_num第0、1、2这3个比特位的值；<<表示左移，3表示移动的位数，即表示将fftgroup_num第0、1、2这3个比特位的值左移3个比特位。
若分解的因子个数为则512，fft_addr0＝fftgroup_num[3:1]<<6+fftgroup_num[6:4]<<3；其中，fftgroup_num[3:1]表示fftgroup_num第1、2、 3这3个比特位，fftgroup_num[6:4]表示fftgroup_num[6:4]的第4、5、6这3个比特位，<<表示左移，需要说明的是，这里先左移以后再执行加法运算。
若分解的因子个数为则4096，fft_addr0＝fftgroup_num[9:7]<<3+fftgroup_num[6:4]<<6+ftgroup_num[3:1]<<9。
其中，fftgroup_num[9:7]表示fftgroup_num第7、8、9这3个比特位，fftgroup_num[6:4]表示fftgroup_num[6:4]的第4、5、6这3个比特位，<<表示左移，fftgroup_num[3:1]表示fftgroup_num第1、2、3这3个比特位，需要说明的是，这里先左移以后再执行加法运算。
参阅图3，图3为本申请实施例中OFDM变换中FFT、IFFT的处理器的硬件结构示意图，如图4所示，图4为本申请实施例的OFDM变换中基8/4/2蝶形运算结构示意图，如图5所示，图5为本申请实施例的OFDM变换中一个4点或2个2点FFT硬件结构示意图。
可以理解的是，用户设备为了实现上述功能，其包含了执行各个功能相应的硬件和/或软件模块。结合本文中所公开的实施例描述的各示例的算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。本领域技术人员可以结合实施例对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本实施例可以根据上述方法示例对电子设备进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块可以采用硬件的形式实现。需要说明的是，本实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用对应各个功能划分各个功能模块的情况下，图6示出了一种用户设备的示意图，如图6所示，该UE 600可以包括：获取单元601和处理单元602。
其中，处理单元602可以用于支持用户设备执行上述步骤S202、步骤S203等，和/或用于本文所描述的技术的其他过程。
获取单元601可以用于支持用户设备执行上述步骤S201等，和/或用于本文所描述的技术的其他过程。
需要说明的是，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
本实施例提供的网络设备，用于执行上述如图2所示方法中的步骤S201，因此可以达到与上述实现方法相同的效果。
在采用集成的单元的情况下，用户设备可以包括处理模块、存储模块和通信模块。其中，处理模块可以用于对用户设备的动作进行控制管理，例如，可以用于支持电子设备执行上述获取单元601和处理单元602执行的步骤。存储模块可以用于支持电子设备执行存储程序代码和数据等。通信模块，可以用于支持电子设备与其他设备的通信。
其中，处理模块可以是处理器或控制器。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。处理器也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理(digital signal processing，DSP)和微处理器的组合等等。存储模块可以是存储器。通信模块具体可以为射频电路、蓝牙芯片、Wi-Fi芯片等与其他电子设备交互的设备。
可以理解的是，本申请实施例示意的各模块间的接口连接关系，只是示意性说明，并不构成对用户设备的结构限定。在本申请另一些实施例中，用户设备也可以采用上述实施例中不同的接口连接方式，或多种接口连接方式的组合。
请参见图7，图7是本申请实施例提供的一种电子设备70，该电子设备70包括处理器701、存储器702和通信接口703，所述处理器701、存储器702和通信接口703通过总线相互连接。
存储器702包括但不限于是随机存储记忆体(random access memory，RAM)、只读存储器(read-only memory，ROM)、可擦除可编程只读存储器(erasable programmable read only memory，EPROM)、或便携式只读存储器(compact disc read-only memory，CD-ROM)，该存储器702用于相关计算机程序及数据。通信接口703用于接收和发送数据。
处理器701可以是一个或多个中央处理器(central processing unit，CPU)，在处理器701是一个CPU的情况下，该CPU可以是单核CPU，也可以是多核 CPU。
处理器701可以包括一个或多个处理单元，例如：处理单元可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的部件，也可以集成在一个或多个处理器中。在一些实施例中，用户设备也可以包括一个或多个处理单元。其中，控制器可以根据指令操作码和时序信号，产生操作控制信号，完成取指令和执行指令的控制。在其他一些实施例中，处理单元中还可以设置存储器，用于存储指令和数据。示例性地，处理单元中的存储器可以为高速缓冲存储器。该存储器可以保存处理单元刚用过或循环使用的指令或数据。如果处理单元需要再次使用该指令或数据，可从所述存储器中直接调用。这样就避免了重复存取，减少了处理单元的等待时间，因而提高了用户设备处理数据或执行指令的效率。
在一些实施例中，处理器701可以包括一个或多个接口。接口可以包括集成电路间(inter-integrated circuit，I2C)接口、集成电路间音频(inter-integrated circuit sound，I2S)接口、脉冲编码调制(pulse code modulation，PCM)接口、通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口、移动产业处理器接口(mobile industry processor interface，MIPI)、用输入输出(general-purpose input/output，GPIO)接口、SIM卡接口和/或USB接口等。其中，USB接口是符合USB标准规范的接口，具体可以是Mini USB接口、Micro USB接口、USB Type C接口等。USB接口可以用于连接充电器为用户设备充电，也可以用于用户设备与外围设备之间传输数据。该USB接口也可以用于连接耳机，通过耳机播放音频。
若该电子设备70为终端侧设备，例如用户设备，该电子设备70中的处理器701用于读取所述存储器702中存储的计算机程序代码，执行以下操作：
获取5G系统中OFDM变换的数据，若该数据小于预设变换尺寸，对该数据执行补零处理得到处理数据，确定5G系统中OFDM变换的阶数stage；依据该stage以及该处理数据的分解的因子个数确定对应的地址映射；
依据该地址映射确定stage取数地址，对取数地址的数据执行运算得到输出运算结果，将输出运算结果写入带该取数地址，对输出运算结果进行部分连续序转换的加速处理得到OFDM变换结果。
其中，上述方法实施例涉及的各场景的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
若该电子设备70为网络侧设备，例如基站。
本申请实施例还提供一种芯片系统，所述芯片系统包括至少一个处理器，存储器和接口电路，所述存储器、所述收发器和所述至少一个处理器通过线路互联，所述至少一个存储器中存储有计算机程序；所述计算机程序被所述处理器执行时，图2所示的方法流程得以实现。
本申请实施例还提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序，当其在网络设备上运行时，图2所示的方法流程得以实现。
本申请实施例还提供一种计算机程序产品，当所述计算机程序产品在终端上运行时，图2所示的方法流程得以实现。
本申请实施例还提供一种终端，包括处理器、存储器、通信接口，以及一个或多个程序，所述一个或多个程序被存储在所述存储器中，并且被配置由所述处理器执行，所述程序包括用于执行图2所示实施例的方法中的步骤的指令。
上述主要从方法侧执行过程的角度对本申请实施例的方案进行了介绍。可以理解的是，电子设备为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模板。本领域技术人员应该很容易意识到，结合本文中所提供的实施例描述的各示例的单元及算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例可以根据上述方法示例对电子设备进行功能单元的划分，例如，可以对应各个功能划分各个功能单元，也可以将两个或两个以上的功能集 成在一个处理单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。需要说明的是，本申请实施例中对单元的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为依据本申请，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模板并不一定是本申请所必须的。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如上述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
上述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
上述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储器中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储器 中，包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本申请各个实施例上述方法的全部或部分步骤。而前述的存储器包括：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序可以存储于一计算机可读存储器中，存储器可以包括：闪存盘、只读存储器(英文：Read-Only Memory，简称：ROM)、随机存取器(英文：Random Access Memory，简称：RAM)、磁盘或光盘等。

Claims (18)

  1. 一种5G系统中OFDM变换方法，其特征在于，所述方法包括如下步骤：
    获取5G系统中OFDM变换的数据，确定5G系统中OFDM变换的阶数stage；依据该stage以及该数据的分解的因子个数确定对应的地址映射；
    在第一stage运算时，依据零值映射对第一stage运算未输入的数值补零处理后执行第一stage运算，在后续stage运算时，依据该地址映射确定stage取数地址，对取数地址的数据执行运算得到输出运算结果，将输出运算结果写入带该取数地址，对输出运算结果进行部分连续序转换的加速处理得到OFDM变换结果。
  2. 根据权利要求1所述的方法，其特征在于，所述依据该stage以及该处理数据分解的因子个数确定对应的地址映射；依据该地址映射确定stage取数地址具体包括：
    依据该stage以及分解的因子个数确定快速傅里叶变换组值fftgroup_num、快速傅里叶变换索引值fftidx_num、快速傅里叶变换索引最大值fftidx_max以及log2_num；
    若该stage为非最后一个stage，依据fftgroup_num、fftidx_num、fftidx_max、log2_num确定stage取数地址。
  3. 根据权利要求1所述的方法，其特征在于，依据fftgroup_max、fftidx_num、fftidx_max、log2_num确定stage取数地址具体包括：
    fft_addr0＝fftidx_num+fftgroup_base；
    fft_addrx＝fft_addr(x-1)+fftidx_max*x；
    其中，x的取值为【1,7】的整数；
    fftgroup_base＝fftgroup_num<<log2_num。
  4. 根据权利要求1所述的方法，其特征在于，所述依据该stage以及该处 理数据分解的因子个数确定对应的地址映射；依据该地址映射确定stage取数地址具体包括：
    依据该stage以及分解的因子个数确定快速傅里叶变换组值fftgroup_num，若该stage为最后一个stage，依据该fftgroup_num的特定比特位以及分解的因子个数确定fft_addr0；依据fft_addr0确定后续fft_addrx，该x的取值为【1,7】的整数。
  5. 根据权利要求4所述的方法，其特征在于，所述依据该fftgroup_num的特定比特位以及分解的因子个数确定fft_addr0；依据fft_addr0确定后续fft_addrx具体包括：
    若分解的因子个数为：64、512、4096，
    fft_addrx＝fft_addr0+x。
  6. 根据权利要求5所述的方法，其特征在于，
    若分解的因子个数为64，则fft_addr0＝fftgroup_num[2:0]<<3；
    若分解的因子个数为则512，fft_addr0＝fftgroup_num[3:1]<<6+fftgroup_num[6:4]<<3；
    若分解的因子个数为则4096，fft_addr0＝fftgroup_num[9:7]<<3+fftgroup_num[6:4]<<6+ftgroup_num[3:1]<<9。
  7. 一种用户设备UE，其特征在于，所述UE包括：
    获取单元，用于获取5G系统中OFDM变换的数据；
    处理单元，用于确定5G系统中OFDM变换的阶数stage；依据该stage以及该数据的分解的因子个数确定对应的地址映射；在第一stage运算时，依据零值映射对第一stage运算未输入的数值补零处理后执行第一stage运算，在后续stage运算时，依据该stage以及该处理数据的分解的因子个数确定对应的地址映射；依据该地址映射确定stage取数地址，对取数地址的数据执行运算得到输出运算结果，将输出运算结果写入带该取数地址，对输出运算结果进行部分连续序转换的加速处理得到OFDM变换结果。
  8. 根据权利要求7所述的用户设备，其特征在于，
    所述处理单元，具体用于依据该stage以及分解的因子个数确定快速傅里叶变换组值fftgroup_num、快速傅里叶变换索引值fftidx_num、快速傅里叶变换索引最大值fftidx_max以及log2_num；
    若该stage为非最后一个stage，依据fftgroup_num、fftidx_num、fftidx_max、log2_num确定stage取数地址。
  9. 根据权利要求7所述的用户设备，其特征在于，依据fftgroup_max、fftidx_num、fftidx_max、log2_num确定stage取数地址具体包括：
    fft_addr0＝fftidx_num+fftgroup_base；
    fft_addrx＝fft_addr(x-1)+fftidx_max*x；
    其中，x的取值为【1,7】的整数；
    fftgroup_base＝fftgroup_num<<log2_num。
  10. 根据权利要求7所述的用户设备，其特征在于，
    所述处理单元，具体用于依据该stage以及分解的因子个数确定快速傅里叶变换组值fftgroup_num，若该stage为最后一个stage，依据该fftgroup_num的特定比特位以及分解的因子个数确定fft_addr0；依据fft_addr0确定后续fft_addrx，该x的取值为【1,7】的整数。
  11. 根据权利要求10所述的用户设备，其特征在于，所述依据该fftgroup_num的特定比特位以及分解的因子个数确定fft_addr0；依据fft_addr0确定后续fft_addrx具体包括：
    若分解的因子个数为：64、512、4096，
    fft_addrx＝fft_addr0+x。
  12. 根据权利要求11所述的用户设备，其特征在于，
    若分解的因子个数为64，则fft_addr0＝fftgroup_num[2:0]<<3；
    若分解的因子个数为则512，fft_addr0＝fftgroup_num[3:1]<<6+ fftgroup_num[6:4]<<3；
    若分解的因子个数为则4096，fft_addr0＝fftgroup_num[9:7]<<3+fftgroup_num[6:4]<<6+ftgroup_num[3:1]<<9。
  13. 一种电子设备，包括处理器、存储器、通信接口，以及一个或多个程序，所述一个或多个程序被存储在所述存储器中，并且被配置由所述处理器执行，所述程序包括用于执行如权利要求1-6任意一项所述的方法的步骤的指令。
  14. 一种芯片系统，所述芯片系统包括至少一个处理器，存储器和接口电路，所述存储器、所述收发器和所述至少一个处理器通过线路互联，所述至少一个存储器中存储有计算机程序；所述计算机程序被所述处理器执行时实现如权利要求1-6任意一项所述的方法。
  15. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序，当其在用户设备上运行时，执行如权利要求1-6任意一项所述的方法。
  16. 一种网络设备，其特征在于，所述网络设备用于支持所述用户设备执行如权利要求1-6任意一项所述的方法。
  17. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序，当其在用户设备上运行时，执行如权利要求1-6任意一项所述的方法。
  18. 一种计算机程序产品，其特征在于，所述计算机程序产品包括存储了计算机程序的非瞬时性计算机可读存储介质，所述计算机程序可操作来使计算机执行如权利要求1-6任意一项所述的方法。
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CN112383497A (zh) * 2020-11-10 2021-02-19 展讯半导体(成都)有限公司 5g系统中ofdm变换方法及相关产品

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