WO2022100003A1

WO2022100003A1 - Multi-resolution output incremental optical encoder and chip and code disc

Info

Publication number: WO2022100003A1
Application number: PCT/CN2021/088580
Authority: WO
Inventors: 叶淼; 王英魁; 崔光日
Original assignee: 北京华大云感科技有限公司
Priority date: 2020-11-12
Filing date: 2021-04-21
Publication date: 2022-05-19
Also published as: CN112556733A

Abstract

Provided are a multi-resolution output incremental optical encoder and chip and code disc; by means of a composite optical sensing phase array (1) and a zero-position signal sensing array (2), and integrating multiple resolutions, the technical effect of user-selectable encoding resolution can be achieved using a defined chip.

Description

A multi-resolution output incremental photoelectric encoder and chip and code disc

technical field

The invention relates to a photoelectric encoder chip technology, in particular to a multi-resolution output incremental photoelectric encoder, a chip and a code disc. Through the composite light sensing phase array and the zero-position signal sensing array, multiple resolution resolutions can be integrated. The technical effect of user-selectable coding resolution can be achieved with a certain chip.

Background technique

At present, with the rapid development of automation in our country, the measurement requirements for linear displacement and angular displacement have spread to all fields of life and work, and the photoelectric encoder is the core product of linear displacement and angular displacement measurement. The photoelectric encoder converts the mechanical geometric displacement on the output shaft into pulse or digital quantity through photoelectric conversion, which is the most widely used sensor at present. The photoelectric encoder is composed of a light source, an optical code disc and a photosensitive element. The optical encoder is actually a disc engraved with regular light-transmitting and opaque lines. The light flux received by the photosensitive element changes synchronously with the light-transmitting lines. After the output waveform of the photosensitive element is shaped, it becomes a pulse signal. , output a group of pulses. According to the change of the pulse, the displacement of the equipment can be accurately measured and controlled. In actual production and life, according to different application requirements, there are many kinds of linear requirements for photoelectric encoders, from low-demand applications with 50 lines per turn to high-demand applications with 10,000 lines per turn, the overall resolution The demand span is huge. In order to meet the diverse needs, a variety of photoelectric encoders are required. Each photoelectric encoder corresponding to the requirements includes a photoelectric encoder chip that meets the requirements and a code disc corresponding to the linear requirements of the photoelectric encoder chip, which virtually increases the manufacturing cost and the difficulty of structural design. Limited efficient product production and testing. This is a very troublesome thing for photoelectric encoder manufacturers and photoelectric encoder application manufacturers. The inventors of the present invention believe that by reducing the restriction of production due to diverse demands in the production process and the complexity of the design structure, the core technology of the production plant can be formed and the core competitiveness of the product can be improved. In view of this, the present inventors have completed the present invention.

SUMMARY OF THE INVENTION

Aiming at the defects or deficiencies existing in the prior art, the present invention provides a multi-resolution output incremental photoelectric encoder, a chip and a code disc. Through the composite optical sensing phase array and the zero-position signal sensing array, various Resolution resolution, a certain chip can achieve the technical effect of user-selectable coding resolution.

The technical solution of the present invention is as follows:

A multi-resolution output incremental photoelectric encoder, characterized in that it includes a photoelectric encoder chip and an optical signal modulation code disc adapted to it, and the photoelectric encoder chip includes a composite light sensing phase array and a zero signal Sensing array, the composite light sensing phase array is connected to the frequency multiplication and frequency division processing module through the first transimpedance amplifier and the hysteresis comparator combination module, and the zero signal sensing array passes through the second transimpedance amplifier and the return hysteresis. The hysteresis comparator combination module is connected to the logic processing and selection module, and the logic processing and selection module is respectively connected to the frequency multiplication and frequency division processing module and the signal output end, and a number of grating tracks are arranged on the optical signal modulation code disc to The composite light sensing phased array is adapted.

The composite optical sensing phase array includes a first resolution photodiode array and a second resolution photodiode array, the optical signal modulation code disc is provided with a first grating track and its first zero-position signal track, and a first grating track and a first zero-position signal track. Two grating tracks and their second zero signal tracks, the zero signal sensing array includes a first grating track zero signal sensor and a second grating track zero signal sensor.

The composite optical sensing phase array includes a third resolution photodiode array, the optical signal modulation code disc is provided with a third grating track and a third zero-position signal track, and the zero-position signal sensing array includes a third grating track and a third zero-position signal track. Three grating track zero signal sensor.

The optical signal modulation code disc has a disc structure, and the transmittance lines of the grating region on each grating track are evenly distributed along the circumference, and the number of transmittance lines in the grating region is the intrinsic resolution line number of the grating track to which it belongs, The intrinsic resolution line number enables the corresponding resolution photodiode array to generate intrinsic signals transmitted to the first transimpedance amplifier and the hysteresis comparator combination module, the intrinsic signals can be used in the frequency doubling and division. Frequency multiplication or frequency division is performed in the frequency processing module.

The frequency multiplication and frequency division processing module can perform signal processing of 1/2, 1/4, ×2, and ×4 on the intrinsic signal to form a multi-resolution optional encoding resolution specification.

A first grating track, a second grating track, a third grating track, a third zero-position signal track, a second zero-position signal track and a first zero-position signal track are sequentially distributed on the optical signal modulation code disc from outside to inside.

The number of transmission lines in the grating region on the first grating track < the number of transmission lines in the grating region on the second grating track < the number of transmission lines in the grating region on the third grating track.

A multi-resolution output incremental photoelectric encoder chip is characterized in that it includes a composite light sensing phase array and a zero-position signal sensing array, and the composite light sensing phase array is compared by a first transimpedance amplifier and a hysteresis. The sensor combination module is connected to the frequency multiplication and frequency division processing module, the zero-position signal sensing array is connected to the logic processing and selection module through the second transimpedance amplifier and the hysteresis comparator combination module, and the logic processing and selection modules are respectively connected to the The frequency multiplication and frequency division processing module and signal output terminal are described.

The composite light sensing phase array includes a first resolution photodiode array, a second resolution photodiode array, and a third resolution photodiode array, and the null signal sensing array includes a first grating track null signal sensor, the second grating track zero signal sensor, and the third grating track zero signal sensor.

An optical signal modulation code disc, characterized in that it comprises a first grating track and its first zero position signal track, a second grating track and its second zero position signal track, and a third grating track and its third zero position Signal track, the optical signal modulation code disc is a disc structure, the light transmission lines in the grating area on each grating track are evenly distributed along the circumference, and the number of light transmission lines in the grating area is the intrinsic resolution of the grating track to which it belongs number of lines.

The technical effects of the present invention are as follows: the present invention is a multi-resolution output incremental photoelectric encoder, chip and code disc, based on a composite optical sensing phase array structure, which integrates as many as ten kinds on a single chip. For the application requirements of the commonly used circular linear resolution, the phase light sensing array of the chip is 2 to 3 independent phase array track windows. Through the chip selection input terminal, the binary digital coding signal is used to select the required output code for each circular rotation. The number of digital pulses can achieve user-selectable coding resolution when a certain chip is reached.

The present invention has the following characteristics: 1. The present invention adopts a composite phase array structure, which integrates the application requirements of more than ten kinds of commonly used circular linear resolutions, and solves the cost of manufacturing due to the wide variety in chip application design. And the difficulty of structural design, which greatly improves the efficiency of product production and testing. 2. The digital logic selection method adopted in the present invention simplifies the cumbersome design structure in the application process, and each group of selected signals of resolution requirements uniquely corresponds to a group of logic outputs, which facilitates the structural design and detection scheme design of the photoelectric encoder. 3. The signal differential frequency multiplication and clock frequency division processing method of the present invention, at this time, according to the preset design state (set resolution requirement), the signal processing circuit selects the corresponding processing, including the preset frequency multiplication processing, and Preset crossover processing. At the same time, it is ensured that the frequency-multiplied or frequency-divided signals are still output in a state of quadrature. 4. In the Z signal processing method adopted in the present invention, the zero position signal corresponding to the output signal has an independent optical signal sensing channel, and according to the preset output signal state characteristics, the correct zero position signal information is selected and output through digital logic.

Description of drawings

FIG. 1 is a schematic structural diagram of a chip circuit implementing a multi-resolution output incremental photoelectric encoder of the present invention.

FIG. 2 is a schematic structural diagram of an optical signal modulation code disc adapted to the chip circuit of FIG. 1 . Fig. 2 is a partial enlarged schematic view of the circular code disc.

The reference numerals are listed as follows: 1-composite light sensing phase array; 2-zero signal sensing array; 3-transimpedance amplifier and hysteresis comparator combination module (hysteresis comparator is also called hysteresis comparator or hysteresis comparator). Mitt trigger Schmidt trigger or hysteresis comparator, transimpedance amplifier TIA, trans-impedance amplifier, converts low-level photodiode current signal into voltage signal); 4-frequency and frequency division processing module (for example, 100Hz times frequency to 200Hz or frequency multiplication to 400Hz or frequency division to 50Hz or frequency division to 25Hz); 5-logic processing and selection module; 6-signal output terminal; 11-first resolution photodiode array; 12-second resolution Photodiode array; 13-third resolution photodiode array; 21-first grating track zero position signal sensor; 22-second grating track zero position signal sensor; 23-third grating track zero position signal sensor; 111-th A grating track (the first grating area); 121 - the second grating track (the second grating area); 131 - the third grating track (the third grating area); 211 - the first zero signal track; 221 - the second zero Bit signal track; 231-third zero signal track; M-first resolution; N-second resolution; P-third resolution; Z-zero signal; M-Z-first zero signal; N-Z- The second zero signal; P-Z-the third zero signal.

Detailed ways

The present invention will be described below with reference to the accompanying drawings (FIG. 1-FIG. 2).

FIG. 1 is a schematic structural diagram of a chip circuit implementing a multi-resolution output incremental photoelectric encoder of the present invention. FIG. 2 is a schematic structural diagram of an optical signal modulation code disc adapted to the chip circuit of FIG. 1 . Fig. 2 is a partial enlarged schematic view of the circular code disc. Referring to Figures 1 to 2, a multi-resolution output incremental photoelectric encoder includes a photoelectric encoder chip and an optical signal modulation code disc adapted to it. The photoelectric encoder chip includes a composite optical sensing phase Array 1 and zero signal sensing array 2, the composite light sensing phase array 1 passes through the first transimpedance amplifier and the hysteresis comparator combined module 3 (the upper middle of FIG. 1, the upper one is the transimpedance amplifier, the lower one is The hysteresis comparator) is connected to the frequency multiplication and frequency division processing module 4, and the zero-position signal sensing array 2 passes through the second transimpedance amplifier and the hysteresis comparator combination module 3 (the middle of the lower part of FIG. 1, and the transimpedance amplifier at the top , the lower is the hysteresis comparator) is connected to the logic processing and selection module 5 (also known as the logic control and selection processing module), and the logic processing and selection module 5 is respectively connected to the frequency multiplication and frequency division processing module 4 and signal output At the end 6 , several grating tracks are arranged on the optical signal modulation code disc to adapt to the composite optical sensing phase array 1 . The composite optical sensing phase array 1 includes a first resolution photodiode array 11 and a second resolution photodiode array 12, and the optical signal modulation code disc is provided with a first grating track 111 and its first zero position signal The track 211 , and the second grating track 121 and its second zero signal track 221 , the zero signal sensing array 2 includes a first grating track zero signal sensor 21 and a second grating track zero signal sensor 22 . The composite optical sensing phase array 1 includes a third resolution photodiode array 13, and a third grating track 131 and a third zero-position signal track 231 are arranged on the optical signal modulation code disc. The sense array 2 includes a third grating track zero signal sensor 23 .

The optical signal modulation code disc has a disc structure, and the transmittance lines of the grating region on each grating track are evenly distributed along the circumference, and the number of transmittance lines in the grating region is the intrinsic resolution line number of the grating track to which it belongs, The intrinsic resolution line number enables the corresponding resolution photodiode array to generate an intrinsic signal transmitted to the first transimpedance amplifier and the hysteresis comparator combination module 3, and the intrinsic signal can be used in the frequency doubling and Frequency multiplication or frequency division is performed in the frequency division processing module 4 . The frequency multiplication and frequency division processing module 4 can perform signal processing of 1/2, 1/4, ×2, and ×4 on the intrinsic signal to form a multi-resolution optional encoding resolution specification. The first grating track 111 , the second grating track 121 , the third grating track 131 , the third zero-position signal track 231 , the second zero-position signal track 221 and the first grating track 111 , the second grating track 121 , the third grating track 131 , the third zero-position signal track 231 , the second Zero signal track 211 . The number of transmitted lines in the grating area on the first grating track 111 < the number of transmitted lines in the grating area on the second grating track 121 < the number of transmitted lines in the grating area on the third grating track 131 .

A multi-resolution output incremental photoelectric encoder chip, comprising a composite light-sensing phase array 1 and a zero-position signal sensing array 2, the composite light-sensing phase array 1 passing through a first transimpedance amplifier and a hysteresis comparator The combination module 3 is connected to the frequency multiplication and frequency division processing module 4, and the zero-position signal sensing array 2 is connected to the logic processing and selection module 5 through the second transimpedance amplifier and the hysteresis comparator combination module 3. The logic processing and selection The module 5 is respectively connected to the frequency multiplication and frequency division processing module 4 and the signal output terminal 6 . The composite light sensing phase array 1 includes a first resolution photodiode array 11 (its resolution is M), a second resolution photodiode array (its resolution is N), and a third resolution photodiode array ( Its resolution is P), and the zero position signal sensor array includes a first grating track zero position signal sensor 21 (M-Z, zero position signal Z of resolution M), a second grating track zero position signal sensor (N-Z, resolution The zero position signal Z of the rate N), and the third grating track zero position signal sensor (P-Z, the zero position signal Z of the resolution P).

An optical signal modulation code wheel, comprising a first grating track 111 and its first zero position signal track 211, a second grating track 121 and its second zero position signal track 221, and a third grating track 131 and its third zero position signal track 221 Bit signal track 231, the optical signal modulation code disc is a disc structure, the grating area transmittance lines on each grating track are evenly distributed along the circumference, and the number of transmittance lines in the grating area is the intrinsic property of the grating track to which it belongs Resolution lines.

Aiming at the single defect existing in the existing products, the present invention provides a composite phase array structure with 2 to 3 independent phase array track windows, which can be matched with the optical encoder chip of the same photoelectric encoder chip. A solution that meets most resolution requirements. On the one hand, this solution increases the production and testing costs required by photoelectric encoder manufacturers to meet various resolution requirements. On the other hand, it reduces the design of photoelectric encoder application manufacturers. Difficulty and Test Difficulty. It solves the difficulty of cooperation that manufacturers need to invest in the face of a variety of resolution requirements. The invention also provides a way of digitally selecting the working state. Through the chip selection input terminal, the number of coded digital pulses that can be output per circular rotation is selected by binary digital coding. The setup and operation are simple, and it can more flexibly meet the needs of different resolution products. The invention also provides a flexible signal processing method, which integrates the digital processing of frequency multiplication and frequency division, performs 1/2, 1/4, ×2, ×4 signal processing on the intrinsic signal, and cooperates with the corresponding differential amplifier. , users can choose from the many resolution specifications of the chip to suit their own application conditions. The invention also provides a method for judging the zero position signal. In order to solve the independence and correlation of the zero signal. In one case, three groups of independent phase arrays correspond to three groups of independent zero-position signals, the channels do not interfere with each other, and the required precision output content is selected through the input selection port.

An incremental photoelectric encoder chip design scheme with multiple resolutions and programmable output. The chip design is based on a composite light sensing phase array structure, which integrates as many as ten kinds of commonly used circular linear resolution application requirements on a single chip. The phase light sensing array of the chip is 2 to 3 independent The phase array track window, through the chip selection input terminal, uses the binary digital encoded signal to select the required number of encoded digital pulses that can be output per circular rotation. Achieving a certain chip enables user-selectable encoding resolution. It is characterized in that the sensor part includes 2 to 3 groups of independent phase array signal sensing units and 2 to 3 groups of independent zero signal sensing units; the signal processing part includes a current sense amplifier circuit and a comparator circuit, a signal Differential frequency multiplication and clock frequency division processing circuit, signal output logic relationship selection circuit, internal testing and debugging circuit. The feature is that the encoder chip and the code wheel are used one-to-one, and the layout of the signal amplifier makes the paired channel matching very good, thus eliminating the need for signal calibration.

After receiving the optical signal modulated by the corresponding circular code disc, the composite phase array sensing unit converts it into a voltage signal through an internal cross-group amplifier unit, and the voltage signal generates a digital signal through a precision voltage comparator with a difference. At the same time, the digital signal outputs the application signals A, B and Z of the photoelectric encoder through the differential push-pull driver. Among them, the A and B signals are the output signals of the phase array sensor, and Z is the corresponding output zero signal. The said signal passes through the differential frequency multiplication and clock frequency division processing circuit, and then passes through the output logic relationship selection circuit, and then selects and outputs the corresponding resolution signal output and the corresponding zero position signal output through digital logic.

After the composite phase array sensing unit receives the optical signal modulated by the optical code disc, the obtained signal is the intrinsic signal. The intrinsic signal is a set of orthogonal A and B signals. According to the state of the signal AB, the photoelectricity can be judged. The working state of the encoder, at this time, according to the preset design state (set resolution requirement), the signal processing circuit selects corresponding processing, including preset frequency multiplication processing and preset frequency division processing. At the same time, it is ensured that the frequency-multiplied or frequency-divided signals are still output in a state of quadrature.

The composite phase array consists of 2 to 3 sensing units, each group of sensing units corresponds to a set of unique eigensignals and their corresponding processed signals (frequency multiplied and frequency-divided processed signals) and a set of The zero signal corresponding to the output signal. And the characteristics of the null signal satisfy the logical relationship of the phase and pulse width corresponding to the output signal. The zero signal corresponding to the output signal has an independent optical signal sensing channel. According to the preset output signal state characteristics, the correct zero signal information is selected and output through digital logic.

The composite phase array consists of 2 to 3 sensing units, and the special detection part of the zero signal corresponding to the corresponding sensing unit is in the same detection channel. According to the different resolutions of the composite phase array, the corresponding zero position relationship phase and pulse width are also different. According to the preset output signal state characteristics, the corresponding zero position signal is identified by the signal characteristics.

The features of the present invention include: 1. The encoder chip is designed based on a composite optical sensing phase array structure, which integrates as many as ten kinds of commonly used circular linear resolution application requirements on a single chip. The phase of the chip The optical sensing array is 2 to 3 independent phased array track windows. Through the chip selection input terminal, the required number of coded digital pulses that can be output per circular rotation is selected with a binary digital coded signal. Achieving a defined chip enables user-selectable encoding resolution. Configure two sets of input selection ports to select different raster areas and interpolation magnifications. 3 different grating areas can be selected; 5 different resolution magnifications can be selected for each grating area, which can be combined into 15 resolution line schemes. 2. The encoder chip integrates the digital processing of frequency multiplication and frequency division, and performs 1/2, 1/4, ×2, ×4 signal processing on the intrinsic signal. With the corresponding differential amplifier, users can Choose from the resolution specifications to suit your application conditions. 3. The encoder chip and the code disc are used one-to-one, and the layout of the signal amplifier makes the paired channel matching excellent, thus eliminating the need for signal calibration. 4. The independence and correlation of the zero position signal of the photoelectric encoder. Three groups of independent phase arrays correspond to three groups of independent zero-position signals, and the channels do not interfere with each other. The required output content of the zero-position signal is selected through the input selection port, including phase information and signal width information. 5. The zero signal can be not only on the three code channels, but also on the same code channel. The three groups of zero signal characteristics correspond to the corresponding main code channels respectively. The sensor element area and phase relationship of the three groups of zero signals are different. Signal feature selection can identify the zero signal corresponding to the code channel, which is characterized by accurate signal feature selection.

Contents that are not described in detail in the specification of the present invention belong to the prior art known to those skilled in the art. It is indicated here that the above description is helpful for those skilled in the art to understand the present invention, but does not limit the protection scope of the present invention. Any equivalent replacement, modification and improvement and/or implementation of simplifying and simplifying the above description without departing from the essential content of the present invention shall fall within the protection scope of the present invention.

Claims

A multi-resolution output incremental photoelectric encoder, characterized in that it includes a photoelectric encoder chip and an optical signal modulation code disc adapted to it, and the photoelectric encoder chip includes a composite light sensing phase array and a zero signal Sensing array, the composite light sensing phase array is connected to the frequency multiplication and frequency division processing module through the first transimpedance amplifier and the hysteresis comparator combination module, and the zero signal sensing array passes through the second transimpedance amplifier and the return hysteresis. The hysteresis comparator combination module is connected to the logic processing and selection module, and the logic processing and selection module is respectively connected to the frequency multiplication and frequency division processing module and the signal output end, and a number of grating tracks are arranged on the optical signal modulation code disc to The composite light sensing phased array is adapted.
The multi-resolution output incremental photoelectric encoder according to claim 1, wherein the composite light sensing phase array comprises a first resolution photodiode array and a second resolution photodiode array, and the optical signal The modulation code disc is provided with a first grating track and its first zero position signal track, and a second grating track and its second zero position signal track, and the zero position signal sensing array includes a first grating track zero position signal sensor and the second grating track zero signal sensor.
The multi-resolution output incremental photoelectric encoder according to claim 2, wherein the composite optical sensing phase array comprises a third resolution photodiode array, and the optical signal modulation code disc is provided with a third A grating track and its third zero position signal track, the zero position signal sensing array includes a third grating track zero position signal sensor.
The multi-resolution output incremental photoelectric encoder according to claim 1, wherein the optical signal modulation code disc is a disc structure, and the light transmission lines of the grating area on each grating track are evenly distributed along the circumference, so The number of transmitted lines in the grating region is the intrinsic resolution line number of the grating track to which it belongs, and the intrinsic resolution line number enables the corresponding resolution photodiode array to generate and transmit to the first transimpedance amplifier and compare with the hysteresis The eigensignal of the frequency multiplication and frequency division processing module can be multiplied or divided in the frequency multiplication and frequency division processing module.
The multi-resolution output incremental photoelectric encoder according to claim 4, wherein the frequency multiplication and frequency division processing module can perform 1/2, 1/4, ×2, × 4 signal processing to form a multi-resolution selectable encoding resolution specification.
The multi-resolution output incremental photoelectric encoder according to claim 1, wherein a first grating track, a second grating track, a third grating track, a second grating track, a third grating track, a A third null signal track, a second null signal track, and a first null signal track.
The multi-resolution output incremental photoelectric encoder according to claim 6, wherein the number of light transmission lines in the grating region on the first grating track < the light transmission lines in the grating region on the second grating track The number of <the number of light transmission lines in the grating region on the third grating track.
A multi-resolution output incremental photoelectric encoder chip is characterized in that it includes a composite light sensing phase array and a zero-position signal sensing array, and the composite light sensing phase array is compared by a first transimpedance amplifier and a hysteresis. The sensor combination module is connected to the frequency multiplication and frequency division processing module, the zero-position signal sensing array is connected to the logic processing and selection module through the second transimpedance amplifier and the hysteresis comparator combination module, and the logic processing and selection modules are respectively connected to the The frequency multiplication and frequency division processing module and signal output terminal are described.
The multi-resolution output incremental photoelectric encoder chip according to claim 8, wherein the composite light sensing phase array comprises a first resolution photodiode array, a second resolution photodiode array, and a third resolution photodiode array. A resolution photodiode array, the zero signal sensing array includes a first grating track zero signal sensor, a second grating track zero signal sensor, and a third grating track zero signal sensor.
An optical signal modulation code disc, characterized in that it comprises a first grating track and its first zero position signal track, a second grating track and its second zero position signal track, and a third grating track and its third zero position Signal track, the optical signal modulation code disc is a disc structure, the light transmission lines in the grating area on each grating track are evenly distributed along the circumference, and the number of light transmission lines in the grating area is the intrinsic resolution of the grating track to which it belongs number of lines.