CN214470936U - Multi-resolution output increment photoelectric encoder, chip and code disc - Google Patents

Abstract

A multi-resolution output increment photoelectric encoder, a chip and a code disc can integrate various resolution resolutions through a composite light sensing phase array and a zero signal sensing array, and achieve the technical effect that one determined chip can realize the encoding resolution selectable by a user.

Description

Multi-resolution output increment photoelectric encoder, chip and code disc

Technical Field

The invention relates to a photoelectric encoder chip technology, in particular to a multi-resolution output increment photoelectric encoder, a chip and a code disc.

Background

At present, with the rapid development of the degree of automation in China, the measurement requirements for linear displacement and angular displacement are distributed in various fields in life and work, and a photoelectric encoder is a core product for measuring linear displacement and angular displacement. The photoelectric encoder converts the mechanical geometric displacement on the output shaft into pulse or digital quantity by photoelectric conversion, which is the most applied sensor at present. The photoelectric encoder consists of a light source, a light code disc and a photosensitive element. The optical code disc is a disc with regular light-transmitting and light-proof lines, the light flux received by the photosensitive element changes synchronously with the light-transmitting lines, the output waveform of the photosensitive element is shaped and then changed into a pulse signal, and a group of pulses are output every turn. According to the change of the pulse, the displacement of the equipment can be accurately measured and controlled. In actual production life, aiming at different application requirements, the linear requirements of the photoelectric encoder are various, the low-requirement application scene with 1 turn of 50 lines is applied to the high-requirement application scene with 1 ten thousand lines, and the whole resolution requirement span is very large. In order to meet the requirements of various varieties, various photoelectric encoders need to be equipped. Each photoelectric encoder corresponding to the requirements comprises a photoelectric encoder chip meeting the requirements and a code disc corresponding to the linear requirements of the photoelectric encoder chip, so that the production and manufacturing cost and the structural design difficulty are increased invisibly, and the production and detection of high-efficiency products are greatly limited. This is a very troublesome problem for both the manufacturers of the photoelectric encoders and the manufacturers of the applications of the photoelectric encoders. The inventor believes that the core technology of a production plant can be formed and the core competitiveness of products can be improved by reducing the production limit caused by diversified requirements in the production process and reducing the complexity of design structures. In view of the above, the present inventors have completed the present invention.

Disclosure of Invention

Aiming at the defects or shortcomings in the prior art, the invention provides the multi-resolution output increment photoelectric encoder, the chip and the code disc, and the resolution of various resolutions can be integrated through the composite light sensing phase array and the zero signal sensing array, so that the technical effect that one determined chip can realize the encoding resolution which can be selected by a user is achieved.

The technical solution of the invention is as follows:

the multi-resolution output increment photoelectric encoder is characterized by comprising a photoelectric encoder chip and a light signal modulation coded disc matched with the photoelectric encoder chip, wherein the photoelectric encoder chip comprises a composite light sensing phase array and a zero position signal sensing array, the composite light sensing phase array is connected with a frequency multiplication and frequency division processing module through a first transimpedance amplifier and a hysteresis comparator combined module, the zero position signal sensing array is connected with a logic processing and selecting module through a second transimpedance amplifier and the hysteresis comparator combined module, the logic processing and selecting module is respectively connected with the frequency multiplication and frequency division processing module and a signal output end, and a plurality of grating tracks are arranged on the light signal modulation coded disc to be matched with the composite light sensing phase array.

The composite light sensing phase array comprises a first-resolution photodiode array and a second-resolution photodiode array, a first grating track and a first zero signal track thereof, and a second grating track and a second zero signal track thereof are arranged on the optical signal modulation code disc, and the zero signal sensing array comprises a first grating track zero signal sensor and a second grating track zero signal sensor.

The composite light sensing phase array comprises a third-resolution photodiode array, a third grating track and a third zero-position signal track are arranged on the optical signal modulation code disc, and the zero-position signal sensing array comprises a third grating track zero-position signal sensor.

The optical signal modulation code disc is of a disc structure, grating area light transmission lines on each grating track are uniformly distributed along the circumference, the number of the grating area light transmission lines is the number of intrinsic resolution lines of the grating track to which the grating area light transmission lines belong, the intrinsic resolution lines enable the resolution photodiode array corresponding to the grating area light transmission lines to generate intrinsic signals which are transmitted to the first transimpedance amplifier and the hysteresis comparator combination module, and the intrinsic signals can be subjected to frequency multiplication or frequency division in the frequency multiplication and frequency division processing module.

The frequency multiplication and division processing module is capable of performing 1/2, 1/4, × 2, × 4 signal processing on the intrinsic signals to form a multiple resolution selectable coding resolution specification.

A first grating track, a second grating track, a third zero-position signal track, a second zero-position signal track and a first zero-position signal track are sequentially distributed on the optical signal modulation code disc from outside to inside.

The number of the grating area light transmission rays on the first grating track is less than that of the grating area light transmission rays on the second grating track and less than that of the grating area light transmission rays on the third grating track.

The multi-resolution output increment photoelectric encoder chip is characterized by comprising a composite light sensing phase array and a zero position signal sensing array, wherein the composite light sensing phase array is connected with a frequency multiplication and frequency division processing module through a first transimpedance amplifier and a hysteresis comparator combined module, the zero position signal sensing array is connected with a logic processing and selecting module through a second transimpedance amplifier and the hysteresis comparator combined module, and the logic processing and selecting module is respectively connected with the frequency multiplication and frequency division processing module and a signal output end.

The composite light sensing phased array comprises a first resolution photodiode array, a second resolution photodiode array and a third resolution photodiode array, and the zero signal sensing array comprises a first grating track zero signal sensor, a second grating track zero signal sensor and a third grating track zero signal sensor.

An optical signal modulation code disc is characterized by comprising a first grating track and a first zero-position signal track thereof, a second grating track and a second zero-position signal track thereof, and a third grating track and a third zero-position signal track thereof, wherein the optical signal modulation code disc is of a disc structure, grating area light transmission rays on each grating track are uniformly distributed along the circumference, and the number of the grating area light transmission rays is the intrinsic resolution linear number of the grating track to which the grating area light transmission rays belong.

The invention has the following technical effects: the invention relates to a multi-resolution output increment photoelectric encoder, a chip and a coded disc, which are based on a composite light sensing phase array structure, the structure integrates application requirements of more than ten kinds of commonly used circumferential linear resolution on a single chip, the phase light sensing array of the chip is 2-3 independent phase array track windows, the number of encoding digital pulses which can be output per circumferential rotation and are required by binary digital encoding signals is selected by a chip selection input end, and the purpose that one determined chip can realize the selectable encoding resolution of a user is achieved.

The invention has the following characteristics: 1. the invention adopts a composite phase array structure, integrates more than ten common application requirements of circumferential linear resolution, solves the problems of production and manufacturing cost and structural design difficulty which are increased due to various types in chip application design, and greatly improves the production and detection efficiency of products. 2. The digital logic selection mode adopted by the invention simplifies the complicated design structure in the application process, and the signal of each selected resolution requirement uniquely corresponds to one group of logic output, thereby facilitating the structure design and the detection scheme design of the photoelectric encoder. 3. According to the signal differential frequency multiplication and clock frequency division processing mode, corresponding processing including preset frequency multiplication processing and preset frequency division processing is selected by the signal processing circuit according to a preset design state (a set resolution requirement). And simultaneously, the frequency multiplication or frequency division signals are ensured to still keep the orthogonal state output. 4. According to the Z signal processing mode adopted by the invention, the zero position signal corresponding to the output signal has an independent optical signal sensing channel, and correct zero position signal information is selected and output through digital logic according to the preset output signal state characteristic.

Drawings

Fig. 1 is a schematic diagram of a chip circuit structure of a multi-resolution output incremental photoelectric encoder according to the present invention.

FIG. 2 is a schematic diagram of an optical signal modulating code wheel adapted to the chip circuit of FIG. 1.

The reference numbers are listed below: 1-composite photo-sensing phase array; 2-a zero signal sensing array; a 3-transimpedance amplifier and hysteresis comparator combined module (a hysteresis comparator is also called a hysteresis comparator or Schmidt trigger or a hysteresis comparator, a transimpedance amplifier TIA, a trans-impedance amplifier converts a low-level photodiode current signal into a voltage signal); 4-frequency and frequency doubling processing module (e.g., frequency doubling to 200Hz or frequency doubling to 400Hz or frequency dividing to 50Hz or frequency dividing to 25 Hz); 5-logic processing and selecting module; 6-a signal output terminal; 11-a first resolution photodiode array; 12-a second resolution photodiode array; 13-a third resolution photodiode array; 21-a first grating track zero signal sensor; 22-a second grating track null signal sensor; 23-a third grating track zero signal sensor; 111-a first grating track (first grating zone); 121-a second grating track (second grating zone); 131-a third grating track (third grating zone); 211-first zero signal track; 221-second zero signal track; 231-third zero signal track; m-a first resolution; n-a second resolution; p-third resolution; a Z-null signal; M-Z-first zero signal; N-Z-second zero signal; P-Z-third zero signal.

Detailed Description

The invention is described below with reference to the accompanying drawings (fig. 1-2).

Fig. 1 is a schematic diagram of a chip circuit structure of a multi-resolution output incremental photoelectric encoder according to the present invention. FIG. 2 is a schematic diagram of an optical signal modulating code wheel adapted to the chip circuit of FIG. 1. Referring to fig. 1 to 2, a multi-resolution output incremental photoelectric encoder includes a photoelectric encoder chip and an optical signal modulation code disc adapted to the photoelectric encoder chip, where the photoelectric encoder chip includes a composite photo-sensing phased array 1 and a null signal sensing array 2, the composite photo-sensing phased array 1 is connected to a frequency multiplication and division processing module 4 through a first transimpedance amplifier and hysteresis comparator combination module 3 (in the middle of the upper part of fig. 1, a transimpedance amplifier is located above, and a hysteresis comparator is located below), the null signal sensing array 2 is connected to a logic processing and selection module 5 (also called a logic control and selection processing module) through a second transimpedance amplifier and hysteresis comparator combination module 3 (in the middle of the lower part of fig. 1, a transimpedance amplifier is located above, and a hysteresis comparator is located below), the logic processing and selection module 5 is connected to the frequency multiplication and division processing module 4 and a signal output terminal 6 respectively, and a plurality of grating tracks are arranged on the optical signal modulation code disc to be matched with the composite photo-sensing phase array 1. The composite light sensing phased array 1 comprises a first-resolution photodiode array 11 and a second-resolution photodiode array 12, a first grating track 111 and a first zero signal track 211 thereof, a second grating track 121 and a second zero signal track 221 thereof are arranged on an optical signal modulation code disc, and the zero signal sensing array 2 comprises a first grating track zero signal sensor 21 and a second grating track zero signal sensor 22. The composite light sensing phase array 1 comprises a third-resolution photodiode array 13, a third grating track 131 and a third zero signal track 231 thereof are arranged on the optical signal modulation code disc, and the zero signal sensing array 2 comprises a third grating track zero signal sensor 23.

The optical signal modulation code disc is of a disc structure, grating area light transmission lines on each grating track are uniformly distributed along the circumference, the number of the grating area light transmission lines is the number of intrinsic resolution lines of the grating track to which the grating area light transmission lines belong, the intrinsic resolution lines enable the resolution photodiode array corresponding to the grating area light transmission lines to generate intrinsic signals which are transmitted to the first transimpedance amplifier and hysteresis comparator combination module 3, and the intrinsic signals can be subjected to frequency multiplication or frequency division in the frequency multiplication and frequency division processing module 4. The frequency multiplication and division processing module 4 is capable of performing 1/2, 1/4, × 2, × 4 signal processing on the intrinsic signals to form a multiple resolution selectable coding resolution specification. The optical signal modulation code disc is sequentially distributed with a first grating track 111, a second grating track 121, a third grating track 131, a third zero signal track 231, a second zero signal track 221 and a first zero signal track 211 from outside to inside. The number of the grating area light transmission lines on the first grating track 111 is less than the number of the grating area light transmission lines on the second grating track 121 is less than the number of the grating area light transmission lines on the third grating track 131.

A multi-resolution output increment photoelectric encoder chip comprises a composite light sensing phase array 1 and a zero position signal sensing array 2, wherein the composite light sensing phase array 1 is connected with a frequency multiplication and frequency division processing module 4 through a first transimpedance amplifier and hysteresis comparator combined module 3, the zero position signal sensing array 2 is connected with a logic processing and selecting module 5 through a second transimpedance amplifier and hysteresis comparator combined module 3, and the logic processing and selecting module 5 is respectively connected with the frequency multiplication and frequency division processing module 4 and a signal output end 6. The composite photo-sensing phased array 1 includes a first resolution photodiode array 11 (resolution M), a second resolution photodiode array (resolution N), and a third resolution photodiode array (resolution P), and the null signal sensing array includes a first grating track null signal sensor 21 (M-Z, null signal Z of resolution M), a second grating track null signal sensor (N-Z, null signal Z of resolution N), and a third grating track null signal sensor (P-Z, null signal Z of resolution P).

An optical signal modulation code wheel comprises a first grating track 111 and a first zero-position signal track 211 thereof, a second grating track 121 and a second zero-position signal track 221 thereof, and a third grating track 131 and a third zero-position signal track 231 thereof, wherein the optical signal modulation code wheel is of a disc structure, grating area light transmission lines on each grating track are uniformly distributed along the circumference, and the number of the grating area light transmission lines is the intrinsic resolution line number of the grating track to which the grating area light transmission lines belong.

The invention provides a composite phase array structure aiming at the defect of singleness of the existing product, and provides a scheme that 2-3 independent phase array track windows are arranged, and the matched optical code discs can meet most resolution requirements by matching with the same photoelectric encoder chip, so that the scheme improves the production and detection cost required to be invested by photoelectric encoder manufacturers to meet various resolution requirements, and reduces the design difficulty and the test difficulty of the photoelectric encoder manufacturers. The matching difficulty that manufacturers need to invest under the condition of various resolution requirements is solved. The invention also provides a mode for digitally selecting the working state. The number of coded digital pulses which can be output per circle rotation of the requirement is selected by a binary digital code through a chip selection input end. The setting and the operation are simple, and the application of different resolution product requirements can be met more flexibly. The invention also provides a flexible signal processing method, which integrates digital processing of frequency multiplication and frequency division, carries out signal processing of 1/2, 1/4, x 2 and x 4 on the intrinsic signal, and is matched with a corresponding differential amplifier, so that a user can select application conditions suitable for the user from a plurality of resolution specifications of the chip. The invention also provides a method for judging the zero position signal. To account for the independence and correlation of the zero signals. In one case, three independent phase arrays correspond to three independent zero signals, channels are not interfered with each other, and needed precision output content is selected through an input selection port.

A design scheme of an incremental photoelectric encoder chip with multiple resolutions and programmable output is provided. The chip design is based on a composite light sensing phase array structure, the application requirements of more than ten kinds of commonly used circumferential linear resolution are integrated on a single chip, the phase light sensing array of the chip is 2-3 independent phase array track windows, the number of required coded digital pulses which can be output in each circumferential rotation is selected by a binary digital coding signal through a chip selection input end. A certain chip is achieved to achieve a user selectable coding resolution. The sensor is characterized by comprising a sensor part and a sensor part, wherein the sensor part comprises 2 to 3 groups of independent phase array signal sensing units and 2 to 3 groups of independent zero position signal sensing units; the signal processing part comprises a current sensing amplifier circuit, a comparator circuit, a signal differential frequency multiplication and clock frequency division processing circuit, a signal output logic relation selection circuit and an internal test debugging circuit. Characterized in that the encoder chip and the code wheel are used one-to-one, and the layout of the signal amplifier makes the matching channel matching very excellent, thereby eliminating the need for signal calibration.

After receiving the optical signal modulated by the corresponding circumferential code disc, the composite phase array sensing unit is converted into a voltage signal through the internal trans-group amplifier unit, and the voltage signal generates a digital signal through the precision voltage comparator with the time difference. Meanwhile, the digital signal outputs an application signal A, B, Z of the photoelectric encoder through a differential push-pull driver. Wherein A, B is the output signal of the phase array sensor, and Z is the corresponding output zero signal. The signals pass through the differential frequency multiplication and clock frequency division processing circuit and then pass through the output logic relation selection circuit, and the corresponding resolution signal output and the corresponding zero position signal output are selected and output through digital logic.

After the composite phase array sensing unit receives the optical signal modulated by the optical code disc, an intrinsic signal is obtained at the moment, the intrinsic signal is a group of orthogonal A, B signals, the working state of the photoelectric encoder can be judged according to the state of the signal AB, and at the moment, according to a preset design state (a set resolution requirement), the signal processing circuit selects corresponding processing, including preset frequency multiplication processing and preset frequency division processing. And simultaneously, the frequency multiplication or frequency division signals are ensured to still keep the orthogonal state output.

The composite phase array is composed of 2 to 3 sensing units, and each group of sensing units corresponds to a group of unique intrinsic signals and corresponding processing signals (signals processed by frequency multiplication and frequency division) and a group of zero signals corresponding to output signals of the intrinsic signals. And the characteristics of the zero position signal meet the corresponding phase and pulse width logical relation of the output signal. The zero position signal corresponding to the output signal has an independent optical signal sensing channel, and correct zero position signal information is selected and output through digital logic according to the preset output signal state characteristic.

The composite phase array is composed of 2 to 3 sensing units, and zero signal specific detection parts corresponding to the corresponding sensing units are in the same detection channel. And according to the different resolutions of the composite phase array, the corresponding zero position relation phase and the pulse width are also different, and according to the preset output signal state characteristics, the corresponding zero position signal is identified through the signal characteristics.

The invention has the characteristics that: 1. the design of the encoder chip is based on a composite light sensing phase array structure, the application requirements of more than ten kinds of commonly used circular linear resolution are integrated on a single chip, the phase light sensing array of the chip is 2-3 independent phase array track windows, the input end is selected through the chip, and the number of encoding digital pulses which can be output by each circular rotation of the requirement is selected through binary digital encoding signals. A certain chip is achieved to achieve a user selectable coding resolution. Two sets of input select ports are configured to select different grating regions and interpolation magnifications. 3 different grating areas can be selected, and each grating area can select 5 different resolution ratios, and can be combined into a 15-resolution line number scheme. 2. The encoder chip integrates digital processing of frequency multiplication and frequency division, carries out signal processing of 1/2, 1/4, x 2 and x 4 on the intrinsic signal, and is matched with a corresponding differential amplifier, so that a user can select application conditions suitable for the user from a plurality of resolution specifications of the chip. 3. The encoder chip and the code wheel are used one-to-one, and the layout of the signal amplifier makes the matching channel matching very excellent, thereby eliminating the need for signal calibration. 4. Independence and correlation of the null signals of the photoelectric encoder. The three groups of independent phase arrays correspond to three groups of independent zero signals, channels are not interfered with each other, and needed zero signal related output contents including phase information and signal width information are selected through the input selection port. 5. The zero signals can be respectively arranged on three code channels and also on the same code channel, three groups of zero signals are characterized by respectively corresponding to the corresponding main code channels, the sensing element areas and the phase relations of the three groups of zero signals are different, the zero signals corresponding to the code channels can be identified through signal characteristic selection, and the method is characterized by accurate signal characteristic selection.

Those skilled in the art will appreciate that the invention may be practiced without these specific details. It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalents, modifications and/or omissions as may be made without departing from the spirit and scope of the invention may be resorted to.

Claims (10)

1. The multi-resolution output increment photoelectric encoder is characterized by comprising a photoelectric encoder chip and a light signal modulation coded disc matched with the photoelectric encoder chip, wherein the photoelectric encoder chip comprises a composite light sensing phase array and a zero position signal sensing array, the composite light sensing phase array is connected with a frequency multiplication and frequency division processing module through a first transimpedance amplifier and a hysteresis comparator combined module, the zero position signal sensing array is connected with a logic processing and selecting module through a second transimpedance amplifier and the hysteresis comparator combined module, the logic processing and selecting module is respectively connected with the frequency multiplication and frequency division processing module and a signal output end, and a plurality of grating tracks are arranged on the light signal modulation coded disc to be matched with the composite light sensing phase array.

2. The multi-resolution output incremental photoelectric encoder of claim 1, wherein the composite photo-sensing phased array comprises a first resolution photodiode array and a second resolution photodiode array, the optical signal modulation code disc has a first grating track and a first null signal track disposed thereon, and a second grating track and a second null signal track disposed thereon, the null signal sensing array comprises a first grating track null signal sensor and a second grating track null signal sensor.

3. The multi-resolution output incremental photoelectric encoder of claim 2, wherein the composite photo-sensing phased array comprises a third resolution photodiode array, a third grating track and a third null signal track are disposed on the optical signal modulation code disc, and the null signal sensing array comprises a third grating track null signal sensor.

4. The multi-resolution output incremental photoelectric encoder according to claim 1, wherein the optical signal modulation code disc is a disc structure, the grating region light transmission lines on each grating track are uniformly distributed along the circumference, the number of the grating region light transmission lines is the number of the intrinsic resolution lines of the grating track to which the grating region light transmission lines belong, the number of the intrinsic resolution lines enables the resolution photodiode array corresponding to the grating region light transmission lines to generate intrinsic signals which are transmitted to the first transimpedance amplifier and the hysteresis comparator combination module, and the intrinsic signals can be subjected to frequency multiplication or frequency division in the frequency multiplication and division processing module.

5. The multi-resolution output incremental photoelectric encoder of claim 4, wherein the frequency multiplication and division processing module is capable of performing 1/2, 1/4, x 2, x 4 signal processing on the intrinsic signals to form a multi-resolution selectable encoding resolution specification.

6. The multi-resolution output incremental photoelectric encoder of claim 1, wherein a first grating track, a second grating track, a third null signal track, a second null signal track and a first null signal track are sequentially distributed on the optical signal modulation code disc from outside to inside.

7. The multi-resolution output incremental photoelectric encoder of claim 6, wherein the number of grating region light transmission lines on the first grating track < the number of grating region light transmission lines on the second grating track < the number of grating region light transmission lines on the third grating track.

8. An optical signal modulation code wheel for the multi-resolution output incremental photoelectric encoder of claim 1, comprising a first grating track and a first zero signal track thereof, a second grating track and a second zero signal track thereof, and a third grating track and a third zero signal track thereof, wherein the optical signal modulation code wheel is of a disc structure, the light transmission lines of the grating regions on each grating track are uniformly distributed along the circumference, and the number of the light transmission lines of the grating regions is the number of the intrinsic resolution lines of the grating track to which the grating regions belong.

9. The multi-resolution output increment photoelectric encoder chip is characterized by comprising a composite light sensing phase array and a zero position signal sensing array, wherein the composite light sensing phase array is connected with a frequency multiplication and frequency division processing module through a first transimpedance amplifier and a hysteresis comparator combined module, the zero position signal sensing array is connected with a logic processing and selecting module through a second transimpedance amplifier and the hysteresis comparator combined module, and the logic processing and selecting module is respectively connected with the frequency multiplication and frequency division processing module and a signal output end.

10. The multi-resolution output incremental photoelectric encoder chip of claim 9, wherein the composite photo-sensing phased array comprises a first resolution photodiode array, a second resolution photodiode array, and a third resolution photodiode array, and the null signal sensing array comprises a first grating-track null signal sensor, a second grating-track null signal sensor, and a third grating-track null signal sensor.

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