WO2022099531A1

WO2022099531A1 - Offloading reliability, availability and serviceability runtime system management interrupt error handling to cpu on-die modules

Info

Publication number: WO2022099531A1
Application number: PCT/CN2020/128265
Authority: WO
Inventors: Fumin Lu; Hong PU; Lei Wang; Jiewen Yao
Original assignee: Intel Corporation
Priority date: 2020-11-12
Filing date: 2020-11-12
Publication date: 2022-05-19

Abstract

Systems, apparatuses and methods may provide for technology that detects a runtime error in a core region of a host processor, notifies an assistant processor of the runtime error, wherein the assistant processor is external to the core region and on a shared die with the core region, and conducts a handling of the runtime error by the assistant processor, wherein the handling bypasses a system management mode (SMM).

Description

OFFLOADING RELIABILITY, AVAILABILITY AND SERVICEABILITY RUNTIME SYSTEM MANAGEMENT INTERRUPT ERROR HANDLING TO CPU ON-DIE MODULES

TECHNICAL FIELD

Embodiments generally relate to error handling. More particularly, embodiments relate to offloading reliability, availability and serviceability (RAS) runtime system management interrupt (SMI) error handling to central processing unit (CPU) on-die modules.

BACKGROUND

RAS criteria may be used in Internet data centers (IDCs) to keep servers operating continuously without compromising data integrity. Additionally, runtime error handling for RAS may improve system fault tolerance and fault management. Conventional system management interrupt (SMI) handlers, however, may degrade performance (e.g., as the number of CPU cores increases) , limit the ability to add features/functionality due to SMI handler complexity and/or present security concerns.

BRIEF DESCRIPTION OF THE DRAWINGS

The various advantages of the embodiments will become apparent to one skilled in the art by reading the following specification and appended claims, and by referencing the following drawings, in which:

FIG. 1 is a block diagram of an example of a host processor semiconductor package according to an embodiment;

FIG. 2 is a block diagram of an example of an error classification hierarchy according to an embodiment;

FIG. 3 is a block diagram of an example of an error signaling flow according to an embodiment;

FIG. 4 is a flowchart of an example of a method of operating a performance-enhanced computing system according to an embodiment;

FIG. 5 is a flowchart of an example of a method of notifying an assistant processor of a runtime error according to an embodiment;

FIG. 6 is a flowchart of an example of a method of handling a recoverable error according to an embodiment;

FIG. 7 is a flowchart of an example of a more detailed method of operating a performance-enhanced computing system according to an embodiment;

FIG. 8 is a block diagram of an example of a performance-enhanced computing system according to an embodiment;

FIG. 9 is an illustration of an example of a semiconductor package apparatus according to an embodiment;

FIG. 10 is a block diagram of an example of a processor according to an embodiment; and

FIG. 11 is a block diagram of an example of a multi-processor based computing system according to an embodiment.

DESCRIPTION OF EMBODIMENTS

Turning now to FIG. 1, a host processor 20 (e.g., CPU semiconductor package) is shown in which a plurality of shared dies 22 (22a-22d) are coupled to a programmable device such as a complex programmable logic device (CPLD) 24. The host processor 20 may generally be deployed in a server of an Internet data center (IDC) having reliability, availability and serviceability (RAS) criteria to keep the server operating continuously without compromising data integrity. In the illustrated example, a first die 22a ( “Die 0” ) includes a core region 26 (26a-26d, e.g., machine check architecture/MCA bank) containing hardware components such as, for example, a core 26a (e.g., CPU core to execute operating system/OS code) , an integrated memory controller (IMC) 26b, a ultra path interconnect (UPI, e.g., socket link) 26c, an integrated input/output (IIO, e.g., IO link) 26d, and so forth. In an embodiment, the first die 22a also includes a configuration controller 28 (e.g., “Ubox” configuration agent) and an assistant processor 30 (e.g., secure systems startup module/S3M microcontroller including read only memory/ROM and/or random access memory/RAM) that is external to the core region 26.

During operation of the core region 26, various hardware runtime errors may be encountered. The runtime errors may include, for example, corrected errors, uncorrectable errors (e.g., detected but uncorrectable/DUE) , uncorrected errors (e.g., uncorrected no action required/UCNA) , recoverable errors (e.g., software recoverable action optional/SRAO, software recoverable action required/SRAR) , etc., or any combination thereof. In general, a runtime error may trigger a corrected machine check interrupt (CMCI) or a machine check exception (MCE) in the core region 26. In an embodiment, the first die 22a includes logic to detect the runtime errors in the core region 26, notify the assistant processor 30 of the runtime errors, and conduct a handling of the runtime errors by the assistant processor 30.

In one example, notifying the assistant processor 30 of the runtime errors includes converting/morphing CMCIs and/or MCEs into assistant interrupts (e.g., CMCI S3M interrupt/CS3MI and/or MCE S3M interrupt/MS3MI) and sending the assistant interrupts to the assistant processor via the configuration controller 28. Thus, rather than converting the CMCIs/MCEs into system management interrupts (SMIs) , the illustrated core region 26 converts the CMCIs/MCEs into assistant interrupts and the configuration controller 28 sends the assistant interrupts to the assistant processor 30. Additionally, ifthe runtime error is a recoverable error (e.g., SRAO or SRAR that triggers an MS3MI) , the logic of the assistant processor 30 may halt the core region 26 and resume the core region 26 in response to a confirmation that the assistant processor 30 has completed the handling of the runtime error.

The runtime error handling that is offloaded to the assistant processor 30 may include a log entry creation, status clear, fault action, etc., conducted through register accesses. In one example, the assistant processor 30 retrieves firmware from a non-volatile RAM (NVRAM) in the CPLD 24 and uses the firmware to handle the runtime errors. Moreover, the handling of the runtime error may be conducted independently of additional assistant processors in the dies 22b-22d of the host processor 20. In an embodiment, the logic of the assistant processor 30 notifies an OS executing on the core 26a in the core region 26 of the runtime error after the core region is resumed. Table I below shows an example comparison between a conventional configuration table and an enhanced configuration table as described herein.

Table I

As will be discussed in greater detail, the runtime error handling may bypass a system management mode (SMM) in which all normal execution, including the OS, is suspended. Bypassing SMM provides several advantages in terms of performance, upgrades and security. For example, as the number of CPU cores 26a increases, adegradation in performance may be avoided. Additionally, features/functionality may be readily added to the host processor 20 without concern over SMI handler complexity. Moreover, security is enhanced because SMM is typically more privileged than the OS and/or a virtual machine monitor (VMM, e.g., hypervisor) and therefore an attractive target for hackers. In addition, the on-die assistant processor 30 is able to handle all correctable errors, unlike an off-package baseboard management controller (BMC) . In an embodiment, the other dies 22b-22d are configured similarly to the first die 22a.

FIG. 2 shows an error classification hierarchy 40 that may be used to categorize the runtime errors. In the illustrated example, the top level error is either an MCA error or an advanced error reporting (AER) error.

FIG. 3 shows an error handling flow 50 in which a host processor architecture is enhanced to morph CMCI to CS3MI and MCE to MS3MI. In an embodiment, aUbox 42 (e.g., configuration agent/controller) is responsible for broadcasting interrupts 56 such as an CS3MI (CMCI S3M interrupt) and a MS3MI (MCE S3M interrupt) to an S3M 54 (e.g., assistant processor) . The interrupt handler of the on-die S3M 54 may then access MCA/AER registers to conduct RAS error handing and report the errors to the OS via a system control interrupt (SCI) . In the illustrated example, the RAS error handling has no interaction with the host system.

FIG. 4 shows a method 60 of operating a performance-enhanced computing system. The method 60 may generally be implemented by a host processor such as, for example, the host processor 20 (FIG. 1) , already discussed. More particularly, the method 60 may be implemented as one or more modules in a set of logic instructions stored in a machine-or computer-readable storage medium such as RAM, ROM, programmable ROM (PROM) , firmware, flash memory, etc., in configurable logic such as, for example, programmable logic arrays (PLAs) , FPGAs, complex programmable logic devices (CPLDs) , in fixed-functionality hardware logic using circuit technology such as, for example, ASIC, complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof.

For example, computer program code to carry out operations shown in the method 60 may be written in any combination of one or more programming languages, including an object oriented programming language such as JAVA, SMALLTALK, C++or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. Additionally, logic instructions might include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, state-setting data, configuration data for integrated circuitry, state information that personalizes electronic circuitry and/or other structural components that are native to hardware (e.g., host processor, central processing unit/CPU, microcontroller, etc. ) .

Illustrated processing block 62 detects a runtime error in a core region of a host processor. The runtime error may be a corrected error, an uncorrectable error, an uncorrected error, a recoverable error, etc., or combinations thereof. In an embodiment, block 64 notifies an assistant processor of the runtime error, wherein the assistant processor is external to the core region and on a shared die with the core region. Block 66 conducts a handling of the runtime error by the assistant processor, wherein the handling bypasses an SMM. In one example, the handling of the runtime error is conducted independently of additional processors in the host processor. Additionally, the handling may include a log entry creation, a status clear, a fault action, etc. (e.g., via MCA and/or AER registers) . The method 60 therefore enhances performance at least to the extent that as the number of CPU cores increases, adegradation in performance may be avoided. Additionally, features/functionality may be readily added to the host processor without concern over SMI handler complexity and security is enhanced because SMM may be targeted by hackers and/or malicious code. Moreover, the on-die assistant processor is able to handle all correctable errors, unlike an off-package BMC.

FIG. 5 shows a method 70 of notifying an assistant processor of a runtime error. The method 70 may generally be incorporated into block 64 (FIG. 4) , already discussed. More particularly, the method 70 may be implemented as one or more modules in a set of logic instructions stored in a machine-or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in configurable logic such as, for example, PLAs, FPGAs, CPLDs, in fixed-functionality hardware logic using circuit technology such as, for example, ASIC, CMOS or TTL technology, or any combination thereof.

Illustrated processing block 72 converts/morphs one or more of a CMCI or an MCE into an assistant interrupt. In an embodiment, block 74 sends the assistant interrupt to the assistant processor via a configuration controller. Thus, the method 70 avoids the generation of an SMI, which further enhances performance.

FIG. 6 shows a method 80 of handling a recoverable error such as an SRAO and/or and SRAR. The method 80 may generally be incorporated into block 66 (FIG. 4) , already discussed. More particularly, the method 80 may be implemented as one or more modules in a set of logic instructions stored in a machine-or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in configurable logic such as, for example, PLAs, FPGAs, CPLDs, in fixed-functionality hardware logic using circuit technology such as, for example, ASIC, CMOS or TTL technology, or any combination thereof.

Illustrated processing block 82 halts the core region if the runtime error is a recoverable error. In an embodiment, block 84 resumes the core region in response to a confirmation that the assistant processor has completed the handling of the runtime error. Block 84 may also include notifying an OS executing in the core region of the runtime error after the core region is resumed. The method 80 therefore enables software recoverable errors to be further processed by the OS without invoking SMM.

FIG. 7 shows a method 90 of operating a performance-enhanced computing system. The method 80 may generally implemented by a host processor such as, for example, the host processor 20 (FIG. 1) , already discussed. More particularly, the method 80 may be implemented as one or more modules in a set of logic instructions stored in a machine-or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in configurable logic such as, for example, PLAs, FPGAs, CPLDs, in fixed-functionality hardware logic using circuit technology such as, for example, ASIC, CMOS or TTL technology, or any combination thereof.

Since the S3M (e.g., assistant processor) and the Ubox 92 (e.g., configuration agent/controller) are in the CPU un-core, embodiments involve the S3M accessing the un-core and offloading the RAS runtime error handling from the CPU to the S3M as shown below:

1) . RAS runtime error handing code is stored in a CPLD NVRAM (e.g., the NVRAM may also store an extensible firmware interface/EFI variable RAS policy) ;

2) . Enhanced MCA (EMCA) technology morphs CMCI to CS3MI and MCE to MS3MI as indicated in Table I;

3) . The Ubox 92 may broadcast CS3MI and MS3MI events to S3M, where the Ubox 92 halts all CPU cores at block 94 until the S3M finishes error handing if the error triggers an MS3MI event;

4) . An S3M can access MCA/AER registers and Peripheral Component Interconnect (PCI) based registers (e.g., memory controller, IIO controller, etc. ) .

5) . Unified EFI (UEFI) firmware may reserve system memory to log RAS error for OS.

- When S3M RAS interrupt is triggered, an S3M interrupt handler 96 programs a memory controller register to lock the system memory and only allow to access by S3M.

- When the S3M interrupt handler 96 finishes the error handing, the handler 96 unlocks the system memory and reports to the OS at block 100;

6) . The S3M may also store the RAS error log into CPLD NVRAM or a BMC.

Turning now to FIG. 8, a performance-enhanced computing system 110 is shown. The system 110 may generally be part of an electronic device/platform having computing functionality (e.g., personal digital assistant/PDA, notebook computer, tablet computer, convertible tablet, server) , communications functionality (e.g., smart phone) , imaging functionality (e.g., camera, camcorder) , media playing functionality (e.g., smart television/TV) , wearable functionality (e.g., watch, eyewear, headwear, footwear, jewelry) , vehicular functionality (e.g., car, truck, motorcycle) , robotic functionality (e.g., autonomous robot) , Internet of Things (IoT) functionality, etc., or any combination thereof.

In the illustrated example, the system 110 includes a host processor 112 (e.g., CPU) having an integrated memory controller (IMC, which may be distributed across multiple dies) 114 that is coupled to a system memory 116. In an embodiment, an IO module 118 is coupled to the host processor 112. The illustrated IO module 118 communicates with, for example, a display 124 (e.g., touch screen, liquid crystal display/LCD, light emitting diode/LED display) , a network controller 126 (e.g., wired and/or wireless) , and a mass storage 128 (e.g., hard disk drive/HDD, optical disc, solid-state drive/SSD, flash memory, etc. ) . The system 110 may also include a graphics processor 120 (e.g., GPU) .

In an embodiment, the host processor 112 is similar to the host processor 20 (FIG. 1) . Accordingly, the host processor 112 may include a CPLD and one or more shared dies coupled to the CPLD, where the one or more shared dies include logic 130 coupled to one or more substrates. In one example, the logic 130 implements one or more aspects of the method 60 (FIG. 4) , the method 70 (FIG. 5) and/or the method 80 (FIG. 6) , already discussed. Thus, the logic 130 may detect a runtime error in a core region of host processor 112, notify an assistant processor of the runtime error, wherein the assistant processor is external to the core region and on the one or more shared dies with the core region, and conduct a handling of the runtime error by the assistant processor, wherein the handling bypasses an SMM.

The system 110 is therefore performance-enhanced at least to the extent that as the number of CPU cores increases, a degradation in performance may be avoided. Additionally, features/functionality may be readily added to the host processor 112 without concern over SMI handler complexity and security is enhanced because SMM may be targeted by hackers and/or malicious code. Moreover, the on-die assistant processor is able to handle all correctable errors, unlike an off-package BMC.

FIG. 9 shows a semiconductor apparatus 140 (e.g., host processor chip and/or package) . The illustrated apparatus 140 includes one or more substrates 142 (e.g., silicon, sapphire, gallium arsenide) and logic 144 (e.g., transistor array and other integrated circuit/IC components) coupled to the substrate (s) 142. In an embodiment, the logic 144 implements one or more aspects of the method 60 (FIG. 4) , the method 70 (FIG. 5) and/or the method 80 (FIG. 6) , already discussed. Thus, the logic 144 may detect a runtime error in a core region of the host processor, notify an assistant processor of the runtime error, wherein the assistant processor is external to the core region and on the one or more shared dies with the core region, and conduct a handling of the runtime error by the assistant processor, wherein the handling bypasses an SMM.

The apparatus 140 is therefore performance-enhanced at least to the extent that as the number of CPU cores increases, a degradation in performance may be avoided. Additionally, features/functionality may be readily added to the host processor without concern over SMI handler complexity and security is enhanced because SMM may be targeted by hackers and/or malicious code. Moreover, the on-die assistant processor is able to handle all correctable errors, unlike an off-package BMC.

The logic 144 may be implemented at least partly in configurable logic or fixed-functionality hardware logic. In one example, the logic 144 includes transistor channel regions that are positioned (e.g., embedded) within the substrate (s) 142. Thus, the interface between the logic 144 and the substrate (s) 142 may not be an abrupt junction. The logic 144 may also be considered to include an epitaxial layer that is grown on an initial wafer of the substrate (s) 142.

FIG. 10 illustrates a processor core 200 according to one embodiment. The processor core 200 may be the core for any type of processor, such as a micro-processor, an embedded processor, a digital signal processor (DSP) , a network processor, or other device to execute code. Although only one processor core 200 is illustrated in FIG. 10, a processing element may alternatively include more than one of the processor core 200 illustrated in FIG. 10. The processor core 200 may be a single-threaded core or, for at least one embodiment, the processor core 200 may be multithreaded in that it may include more than one hardware thread context (or “logical processor” ) per core.

FIG. 10 also illustrates a memory 270 coupled to the processor core 200. The memory 270 may be any of a wide variety of memories (including various layers of memory hierarchy) as are known or otherwise available to those of skill in the art. The memory 270 may include one or more code 213 instruction (s) to be executed by the processor core 200, wherein the code 213 may implement the method 60 (FIG. 4) , the method 70 (FIG. 5) and/or the method 80 (FIG. 6) , already discussed. The processor core 200 follows a program sequence of instructions indicated by the code 213. Each instruction may enter a front end portion 210 and be processed by one or more decoders 220. The decoder 220 may generate as its output a micro operation such as a fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals which reflect the original code instruction. The illustrated front end portion 210 also includes register renaming logic 225 and scheduling logic 230, which generally allocate resources and queue the operation corresponding to the convert instruction for execution.

The processor core 200 is shown including execution logic 250 having a set of execution units 255-1 through 255-N. Some embodiments may include a number of execution units dedicated to specific functions or sets of functions. Other embodiments may include only one execution unit or one execution unit that can perform a particular function. The illustrated execution logic 250 performs the operations specified by code instructions.

After completion of execution of the operations specified by the code instructions, back end logic 260 retires the instructions of the code 213. In one embodiment, the processor core 200 allows out of order execution but requires in order retirement of instructions. Retirement logic 265 may take a variety of forms as known to those of skill in the art (e.g., re-order buffers or the like) . In this manner, the processor core 200 is transformed during execution of the code 213, at least in terms of the output generated by the decoder, the hardware registers and tables utilized by the register renaming logic 225, and any registers (not shown) modified by the execution logic 250.

Although not illustrated in FIG. 10, a processing element may include other elements on chip with the processor core 200. For example, a processing element may include memory control logic along with the processor core 200. The processing element may include I/O control logic and/or may include I/O control logic integrated with memory control logic. The processing element may also include one or more caches.

Referring now to FIG. 11, shown is a block diagram of a computing system 1000 embodiment in accordance with an embodiment. Shown in FIG. 11 is a multiprocessor system 1000 that includes a first processing element 1070 and a second processing element 1080. While two

processing elements

1070 and 1080 are shown, it is to be understood that an embodiment of the system 1000 may also include only one such processing element.

The system 1000 is illustrated as a point-to-point interconnect system, wherein the first processing element 1070 and the second processing element 1080 are coupled via a point-to-point interconnect 1050. It should be understood that any or all of the interconnects illustrated in FIG. 11 may be implemented as a multi-drop bus rather than point-to-point interconnect.

As shown in FIG. 11, each of

processing elements

1070 and 1080 may be multicore processors, including first and second processor cores (i.e.,

processor cores

1074a and 1074b and

processor cores

1084a and 1084b) .

Such cores

1074a, 1074b, 1084a, 1084b may be configured to execute instruction code in a manner similar to that discussed above in connection with FIG. 10.

Each

processing element

1070, 1080 may include at least one shared

cache

1896a, 1896b. The shared

cache

1896a, 1896b may store data (e.g., instructions) that are utilized by one or more components of the processor, such as the

cores

1074a, 1074b and 1084a, 1084b, respectively. For example, the shared

cache

1896a, 1896b may locally cache data stored in a

memory

1032, 1034 for faster access by components of the processor. In one or more embodiments, the shared

cache

1896a, 1896b may include one or more mid-level caches, such as level 2 (L2) , level 3 (L3) , level 4 (L4) , or other levels of cache, a last level cache (LLC) , and/or combinations thereof.

While shown with only two

processing elements

1070, 1080, it is to be understood that the scope of the embodiments are not so limited. In other embodiments, one or more additional processing elements may be present in a given processor. Alternatively, one or more of

processing elements

1070, 1080 may be an element other than a processor, such as an accelerator or a field programmable gate array. For example, additional processing element (s) may include additional processors (s) that are the same as a first processor 1070, additional processor (s) that are heterogeneous or asymmetric to processor a first processor 1070, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units) , field programmable gate arrays, or any other processing element. There can be a variety of differences between the

processing elements

1070, 1080 in terms of a spectrum of metrics of merit including architectural, micro architectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the

processing elements

1070, 1080. For at least one embodiment, the

various processing elements

1070, 1080 may reside in the same die package.

The first processing element 1070 may further include memory controller logic (MC) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, the second processing element 1080 may include a MC 1082 and

P-P interfaces

1086 and 1088. As shown in FIG. 11, MC’s 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory locally attached to the respective processors. While the

MC

1072 and 1082 is illustrated as integrated into the

processing elements

1070, 1080, for alternative embodiments the MC logic may be discrete logic outside the

processing elements

1070, 1080 rather than integrated therein.

The first processing element 1070 and the second processing element 1080 may be coupled to an I/O subsystem 1090 via P-P interconnects 1076 1086, respectively. As shown in FIG. 11, the I/O subsystem 1090 includes

P-P interfaces

1094 and 1098. Furthermore, I/O subsystem 1090 includes an interface 1092 to couple I/O subsystem 1090 with a high performance graphics engine 1038. In one embodiment, bus 1049 may be used to couple the graphics engine 1038 to the I/O subsystem 1090. Alternately, a point-to-point interconnect may couple these components.

In turn, I/O subsystem 1090 may be coupled to a first bus 1016 via an interface 1096. In one embodiment, the first bus 1016 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the embodiments are not so limited.

As shown in FIG. 11, various I/O devices 1014 (e.g., biometric scanners, speakers, cameras, sensors) may be coupled to the first bus 1016, along with a bus bridge 1018 which may couple the first bus 1016 to a second bus 1020. In one embodiment, the second bus 1020 may be a low pin count (LPC) bus. Various devices may be coupled to the second bus 1020 including, for example, a keyboard/mouse 1012, communication device (s) 1026, and a data storage unit 1019 such as a disk drive or other mass storage device which may include code 1030, in one embodiment. The illustrated code 1030 may implement the method 60 (FIG. 4) , the method 70 (FIG. 5) and/or the method 80 (FIG. 6) , already discussed, and may be similar to the code 213 (FIG. 10) , already discussed. Further, an audio I/O 1024 may be coupled to second bus 1020 and a battery 1010 may supply power to the computing system 1000.

Note that other embodiments are contemplated. For example, instead of the point-to-point architecture of FIG. 11, a system may implement a multi-drop bus or another such communication topology. Also, the elements of FIG. 11 may alternatively be partitioned using more or fewer integrated chips than shown in FIG. 11.

Additional Notes and Examples:

Example 1 includes a performance-enhanced computing system comprising a network controller and a host processor coupled to the network controller, the host processor including a complex programmable logic device (CPLD) and one or more shared dies coupled to the CPLD, the one or more shared dies including logic coupled to one or more substrates, wherein the logic is to detect a runtime error in a core region of a host processor, notify an assistant processor of the runtime error, wherein the assistant processor is external to the core region and on the one or more shared dies with the core region, and conduct a handling of the runtime error by the assistant processor, wherein the handling bypasses a system management mode (SMM) .

Example 2 includes the computing system of Example 1, wherein to notify the assistant processor of the runtime error, the logic is to convert one or more of a corrected machine check interrupt or a machine check exception into an assistant interrupt, and send the assistant interrupt to the assistant processor via a configuration controller.

Example 3 includes the computing system of Example 1, wherein the handling of the runtime error is to be conducted independently of additional assistant processors in the host processor, and wherein the handling is to include one or more of a log entry creation, a status clear or a fault action.

Example 4 includes the computing system of Example 1, wherein the logic is to halt the core region if the runtime error is a recoverable error, and resume the core region in response to a confirmation that the assistant processor has completed the handling of the runtime error.

Example 5 includes the computing system of Example 4, wherein the logic is to notify an operating system executing in the core region of the runtime error after the core region is resumed.

Example 6 includes the computing system of any one of Examples 1 to 5, wherein the runtime error is to include one or more of a corrected error, an uncorrectable error, an uncorrected error or a recoverable error.

Example 7 includes a host processor comprising a complex programmable logic device (CPLD) , and one or more shared dies coupled to the CPLD, the one or more shared dies including logic coupled to one or more substrates, wherein the logic is to detect a runtime error in a core region of the host processor, notify an assistant processor of the runtime error, wherein the assistant processor is external to the core region and on the one or more shared dies with the core region, and conduct a handling of the runtime error by the assistant processor, wherein the handling bypasses a system management mode (SMM) .

Example 8 includes the host processor of Example 7, wherein to notify the assistant processor of the runtime error, the logic is to convert one or more of a corrected machine check interrupt or a machine check exception into an assistant interrupt, and send the assistant interrupt to the assistant processor via a configuration controller.

Example 9 includes the host processor of Example 7, wherein the handling of the runtime error is to be conducted independently of additional assistant processors in the host processor, and wherein the handling is to include one or more of a log entry creation, a status clear or a fault action.

Example 10 includes the host processor of Example 7, wherein the logic is to halt the core region if the runtime error is a recoverable error, and resume the core region in response to a confirmation that the assistant processor has completed the handling of the runtime error.

Example 11 includes the host processor of Example 10, wherein the logic is to notify an operating system executing in the core region of the runtime error after the core region is resumed.

Example 12 includes the host processor of any one of Examples 7 to 11, wherein the runtime error is to include one or more of a corrected error, an uncorrectable error, an uncorrected error or a recoverable error.

Example 13 includes the host processor of any one of Examples 7 to 11, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

Example 14 includes at least one computer readable storage medium comprising a set of executable program instructions, which when executed by a computing system, cause the computing system to detect a runtime error in a core region of a host processor, notify an assistant processor of the runtime error, wherein the assistant processor is external to the core region and on a shared die with the core region, and conduct a handling of the runtime error by the assistant processor, wherein the handling bypasses a system management mode (SMM) .

Example 15 includes the at least one computer readable storage medium of Example 14, wherein to notify the assistant processor of the runtime error, the instructions, when executed, cause the computing system to convert one or more of a corrected machine check interrupt or a machine check exception into an assistant interrupt, and send the assistant interrupt to the assistant processor via a configuration controller.

Example 16 includes the at least one computer readable storage medium of Example 14, wherein the handling of the runtime error is to be conducted independently of additional assistant processors in the host processor, and wherein the handling is to include one or more of a log entry creation, a status clear or a fault action.

Example 17 includes the at least one computer readable storage medium of Example 14, wherein the instructions, when executed, further cause the computing system to halt the core region if the runtime error is a recoverable error, and resume the core region in response to a confirmation that the assistant processor has completed the handling of the runtime error.

Example 18 includes the at least one computer readable storage medium of Example 17, wherein the instructions, when executed, further cause the computing system to notify an operating system executing in the core region of the runtime error after the core region is resumed.

Example 19 includes the at least one computer readable storage medium of any one of Examples 14 to 18, wherein the runtime error is to include one or more of a corrected error, an uncorrectable error, an uncorrected error or a recoverable error.

Example 20 includes a method of operating a host processor, the method comprising detecting a runtime error in a core region of the host processor, notifying an assistant processor of the runtime error, wherein the assistant processor is external to the core region and on a shared die with the core region, and conducting a handling of the runtime error by the assistant processor, wherein the handling bypasses a system management mode (SMM) .

Example 21 includes the method of Example 20, wherein notifying the assistant processor of the runtime error includes converting one or more of a corrected machine check interrupt or a machine check exception into an assistant interrupt, and sending the assistant interrupt to the assistant processor via a configuration controller.

Example 22 includes the method of Example 20, wherein the handling of the runtime error is conducted independently of additional assistant processors in the host processor, and wherein the handling includes one or more of a log entry creation, a status clear or a fault action.

Example 23 includes the method of Example 20, further including halting the core region if the runtime error is a recoverable error, and resuming the core region in response to a confirmation that the assistant processor has completed the handling of the runtime error.

Example 24 includes the method of Example 23, further including notifying an operating system executing in the core region of the runtime error after the core region is resumed.

Example 25 includes the method of any one of Examples 20 to 24, wherein the runtime error includes one or more of a corrected error, an uncorrectable error, an uncorrected error or a recoverable error.

Example 26 includes means for performing the method of any one of Examples 20 to 25.

Thus, technology described herein offloads CPU RAS runtime execution into an assistant processor (e.g., S3M) . The technology also improves system performance (e.g., no SMI/OS interaction) and security by removing SMI. Moreover, each on-die S3M may execute RAS error handing independently and in parallel for a multi-die architecture. Additionally, the technology separates RAS runtime error code to S3M firmware for modularization.

Embodiments are applicable for use with all types of semiconductor integrated circuit ( “IC” ) chips. Examples of these IC chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLAs) , memory chips, network chips, systems on chip (SoCs) , SSD/NAND controller ASICs, and the like. In addition, in some of the drawings, signal conductor lines are represented with lines. Some may be different, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. This, however, should not be construed in a limiting manner. Rather, such added detail may be used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit. Any represented signal lines, whether or not having additional information, may actually comprise one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, optical fiber lines, and/or single-ended lines.

Example sizes/models/values/ranges may have been given, although embodiments are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the figures, for simplicity of illustration and discussion, and so as not to obscure certain aspects of the embodiments. Further, arrangements may be shown in block diagram form in order to avoid obscuring embodiments, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the embodiment is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments, it should be apparent to one skilled in the art that embodiments can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

The term “coupled” may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms “first” , “second” , etc. may be used herein only to facilitate discussion, and carry no particular temporal or chronological significance unless otherwise indicated.

As used in this application and in the claims, a list of items joined by the term “one or more of” may mean any combination of the listed terms. For example, the phrases “one or more of A, B or C” may mean A, B, C; A and B; A and C; B and C; or A, B and C.

Those skilled in the art will appreciate from the foregoing description that the broad techniques of the embodiments can be implemented in a variety of forms. Therefore, while the embodiments have been described in connection with particular examples thereof, the true scope of the embodiments should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.

Claims

A performance-enhanced computing system comprising:

a network controller; and

a host processor coupled to the network controller, the host processor including a complex programmable logic device (CPLD) and one or more shared dies coupled to the CPLD, the one or more shared dies including logic coupled to one or more substrates, wherein the logic is to:

detect a runtime error in a core region of a host processor;

notify an assistant processor of the runtime error, wherein the assistant processor is external to the core region and on the one or more shared dies with the core region; and

conduct a handling of the runtime error by the assistant processor, wherein the handling bypasses a system management mode (SMM) .
The computing system of claim 1, wherein to notify the assistant processor of the runtime error, the logic is to:

convert one or more of a corrected machine check interrupt or a machine check exception into an assistant interrupt; and

send the assistant interrupt to the assistant processor via a configuration controller.
The computing system of claim 1, wherein the handling of the runtime error is to be conducted independently of additional assistant processors in the host processor, and wherein the handling is to include one or more of a log entry creation, a status clear or a fault action.
The computing system of claim 1, wherein the logic is to:

halt the core region if the runtime error is a recoverable error; and

resume the core region in response to a confirmation that the assistant processor has completed the handling of the runtime error.
The computing system of claim 4, wherein the logic is to notify an operating system executing in the core region of the runtime error after the core region is resumed.
The computing system of any one of claims 1 to 5, wherein the runtime error is to include one or more of a corrected error, an uncorrectable error, an uncorrected error or a recoverable error.
A host processor comprising:

a complex programmable logic device (CPLD) ; and

one or more shared dies coupled to the CPLD, the one or more shared dies including logic coupled to one or more substrates, wherein the logic is to:

detect a runtime error in a core region of the host processor;

notify an assistant processor of the runtime error, wherein the assistant processor is external to the core region and on the one or more shared dies with the core region; and

conduct a handling of the runtime error by the assistant processor, wherein the handling bypasses a system management mode (SMM) .
The host processor of claim 7, wherein to notify the assistant processor of the runtime error, the logic is to:

convert one or more of a corrected machine check interrupt or a machine check exception into an assistant interrupt; and

send the assistant interrupt to the assistant processor via a configuration controller.
The host processor of claim 7, wherein the handling of the runtime error is to be conducted independently of additional assistant processors in the host processor, and wherein the handling is to include one or more of a log entry creation, a status clear or a fault action.
The host processor of claim 7, wherein the logic is to:

halt the core region if the runtime error is a recoverable error; and

resume the core region in response to a confirmation that the assistant processor has completed the handling of the runtime error.
The host processor of claim 10, wherein the logic is to notify an operating system executing in the core region of the runtime error after the core region is resumed.
The host processor of any one of claims 7 to 11, wherein the runtime error is to include one or more of a corrected error, an uncorrectable error, an uncorrected error or a recoverable error.
The host processor of any one of claims 7 to 11, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.
At least one computer readable storage medium comprising a set of executable program instructions, which when executed by a computing system, cause the computing system to:

detect a runtime error in a core region of a host processor;

notify an assistant processor of the runtime error, wherein the assistant processor is external to the core region and on a shared die with the core region; and

conduct a handling of the runtime error by the assistant processor, wherein the handling bypasses a system management mode (SMM) .
The at least one computer readable storage medium of claim 14, wherein to notify the assistant processor of the runtime error, the instructions, when executed, cause the computing system to:

convert one or more of a corrected machine check interrupt or a machine check exception into an assistant interrupt; and

send the assistant interrupt to the assistant processor via a configuration controller.
The at least one computer readable storage medium of claim 14, wherein the handling of the runtime error is to be conducted independently of additional assistant processors in the host processor, and wherein the handling is to include one or more of a log entry creation, a status clear or a fault action.
The at least one computer readable storage medium of claim 14, wherein the instructions, when executed, further cause the computing system to:

halt the core region if the runtime error is a recoverable error; and

resume the core region in response to a confirmation that the assistant processor has completed the handling of the runtime error.
The at least one computer readable storage medium of claim 17, wherein the instructions, when executed, further cause the computing system to notify an operating system executing in the core region of the runtime error after the core region is resumed.
The at least one computer readable storage medium of any one of claims 14 to 18, wherein the runtime error is to include one or more of a corrected error, an uncorrectable error, an uncorrected error or a recoverable error.
A method of operating a host processor, the method comprising:

detecting a runtime error in a core region of the host processor;

notifying an assistant processor of the runtime error, wherein the assistant processor is external to the core region and on a shared die with the core region; and

conducting a handling of the runtime error by the assistant processor, wherein the handling bypasses a system management mode (SMM) .
The method of claim 20, wherein notifying the assistant processor of the runtime error includes:

converting one or more of a corrected machine check interrupt or a machine check exception into an assistant interrupt; and

sending the assistant interrupt to the assistant processor via a configuration controller.
The method of claim 20, wherein the handling of the runtime error is conducted independently of additional assistant processors in the host processor, and wherein the handling includes one or more of a log entry creation, a status clear or a fault action.
The method of claim 20, further including:

halting the core region if the runtime error is a recoverable error; and

resuming the core region in response to a confirmation that the assistant processor has completed the handling of the runtime error.
The method of claim 23, further including notifying an operating system executing in the core region of the runtime error after the core region is resumed.
An apparatus comprising means for performing the method of any one of claims 20 to 24.