WO2022086538A1

WO2022086538A1 - Logic circuitry

Info

Publication number: WO2022086538A1
Application number: PCT/US2020/056847
Authority: WO
Inventors: Stephen D. Panshin
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2020-10-22
Filing date: 2020-10-22
Publication date: 2022-04-28

Abstract

A logic circuit including a data interface to transmit communications is provided. The logic circuit may be configured to, in response to a task command over the data interface, the task command including (i) a task parameter and (ii) a time parameter of zero, execute a task of the task parameter for a predetermined time period, and/or, execute the task while not responding to communications of the first protocol.

Description

LOGIC CIRCUITRY

BACKGROUND

[0001] Logic circuitries that communicate with, and are exchangeable with respect to, host apparatus such as print apparatus may form a stand-alone logic circuit or may be intended for further assembly or integration as an intermediate logic circuit. Certain logic circuits may be adapted for integration with, for example, 2D and 3D print agent cartridges or toner transfer components, the latter including developer roller components, fuser assemblies, photo sensitive drum components or toner reservoirs. Print agent cartridge could include ink supplies or 3D build material supplies or the like. It could be beneficial to provide such logic circuits with additional functionalities such as additional security or data features.

BRIEF DESCRIPTION OF DRAWINGS

[0002] Non-limiting examples will now be described with reference to the accompanying drawings, in which:

[0003] Fig. 1 is a diagram of an example of a logic circuit;

[0004] Fig. 2 is a diagram of an example of a task command;

[0005] Fig. 3 is a table of examples of modes and tasks for a logic circuit;

[0006] Fig. 4 is a flow chart of an example of a method of executing at least one device task in a device attribute mode; and

[0007] Fig. 5 is a diagram of an example of component including a logic circuit and a device.

DETAILED DESCRIPTION

[0008] Some examples of applications described herein are in the context of print apparatus. However, not all the examples are limited to such applications, and at least some of the principles set out herein may be used in other contexts. Another context may be a field of professional or home diagnostics, pharmaceutics, forensic or laboratory equipment, etc.

[0009] The contents of other applications and patents cited in this disclosure are incorporated by reference. [0010] In certain examples, Inter-integrated Circuit (l²C, or I2C, which notation is adopted herein) protocol allows at least one ‘master’ integrated circuit (IC) to communicate with at least one ‘slave’ IC, for example via a bus. In certain examples of this disclosure, a logic circuit may be or include such slave IC while a host logic circuit may include the master IC. I2C, and other communications protocols, communicate data according to a clock frequency. For example, voltage signals may be generated at the clock frequency, where the value of the voltage is associated with data. For example, a voltage value above x may indicate a logic “1” whereas a voltage value below x volts may indicate a logic “0”, where x is a predetermined numerical value. By generating an appropriate voltage in each of a series of clock periods, data can be communicated via a bus or another communication link.

[0011] Certain example print material containers have slave logic that utilize I2C communications, although in other examples, other forms of digital or analogue communications could also be used, or replaceable components other than print material containers. In the example of I2C communication, a master IC may generally be provided as part of the host apparatus and a replaceable component may comprise a ‘slave’ IC, although this need not be the case in all examples. There may be a plurality of slave ICs connected to an I2C communication link or bus of the host apparatus (for example, containers of different colors of print agent). The slave IC(s) may comprise a processor (CPU, Central Processing Unit) to perform data operations before responding to requests from logic circuitry of the print system. In this disclosure, slave ICs are sometimes referred to as logic circuits. Certain example slave ICs or logic circuits may function as secure microcontrollers.

[0012] Logic circuits for replaceable components that communicate with host apparatus may facilitate various functions including authentication, communicating a state of the component, contents of the component, material type information, color conversion maps, print material level data, a product identifier, etc.

[0013] Logic circuits of the host apparatus may receive information from the component side circuits via a communications interface, and/or may send commands to the replaceable component logic circuits, which may comprise commands to write data to a memory associated therewith, or to read data therefrom. Host apparatus may physically or wirelessly connect to certain example components of this disclosure, such as by physical I2C connection or by network connection. Certain host apparatus logic circuits may be provided on distant servers such as secure servers.

[0014] Examples of logic circuits addressed in this disclosure are provided with novel functionalities. These functionalities may enable authentication functions for devices connected to the logic circuits. With some of the logic circuits of this disclosure, a technical barrier to produce certain replaceable components may be raised. With some of the logic circuits of this disclosure, novel authentication functions can be added to the components, thereby increasing a reliability of the entire system of a host apparatus and its components. Certain authentication functions and other functionalities as encompassed by this disclosure can be added to logic circuits without (overly) increasing a latency of the logic circuits or of the component’s devices to which they are connected. The integration of the logic circuit to the different device types (e.g., logic circuit plus sensor, electrophotographic transfer component, printhead or MEMS device) may be achieved while controlling costs and failure points. Certain examples of this disclosure will focus on logic circuits that, once assembled, facilitate these and/or other advantages, although this disclosure also covers the logic circuit as intermediate product.

[0015] In certain scenarios it may be desired to have a logic circuit enable (communication to/from) a secondary device for a flexible and/or long time period, for example in a relatively secure manner. Examples of secondary devices include one or a combination of a sensor, printhead, electrophotographic printing component, MEMS device and another device.

[0016] Fig. 1 illustrates an example of a logic circuit 1. The logic circuit 1 includes a data interface 3 to transmit communications with respect to a host logic circuit 5. In this disclosure, a logic circuit 1 transmitting communications encompasses both receiving (e.g., requests) and sending (e.g., response) communications by the logic circuit 1 , whereby sending communications includes transmitting requested data in response to a read request. The logic circuit 1 includes a memory to store data. The logic circuit 1 includes a CPU to execute tasks. The logic circuit 1 is configured to transmit communications of at least a first protocol over the data interface 3. The first protocol may be a serial data communications protocol such as I2C. The data interface 3 comprises at least a data contact. The data interface 3 may comprise a three or four wire I2C communications interface to communicate with the host logic circuit 5 over an I2C serial interface bus. The data interface 3 may comprise, in addition to data, a clock, power and ground contact. In certain examples, two or three wire interfaces could be used whereby certain functions such as power or ground could be harvested from, or combined with, other functions, such as clock. The logic circuit 1 may be provided with a communications address such as an I2C address to execute commands sent over the serial interface bus including such address. Other logic circuits with other addresses may be connected to the same serial data interface 3 and provided with different addresses. The logic circuit 1 may be configured to respond to commands from the host logic circuit 5 over the data interface 3 directed to the logic circuit’s address.

[0017] The logic circuit 1 may be configured to enable a device signal, for example over a device signal contact 23. In this disclosure, such enabling of a device signal may be considered a task. Also other tasks are addressed in this disclosure. The logic circuit 1 may be an intermediate component to be attached to a further device or component such as a print apparatus component, wherein the device contact 23 may be connected to such further device. In one example, communications over the device signal contact 23 may be transmitted to the data interface 3 by the logic circuit 1 .

[0018] Certain examples of logic circuits of this disclosure are configured to function at least one of a latched mode and a device attribute mode, for example in addition to a momentary mode.

[0019] A first example of the logic circuit 1 is configured to, in response to a task command

7 including a task parameter 13 and a time parameter 11 of zero, not respond to communications of the first protocol. For example, this functionality may correspond to the tasks of the latched mode as indicated in Fig. 3.

[0020] A second example of the logic circuit is configured to store a time attribute 50, and in response to a task command over the data interface, the task command 7 including (i) a task parameter 13 and (ii) a time parameter of zero 11 , execute the task for a time period corresponding to the time attribute 50. This functionality may pertain to the device attribute mode as indicated in Fig. 3. The time attribute 50 may be referred to by firmware instructions stored on the logic circuit 1 for causing the CPU to execute the task for a time period determined by the time attribute 50 where the time parameter is zero. The time attribute 50 is stored in a separate partition and/or access mode as compared to other EEPROM R/W data for transmission to the host logic circuit 5. The time attribute 50 is not intended for external reading/writing but intended to be used in CPU task executions as part of firmware.

[0021] In contrast with the device attribute mode, the momentary mode functions can be associated with time parameters greater than zero, irrespective of the time attribute 50, to enable tasks for a duration associated with a received time parameter of a command.

[0022] The time attribute 50, in conjunction with the time parameter of zero, may add novel functionalities to the logic circuit 1 , for example in addition to the momentary mode tasks where the duration is based on the time parameter (greater than zero). In one example the time attribute 50 is configured to be set during a process of customization/personalization after the hardware and secure firmware of the logic circuit 1 has been built in manufacture, to allow for choosing between a latched or device attribute mode, for example depending on the requirements or desires for the particular component.

[0023] It is noted that, certain example logic circuits may be configured to respond to task commands in a way that is accepted by the host logic circuit, whereby the logic circuit need not be provided with the time attribute to perform the task for the appropriate time period. Also, certain example logic circuits of this disclosure may be configured to only perform one or two tasks, in one or two modes. For example, these example logic circuits may be configured to generate responses that the host logic circuit 5 accepts. [0024] Back to the illustrated example, the time attribute 50 may be set in a register and/or as part of firmware instructions for execution by the CPU. The time attribute may be digitally stored on a memory. For example, the time attribute may be relatively securely stored, e.g., as a read-only value. The time attribute 50 may be referred to by firmware instructions stored on the logic circuit 1. The time attribute 50 may be stored in memory hardware and/or a memory partition that is separate from the read and/or write data that is configured to be more readily accessible by the host logic circuit such as print cartridge characteristics, product ID, etc. In another example, the time attribute can be set and/or changed in response to a command from a host logic circuit, for example even after a first sale or usage of the logic circuit.

[0025] In said first example associated with the latched mode, the logic circuit 1 may be configured to ignore communications after receiving the task command. The time attribute may be set to zero for this mode. For example, the logic circuit 1 disables itself or sets itself to a hibernate or other mode wherein it does not respond to communications of the first protocol. In again other examples, the logic circuit 1 could respond with signals not of the first protocol that the host logic circuit 5 may subsequently ignore, which would have the same effect. Not responding or ignoring communications may be achieved by keeping the logic circuit 1 busy, for example, executing a predetermined calculation, whereby it de facto ignores communications directed to its address.

[0026] Further to the first example and latched mode, the logic circuit 1 may be configured to, in response to said task command 7, execute the task until a new power cycle is initiated. The logic circuit 1 may be configured to, while executing the task, not respond to communications of the first protocol over the data interface 3 until after a new power cycle. After such power cycle, the logic circuit 1 is enabled again to respond to communications of the first protocol. In one example, the logic circuit 1 responds to communications of the first protocol in a default state, and, sets itself to the default state after a power cycle/initiation. In one example, the task command 7 having a time parameter of zero sets the logic circuit 1 in, de facto, a “deaf’ state for an indefinite period until it is re-initiated by a new power cycle. Within and during the time period, the task is executed, for example a device signal may be enabled in response to a device task and time parameter of zero, where the time attribute is zero, until a new power cycle is initiated.

[0027] Referring to the second example, or device attribute mode, the logic circuit 1 can be configured to, in response to the task command 7, enable a device signal until the end of a time period associated with the time attribute 50 where the time attribute value is greater than zero. During the time period the logic circuit 1 may still respond to communications including its address. The logic circuit 1 may be configured to, both inside and outside of the time period, respond to communications directed to its default communications address, to the extent these communications are of the logic circuit’s communications protocol such as I2C protocol. During the time period, the device signal contact 23 may be enabled for input or output communications or for driving a device. Given that the logic circuit 1 of the second example may remain responsive to communications, the logic circuit 1 may be configured to, in response to the device task and time parameter of zero, enable the device signal until the end (e.g., expiry) of the time period associated with the time attribute, or until a new task command is received when a new task command is received within said time period. The logic circuit may be configured to, at the end of the time period, disable the device signal and/or reboot itself, having a disabled device signal after the boot.

[0028] Fig. 2 illustrates a diagram of an example of a task command 107 of the first protocol, to which the logic circuit 1 is configured to respond. The first protocol may be an I2C protocol. The task command 107 includes a communications address 115 so that a logic circuit 1 of that address may execute the command 107. The address 115 may be a 7 or 10 bit I2C communications address. The logic circuit 1 is configured to process commands including its address 115.

[0029] The example task command 107 may further include a task parameter 117. In an example, there may be at least three different task parameters 117, each different task parameter to be associated with a (i) non-response task, (ii) data signal task or (iii) device task. Hence, the task parameters 117 may be referred to as a (i) non-response task parameter, (ii) data signal task parameter or (iii) device task parameter; or, in short, a (i) non-response task, (ii) data signal task or (iii) device task, respectively. The task command 107 may further include a time parameter. In the example illustrated in Fig. 2, the time parameter is zero, corresponding to a latched mode or device attribute mode .

[0030] In a momentary mode (row 301 of Fig. 3), the time parameter is not zero. In a latched mode (row 302 of Fig. 3) or device attribute mode (row 303 of Fig. 3), the time parameter 119 may be zero whereby the task of the task parameter 117 is executed, either for an indefinite time period until a power cycle is initiated per the latched mode, or for a time period defined by the time attribute 50 per the device attribute mode. Whether the logic circuit 1 for usage operates, during usage, in the latched or device attribute mode can be defined by the time attribute 50, for example during manufacture and/or logic circuit firmware customization prior to such usage. For example, the logic circuit 1 may have a (pre-set) time attribute 50 greater than zero so that a time parameter 119 of zero may initiate the device attribute mode, whereby the task parameter 117 may be a device task; or, the logic circuit 1 may have a (pre-set) time attribute 50 of zero so that a time parameter of zero 119 may initiate the latched mode, at least for the device task. The different tasks (i), (ii), or (iii) defined by the task parameter 117 may be executed for a time period defined by at least the time parameter 119, zero or not zero. Task (iii) may be co-defined by the time attribute 50, zero or not zero, where the time parameter 117 is zero.

[0031] Referring to Fig. 3, the momentary mode functions are indicated by row 301 , quadrants A, B and C. In Fig. 3, the “chip” may refer to the logic circuit 1. The logic circuit 1 may be configured to have a certain maximum duration for executing the tasks of the momentary task commands. These durations correspond to the time parameter (greater than zero). The logic circuit may be configured to have a maximum time duration, as associated with the non-zero time parameter, of no more than approximately 65 seconds, or 2 minutes. The logic circuit 1 may be configured to, after the duration, return to its default state or condition, and be responsive to I2C communication after the duration.

[0032] For example, the logic circuit 1 is configured to, in response to (i) the non-response task and a time parameter greater than zero, not respond to communications until the end of a duration associated with that time parameter. International patent application publication numbers W02020/117193A1 and W02020/117194A1 disclose examples of the non-response task, whereby the logic circuit 1 may ignore, or at least not respond to, communications for the duration corresponding to the time parameter. In one example, the logic circuit 1 is designed to keep itself busy so that it does not or cannot respond to communications. An example of this task is indicated in quadrant A of the table of Fig. 3.

[0033] For example, the logic circuit 1 is configured to, in response to (ii) the data signal task, and the time parameter being greater than zero, pull the data signal low and not respond to communications until the end of the duration associated with the time parameter greater than zero. The serial data bus of an I2C communications bus may be pulled by the data contact, for example down to approximately 0V. International patent application publication numbers W02020/117196A1 and W02020/117297A1 disclose examples of this data signal task. In an example this task can be used for determining that the logic circuit 1 is connected to the appropriate one of multiple receiving slots of the host apparatus. An example of this task is indicated in quadrant B of the table of Fig. 3. After the duration, the data interface voltage may again be pulled or released to a default state, for example to approximately 3V.

[0034] For example, the logic circuit 1 is configured to, in response to (iii) the device task, and the time parameter being greater than zero, enable a device signal and not respond to communications to its default communications address until the end of a duration associated with the time parameter greater than zero. A device signal may be enabled over a separate device signal contact 23 (e.g., any line or pad) to transmit signals and/or data to a device. An example of the device signal contact 23 is a GPIO (General Purpose Input/Output) pad. The contact 523 can be part of the logic circuit 1 yet separate from the contacts of the interface 3 that are to directly interface with the host logic circuit 5. The device pad can be a fifth contact separate from the four I2C contacts. The device pad can be a GPIO pad of the logic circuit. The device may connect to that device signal contact 23. In certain examples, the device may include other connections to the interface 3, for example, not connected to the logic circuit 1 and/or not of the first protocol. International patent application publication numbers W02020/117195A1 and W02020/117194A1 disclose examples of device signal tasks, for example, to drive and/or establish communication with a sensor array or other secondary logic circuitry, also considered “devices” in the context of this disclosure. An example of the device task is indicated in quadrant C of the table of Fig. 3. Further examples of a device to be enabled, or to/from which communication is to be enabled, include a sensor, printhead, electrophotographic printing component, MEMS device, another device, or a combination of any of those devices.

[0035] As said, the logic circuit 1 may be configured to, after the duration, return to its default state or condition. For example, the logic circuit 1 is configured to, before and after said duration, respond to communications of the first protocol, directed to its default communications address, at least until a new task command is received. In an example the task command is an authenticated command that is cryptographically authenticated using a base key stored on the host logic circuit 5, for example, any key derived from a host-side master key, and that is authenticated by the logic circuit 1 using its corresponding base key, so that the tasks can be executed in a relatively secure manner. In one example, the base key on the logic circuit 1 is derived from a master key of the host logic circuit 5.

[0036] The latched mode is indicated by row 302, quadrants D, E and F, of the table of Fig. 3. In the latched mode, the logic circuit 1 may be configured to not respond to communications of the first protocol in response to a task command including a time parameter of zero, while executing the task, until it initiates a new power cycle. For the device task, the latched mode may be associated with a time attribute 50 of zero, or, in some examples, no time attribute, or, in again other examples, any time attribute different than a time attribute that initiates the device attribute mode.

[0037] For the non-response and the data signal task per quadrant D and E, the time attribute 50, if any, may be disregarded. The logic circuit may be configured to, in response to a non-response task parameter and/or data signal task parameter, and a time parameter of zero, execute the non-response task and/or data signal task, respectively, irrespective of the time attribute, for example even where the time attribute is greater than zero. For example, post-customization the logic circuit may be configured to execute the tasks of D, E and G, where the time attribute may be greater than zero for the task of G.

[0038] In certain scenarios the latched mode may provide for the option to have certain tasks executed by the logic circuit 1 for longer durations than tasks of the mentioned momentary mode. The logic circuit may be configured to not respond to communications (e.g., “ignore”) over the interface 3 in the latched mode, for example to avoid communication conflicts with other protocols over the same interface 3.

[0039] The logic circuit 1 may be configured to, in response to a task command including the non-response task and the time parameter of zero, not respond to communications until after a new power cycle, as indicated by quadrant D. The logic circuit 1 may be configured to, in response to a task command including the data signal task and the time parameter of zero, pull the data signal low and not respond to communications until after a new power cycle, as indicated by quadrant E.

[0040] The logic circuit 1 may be configured to, in response to a task command including the device task and the time parameter of zero, enable the device signal and not respond to communications to its default communications address until after a new power cycle, as indicated by quadrant F. As also indicated in quadrant F, the time attribute 50 may be pre-set to zero to trigger the device task in the latched mode. In one example, the device signal may drive or instruct a separate device, or enable communications to and/or from the device, until the new power cycle. For example, the device may be a printhead configured to eject print liquid or a sensor. The logic circuit 1 may be configured to, after the new power cycle, again respond to communications directed to its default communications address, similar to a default state after a default power cycle, where the task or device signal is disabled.

[0041] A device attribute mode, as illustrated in quadrant G, row 303, of Fig. 3, may be associated with a time attribute greater than zero. The time attribute greater than zero may cause the logic circuit 1 to, in response to a task command including a device task and time parameter of zero, enable the device signal for a time period based on the time attribute 50 while remaining responsive to I2C communications.

[0042] As illustrated by quadrant G, row 303, the logic circuit 1 may be configured to, in response to a command including the device task and time parameter of zero, whereby the time attribute is greater than zero, execute the task in a device attribute mode. In one example, the device attribute mode is associated only with the device task and not with the nonresponse task or the data signal task. In one example an out-of-factory logic circuit 1 (postmanufacturing and customization) is pre-configured to operate in only one of the device attribute mode per row 303 or the latched mode per row 302. In another example an out-of- factory logic circuit 1 is configured to operate in the latched mode for a non-response task and/or data signal task and the device attribute mode for the device task. This may be determined by the time attribute 50.

[0043] Further to the device attribute mode, the logic circuit 1 may be configured to, in response to the task command including a device task and a time parameter of zero, enable the device signal until the end of a time period associated with the time attribute, or until a new task command is received, and in the time period, respond to communications of the first protocol over its default communications address. The logic circuit 1 may be configured to, when a new task command is received within that time period, execute the associated task and stop enabling the device signal, unless the task command includes again a device task whereby the enabling of the device signal may be continued for a new time period.

[0044] The logic circuit may be configured to, at the end of the time period associated with the time attribute, stop enabling the device signal. In a further example, the logic circuit is configured to reboot itself after the time period has been completed. The logic circuit may be configured to have an inactive device signal after the reboot. The reboot may be associated with one or both of a power cycle and reset of the logic circuit and/or reinitiating the operating system of the logic circuit 1 . The logic circuit 1 may be configured to, after the time period associated with the time attribute, return itself to its default state, whereby the device signal is again inactive until activated again by a new task command that includes the device task.

[0045] The logic circuit 1 may be configured to, during execution of a device task in the device attribute mode, upon receiving a new task command within the time period of the time attribute greater than zero, stop a timer that monitors the time period, and initiate the task of that task command. Where the new task command within the attribute time period includes again a device task and a time parameter of zero, this initiates a new time period corresponding to the time attribute. For example, the logic circuit 1 is configured to not reboot if a new device task command, including a device task, is received within the time period associated with the time attribute greater than zero. For example, the device signal may be continuously enabled without interruption by repetitive refreshing through device task commands that include the device task and time parameter, where the time attribute is greater than zero, and where such command is received, each time, before the expiry of the respective time period.

[0046] In certain examples, the logic circuits are not provided with the time attribute. Certain example logic circuits may be configured to execute a device task, for a time period associated with that device task, without using a time attribute. These logic circuits need not store a time attribute. In other examples, the time attribute facilitates customization after manufacture and before usage. In again other examples the time attribute need not be fixed prior to usage and the logic circuit may be configured to facilitate (re)setting the time attribute value, for example, by a command from the host logic circuit.

[0047] The logic circuit may comprise a pre-set time attribute and be configured to execute the task for a duration that is dependent of the time attribute. Where the time attribute is set to zero, the tasks are executed up until a new power cycle, where the time attribute is greater than zero, the task is executed for the duration corresponding to the time attribute.

[0048] For logic circuits configured to operate in the latched mode, e.g., where the time attribute is zero, the logic circuit is configured to, in response to the task command including a device task and a time parameter of zero, enable the device signal and not respond to (e.g., ignore) communications to its default communications address until after a new power cycle. This may facilitate relatively long time durations for executing the respective tasks, such as for enabling communications with a secondary device or for driving and/or transmitting communications to the secondary device through the device signal contact 23.

[0049] Fig. 4 illustrates a flow chart of an example method of processing at least a task command in the device attribute mode. As said, in one example, the time attribute may be set to greater than zero. At block 400, the logic circuit receives a device task command including its default communications address, a device task and a time parameter of zero. At block 410, the logic circuit starts enabling the device signal. While enabling the device signal, the logic circuit remains responsive to communications including its default communications address. By enabling the device signal, communications and/or signals may be transmitted over the device signal contact 23 by a connected device. The logic circuit may use a timer to monitor the time period of the device signal enablement. At block 410 the timer starts counting. Per line 420, if, before the end of a time period, the device task command of block 410 is again received, then the logic circuit continues enabling the device signal, for example, without interruption. For example, the device signal may remain high or serial bit transmission may continue over the device signal contact 23. Per block 410, the timer reinitiates counting and the logic circuit remains responsive to new commands. When, at some point, no new task command is received within said time period, at block 430, the logic circuit reboots at the end of the time period associated with the last received time attribute and stops enabling the device signal. The device signal may be disabled after the reboot.

[0050] It is noted that also other task commands, not device tasks of the device attribute mode, for example any of the tasks associated with quadrants A - F of Fig. 3, may be received in the time period, whereby the logic circuit may execute that other task before the time period expires. Then, the logic circuit may exit the task by a power cycle in the latched mode per quadrant D or E, or after the time duration associated with the time parameter greater than zero of the momentary mode per quadrants A, B or C.

[0051] In accordance with Fig. 4, the logic circuit is configured to, in response to a device task command, enable a device signal; in response to a new device task command, received within the time period associated with the previous device task command, continue enabling the device signal without interruption until the end of a new time period associated with the new device time attribute unless again a new task command is received; and, continue enabling the device signal without interruption in response to new device task commands that are each time received within the running time period associated with the previous device task command. In the device attribute mode, repetitive device task commands can be used to each time extend the enablement of the device signal and/or postpone the disablement thereof. [0052] The logic circuit 1 may be configured to associate its time attribute with longer maximum time periods than the time parameter. For example, the logic circuit 1 may be configured to, in the device attribute mode, enable the device signal based on the time attribute for a longer time than based on the time parameter in the momentary mode. In further examples, the logic circuit can be configured to execute tasks in the momentary mode for many different durations at a relatively high resolution, for example between 1 and approximately 65 seconds with 1 ms increments, based on different corresponding time parameters. In certain examples, such as prior to customization, the logic circuit may be configured to vary the time attribute in less steps (i.e. lower resolution), such as for example between 1 and 300 seconds in one second increments. The device attribute mode may add more flexibility to the logic circuit for securely enabling the device signal based on its intended purpose. Also, in contrast with the latched mode, the logic circuit may still be receptive and/or responsive to communications in the device attribute mode.

[0053] Fig. 5 illustrates a replaceable component 529 comprising a logic circuit 501 and a device 525. The logic circuit 501 can be a stand-alone device or an intermediate product, not necessarily mounted to the replaceable component 529. However, for the purpose of explaining, in the drawing of Fig. 5, the logic circuit is mounted to the replaceable component. The logic circuit 501 is provided with a CPU (Central Processing Unit) 531 and a memory 533. The logic circuit 501 may comprise firmware including instructions to cause the CPU 531 to execute any of the tasks of any of the task commands explained previously and as follows.

[0054] The device 525 may be, at least in part, driven and/or instructed by the device signal on the device signal line 523 as controlled by the logic circuit 501 , or, in some examples, the device 525 may communicate over the device signal line 523 as enabled by the logic circuit 501. In an example the replaceable component 529 is a replaceable print apparatus component, to be replaced with respect to 2D or 3D host print apparatus, whereby the device 525 may be an image transfer circuit such as a print head die or electrophotographic printing component for transferring toner, or a sensor. In an example, further contacts 547 of the interface 503 are to communicate directly from the host logic circuit 505 to the device 525, without intervention by the logic circuit 501 .

[0055] In other examples, the component need not be replaceable, for example the component can be fixedly mounted with respect to a host apparatus, in connection with the interface bus of the host apparatus. In again other examples, the component need not relate to image transfer, whereby the device can be, for example, any type of MEMS or high precision device for analysis or transfer of materials such as fluids, for example for diagnostic, forensic, laboratory and/or pharmaceutical use.

[0056] The component 529 may comprise an interface 503 including I2C interface contacts V3P3, CLK, DATA. The interface 503 may comprise an I2C interface comprising data DATA, clock CLK, power V3P3 and ground contacts. The interface 503 may comprise further contacts or lines 547 to directly contact the host logic circuit 505 to the device 525, for example to communicate with the device 525 without intervention by the logic circuit 501. The logic circuit 501 may comprise the device signal line or contact 523 that connects to the device 525. The device contact 523 may be a GPIO pad, be separate from the interface 503.

[0057] In a further example, the replaceable component 529 is configured to have the device 525 enabled through the device line 523 whereafter such direct communications between the host logic circuit 505 and the device 525 over the further lines 547 can be established. For example the logic circuit 501 is configured to enable the device 525 in response to the task command, using the first (e.g., I2C) communications protocol, to enable the device 525 to transfer material, or sense, in response to signals over the lines 547 of a different, second protocol. The further lines or contacts 547 need not be I2C compatible.

[0058] The device 525 may be configured to transmit and process communications of a different protocol than the I2C protocol, such as a customized device specific protocol. In the example where the device comprises an image transfer circuit for printing, the device 525 may be configured to transfer images based on a custom image transfer protocol, for example as customized by an OEM (Original Equipment Manufacturer).

[0059] In an example the component 529 is an image transfer or MEMS component. In the example of an image transfer component the device 525 may comprise an image transfer circuit configured to transfer a print image towards media based on print instructions received over the interface 503. The image transfer circuit may be a printhead die or a toner transfer circuit for transferring electrophotographic images and/or toner. In the example of a MEMS component the device may comprise a MEMS circuit configured to address thin film actuators in the device 525 to propel or sense material that is input or throughput with respect to the MEMS circuit, over the interface 503. The logic circuit 501 may be configured to, in response to a device task, generate the device signal to the device 525 to enable image transfer by the image transfer circuit or material transfer or sense functions by the MEMS circuit. Respective image transfer instructions or sense instructions may be at least partly transmitted over separate interface contacts 547. When the device task as executed by the logic circuit 501 has stopped or expired, said image transfer or sense function may be disabled. A time period for executing the task may be based on the time parameter and/or a time attribute 550, as explained previously. The time attribute 550 may be stored in the memory and/or programmed in firmware. In this disclosure, both such instances of the time attribute 550 may be considered as being stored on the memory. [0060] The logic circuit 501 may comprise at least one timer 543. The logic circuit 501 is configured to control the time parameter duration and/or time attribute time period using the at least one timer 543, irrespective of a clock frequency. The at least one timer 543 may be configured to count during the time period, at least until the expiry of the time period. For a data signal task in the momentary mode, the data signal may be driven/pulled low until the expiry of the time period per the time parameter. For the device task in the device attribute mode, the device signal may be enabled until the expiry of the time period per the time attribute. The logic circuit 501 may monitor the timer 543 to discontinue its task at the end of the duration.

[0061] In one example, the time parameter and the time attribute are associated with each a different timer, whereby the logic circuit 501 is configured to use/monitor a different timer depending on the type of command. A momentary command may enable one timer and a device attribute mode command may enable anothertimer of the logic circuit 501 . The latched mode may function without using the timer 543. The at least one timer 543 may be adapted to count irrespective of an I2C clock frequency. The at least one timer 543 may be adapted to count at a higher frequency than a clock frequency of the host logic circuit 505. The at least one timer 543 may work similar to the timer disclosed in international patent application publication numbers W02020/117196A1 and W02020/117297A1 .

[0062] The logic circuit 501 of Fig. 5 may execute the device tasks without a device 525 connected to it, whereby a host logic circuit 505 may connect to and/or check the device signal. In most instances described in this disclosure, the logic circuit 501 may be an intermediate product for assembly and connection with a device 525. The logic circuit may be a secure microcontroller. The memory 533 may comprise multiple partitions, multiple access modes, and different memory hardware types having different security levels. The memory 533 may store at least one base key 535 related to at least one master key of the host logic circuit 505, for cryptographic authentication of communications. In another example, base keys may be generated for separate sessions or groups of sessions. The base key 535 may be used for generating session keys. Also session key identifiers and/or message authentication codes may be generated for each session, such as described in United States patent application publication No. US9619663B2. The memory 533 may store secure authentication instructions 537 to instruct the CPU 531 to cryptographically authenticate communications.

[0063] In one example, the logic circuit 501 is a secure logic circuit such as a secure microcontroller. The secure logic circuit 501 can be configured to send and receive authenticated messages. The secure logic circuit 501 can be configured to send authenticated messages in response to authenticated commands from the host logic circuit 505. The secure logic circuit 501 can be configured to transmit communications over the first protocol (e.g., I2C). The secure logic circuit 1 can be configured to generate a session key that is different for each communication session and that is based on at least one base key 535. The logic circuit 501 may be configured to generate session key identifiers and/or MACs (messages authentication codes), using the session key, which session key identifiers and/or MACs may be included in the transmitted messages.

[0064] The logic circuit 501 can be a separate component from the device 525. For example, the CPU 531 and the at least one memory 533 of the logic circuit 501 may be provided on a different substrate and/or in a different packaging than the device 525. The logic circuit 501 can be configured to enable and/or disable the device of the replaceable component using the device signal. The device 525, and at least partly, the device line 523, may be provided in or on a different packaging or substrate separate from the substrate of the logic circuit 501. Then again, the logic circuit 501 and device 525 may be part of the same component and/or packaging.

[0065] The logic circuit 501 can be configured to securely authenticate communications including the device task command, the device task command being a task command 107 including the device task as task parameter 117. The command can be cryptographically authenticated by the host logic circuit 5, 505. The logic circuit 501 can be configured to not enable image transfer or sensing by the device 525 until the device task command is received and authenticated by the logic circuit 501 .

[0066] In one example, non-l2C interface bus contacts 547 are configured to transmit the print instructions to the device 525. Hence, the interface 503 may comprise a first group of interface contacts V3P3, CLK, DATA for I2C communications and a second group of interface contacts 547 for communications of another communications protocol. In certain other examples, the logic circuit 501 may be configured to communicate at least a portion of print instructions or print settings over the device line 523, to the device 525, for example as based on received communications over DATA.

[0067] The logic circuit 501 may be configured to, in response to a device task command received over the interface 503, the command being of the first communications protocol and including a time indication, enable, for a duration determined by the time indication, the image transfer circuit 525 to transfer images towards media based on the print instructions. The task command may be received over said I2C interface contacts. The print instructions may be received over the other non-l2C contacts 547. The time indication comprises a time parameter and/or a time attribute. A duration (e.g., time period) of the image transfer by the image transfer circuit is determined by the received time parameter and/or the time attribute, respectively, in accordance with earlier examples of this disclosure. The image transfer circuit 525 may be enabled over the device line 523, for example over a GPIO pad of the logic circuit 501 .

[0068] In an example, the logic circuit 501 is configured to, in response to a device task and a time parameter of zero, enable, for a time period associated with a time attribute greater than zero, an image transfer device to transfer an image towards media, over the device line 523. In accordance with previous examples, the logic circuit 501 may be configured to prolong image transfer without interruption by receiving subsequent device task commands from the host print apparatus logic circuit, each device task command being received within a duration associated with the previous device task command. This may facilitate uninterrupted image transfer for longer periods while the logic circuit 501 remains receptive and/or responsive to communications. The logic circuit 501 may be configured to respond to a new device task command of the momentary mode (e.g., C of Fig. 3) within the duration of the previous device task command of the device attribute mode, associated with the time attribute, and act in accordance with the new device task and time parameter of the momentary mode. Hence, image transfer may be flexibly enabled, prolonged, interrupted and/or disabled in accordance with the tasks and commands of this disclosure, and in some examples, in a relatively secure manner.

[0069] In certain examples (not shown) a value other than zero could be used for the time parameter associated with the latched mode or device attribute mode, in which example this other value should be excluded from the momentary mode. In certain examples (not shown) a value other than zero could be used for the time attribute associated with the latched mode which value should be excluded from the device attribute mode. For example, the logic circuit 501 is configured to, when the task command includes a task parameter and a first time parameter, execute the task of the command for a duration corresponding to the first time parameter (momentary mode), and when the task command includes a device task and a second time parameter (device attribute mode), associate the second time parameter with the time attribute, and enable a device function (a) for a time period corresponding to the time attribute if no new task command is received before the time period expires. In most examples illustrated in this disclosure, the first time parameter is greater than zero and the second time parameter is zero, but other values could be used. Also, in certain examples of this disclosure the time attribute for the latched mode is zero but other non-zero values could be used for the latched mode. An advantage of using the value of zero for triggering the latched mode and/or device attribute mode is that all other non-zero values can be used for defining the task execution duration. [0070] In certain examples of this disclosure, the logic circuit 1 , 501 is programmed to execute a task for a certain time based on a task parameter, a time parameter and a time attribute. In one example, a relatively secure and time-flexible enablement of a (e.g., print- or MEMS) device may be obtained with relatively low latency.

[0071] It is noted that in this disclosure a “time period” is not intended to have a different technical meaning than the earlier mentioned “duration”. Both terms may refer to a time during which something (e.g., a task such as enabling a device signal, not responding to commands, or pulling a data signal high/low) continues. However, for reasons of clarity, sometimes the “time period” is associated with the time attribute and the “duration” is associated with the time parameter. That said, these terms could be inter-changed or the same term, duration or time period, could be used for both the time parameter and time attribute.

[0072] In this disclosure transmitting communications may include both receiving and sending, for example both receiving commands and sending a response. A read request from a host may be transmitted (i.e., received) by the logic circuit and a response including the requested data may be transmitted (i.e., send by the logic circuit or fetched by the host) by the logic circuit in response to a read request. Communications may include commands, requests, responses, etc.

[0073] In this disclosure different examples are addressed where a device attribute mode or a latched mode is pre-fixed in the logic circuit. Other example logic circuits of this disclosure can operate in both modes, for example where a host logic circuit may issue a task command including a time attribute parameter. In other examples, a logic circuit could be configured that executes a device task for a time duration that corresponds to a time attribute of this disclosure without being provided with that time attribute. Other time based circuitry could be used to facilitate executing the device task for a certain time period that a host print apparatus expects, in response to a device task and time parameter of zero in the device attribute mode. Hence, a logic circuit may be provided including a data interface to transmit communications, the logic circuit configured to, in response to a task command over the data interface, the task command including (i) a task parameter and (ii) a time parameter of zero, execute a task of the task parameter for a predetermined time period.

[0074] In certain examples, the latched mode allows for the logic circuit to ignore I2C communications on the I2C serial bus. In further example, the latched mode allows for the logic circuit to ignore I2C communications on the I2C serial bus while a connected device of the same component as the logic circuit may continue to operate and/or transmit communications from the bus, for example of a different protocol than I2C. [0075] In certain examples, the device attribute mode may facilitate repetitive authentication by the logic circuit, for the device to continue to transmit communications and operate.

Claims

1. A logic circuit including a data interface to transmit communications, the logic circuit configured to, store a time attribute, and in response to a task command over the data interface, the task command including (i) a task parameter and (ii) a time parameter of zero, execute a task of the task parameter for a time period associated with the time attribute.

2. The logic circuit of claim 1 , configured to, in response to said task command, enable a device signal until the end of the time period, and disable the device signal once the time period has expired.

3. The logic circuit of claim 1 or 2 configured to associate the time attribute with a time period for executing the task, wherein a value of the time attribute is greater than zero.

4. The logic circuit of any preceding claim having a communications address and configured to both inside and outside of the time period, respond to communications directed to its default communications address.

5. The logic circuit of any preceding claim, configured to, in response to a device task command comprising a time parameter of zero, enable a device signal until the end of the time period, or until a new task command is received when a new task command is received within that time period.

6. The logic circuit of any of preceding claim, wherein the logic circuit is configured to in response to the task command being a device task command, enable a device signal; in response to a new device task command, received within the time period associated with the previous command, continue enabling the device signal without interruption until expiry of a new time period associated with the new device task command unless another new device task command is received before that expiry; and continue enable the device signal without interruption in response to new device task commands, that are each time received within the running time period associated with the previous device task command.

7. The logic circuit of any preceding claim wherein the task command is a device task command and the task parameter comprises a device task.

8. The logic circuit of any preceding claim configured to, at the end of the time period, disable the device signal.

9. The logic circuit of any preceding claim, wherein the logic circuit is configured to, at the end of the time period, reboot itself, having a disabled device signal after boot.

10. A logic circuit including a data interface to transmit communications, the logic circuit configured to, in response to a task command over the data interface, the task command including (i) a task parameter and (ii) a time parameter of zero, execute the task while not responding to communications of the first protocol.

11 . The logic circuit of claim 10 configured such that in response to said task command the logic circuit executes the task and does not respond to communications of the first protocol over the data interface until after a new power cycle.

12 The logic circuit of claim 10 or 11 , comprising a default communications address to execute tasks directed to such address, the logic circuit configured to, in response to a device task parameter and a time parameter of zero, enable a device signal and not respond to communications to its default communications address until after a new power cycle

13. The logic circuit of any of claims 10 -12 wherein the task parameter includes at least one of a non-response task, data signal task and device task, and the logic circuit is configured to, in response to the non-response task and said time parameter of zero, not respond to communications until after a new power cycle, and/or in response to the data signal task and said time parameter of zero, pull the data signal low and not respond to communications until after a new power cycle.

14. The logic circuit of any of claims 10 - 13 configured to store a time attribute of zero.

15. The logic circuit of any preceding claim wherein the logic circuit comprises a pre-set time attribute greater than zero, and is configured to, in response to the time parameter of zero, enable a device signal for a duration that is dependent of the time attribute.

16. The logic circuit of any previous claim configured to execute a task for a longer maximum time period/duration based on the time attribute than based on the time parameter.

17. The logic circuit of any previous claim wherein the logic circuit is configured to set the time attribute based on a time attribute parameter in a received command.

18. The logic circuit of any preceding claim wherein the task parameter includes at least one of a non-response task, data signal task and device task, and the logic circuit is configured to, in response to the non-response task and a time parameter greater than zero, not respond to communications until the end of a duration associated with the time parameter greater than zero, in response to the data signal task and a time parameter greater than zero, pull the data signal low and not respond to communications until the end of a duration associated with the time parameter greater than zero, and/or, in response to the device task and a time parameter greater than zero, enable device signals and not respond to communications to its default communications address until the end of a duration associated with the time parameter greater than zero.

19. The logic circuit of the previous claim wherein the logic circuit is configured to, before and after said duration, respond to communications of the first protocol directed to its default communications address, at least until a new task command is received.

20. The logic circuit of any previous claim comprising at least one timer, whereby the logic circuit is configured to control the task duration using the at least one timer, irrespective of a clock frequency transmitted over said interface.

21 . The logic circuit of any preceding claim being a secure logic circuit configured to send authentication messages in response to authenticated commands over said first protocol by generating a session key that is different for each communication session and that is based on at least one base key.

22. The logic circuit of any previous claim comprising I2C interface contacts to communicate with the host including data, clock, power and ground, and in addition to the I2C interface contacts, a device contact, wherein the logic circuit is configured to enable the device contact in response to the task command being a device task command. 22

23. The logic circuit of the previous claim wherein the device signal contact comprises a GPIO pad for at least one of driving and/or transmitting communications with respect to a connected device.

24. The logic circuit of claim 22 or 23 wherein enabling the device signal means enabling the device contact for data communications and/or setting it to a high voltage state for data communications.

25. A replaceable component comprising the logic circuit of any preceding claim and a device, wherein the logic circuit is to drive, enable and/or disable the device, and/or enable and/or disable communications to/from the device, by said enabling of the device signal, in response to the task command including a device task.

26. An (i) image transfer or (ii) MEMS component, comprising the logic circuit of any preceding claim and including

(i) an image transfer circuit to transfer a print image towards media based on instructions received over the data interface, or

(ii) a MEMS circuit to address thin film actuators to propel or sense material that is input or throughput with respect to the MEMS circuit based on instructions received over the interface, respectively, wherein the logic circuit is configured to, in response to a device task command, enable (i) image transfer by the print circuit or (ii) material transfer or sense functions by the MEMS circuit, respectively.

27. The component of the previous claim wherein the instructions are of a custom protocol different than the first protocol and the first protocol is an I2C serial data communications protocol.

28. The component of any of claims 25 - 27 comprising the logic circuit and an image transfer circuit to transfer a print image towards media wherein the image circuit includes or is an integral part of at least one of a printhead die and electrophotographic printing component and is, at least partially, to be enabled by the logic circuit in response to the task command.

29. A logic circuit including a CPU (Central Processing Unit), logic circuit firmware instructions to cause the CPU to execute tasks based on commands, 23 an interface to transmit communications including said commands, and a time attribute, wherein said firmware instructions, when executed, cause the CPU to, when the task command includes a task parameter and a first time parameter, execute the task of the command for a duration corresponding to the first time parameter, and when the task command includes a device task and a second time parameter, enable a device signal for a time period corresponding to the time attribute if no new task command is received before the time period expires.

30. A logic circuit of the previous claim wherein the firmware instructions cause the CPU to, without interruption, reinitiate the time period if a new task command is received before the previous time period expires.

31 . The logic circuit of claim 29 or 30 wherein the value of the second time parameter is zero and/or the value of the time attribute is greater than zero.

32. A print imaging component comprising the logic circuit of any of claims 29 - 31 , and a device configured to respond to communications of a second protocol via the interface, wherein the interface is configured to transmit, with respect to at least one print apparatus logic circuit, communications of a first communications protocol and communications of the second communications protocol different than the first communications protocol, the firmware instructions further cause the CPU to enable, for a duration determined by the time parameter and/or time attribute, the device to communicate and/or execute instructions of the second protocol over the interface.

33. The print imaging component of claim 32 wherein the firmware instructions cause the CPU to enable the device for a duration corresponding to the time attribute while being responsive to communications of the first protocol, the device being responsive to communications of the second protocol received via the logic circuit and/or directly via the interface not over the logic circuit, 24 respond to, and execute, new task commands of the first protocol received within the duration.

34. The print imaging component of claim 32 or 33 the logic circuit further comprising firmware instructions that cause the CPU to securely authenticate communications including the device task command, and not enable the device until the device task command is authenticated.