WO2022083313A1 - 多路选择电路、多路选择器、驱动方法、显示面板、显示装置 - Google Patents

多路选择电路、多路选择器、驱动方法、显示面板、显示装置 Download PDF

Info

Publication number
WO2022083313A1
WO2022083313A1 PCT/CN2021/116327 CN2021116327W WO2022083313A1 WO 2022083313 A1 WO2022083313 A1 WO 2022083313A1 CN 2021116327 W CN2021116327 W CN 2021116327W WO 2022083313 A1 WO2022083313 A1 WO 2022083313A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminal
coupled
control
circuit
voltage
Prior art date
Application number
PCT/CN2021/116327
Other languages
English (en)
French (fr)
Inventor
袁粲
李永谦
袁志东
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/793,536 priority Critical patent/US11769445B2/en
Publication of WO2022083313A1 publication Critical patent/WO2022083313A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a multiplexer circuit, a multiplexer, a driving method, a display panel, and a display device.
  • Self-luminous devices have the advantages of high brightness, continuously adjustable luminous color, low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range, simple production process, and high luminous efficiency.
  • a multiplexing circuit includes a first selection sub-circuit and a second selection sub-circuit.
  • the first selection sub-circuit is coupled to the first control terminal, the second control terminal, the input signal terminal, the power supply voltage terminal and the first output terminal.
  • the second selection sub-circuit is coupled to the third control terminal, the fourth control terminal, the input signal terminal, the power supply voltage terminal and the second output terminal.
  • the first selection subcircuit is configured to transmit an input signal received at the input signal terminal to the first output terminal in response to a first control signal received at the first control terminal; and, in response to The voltage of the power supply voltage terminal is transmitted to the first output terminal based on the second control signal received at the second control terminal.
  • the second selection subcircuit is configured to transmit the input signal received at the input signal terminal to the second output terminal in response to a third control signal received at the third control terminal; and, The voltage of the supply voltage terminal is transferred to the second output terminal in response to a fourth control signal received at the fourth control terminal.
  • the first selection subcircuit includes a first transistor and a second transistor.
  • the control electrode of the first transistor is coupled to the first control terminal, the first electrode of the first transistor is coupled to the input signal terminal, and the second electrode of the first transistor is coupled to the first The output terminal is coupled.
  • the control electrode of the second transistor is coupled to the second control end, the first electrode of the second transistor is coupled to the power supply voltage end, and the second electrode of the second transistor is coupled to the first The output terminal is coupled.
  • the second selection subcircuit includes a third transistor and a fourth transistor.
  • the control electrode of the third transistor is coupled to the first control end, the first electrode of the third transistor is coupled to the input signal end, and the second electrode of the third transistor is coupled to the second The output terminal is coupled.
  • the control electrode of the fourth transistor is coupled to the second control end, the first electrode of the fourth transistor is coupled to the power supply voltage end, and the second electrode of the fourth transistor is coupled to the second control end The output terminal is coupled.
  • the multiplexing circuit further includes a first voltage control subcircuit.
  • the first voltage control sub-circuit is coupled to the power supply voltage terminal, the second control terminal and the first selection sub-circuit.
  • the first voltage control subcircuit is configured to control the first selection subcircuit at the second control terminal according to the voltage at the supply voltage terminal and a second control signal received at the second control terminal The voltage of the second control signal received at .
  • the first voltage control subcircuit includes a first capacitor. A first end of the first capacitor is coupled to the power supply voltage end, and a second end of the first capacitor is coupled to the second control end and the first selection sub-circuit.
  • the multiplexing circuit further includes a second voltage control subcircuit.
  • the second voltage control sub-circuit is coupled to the power supply voltage terminal, the fourth control terminal and the second selection sub-circuit.
  • the second voltage control subcircuit is configured to control the second selection subcircuit at the fourth control terminal according to the voltage at the supply voltage terminal and a fourth control signal received at the fourth control terminal The voltage of the fourth control signal received at .
  • the second voltage control subcircuit includes a second capacitor.
  • the first end of the second capacitor is coupled to the power supply voltage end, and the second end of the second capacitor is coupled to the fourth control end.
  • a multiplexing circuit in another aspect, includes a first transistor, a second transistor, a third transistor and a fourth transistor.
  • the control electrode of the first transistor is coupled to the first control end, the first electrode of the first transistor is coupled to the input signal end, and the second electrode of the first transistor is coupled to the first output end.
  • the control electrode of the second transistor is coupled to the second control end, the first electrode of the second transistor is coupled to the power supply voltage end, and the second electrode of the second transistor is coupled to the first output end .
  • the control electrode of the third transistor is coupled to the first control end, the first electrode of the third transistor is coupled to the input signal end, and the second electrode of the third transistor is coupled to the second output end coupled.
  • the control electrode of the fourth transistor is coupled to the second control end, the first electrode of the fourth transistor is coupled to the power supply voltage end, and the second electrode of the fourth transistor is coupled to the second control end
  • the output terminal is coupled.
  • a multiplexer in yet another aspect, includes: a plurality of multiplexing circuits as described in any of the above embodiments.
  • the input signal terminals of the multiplexing circuits are different, the first output terminals are different, and the second output terminals are different.
  • the number of the multiplexing circuits is three.
  • a display panel in yet another aspect, includes a plurality of pixels and at least one multiplexer as described in any of the above embodiments. Each multiplexer is coupled to a plurality of pixels.
  • the plurality of pixels are arranged in an array.
  • the multiplexer is coupled to two columns of pixels.
  • a first output of each multiplexing circuit in the multiplexer is coupled to one of the two columns of pixels, and a second output of each multiplexing circuit in the multiplexer
  • the terminal is coupled to the other one of the two columns of pixels.
  • two columns of pixels coupled by the multiplexer are adjacent.
  • each pixel includes multiple sub-pixels.
  • the first output terminal and the second output terminal of each multiplexing circuit are respectively coupled to sub-pixels with the same emission color in different pixels.
  • the display panel further includes a plurality of sensing lines.
  • a plurality of pixels coupled to the multiplexer are coupled to one sensing line.
  • a display device in yet another aspect, includes the display panel and the source driver described in any one of the above embodiments.
  • the source driver is coupled to at least one multiplexer in the display panel.
  • a method for driving a multiplexing circuit includes: the first selection sub-circuit transmits the input signal received at the input signal terminal to the first output terminal in response to the first control signal received at the first control terminal; the second selection sub-circuit is in response to the first control signal at the first output terminal; The fourth control signal received at the fourth control terminal transmits the voltage of the power supply voltage terminal to the second output terminal; the first selection sub-circuit is responsive to the second control signal received at the second control terminal, and the voltage of the power supply voltage terminal is transmitted. the voltage is transmitted to the first output terminal; the second selection subcircuit transmits the input signal received at the input signal terminal to the second in response to the third control signal received at the third control terminal output.
  • a method for driving a multiplexer includes a plurality of multiplexing circuits; each multiplexing circuit includes a first selection sub-circuit and a second selection sub-circuit; the first selection sub-circuit is connected with the first control terminal and the second control terminal , the input signal terminal, the power supply voltage terminal and the first output terminal are coupled; the second selection sub-circuit is connected to the third control terminal, the fourth control terminal, the input signal terminal, the power supply voltage terminal and the second output terminal Coupling; the input signal terminals of the multiplexing circuits are different, the first output terminals are different, and the second output terminals are different.
  • the driving method includes: a first selection sub-circuit in each multiplexing circuit, in response to a first control signal received at the first control terminal, converts the input signal received at the input signal terminal to which it is coupled to the first output terminal to which it is coupled; the second selection sub-circuit in each multiplexing circuit transmits the voltage of the supply voltage terminal in response to the fourth control signal received at the fourth control terminal to the second output terminal to which it is coupled; the first selection sub-circuit in each multiplexing circuit transmits the voltage of the supply voltage terminal to the second control signal received at the second control terminal the first output terminal to which it is coupled; the second selection sub-circuit in each multiplexing circuit responds to the third control signal received at the third control terminal, the input signal terminal to which it is coupled The input signal received at is transmitted to the second output terminal to which it is coupled.
  • a method for driving a display device includes a plurality of sub-pixels; each sub-pixel includes a pixel circuit; the pixel circuit includes a driving transistor; the display panel further includes a plurality of sensing lines; A plurality of pixels coupled to the multiplexer are coupled to one sensing line.
  • the driving method of the display device includes: a source driver provides an input signal to each multiplexing circuit in a multiplexer in the display panel. The first selection subcircuit in the multiplexing circuit in the multiplexer transmits the input signal received at the input signal terminal to which it is coupled in response to the first control signal received at the first control terminal.
  • the second selection sub-circuit in the multiplexing circuit in the multiplexer transmits the voltage of the power supply voltage terminal in response to the fourth control signal received at the fourth control terminal to the second output terminal to which it is coupled.
  • the sensing line senses a threshold voltage of a driving transistor of a pixel circuit in a sub-pixel in a pixel to which the first output terminal is coupled.
  • the first selection sub-circuit in the multiplexing circuit in the multiplexer transmits the voltage of the supply voltage terminal to the first selection sub-circuit to which it is coupled in response to the second control signal received at the second control terminal an output terminal; the second selection sub-circuit in the multiplexing circuit in the multiplexer responds to the third control signal received at the third control terminal, and will receive at the input signal terminal to which it is coupled The input signal is transmitted to the second output terminal to which it is coupled.
  • the sensing line senses a threshold voltage of a driving transistor of a pixel circuit in a sub-pixel in a pixel to which the second output terminal is coupled.
  • FIG. 1 is a structural diagram of a display device according to some embodiments.
  • FIG. 2 is a schematic diagram of a sub-pixel according to some embodiments.
  • FIG. 3 is a circuit diagram of a pixel circuit according to some embodiments.
  • FIG. 4 is a schematic diagram of a multiplexing circuit according to some embodiments.
  • FIG. 5 is a schematic diagram of a display device according to some embodiments.
  • FIG. 6 is a circuit diagram of a multiplexing circuit according to some embodiments.
  • FIG. 7 is a schematic diagram of another multiplexing circuit according to some embodiments.
  • FIG. 8 is a circuit diagram of another multiplexing circuit according to some embodiments.
  • FIG. 9 is a schematic diagram of a multiplexer according to some embodiments.
  • FIG. 10 is a circuit diagram of another multiplexer according to some embodiments.
  • 11 is a circuit diagram of another multiplexer according to some embodiments.
  • FIG. 12A is a schematic diagram of another display device according to some embodiments.
  • 12B is a diagram illustrating the connection relationship between a multiplexer and a pixel according to some embodiments.
  • 13A is a driving timing diagram of a multiplexing circuit according to some embodiments.
  • 13B is a driving timing diagram of another multiplexing circuit according to some embodiments.
  • 14A and 14B are simulated signal diagrams of a multiplexing circuit according to some embodiments.
  • 15 is a driving timing diagram of a multiplexer according to some embodiments.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • some embodiments may be described using the term “coupled” to indicate that two or more components are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • the term “if” is optionally construed to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that" or “if a [statement or event] is detected” are optionally interpreted to mean “in determining" or “in response to determining" or “on detection of [recited condition or event]” or “in response to detection of [recited condition or event]”.
  • the display device may be any device that displays text or images, whether in motion (eg, video) or stationary (eg, still images). More specifically, the display device may be one of a variety of electronic devices in which the embodiments may be implemented or associated with a variety of electronic devices, such as (but not limited to) Mobile Phones, Wireless Devices, Personal Data Assistants (PDAs), Handheld or Portable Computers, GPS Receivers/Navigators, Cameras, MP4 Video Players, Video Cameras, Game Consoles, Watches, Clocks, Calculators, TV Monitors, Flat panel displays, computer monitors, automotive displays (eg, odometer displays, etc.), navigators, cockpit controls and/or displays, camera view displays (eg, displays for rear view cameras in vehicles), electronic photos, electronic billboards Or signage, projectors, architectural structures, packaging and aesthetic structures (eg, a display for an image of a piece of jewelry), etc.
  • the embodiments of the present disclosure do not specifically limit
  • the display device 200 includes the display panel 100 .
  • the display panel 100 has a display area AA and a peripheral area S.
  • the peripheral area S is located at least on the outer side of the display area AA.
  • the display panel 100 includes a plurality of pixels P disposed in the display area AA.
  • the plurality of pixels P may be arranged in an array.
  • the pixels P arranged in a row along the X direction in FIG. 1 are referred to as the same pixel, and the pixels P arranged in a row along the Y direction in FIG. 1 are referred to as the same column of pixels.
  • each pixel P includes a plurality of sub-pixels Q.
  • the plurality of sub-pixels include first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels; for example, the first color, the second color, and the third color are three primary colors; The second and third colors are red, green, and blue, respectively; that is, the plurality of subpixels includes red, green, and blue subpixels.
  • each sub-pixel Q includes a pixel circuit 101 and a light-emitting device L.
  • the pixel circuit 101 is coupled to the light emitting device L.
  • the light-emitting device L may be an organic OLED or a light-emitting diode (Light Emitting Diode, LED).
  • the working duration described herein can be understood as the lighting duration of the light emitting device L; the first pole and the second pole of the light emitting device L are the anode and the cathode of the light emitting diode, respectively.
  • the pixel circuit is composed of electronic devices such as thin film transistors (Thin Film Transistor, TFT for short), capacitors (Capacitor, C for short).
  • the pixel circuit may include two thin film transistors (a switching transistor and a driving transistor) and a capacitor to form a 2T1C structure; of course, the pixel circuit may also include more than two thin film transistors (multiple switching transistors and a driving transistor) With at least one capacitor, for example, referring to FIG. 3 , the pixel circuit may include a capacitor and three transistors (two switching transistors and one driving transistor) to form a 3T1C structure.
  • the display panel 100 further includes a plurality of gate lines GL and a plurality of data lines DL.
  • the plurality of gate lines GL extend along the X direction in FIG. 1
  • the plurality of data lines DL extend along the Y direction in FIG. 1 .
  • the gate lines GL are configured to transmit scan signals
  • the data lines DL are configured to transmit data signals.
  • each pixel circuit 101 is coupled to at least one gate line GL and one data line DL, and the gate line GL and the data line DL provide the pixel circuit 101 with operating signals, so that the pixel circuit 101 drives the light emitting device L to emit light.
  • each row of pixel circuits is coupled with two gate lines, wherein one gate line transmits the first scan signal ( G1 ) to the pixel circuit, and the other gate line transmits the second scan signal ( G2 ) to the pixel circuit.
  • the display panel 100 further includes a plurality of sensing lines SL.
  • the plurality of sensing lines SL extend along the Y direction in FIG. 1 .
  • the pixel circuit 101 is coupled to the sensing line SL.
  • the control electrode (gate) of one switching transistor M1 is used to receive the first scan signal G1.
  • the first electrode of the switching transistor M1 is coupled to the data line DL to receive the data signal Vdata transmitted on the data line DL.
  • the second electrode of the switching transistor M1 is coupled to the control electrode of the driving transistor M2, the second electrode of the driving transistor M2 is coupled to the first voltage terminal V1 to receive the first voltage VDD (high voltage), and the first electrode of the driving transistor M2
  • the (source) is coupled to the first electrode of the light emitting device L, and the second electrode of the light emitting device L is coupled to the second voltage terminal V2.
  • the first terminal of the storage capacitor Cst is coupled to the second pole of the switching transistor M1 and the control pole of the driving transistor M2, and the second terminal of the storage capacitor Cst is coupled to the first pole of the driving transistor M2 and the first pole of the light emitting device L .
  • the control electrode of the sensing transistor M3 (ie, another switching transistor) is used to receive the second scan signal G2.
  • the first electrode of the sensing transistor M3 is coupled to the second end of the storage capacitor Cst, the second electrode of the driving transistor M2 and the first electrode of the light emitting device L, and the second electrode of the sensing transistor M3 is coupled to the sensing line SL .
  • the sensing line SL is coupled to a detection circuit (not shown). In this case, when the driving transistor M2 is turned on, the sensing line is discharged via the sensing transistor M3, so that the voltage of the second pole of the driving transistor M2 changes.
  • the detection circuit is discharged via the sensing transistor M3 or the capacitance or parasitic capacitance set on the sensing line via the sensing transistor M3 is charged, so that the source voltage Vs of the driving transistor M2 changes .
  • the source voltage Vs of the driving transistor M2 is equal to the difference between the gate voltage Vg of the driving transistor M2 and the threshold voltage Vth of the driving transistor, the driving transistor M2 will be turned off and the source voltage Vs of the driving transistor M2 will not change.
  • the turned-off source voltage ie, the source voltage Vb after the driving transistor M2 is turned off
  • the data signal (data voltage) to be displayed in the pixel circuit can be compensated based on the threshold voltage of the driving transistor in each pixel circuit, and the pixel circuit is driven by using the compensated data signal, so that it is possible to achieve a specific target for each display panel.
  • one sense line is coupled to a plurality of pixel circuits.
  • pixel circuits in two adjacent columns of pixels may be coupled to one sense line.
  • one sense line may be coupled to pixel circuits in six sub-pixels in two adjacent columns of pixels, respectively, to detect the drive in each pixel circuit Threshold voltage of the transistor.
  • the display device 200 further includes a source driver (ie, a source driver IC (Source IC)) 210 .
  • the source driver 210 is bonded to the display panel 100 , and the source driver 210 is configured to provide a signal to the display panel 100 .
  • the signal may be a data signal; for example, a plurality of data lines DL in the display panel 100 may transmit the data signal.
  • the source driver 210 may adopt a COF (Chip On Film) process, that is, the source driver 210 is arranged on an FPC (Flexible Printed Circuit Board, flexible circuit board), through the FPC Bonded with the display panel 100.
  • COF Chip On Film
  • the number of pixel circuits in the display panel is relatively large, and the number of signal lines (such as gate lines and data lines) that provide working signals for the pixel circuits in the display panel is also relatively large.
  • the number of pins (Pin) or output ports required by line-coupled drivers (such as source drivers that provide data signals for data lines) will also increase.
  • the output ports of source drivers are coupled to data lines in one-to-one correspondence.
  • the connection increases the number of output ports of the source driver, which increases the production cost, increases the occupied area, and limits the layout space in the bonding area of the display panel, which easily leads to a decrease in product yield.
  • An embodiment of the present disclosure provides a multiplexing circuit 10 .
  • the multiplexing circuit 10 includes a first selection sub-circuit 11 and a second selection sub-circuit 12 .
  • the first selection sub-circuit 11 is coupled to the first control terminal MUX1, the second control terminal MUX2, the input signal terminal IN, the power supply voltage terminal S and the first output terminal OUT1.
  • the second selection sub-circuit 12 is coupled to the third control terminal MUX3, the fourth control terminal MUX4, the input signal terminal IN, the power supply voltage terminal S and the second output terminal OUT2.
  • the first selection sub-circuit 11 is configured to transmit the input signal received at the input signal terminal IN to the first output terminal OUT1 in response to the first control signal received at the first control terminal MUX1; and, in response to the first control signal received at the first control terminal MUX1;
  • the second control signal received at the two control terminals MUX2 transmits the voltage of the power supply voltage terminal S to the first output terminal OUT1.
  • the second selection subcircuit 12 is configured to transmit the input signal received at the input signal terminal IN to the second output terminal OUT2 in response to the third control signal received at the third control terminal MUX3; and, in response to the third control signal received at the third control terminal MUX3;
  • the fourth control signal received at the four control terminals MUX4 transmits the voltage of the power supply voltage terminal S to the second output terminal OUT2.
  • the display panel 100 further includes a first control signal line M_G1 , a second control signal line M_G2 , a third control signal line M_G3 , a fourth control signal line M_G4 and a power supply voltage line V_S, wherein , the first control terminal MUX1 of the multiplexing circuit 10 is coupled to the first control signal line M_G1, the second control terminal MUX2 is coupled to the second control signal line M_G2, and the third control terminal MUX3 is coupled to the third control signal line M_G3 Then, the fourth control terminal MUX4 is coupled to the fourth control signal line M_G4, and the power supply voltage terminal S is coupled to the power supply voltage line V_S.
  • the supply voltage terminal S is configured to transmit a DC voltage, such as a DC low voltage.
  • a DC voltage such as a DC low voltage.
  • the voltage of the power supply voltage terminal S is the same as the second voltage VSS (low voltage) of the second voltage terminal V2 to which the second pole of the light emitting device L is coupled, that is, the voltage of the power supply voltage terminal S is equal to the second voltage VSS.
  • the power supply voltage terminal and the second voltage terminal are the same voltage terminal.
  • the voltage of the power supply voltage terminal and the second voltage of the second voltage terminal can be transmitted by the same signal line, and the power supply voltage terminal and the second voltage terminal are coupled to the same signal line, which simplifies the wiring of the display panel.
  • the first output terminal OUT1 and the second output terminal OUT2 are respectively coupled to different pixel circuits, and the sub-pixels where the different pixel circuits are located emit light of the same color.
  • the first output terminal OUT1 of a multiplexing circuit 10 is coupled to the first color sub-pixel QR in a column of pixels through a data line DL, and the second output terminal OUT2 is connected to the second output terminal OUT2 through another data line DL.
  • the first color sub-pixel QR in another column of pixels is coupled; the first output terminal OUT1 of a multiplexing circuit 10 is coupled to the second color sub-pixel Q G in a column of pixels through a data line DL, and the second output The terminal OUT2 is coupled to the second color sub-pixel Q G in another column of pixels through another data line DL; the first output terminal OUT1 of a multiplexing circuit 10 is coupled to the third color sub-pixel Q G in a column of pixels through a data line DL.
  • the pixel Q B is coupled, and the second output terminal OUT2 is coupled to the third color sub-pixel Q B in another column of pixels through another data line DL.
  • an output port of the source driver is coupled to an input signal terminal of a multiplexing circuit, and the first output terminal and the second output terminal of the multiplexing circuit are respectively coupled to two data lines, namely, , one output port of the source driver can output signals to two data lines, thereby reducing the number of output ports of the source driver, and reducing the number of pins bonded between the source driver and the display panel, simplifying the display panel.
  • the layout design of the Bonding area reduces the production cost and improves the display effect.
  • the pixel circuit coupled to the first output terminal OUT1 of the multiplexing circuit 10 and the pixel circuit coupled to the second output terminal OUT2 of the multiplexing circuit 10 are coupled to the same sensing line.
  • one sensing line detects the threshold voltages (ie, the threshold voltages of the driving transistors) of a plurality of pixel circuits to which it is coupled in time division.
  • the first output terminal OUT1 of the multiplexing circuit 10 is coupled to the first color sub-pixels in one column of pixels
  • the second output terminal OUT2 is coupled to the first color sub-pixels in another column of pixels
  • the first color sub-pixels in one column of pixels The color sub-pixels and the first color sub-pixels in the other column of pixels are coupled with a sense line that can detect the threshold voltage of the pixel circuits in the first color sub-pixels in one column of pixels after detecting the threshold voltage of the other column of pixels The threshold voltage of the pixel circuit in the first color sub-pixel in the pixel.
  • the sensing line detects the threshold voltage of the pixel circuit in the first color sub-pixel in a column of pixels to which the first output terminal OUT1 is coupled
  • the first color sub-pixel in a column of pixels to which the first output terminal OUT1 is coupled The pixel circuit of the pixel circuit receives the input signal received at the input signal terminal IN, and the second output terminal OUT2 is coupled to the pixel circuit of the first color sub-pixel in another column of pixels.
  • the signal transmitted by the data line coupled to the pixel circuit in one color sub-pixel is the input signal, and the data line of the pixel circuit in the first color sub-pixel in another column of pixels does not transmit the input signal.
  • the signal of the data line will have noise interference due to the uncontrolled potential (for example, in a floating state), resulting in a signal coupled to the second output terminal OUT2.
  • the wrong turn-on of the sub-pixel affects the accuracy of the sensing line detecting the threshold voltage of the pixel circuit in the sub-pixel coupled to the first output terminal OUT1.
  • the sensing line detects the threshold voltage of the pixel circuit in the first color sub-pixel in a column of pixels coupled to the first output terminal OUT1
  • the first color sub-pixel in a column of pixels coupled to the first output terminal OUT1 The pixel circuit in the pixel receives the input signal received at the input signal terminal IN
  • the pixel circuit in the first color sub-pixel in another column of pixels coupled to the second output terminal OUT2 receives the voltage of the power supply voltage terminal S
  • the signal transmitted by the data line coupled to the pixel circuit in the first color sub-pixel is the voltage of the power supply voltage terminal, which can avoid the signal of the data line coupled to the output terminal of the second output terminal OUT2 due to uncontrolled potential.
  • the signal of the data line has noise interference, so that the sub-pixel coupled to the second output terminal OUT2 is erroneously turned on, which affects the accuracy of the sensing line detecting the threshold voltage of the pixel circuit in the sub-pixel coupled to the first output terminal OUT1 , thereby improving the accuracy of the sensing data and improving the display effect.
  • the second output terminal OUT2 receives the input signal received at the input signal terminal IN, and the pixel circuit in the sub-pixel of the first color in a row of pixels coupled to the first output terminal OUT1 receives the voltage of the power supply voltage terminal S, a row
  • the signal transmitted by the data line coupled to the pixel circuit in the first color sub-pixel in the pixel is the voltage of the power supply voltage terminal, so that the signal of the data line coupled to the output terminal of the first output terminal OUT1 can be avoided due to potential uncontrolled
  • there is noise interference in the signal of the data line so that the sub-pixel coupled to the first output terminal OUT1 is erroneously turned on, which affects the accuracy of the sensing line detecting the threshold voltage of the pixel circuit in the sub-pixel coupled to the
  • the first selection sub-circuit transmits the input signal received at the input signal terminal to the first output terminal in response to the first control signal received at the first control terminal and, in response to a second control signal received at the second control terminal, transmitting the voltage of the supply voltage terminal to the first output terminal.
  • the second selection subcircuit transmits the input signal received at the input signal terminal to the second output terminal in response to the third control signal received at the third control terminal; and, in response to the third control signal received at the fourth control terminal
  • the four control signals transmit the voltage of the power supply voltage terminal to the second output terminal.
  • the sensing line detects the threshold voltage of the pixel circuit in the sub-pixel coupled to the first output end
  • the voltage of the signal of the data line coupled to the second output end is the voltage of the power supply voltage end
  • the voltage of the signal of the data line coupled to the first output end is the voltage of the power supply voltage end. Therefore, in the process of detecting the threshold voltage of the pixel circuit in the sub-pixel to which one output terminal of the multiplexing circuit is coupled, the signals of the data lines coupled to the remaining output terminals of the multiplexing circuit may be prevented from having different potentials.
  • noise interference under control which causes sub-pixels to be turned on incorrectly, which affects the accuracy of sensing line detection, thereby improving the accuracy of sensing data and improving the display effect.
  • the first selection sub-circuit 11 includes a first transistor T1 and a second transistor T2.
  • the control electrode of the first transistor T1 is coupled to the first control end MUX1, the first electrode of the first transistor T1 is coupled to the input signal end IN, and the second electrode of the first transistor T1 is coupled to the first output end OUT1 .
  • the control electrode of the second transistor T2 is coupled to the second control terminal MUX2, the first electrode of the second transistor T2 is coupled to the power supply voltage terminal S, and the second electrode of the second transistor T2 is coupled to the first output terminal OUT1.
  • the second selection sub-circuit 12 includes a third transistor T3 and a fourth transistor T4.
  • the control electrode of the third transistor T3 is coupled to the third control end MUX3, the first electrode of the third transistor T3 is coupled to the input signal end IN, and the second electrode of the third transistor T3 is coupled to the second output end OUT2 .
  • the control electrode of the fourth transistor T4 is coupled to the fourth control terminal MUX4, the first electrode of the fourth transistor T4 is coupled to the power supply voltage end S, and the second electrode of the fourth transistor T4 is coupled to the second output end OUT2.
  • the multiplexing circuit 10 further includes a first voltage control sub-circuit 13 .
  • the first voltage control sub-circuit 13 is coupled to the power supply voltage terminal S, the second control terminal MUX2 and the first selection sub-circuit 11 .
  • the first voltage control sub-circuit 13 is configured to control the second control signal received at the second control terminal MUX2 by the first selection sub-circuit 11 according to the voltage of the supply voltage terminal S and the second control signal received at the second control terminal MUX2. Voltage of the control signal.
  • the voltage of the second control signal received by the first selection sub-circuit 11 at the second control terminal MUX2 can be controlled by the first voltage control sub-circuit 13, so that in the display stage, the first selection sub-circuit 11 is in the first
  • the voltage of the second control signal received at the two control terminals MUX2 is provided by the first voltage control sub-circuit 13 and not provided by the signal line coupled to the second control terminal MUX2, so that the display device does not need to supply the second control terminal MUX2 for a long time
  • the coupled signal lines are powered on, thereby reducing the power consumption of the display device.
  • the first voltage control sub-circuit 13 includes a first capacitor C1 .
  • the first end of the first capacitor C1 is coupled to the power supply voltage end S, and the second end of the first capacitor C1 is coupled to the second control end MUX2 and the first selection sub-circuit 11 .
  • the second terminal of the first capacitor C1 is coupled to the control electrode of the second transistor T2.
  • the multiplexing circuit 10 further includes a second voltage control subcircuit 14, as shown in FIG. 7 .
  • the second voltage control sub-circuit 14 is coupled to the power supply voltage terminal S, the fourth control terminal MUX4 and the second selection sub-circuit 12 .
  • the second voltage control sub-circuit 14 is configured to control the fourth control signal received at the fourth control terminal MUX4 by the second selection sub-circuit 12 according to the voltage of the supply voltage terminal S and the fourth control signal received at the fourth control terminal MUX4 Voltage of the control signal.
  • the voltage of the fourth control signal received by the second selection sub-circuit 12 at the fourth control terminal MUX4 can be controlled by the second voltage control sub-circuit 14, so that in the display stage, the second selection sub-circuit 12 is in the first
  • the voltage of the fourth control signal received at the four control terminals MUX4 is provided by the second voltage control sub-circuit 14, but not provided by the signal line coupled to the fourth control terminal MUX4, so that the display device does not need to supply the fourth control terminal MUX4 for a long time.
  • the coupled signal lines are powered on, thereby reducing the power consumption of the display device.
  • the second voltage control sub-circuit 14 includes a second capacitor C2.
  • the first end of the second capacitor C2 is coupled to the power supply voltage end S, and the second end of the second capacitor C2 is coupled to the fourth control end MUX4 and the second selection sub-circuit 12 .
  • the second terminal of the second capacitor C2 is coupled to the control electrode of the fourth transistor T4.
  • Embodiments of the present disclosure provide a multiplexing circuit.
  • the multiplexing circuit 10 includes a first transistor T1 , a second transistor T2 , a third transistor T3 and a fourth transistor T4 .
  • the control electrode of the first transistor T1 is coupled to the first control end MUX1, the first electrode of the first transistor T1 is coupled to the input signal end IN, and the second electrode of the first transistor T1 is coupled to the first output end OUT1 .
  • the control electrode of the second transistor T2 is coupled to the second control terminal MUX2, the first electrode of the second transistor T2 is coupled to the power supply voltage terminal S, and the second electrode of the second transistor T2 is coupled to the first output terminal OUT1.
  • the control electrode of the third transistor T3 is coupled to the third control end MUX3, the first electrode of the third transistor T3 is coupled to the input signal end IN, and the second electrode of the third transistor T3 is coupled to the second output end OUT2.
  • the control electrode of the fourth transistor T4 is coupled to the fourth control terminal MUX4, the first electrode of the fourth transistor T4 is coupled to the power supply voltage end S, and the second electrode of the fourth transistor T4 is coupled to the second output end OUT2.
  • the transistors used in the multiplexing circuit provided by the embodiments of the present disclosure may be thin film transistors (Thin Film Transistor, TFT), field effect transistors (Field Effect Transistor, FET) or other switching devices with the same characteristics , the embodiments of the present disclosure are not limited thereto.
  • the control electrode of each transistor used in the multiplexing circuit is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor.
  • the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure Diodes may be indistinguishable in structure.
  • the transistor is a P-type transistor
  • the first electrode of the transistor is the source electrode
  • the second electrode is the drain electrode
  • the transistor is an N-type transistor
  • the first electrode electrode of the transistor is the drain electrode
  • the second pole is the source.
  • each sub-circuit is not limited to the above-described manner, which can be any implementation manner, such as a conventional connection manner well known to those skilled in the art, Just make sure to implement the corresponding function.
  • the above examples do not limit the scope of protection of the present disclosure.
  • the skilled person may choose to use or not apply one or more of the above sub-circuits according to the situation, and the various combinations and modifications of the foregoing sub-circuits do not deviate from the principles of the present disclosure, and will not be repeated here.
  • Embodiments of the present disclosure provide a multiplexer that includes a plurality of multiplexing circuits.
  • the multiple multiplexing circuits are multiple multiplexing circuits in any of the above embodiments.
  • the multiplexer 110 includes a plurality of multiplexing circuits (10A, 10B, and 10C).
  • the number of multiple multiplexing circuits is three.
  • the input signal terminals IN of the multiplexing circuits 10 in the multiplexer 110 are different, the first output terminals OUT1 are different, and the second output terminals OUT2 are different.
  • the input signals received by the input signal terminals IN of the multiple multiplexing circuits 10 in the multiplexer 110 are different; for example, the input signal terminals IN of each multiplexing circuit 10 in the multiplexer 110 are The coupled data transmission channels are different.
  • the sub-pixels coupled to the first output terminals OUT1 of the multiple multiplexing circuits 10 in the multiplexer 110 are different, that is, the first output terminals OUT1 of the multiple multiplexing circuits 10 in the multiplexer 110
  • the light emission colors of the coupled sub-pixels are different; the sub-pixels coupled to the second output terminals OUT2 of the multiplexing circuits 10 in the multiplexer 110 are different, that is, the multiplexer 110
  • the light-emitting colors of the sub-pixels coupled to the second output terminal OUT2 of the multiplexing circuit 10 are different; however, the light-emitting colors of the sub-pixels coupled to the first output terminal OUT1 and the second output terminal OUT2 of each multiplexing circuit 10 are the same. .
  • the display panel further includes at least one multiplexer.
  • Each multiplexer is coupled to a plurality of pixels.
  • a multiplexer is coupled to pixel circuits of the plurality of pixels.
  • the plurality of pixels may be at least two pixels.
  • a multiplexer is coupled to two adjacent columns of pixels.
  • a multiplexer is coupled to odd-column pixels and even-column pixels.
  • the first output terminal of each multiplexing circuit in the multiplexer is coupled to odd-numbered column pixels
  • the second output terminal of each multiplexing circuit in the multiplexer is coupled to even-numbered column pixels.
  • each pixel includes a plurality of sub-pixels; in each multiplexer, the first output terminal and the second output terminal of each multiplexing circuit are respectively coupled to sub-pixels with the same emission color in different pixels. catch.
  • each pixel includes three sub-pixels, for example, the multiple multiplexing circuits in the multiplexer are three multiplexing circuits, and each multiplexing circuit is respectively associated with the sub-pixels that emit the same color light in the multiple pixels.
  • the pixel circuits in are coupled.
  • the plurality of pixels are respectively at least one pixel P O and at least one pixel PE , at least one pixel PO is in an odd-numbered column of pixels of the pixel arrangement, and at least one pixel PE is in an even-numbered column of the pixel arrangement.
  • three sub-pixels in the pixel P O in the plurality of pixels are respectively the first color sub-pixel Q R_O , the second color sub-pixel Q G_O and the third color sub-pixel Q B_O
  • the three sub-pixels in the pixel PE among the plurality of pixels are respectively the first-color sub-pixel Q R_E , the second-color sub-pixel Q G_E and the third-color sub-pixel Q B_E .
  • the multiple multiplexing circuits 10 in the multiplexer 110 are respectively a multiplexing circuit 10A, a multiplexing circuit 10B and a multiplexing circuit 10C, and the multiplexing circuit 10A is connected to the first color sub-pixel in the pixel PO .
  • Q R_O is coupled to the first color sub-pixel Q R_E in the pixel PE , that is, the first output OUT1A of the multiplexing circuit 10A is coupled to the first color sub-pixel Q R_O, and the second output terminal OUT1A of the multiplexing circuit 10A is coupled to the first color sub-pixel Q R_O .
  • the output terminal OUT2A is coupled to the first color sub-pixel QR_E ; the first output terminal OUT1A of the multiplexing circuit 10A is coupled to a row of first-color sub-pixels Q R_O , and the second output terminal OUT2A of the multiplexing circuit 10A is coupled to a row of The first color sub-pixel Q R_E is coupled; the multiplexing circuit 10B is coupled to the second color sub-pixel Q G_O in the pixel PO and the second color sub-pixel Q G_E in the pixel P E , that is, the multiplexing circuit
  • the first output terminal OUT1B of 10B is coupled to the second color sub-pixel Q G_E , the second output terminal OUT2B of the multiplexing circuit 10B is coupled to the second color sub-pixel Q G_E ; the first output terminal of the multiplexing circuit 10B OUT1B is coupled to a row of second color sub-pixels Q G_E , the second output terminal OUT2B of the multiplexing circuit
  • the input signal received by the multiplexing circuit at the input signal terminal is related to the gray scale to be displayed by the sub-pixels coupled to the first output terminal and the second output terminal of the multiplexing circuit.
  • the input signal received by the multiplexing circuit 10A at the input signal terminal INA may be the first color data signal, so that the first color sub-pixel Q R_O and the first color sub-pixel Q R_E display the first color data signal after receiving the first color data signal
  • the input signal received by the multiplexing circuit 10B at the input signal terminal INB may be the second color data signal, so that the second color sub-pixel Q G_O and the second color sub-pixel Q G_E After receiving the second color data signal, the gray scale corresponding to the second color sub-pixel is displayed;
  • the input signal received by the multiplexing circuit 10C at the input signal terminal INC may be the third color data signal, so that the third color sub-pixel Q B_O and the third color sub-pixel Q B_E displays
  • each transistor in the multiplexing circuit is an N-type transistor.
  • the first selection sub-circuit in the multiplexing circuit transmits the input signal received at the input signal terminal to the first output terminal in response to the first control signal received at the first control terminal .
  • the second selection subcircuit in the multiplexing circuit transmits the input signal received at the input signal terminal to the second output terminal in response to the third control signal received at the third control terminal.
  • the input signal received at the input signal terminal is a reference signal, for example, the voltage of the reference signal is 0V.
  • the first selection sub-circuit 11 in the multiplexing circuit 10 transmits the input signal received at the input signal terminal IN to the first control signal received at the first control terminal MUX1 in response to the first control signal received at the first control terminal MUX1.
  • the second selection subcircuit 12 in the multiplexing circuit 10 transmits the input signal received at the input signal terminal IN to the second output terminal OUT2 in response to the third control signal received at the third control terminal MUX3.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and transmits the low-voltage input signal received at the input signal terminal IN to the first output terminal OUT1, and the first transistor T1 is turned on.
  • the output signal of an output terminal OUT1 is a low-voltage signal;
  • the third transistor T3 is turned on in response to the high-voltage third control signal, and transmits the low-voltage input signal received at the input signal terminal IN to the third transistor T3.
  • Two output terminals OUT2, the output signal of the second output terminal OUT2 is a low voltage signal.
  • the signal transmitted on the data line coupled to the first output terminal OUT1 and the second output terminal OUT2 is a low voltage signal
  • each sub-pixel coupled to the first output terminal OUT1 and the second output terminal OUT2 is a low voltage signal. is reset.
  • the sub-pixels from the first row to the n-th row are scanned row by row, that is, the first row to the n-th row is scanned row by row.
  • the sub-pixels from the row to the n-th row are reset row by row to realize full screen reset.
  • the sub-pixels in the first row to the n-th row sequentially receive the first scan signal G1 and the second scan signal G2 row by row (for example, the sub-pixels in the first row receive the first scan signal G1(1) and The second scan signal G2(1), the sub-pixel in the nth row receives the first scan signal G1(n) and the second scan signal G2(n)), and writes the signal output by the multiplexing circuit into the corresponding sub-pixel pixel circuit.
  • the pixel circuit In response to the high-voltage first scan signal, the switch transistor M1 in the switch transistor M1 is turned on, and the low-voltage signal output by the first output terminal OUT1 of the multiplexing circuit is written into the control electrode of the drive transistor M2, and the drive transistor M2 For reset, the sensing transistor M3 is turned on in response to the high-voltage second scanning signal, and the low-voltage signal output by the second output terminal OUT2 of the multiplexing circuit is written into the first pole of the light-emitting device L, The light-emitting device L is reset to realize the reset of the sub-pixels.
  • the working conditions of the pixel circuits in the sub-pixels in the remaining rows are similar to the working conditions of the pixel circuits in the sub-pixels in the first row, and are not repeated here.
  • the second stage is entered after the sub-pixels in the first row to the n-th row are reset row by row.
  • the first control signal and the third control signal may be clock signals (refer to FIG. 13A ), and the first control signal and the third control signal are inverted signals of each other, for example, in the first When the control signal is a high voltage signal, the third control signal is a low voltage signal, and when the first control signal is a low voltage signal, the third control signal is a high voltage signal.
  • the first selection sub-circuit 11 and the second selection sub-circuit 12 in the multiplexing circuit 10 can work alternately, for example, the first selection sub-circuit 11 and the second selection sub-circuit 12 can output low-voltage signals alternately, that is, The first output terminal OUT1 and the second output terminal OUT2 output low voltage signals alternately.
  • the first control signal and the third control signal may be the same DC signal (refer to FIG. 13B ), for example, the first control signal and the third control signal are both DC high voltage signals.
  • the first selection sub-circuit 11 and the second selection sub-circuit 12 in the multiplexing circuit 10 can work at the same time, for example, the first selection sub-circuit 11 and the second selection sub-circuit 12 can output low-voltage signals at the same time, that is, The first output terminal OUT1 and the second output terminal OUT2 simultaneously output a low voltage signal.
  • the first selection sub-circuit in the multiplexing circuit in response to the first control signal received at the first control terminal, will The input signal is transmitted to the first output terminal.
  • the second selection subcircuit in the multiplexing circuit transmits the voltage of the supply voltage terminal to the second output terminal in response to the fourth control signal received at the fourth control terminal.
  • the first selection sub-circuit 11 in the multiplexing circuit 10 transmits the input signal received at the input signal terminal IN to the first control signal received at the first control terminal MUX1 in response to the first control signal received at the first control terminal MUX1.
  • the second selection sub-circuit 12 in the multiplexing circuit 10 transmits the voltage of the power supply voltage terminal S to the second output terminal OUT2 in response to the fourth control signal received at the fourth control terminal MUX4.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and transmits the high-voltage input signal received at the input signal terminal IN to the first output terminal OUT1, and the first transistor T1 is turned on.
  • the output signal of an output terminal OUT1 is a high voltage signal;
  • the fourth transistor T4 is turned on in response to the fourth control signal of the high voltage, and transmits the low voltage of the power supply voltage terminal S to the second output terminal OUT2.
  • the output signal of the two output terminals OUT2 is a low voltage signal.
  • a high-voltage signal is transmitted on the data line coupled to the first output terminal OUT1
  • a low-voltage signal is transmitted on the data line coupled to the second output terminal OUT2.
  • the pixel circuit in the sub-pixel coupled to the first output terminal OUT1 is written as a high voltage signal, that is, the switching transistor in the pixel circuit (eg, the switching transistor in the pixel circuit in the second row of pixels responds to a high voltage signal)
  • the first scanning signal G1 (2) of the voltage, the switching transistor is turned on writes a high voltage signal to the control electrode (ie the gate) of the driving transistor, so that the voltage of the gate of the driving transistor is a high voltage, and the driving transistor will be turned on.
  • the sensing transistor (for example, the sensing transistor in the pixel circuit in the second row of pixels in response to the high-voltage second scan signal G2(2)) is in the conducting state, and the sensing line detects the driving transistor through the sensing transistor
  • the voltage of the source of OUT1 is used to sense the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled with the first output terminal OUT1.
  • the pixel circuit of the sub-pixel coupled with the second output terminal OUT2 is written as a low voltage signal, that is, the switching transistor in the pixel circuit writes the low voltage signal into the control electrode (ie the gate) of the driving transistor, so that the driving The voltage of the gate of the transistor is a low voltage, and the driving transistors are all turned off.
  • the threshold voltage of the driving transistor in the pixel circuit of the sub-pixel coupled to the second output terminal OUT2 will not affect the sensing and the first output terminal.
  • the controlled state (such as Floating) causes the signal to have noise interference, so that the sub-pixel coupled to the second output terminal OUT2 is erroneously turned on, and the sensing line can detect the pixel circuit in the sub-pixel coupled to the first output terminal OUT1.
  • the accuracy of the threshold voltage of the driving transistor in the device improves the accuracy of the sensing data and improves the display effect.
  • the first selection sub-circuit in the multiplexing circuit transmits the voltage of the power supply voltage terminal to the second control signal received at the second control terminal in response to the second control signal received at the second control terminal. an output.
  • the second selection subcircuit in the multiplexing circuit transmits the input signal received at the input signal terminal to the second output terminal in response to the third control signal received at the third control terminal.
  • the first selection sub-circuit 11 in the multiplexing circuit 10 transmits the voltage of the power supply voltage terminal S to the first output terminal OUT1 in response to the second control signal received at the second control terminal MUX2.
  • the second selection subcircuit 12 in the multiplexing circuit 10 transmits the input signal received at the input signal terminal IN to the second output terminal OUT2 in response to the third control signal received at the third control terminal MUX3.
  • the second transistor T2 is turned on in response to the second control signal of the high voltage, and transmits the low voltage of the power supply voltage terminal to the first output terminal OUT1, and the output signal of the first output terminal OUT1 is Low voltage signal;
  • the third transistor T3 is turned on in response to the high voltage third control signal, and transmits the high voltage input signal received at the input signal terminal IN to the second output terminal OUT2, and the second output The output signal of the terminal OUT2 is a high voltage signal.
  • a low voltage signal is transmitted on the data line coupled to the first output terminal OUT1
  • a high voltage signal is transmitted on the data line coupled to the second output terminal OUT2.
  • the pixel circuit in the sub-pixel coupled to the second output terminal OUT2 is written as a high voltage signal, that is, the switching transistor in the pixel circuit writes the high voltage signal into the control electrode (ie gate) of the driving transistor, so that The voltage of the gate of the driving transistor is a high voltage, and the driving transistor will be turned on; the sensing transistor is in the on state, and the sensing line detects the voltage of the source of the driving transistor through the sensing transistor to sense the second output terminal.
  • the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel to which OUT2 is coupled is written as a low voltage signal, that is, the switching transistor in the pixel circuit writes the low voltage signal into the control electrode (ie the gate) of the driving transistor, so that the driving The voltage of the gate of the transistor is a low voltage, and the driving transistors are all turned off.
  • the threshold voltage of the driving transistor in the pixel circuit of the sub-pixel coupled to the first output terminal OUT1 will not affect the sensing and the second output terminal.
  • the sensing line can detect the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled with the second output terminal OUT2
  • the sub-pixel coupled with the first output terminal OUT1 can be prevented from having different potentials due to different potentials.
  • the controlled state (such as Floating) causes the signal to have noise interference, so that the sub-pixel coupled to the first output terminal OUT1 is erroneously turned on, and the affected sensing line can detect the pixel circuit in the sub-pixel coupled to the second output terminal OUT2
  • the accuracy of the threshold voltage of the driving transistor in the device improves the accuracy of the sensing data and improves the display effect.
  • the sub-pixels coupled to the first output end of the multiplexing circuit and the sub-pixels coupled to the second output end are located in pixels in different columns, respectively.
  • the first output terminal OUT1 of the multiplexing circuit 10 can be coupled to the monochromatic sub-pixels in the pixels in the odd-numbered columns
  • the second output terminal OUT2 of the multiplexing circuit 10 can be connected with the sub-pixels corresponding to the same color in the pixels in the even-numbered columns.
  • the first output terminal OUT1 may be coupled with the first color sub-pixels in the odd-numbered columns of pixels
  • the second output terminal OUT2 may be coupled with the first-color sub-pixels in the even-numbered columns of pixels.
  • the pixel circuit in each sub-pixel coupled to the multiplexing circuit can be coupled with one sensing line, so that one sensing line can time-divisionally sense the pixel in each sub-pixel coupled to the multiplexing circuit Threshold voltage of the drive transistor in the circuit.
  • the first output terminal and the second output terminal of the multiplexing circuit output a low voltage signal, and the data line coupled to the first output terminal is coupled to the second output terminal.
  • the signals on the connected data lines are reset.
  • the sensing lines sense the threshold voltage of the pixel circuit in the sub-pixel coupled with the first output terminal and the threshold voltage of the pixel circuit in the sub-pixel coupled with the second output terminal, respectively.
  • the first output terminal of the multiplexing circuit outputs a high voltage signal (for example, the voltage is 3V),
  • the voltage of the signal transmitted by the data line coupled to the first output end is made to be a high voltage. If the second output terminal of the multiplexing circuit has no output signal, that is, the data line coupled to the second output terminal has no signal and is in a floating state, then the transistor coupled to the data line has leakage current, resulting in the voltage of the second output terminal.
  • the voltage of the second output terminal OUT2 rises from 0V to about 0.4V, and then due to the signal noise interference of the data line, the voltage of the second output terminal further rises, for example, as shown in Figure 14A As shown, the voltage of the second output terminal OUT2 is raised from 0.4V to about 0.6V.
  • the sensing time is about several tens of milliseconds (ms)
  • noise will continue to accumulate, causing the signal on the data line coupled to the second output terminal to reach a larger voltage, thereby
  • the driving transistor in the pixel circuit coupled with the second output terminal is erroneously turned on, and the sensing line is charged, which affects the accuracy of sensing the threshold voltage in the pixel circuit coupled with the first output terminal.
  • the data line coupled to the second output end of the multiplexing circuit is The upper transmission signal (the voltage of the signal transmitted on the data line is the voltage of the power supply voltage terminal), for example, as shown in FIG. 14B, the voltage of the second output terminal OUT2 is 0V, then the second output terminal OUT2 is coupled to the data line.
  • the voltage of the signal is 0V, which can prevent the signal of the data line coupled to the second output end from being interfered, reduce noise, improve the anti-interference performance of the circuit, and prevent the drive transistor in the pixel circuit coupled to the second output end from being turned on, thereby Improved accuracy of sensing threshold voltage.
  • the transistors in each multiplexing circuit in the multiplexer are all N-type transistors.
  • a multiplexer may be coupled with two columns of pixels, eg, two columns of pixels are respectively an odd column of pixels and an even column of pixels, eg, odd and even columns of pixels coupled by the multiplexer adjacent.
  • a threshold voltage of a pixel circuit in each subpixel in each column of pixels to which the multiplexer is coupled can be detected by one sense line.
  • each pixel includes three sub-pixels, and the three sub-pixels are the first color sub-pixel, the second color sub-pixel and the third color sub-pixel; for example, referring to FIG. There are three multiplexing circuits.
  • the three multiplexing circuits are respectively a multiplexing circuit 10A, a multiplexing circuit 10B and a multiplexing circuit 10C.
  • the first output terminal OUT1A of the multiplexing circuit 10A and the multiplexing circuit 10B The first output terminal OUT1B of the multiplexing circuit 10C and the first output terminal OUT1C of the multiplexing circuit 10C are respectively coupled to the first color sub-pixels, the second color sub-pixels and the third color sub-pixels in the odd-numbered columns of pixels, and the multiplexing circuit 10A
  • the second output terminal OUT2A of the multiplexing circuit 10B, the second output terminal OUT2B of the multiplexing circuit 10B, and the second output terminal OUT2C of the multiplexing circuit 10C are respectively associated with the first color sub-pixels, the second color sub-pixels and the first color sub-pixels in the even-numbered columns of pixels.
  • Three-color sub-pixels are coupled.
  • the first selection sub-circuit therein will be responsive to the first control signal received at the first control terminal, at the input signal terminal
  • the input signal received at is transmitted to the first output terminal.
  • the second selection subcircuit in each multiplexing circuit transmits the input signal received at the input signal terminal to the second output terminal in response to the third control signal received at the third control terminal.
  • the input signal received at the input signal terminal is a reference signal, for example, the voltage of the reference signal is 0V.
  • the first selection sub-circuit 11A in the multiplexer circuit 10A responds to the first control signal received at the first control terminal MUX1, at the input signal terminal INA The received input signal is transmitted to the first output terminal OUT1A.
  • the second selection subcircuit 12A in the multiplexing circuit 10A transmits the input signal received at the input signal terminal INA to the second output terminal OUT2A in response to the third control signal received at the third control terminal MUX3.
  • the first selection sub-circuit 11B in the multiplexing circuit 10B transmits the input signal received at the input signal terminal INB to the first output terminal OUT1B in response to the first control signal received at the first control terminal MUX1.
  • the second selection sub-circuit 12B in the multiplexing circuit 10B transmits the input signal received at the input signal terminal INB to the second output terminal OUT2B in response to the third control signal received at the third control terminal MUX3.
  • the first selection sub-circuit 11C in the multiplexing circuit 10C transmits the input signal received at the input signal terminal INC to the first output terminal OUT1C in response to the first control signal received at the first control terminal MUX1.
  • the second selection subcircuit 12C in the multiplexing circuit 10C transmits the input signal received at the input signal terminal INC to the second output terminal OUT2C in response to the third control signal received at the third control terminal MUX3.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and transmits the low-voltage input signal received at the input signal terminal INA
  • the output signal of the first output terminal OUT1A is a low-voltage signal
  • the third transistor T3 is turned on in response to the high-voltage third control signal, and will receive the signal received at the input signal terminal INA.
  • the low-voltage input signal is transmitted to the second output terminal OUT2A, and the output signal of the second output terminal OUT2A is a low-voltage signal.
  • the signal transmitted on the data line coupled to the first output terminal OUT1A and the second output terminal OUT2A is a low voltage signal
  • each sub-pixel coupled to the first output terminal OUT1A and the second output terminal OUT2A is a low voltage signal. is reset.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and transmits the low-voltage input signal received at the input signal terminal INB to the first output terminal OUT1B , the output signal of the first output terminal OUT1B is a low-voltage signal;
  • the third transistor T3 is turned on in response to the high-voltage third control signal, and transmits the low-voltage input signal received at the input signal terminal INB To the second output terminal OUT2B, the output signal of the second output terminal OUT2B is a low voltage signal.
  • the signal transmitted on the data line coupled to the first output terminal OUT1B and the second output terminal OUT2B is a low voltage signal
  • each sub-pixel coupled to the first output terminal OUT1B and the second output terminal OUT2B is a low voltage signal. is reset.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and transmits the low-voltage input signal received at the input signal terminal INC to the first output terminal OUT1C , the output signal of the first output terminal OUT1C is a low-voltage signal;
  • the third transistor T3 is turned on in response to the high-voltage third control signal, and transmits the low-voltage input signal received at the input signal terminal INC To the second output terminal OUT2C, the output signal of the second output terminal OUT2C is a low voltage signal.
  • the signal transmitted on the data line coupled to the first output terminal OUT1C and the second output terminal OUT2C is a low voltage signal
  • each sub-pixel coupled to the first output terminal OUT1C and the second output terminal OUT2C is a low voltage signal. is reset.
  • the first control signal and the third control signal may be inverted signals of each other, or the first control signal and the third control signal may be the same DC signal, for example, the first control signal The same as the third control signal is a DC high voltage signal.
  • each row of sub-pixels in the display panel is reset row by row.
  • the switch transistor in the pixel circuit responds to the high-voltage first scan signal, the switch transistor is turned on, and the multiplexer is turned on.
  • the low-voltage signal output by the first output terminal of the corresponding multiplexing circuit in the pixel circuit is written into the control electrode of the driving transistor in the corresponding pixel circuit to reset the driving transistor, and the corresponding sensing transistor responds to the second high-voltage signal.
  • the sensing transistor is turned on, the low-voltage signal output by the second output terminal of the corresponding multiplexing circuit in the multiplexer is written into the first pole of the light-emitting device, the light-emitting device is reset, and the sub-pixel reset.
  • the display panel realizes full-screen reset, and at this time, the display panel is not displayed (for example, in a shutdown state).
  • the first selection sub-circuit in the multiplexing circuit in response to the first control signal received at the first control terminal, selects The input signal received at the input signal terminal is transmitted to the first output terminal.
  • the second selection subcircuit in each multiplexing circuit transmits the voltage of the power supply voltage terminal to the second output terminal in response to the fourth control signal received at the fourth control terminal.
  • the first selection sub-circuit 11A in the multiplexer circuit 10A responds to the first control signal received at the first control terminal MUX1, at the input signal terminal INA The received input signal is transmitted to the first output terminal OUT1A.
  • the second selection sub-circuit 12A in the multiplexing circuit 10A transmits the voltage of the power supply voltage terminal S to the second output terminal OUT2A in response to the fourth control signal received at the fourth control terminal MUX4.
  • the first selection sub-circuit 11B in the multiplexing circuit 10B transmits the input signal received at the input signal terminal INB to the first output terminal OUT1B in response to the first control signal received at the first control terminal MUX1.
  • the second selection sub-circuit 12B in the multiplexing circuit 10B transmits the voltage of the power supply voltage terminal S to the second output terminal OUT2B in response to the fourth control signal received at the fourth control terminal MUX4.
  • the first selection sub-circuit 11C in the multiplexing circuit 10C transmits the input signal received at the input signal terminal INC to the first output terminal OUT1C in response to the first control signal received at the first control terminal MUX1.
  • the second selection sub-circuit 12C in the multiplexing circuit 10C transmits the voltage of the power supply voltage terminal S to the second output terminal OUT2C in response to the fourth control signal received at the fourth control terminal MUX4.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and transmits the high-voltage input signal received at the input signal terminal INA To the first output terminal OUT1A, the output signal of the first output terminal OUT1A is a high voltage signal; the fourth transistor T4 is turned on in response to the fourth control signal of the high voltage, and transmits the low voltage of the power supply voltage terminal S To the second output terminal OUT2A, the output signal of the second output terminal OUT2A is a low voltage signal.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and transmits the low-voltage input signal (eg, the reference voltage) received at the input signal terminal INB to The first output terminal OUT1B, the output signal of the first output terminal OUT1B is a low voltage signal;
  • the fourth transistor T4 responds to the high voltage fourth control signal, the fourth transistor T4 is turned on, and transmits the low voltage of the power supply voltage terminal S to The second output terminal OUT2B, the output signal of the second output terminal OUT2B is a low voltage signal.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and transmits the low-voltage input signal (eg, the reference voltage) received at the input signal terminal INC to The first output terminal OUT1C, the output signal of the first output terminal OUT1C is a low voltage signal;
  • the fourth transistor T4 responds to the high voltage fourth control signal, the fourth transistor T4 is turned on, and transmits the low voltage of the power supply voltage terminal S to The second output terminal OUT2C, the output signal of the second output terminal OUT2C is a low voltage signal.
  • the data line coupled to the first output terminal OUT1A of the multiplexing circuit 10A transmits a high-voltage signal, and the other output terminals are coupled to the data line for transmitting signals. Both are low voltage signals.
  • the pixel circuit in the sub-pixel to which the first output terminal OUT1A of the multiplexing circuit 10A is coupled is written as a high voltage signal, that is, the switching transistor in the pixel circuit (for example, in the pixel circuit in the second row of pixels)
  • the switch transistor of the switch transistor is turned on) and writes the high-voltage signal into the control electrode (ie the gate) of the drive transistor, so that the voltage of the gate of the drive transistor is a high voltage , the driving transistor will be turned on;
  • the sensing transistor (for example, the sensing transistor in the pixel circuit in the second row of pixels in response to the high-voltage second scan signal G2(2)) is in the conducting state, and the sensing line passes through
  • the sensing transistor detects the voltage of the source of the driving transistor to sense the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the first output terminal OUT1A of the multiplexing circuit 10A.
  • the pixel circuits of the sub-pixels coupled to the remaining output terminals are written as low-voltage signals, that is, the switching transistors in the pixel circuits write the low-voltage signals into the control electrodes (ie gates) of the driving transistors, so that the driving transistors The voltage of the gate is low, the driving transistors are all turned off, and the threshold voltages of the driving transistors in the pixel circuits of the sub-pixels coupled to the remaining output terminals will not affect the sensing and multiplexing circuit 10A.
  • the sense line can detect the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel (eg, the first color sub-pixel in the odd-column pixel) coupled to the first output terminal OUT1A of the multiplexing circuit 10A During the process, the sub-pixels coupled with the remaining output terminals can be prevented from causing noise interference in the signal due to an uncontrolled potential state (such as Floating), so that the sub-pixels coupled with the remaining output terminals are erroneously turned on, affecting the sensing.
  • the line can detect the accuracy of the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the first output terminal OUT1A of the multiplexing circuit 10A, thereby improving the accuracy of sensing data and improving the display effect.
  • the sensing line when the sensing line is coupled to multiple pixel circuits, the threshold voltages of the driving transistors in the multiple pixel circuits need to be time-divisionally sensed.
  • one sensing line is coupled to two adjacent columns of pixels.
  • the sensing line senses the threshold voltage of the driving transistor in each pixel circuit at different times. For example, for each sensing line, the threshold voltages of the first color sub-pixels, the second color sub-pixels and the third color sub-pixels in the pixels of the odd-numbered columns to which it is coupled can be sensed first, and then the threshold voltages of the sub-pixels of the second color and the third color sub-pixels can be sensed.
  • Threshold voltages in the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels in the even-numbered columns of pixels that are coupled Exemplarily, each pixel in the display panel is sensed row by row, and for a row of pixels, the sensing line senses the threshold voltage corresponding to the pixel circuit in each sub-pixel column by column.
  • sensing the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the first output terminal OUT1A of the multiplexing circuit 10A is to sense the sub-pixel of the first color in the pixels in the odd-numbered columns.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and the low-voltage input received at the input signal terminal INA is turned on.
  • the signal (for example, the reference voltage) is transmitted to the first output terminal OUT1A, and the output signal of the first output terminal OUT1A is a low voltage signal;
  • the fourth transistor T4 responds to the fourth control signal of high voltage, the fourth transistor T4 is turned on, and the power supply
  • the low voltage of the voltage terminal S is transmitted to the second output terminal OUT2A, and the output signal of the second output terminal OUT2A is a low voltage signal.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and transmits the high-voltage input signal received at the input signal terminal INB to the first output terminal OUT1B , the output signal of the first output terminal OUT1B is a high voltage signal;
  • the fourth transistor T4 is turned on in response to the fourth control signal of the high voltage, and transmits the low voltage of the power supply voltage terminal S to the second output terminal OUT2B , the output signal of the second output terminal OUT2B is a low voltage signal.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and transmits the low-voltage input signal (eg, the reference voltage) received at the input signal terminal INC to The first output terminal OUT1C, the output signal of the first output terminal OUT1C is a low voltage signal;
  • the fourth transistor T4 responds to the high voltage fourth control signal, the fourth transistor T4 is turned on, and transmits the low voltage of the power supply voltage terminal S to The second output terminal OUT2C, the output signal of the second output terminal OUT2C is a low voltage signal.
  • the data line coupled to the first output terminal OUT1B of the multiplexing circuit 10B transmits the high-voltage signal, and the other output terminals are coupled to the data line for transmitting the signal Both are low voltage signals.
  • the pixel circuit in the sub-pixel to which the first output terminal OUT1B of the multiplexing circuit 10B is coupled is written as a high-voltage signal, that is, the switching transistor in the pixel circuit writes the high-voltage signal into the control electrode of the driving transistor ( That is, the gate), so that the voltage of the gate of the driving transistor is a high voltage, and the driving transistor will be turned on; the sensing transistor is in an on state, and the sensing line detects the voltage of the source of the driving transistor through the sensing transistor to sense The threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the first output terminal OUT1B of the multiplexing circuit 10B is measured.
  • the pixel circuits of the sub-pixels coupled to the remaining output terminals are written as low-voltage signals, that is, the switching transistors in the pixel circuits write the low-voltage signals into the control electrodes (ie gates) of the driving transistors, so that the driving transistors The voltage of the gate is low, the driving transistors are all turned off, and the threshold voltages of the driving transistors in the pixel circuits of the sub-pixels coupled to the remaining output terminals will not affect the sensing and multiplexing circuit 10B.
  • the sense line can detect the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the first output terminal OUT1B of the multiplexing circuit 10B (eg, the second color sub-pixel in the odd-column pixels) During the process, it can avoid that the sub-pixels coupled to the remaining output terminals cause noise interference in the signal due to the uncontrolled potential (such as Floating), so that the sub-pixels coupled to the remaining output terminals are erroneously turned on, affecting the sensing.
  • the line can detect the accuracy of the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the first output terminal OUT1B of the multiplexing circuit 10B, thereby improving the accuracy of sensing data and improving the display effect.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and the low-voltage input received at the input signal terminal INA is turned on.
  • the signal (for example, the reference voltage) is transmitted to the first output terminal OUT1A, and the output signal of the first output terminal OUT1A is a low voltage signal;
  • the fourth transistor T4 responds to the fourth control signal of high voltage, the fourth transistor T4 is turned on, and the power supply
  • the low voltage of the voltage terminal S is transmitted to the second output terminal OUT2A, and the output signal of the second output terminal OUT2A is a low voltage signal.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and transmits the low-voltage input signal (eg, the reference voltage) received at the input signal terminal INB to The first output terminal OUT1B, the output signal of the first output terminal OUT1B is a low voltage signal;
  • the fourth transistor T4 responds to the high voltage fourth control signal, the fourth transistor T4 is turned on, and transmits the low voltage of the power supply voltage terminal S to The second output terminal OUT2B, the output signal of the second output terminal OUT2B is a low voltage signal.
  • the first transistor T1 is turned on in response to the high-voltage first control signal, and transmits the high-voltage input signal received at the input signal terminal INC to the first output terminal OUT1C , the output signal of the first output terminal OUT1C is a high voltage signal;
  • the fourth transistor T4 is turned on in response to the fourth control signal of the high voltage, and transmits the low voltage of the power supply voltage terminal S to the second output terminal OUT2C , the output signal of the second output terminal OUT2C is a low voltage signal.
  • the data line coupled to the first output terminal OUT1C of the multiplexing circuit 10C transmits the high-voltage signal, and the other output terminals are coupled to the data line for transmitting the signal Both are low voltage signals.
  • the pixel circuit in the sub-pixel to which the first output terminal OUT1C of the multiplexing circuit 10C is coupled is written as a high-voltage signal, that is, the switching transistor in the pixel circuit writes the high-voltage signal into the control electrode of the driving transistor ( That is, the gate), so that the voltage of the gate of the driving transistor is a high voltage, and the driving transistor will be turned on; the sensing transistor is in an on state, and the sensing line detects the voltage of the source of the driving transistor through the sensing transistor to sense The threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the first output terminal OUT1C of the multiplexing circuit 10C is measured.
  • the pixel circuits of the sub-pixels coupled to the remaining output terminals are written as low-voltage signals, that is, the switching transistors in the pixel circuits write the low-voltage signals into the control electrodes (ie gates) of the driving transistors, so that the driving transistors The voltage of the gate is low, the driving transistors are all turned off, and the threshold voltages of the driving transistors in the pixel circuits of the sub-pixels coupled to the other output terminals will not affect the sensing and multiplexing circuit 10C.
  • the sense line can detect the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel (eg, the third color sub-pixel in the odd-column pixel) coupled to the first output terminal OUT1C of the multiplexing circuit 10C During the process, the sub-pixels coupled with the remaining output terminals can be prevented from causing noise interference in the signal due to an uncontrolled potential state (such as Floating), so that the sub-pixels coupled with the remaining output terminals are erroneously turned on, affecting the sensing.
  • the line can detect the accuracy of the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the first output terminal OUT1C of the multiplexing circuit 10C, thereby improving the accuracy of sensing data and improving the display effect.
  • the first selection sub-circuit in the multiplexing circuit transmits the voltage of the power supply voltage terminal to the first selection sub-circuit in response to the second control signal received at the second control terminal output.
  • the second selection subcircuit in the multiplexing circuit transmits the input signal received at the input signal terminal to the second output terminal in response to the third control signal received at the third control terminal.
  • the first selection sub-circuit 11A in the multiplexer circuit 10A responds to the second control signal received at the second control terminal MUX2 to change the voltage of the power supply voltage terminal S transmitted to the first output terminal OUT1A.
  • the second selection subcircuit 12A in the multiplexing circuit 10A transmits the input signal received at the input signal terminal INA to the second output terminal OUT2A in response to the third control signal received at the third control terminal MUX3.
  • the first selection sub-circuit 11B in the multiplexing circuit 10B transmits the voltage of the power supply voltage terminal S to the first output terminal OUT1B in response to the second control signal received at the second control terminal MUX2.
  • the second selection sub-circuit 12B in the multiplexing circuit 10B transmits the input signal received at the input signal terminal INB to the second output terminal OUT2B in response to the third control signal received at the third control terminal MUX3.
  • the first selection sub-circuit 11C in the multiplexing circuit 10C transmits the voltage of the power supply voltage terminal S to the first output terminal OUT1C in response to the second control signal received at the second control terminal MUX2.
  • the second selection subcircuit 12C in the multiplexing circuit 10C transmits the input signal received at the input signal terminal INC to the second output terminal OUT2C in response to the third control signal received at the third control terminal MUX3.
  • the second transistor T2 is turned on in response to the second control signal of the high voltage, and transmits the low voltage of the power supply voltage terminal S to the first output terminal OUT1A , the output signal of the first output terminal OUT1A is a low-voltage signal;
  • the third transistor T3 is turned on in response to the high-voltage third control signal, and transmits the high-voltage input signal received at the input signal terminal INA To the second output terminal OUT2A, the output signal of the second output terminal OUT2A is a high voltage signal.
  • the second transistor T2 is turned on in response to the second control signal of the high voltage, and the second transistor T1 is turned on to transmit the low voltage of the power supply voltage terminal S to the first output terminal OUT1B, the first output terminal OUT1B
  • the output signal is a low-voltage signal
  • the third transistor T3 is turned on in response to the high-voltage third control signal, and transmits the low-voltage input signal received at the input signal terminal INB to the second output terminal OUT2B , the output signal of the second output terminal OUT2B is a low voltage signal.
  • the second transistor T2 is turned on in response to the second control signal of the high voltage, and transmits the low voltage of the power supply voltage terminal S to the first output terminal OUT1C, the first output terminal OUT1C
  • the output signal is a low-voltage signal
  • the third transistor T3 is turned on in response to the high-voltage third control signal, and transmits the low-voltage input signal received at the input signal terminal INB to the second output terminal OUT2C , the output signal of the second output terminal OUT2C is a low voltage signal.
  • the data line coupled to the second output terminal OUT2A of the multiplexing circuit 10A transmits the high-voltage signal, and the other output terminals are coupled to the data line for transmitting the signal Both are low voltage signals.
  • the pixel circuit in the sub-pixel to which the second output terminal OUT2A of the multiplexing circuit 10A is coupled is written as a high-voltage signal, that is, the switching transistor in the pixel circuit writes the high-voltage signal into the control electrode of the driving transistor ( That is, the gate), so that the voltage of the gate of the driving transistor is a high voltage, and the driving transistor will be turned on; the sensing transistor is in an on state, and the sensing line detects the voltage of the source of the driving transistor through the sensing transistor to sense The threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the second output terminal OUT2A of the multiplexing circuit 10A is measured.
  • the pixel circuits of the sub-pixels coupled to the remaining output terminals are written as low-voltage signals, that is, the switching transistors in the pixel circuits write the low-voltage signals into the control electrodes (ie gates) of the driving transistors, so that the driving transistors
  • the voltage of the gate is low voltage, the driving transistors are all turned off, and the threshold voltages of the driving transistors in the pixel circuits of the sub-pixels coupled to the other output terminals will not affect the sensing and multiplexing circuit 10A.
  • the sense line can detect the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel (eg, the first color sub-pixel in the even-numbered column pixel) coupled to the second output terminal OUT2A of the multiplexing circuit 10A During the process, it can avoid that the sub-pixels coupled to the remaining output terminals cause noise interference in the signal due to the uncontrolled potential (such as Floating), so that the sub-pixels coupled to the remaining output terminals are erroneously turned on, affecting the sensing.
  • the line can detect the accuracy of the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the second output terminal OUT2A of the multiplexing circuit 10A, thereby improving the accuracy of sensing data and improving the display effect.
  • the second transistor T2 is turned on in response to the second control signal of the high voltage, and transmits the low voltage of the power supply voltage terminal S to the first output terminal OUT1A, the output signal of the first output terminal OUT1A is a low-voltage signal; the third transistor T3 is turned on in response to the high-voltage third control signal, and the low-voltage input received at the input signal terminal INA The signal is transmitted to the second output terminal OUT2A, and the output signal of the second output terminal OUT2A is a low voltage signal.
  • the second transistor T2 is turned on in response to the second control signal of the high voltage, and the second transistor T1 is turned on to transmit the low voltage of the power supply voltage terminal S to the first output terminal OUT1B, the first output terminal OUT1B
  • the output signal is a low-voltage signal
  • the third transistor T3 is turned on in response to the high-voltage third control signal, and transmits the high-voltage input signal received at the input signal terminal INB to the second output terminal OUT2B , the output signal of the second output terminal OUT2B is a high voltage signal.
  • the second transistor T2 is turned on in response to the second control signal of the high voltage, and transmits the low voltage of the power supply voltage terminal S to the first output terminal OUT1C, the first output terminal OUT1C
  • the output signal is a low-voltage signal
  • the third transistor T3 is turned on in response to the high-voltage third control signal, and transmits the low-voltage input signal received at the input signal terminal INB to the second output terminal OUT2C , the output signal of the second output terminal OUT2C is a low voltage signal.
  • the data line coupled to the second output terminal OUT2B of the multiplexing circuit 10B transmits the high-voltage signal, and the other output terminals are coupled to the data line for transmitting the signal Both are low voltage signals.
  • the pixel circuit in the sub-pixel to which the second output terminal OUT2B of the multiplexing circuit 10B is coupled is written as a high-voltage signal, that is, the switching transistor in the pixel circuit writes the high-voltage signal into the control electrode of the driving transistor ( That is, the gate), so that the voltage of the gate of the driving transistor is a high voltage, and the driving transistor will be turned on; the sensing transistor is in an on state, and the sensing line detects the voltage of the source of the driving transistor through the sensing transistor to sense The threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the second output terminal OUT2B of the multiplexing circuit 10B is measured.
  • the pixel circuits of the sub-pixels coupled to the remaining output terminals are written as low-voltage signals, that is, the switching transistors in the pixel circuits write the low-voltage signals into the control electrodes (ie gates) of the driving transistors, so that the driving transistors The voltage of the gate is low, the driving transistors are all turned off, and the threshold voltages of the driving transistors in the pixel circuits of the sub-pixels coupled to the remaining output terminals will not affect the sensing and multiplexing circuit 10B.
  • the sense line can detect the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel (eg, the second color sub-pixel in the even-numbered column pixel) coupled to the second output terminal OUT2B of the multiplexing circuit 10B During the process, it can avoid that the sub-pixels coupled to the remaining output terminals cause noise interference in the signal due to the uncontrolled potential (such as Floating), so that the sub-pixels coupled to the remaining output terminals are erroneously turned on, affecting the sensing.
  • the line can detect the accuracy of the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the second output terminal OUT2B of the multiplexing circuit 10B, thereby improving the accuracy of sensing data and improving the display effect.
  • the second transistor T2 is turned on in response to the second control signal of the high voltage, and transmits the low voltage of the power supply voltage terminal S to the first output terminal OUT1A, the output signal of the first output terminal OUT1A is a low-voltage signal; the third transistor T3 is turned on in response to the high-voltage third control signal, and the low-voltage input received at the input signal terminal INA The signal is transmitted to the second output terminal OUT2A, and the output signal of the second output terminal OUT2A is a low voltage signal.
  • the second transistor T2 is turned on in response to the second control signal of the high voltage, and the second transistor T1 is turned on to transmit the low voltage of the power supply voltage terminal S to the first output terminal OUT1B, the first output terminal OUT1B
  • the output signal is a low-voltage signal
  • the third transistor T3 is turned on in response to the high-voltage third control signal, and transmits the low-voltage input signal received at the input signal terminal INB to the second output terminal OUT2B , the output signal of the second output terminal OUT2B is a low voltage signal.
  • the second transistor T2 is turned on in response to the second control signal of the high voltage, and transmits the low voltage of the power supply voltage terminal S to the first output terminal OUT1C, the first output terminal OUT1C
  • the output signal is a low-voltage signal
  • the third transistor T3 is turned on in response to the high-voltage third control signal, and transmits the high-voltage input signal received at the input signal terminal INB to the second output terminal OUT2C , the output signal of the second output terminal OUT2C is a high voltage signal.
  • the data line coupled to the second output terminal OUT2C of the multiplexing circuit 10C transmits the high-voltage signal, and the other output terminals are coupled to the data line for transmitting the signal Both are low voltage signals.
  • the pixel circuit in the sub-pixel to which the second output terminal OUT2C of the multiplexing circuit 10C is coupled is written as a high-voltage signal, that is, the switching transistor in the pixel circuit writes the high-voltage signal into the control electrode of the driving transistor ( That is, the gate), so that the voltage of the gate of the driving transistor is a high voltage, and the driving transistor will be turned on; the sensing transistor is in an on state, and the sensing line detects the voltage of the source of the driving transistor through the sensing transistor to sense The threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the second output terminal OUT2C of the multiplexing circuit 10C is measured.
  • the pixel circuits of the sub-pixels coupled to the remaining output terminals are written as low-voltage signals, that is, the switching transistors in the pixel circuits write the low-voltage signals into the control electrodes (ie gates) of the driving transistors, so that the driving transistors The voltage of the gate is low, the driving transistors are all turned off, and the threshold voltages of the driving transistors in the pixel circuits of the sub-pixels coupled to the other output terminals will not affect the sensing and multiplexing circuit 10C.
  • the sense line can detect the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel (eg, the third color sub-pixel in the pixels in the even columns) coupled to the second output terminal OUT2C of the multiplexing circuit 10C.
  • the sub-pixels coupled to the remaining output terminals cause noise interference in the signal due to the uncontrolled potential (such as Floating), so that the sub-pixels coupled to the remaining output terminals are erroneously turned on, affecting the sensing.
  • the line can detect the accuracy of the threshold voltage of the driving transistor in the pixel circuit in the sub-pixel coupled to the second output terminal OUT2C of the multiplexing circuit 10C, thereby improving the accuracy of sensing data and improving the display effect.
  • the sensing line is between the time when the sensing of the first color sub-pixels in the odd-column pixels in one row of pixels ends to the time when the second-color sub-pixels in the odd-column pixels in one row begin to be sensed. (eg time period w in FIG.
  • the sensing line for example, for the second row of pixels, the first scan signal G1( 2 ) and the second scan signal G2 ( 2 ) continue to be high voltage signals, the pixel
  • the switching transistor and the sensing transistor in the circuit are turned on, the input signal is a low-voltage signal (ie, a reset signal), the signal on the data line is a low-voltage signal, and the signals on the sensing line are all low-voltage signals at this time.
  • the data lines in the display panel transmit data signals required for display.
  • the multiplexing circuit will not output the voltage of the power supply voltage terminal, that is, neither the first output terminal nor the second output terminal will output the voltage of the power supply voltage terminal.
  • the second transistor in the first selection sub-circuit is turned off in response to the second control signal (eg, a low voltage signal), and the second transistor does not transmit the voltage of the power supply voltage terminal to the first
  • the fourth transistor in the second selection sub-circuit responds to the fourth control signal (eg, a low voltage signal), the fourth transistor is turned off, and the fourth transistor does not transmit the voltage of the power supply voltage end to the second output end.
  • the first transistor in the first selection sub-circuit responds to the first control signal (such as a high voltage signal), the first transistor is turned on, and transmits the input signal from the input signal terminal to the first output terminal, and the second selects
  • the third transistor in the sub-circuit is turned on in response to a third control signal (eg, a high voltage signal), and transmits the input signal from the input signal terminal to the second output terminal.
  • a third control signal eg, a high voltage signal
  • the first voltage control sub-circuit controls the voltage of the second control signal received at the second control terminal by the first selection sub-circuit according to the voltage at the power supply voltage terminal and the second control signal received at the second control terminal .
  • the voltage of the power supply voltage terminal is a low voltage
  • the first voltage control sub-circuit can control the second control signal received at the second control terminal by the first selection sub-circuit according to the second control signal of the low voltage received at the second control terminal.
  • the voltage of the control signal is a low voltage.
  • the first voltage controls the storage function of the first capacitor in the sub-circuit, stores the second control signal of low voltage, and controls the voltage of the control electrode of the second transistor in the first selection sub-circuit to be a low voltage, and controls the first
  • the second control signal that the second transistor in the selection sub-circuit responds to is a low voltage, and at this time, the voltage of the control electrode of the second transistor is a low voltage, so that the second transistor is turned off, and the voltage of the power supply voltage terminal will not be transmitted to the first output.
  • the second voltage control subcircuit controls the voltage of the fourth control signal received at the fourth control terminal by the second selection subcircuit according to the voltage of the power supply voltage terminal and the fourth control signal received at the fourth control terminal.
  • the voltage of the power supply voltage terminal is a low voltage
  • the second voltage control sub-circuit controls the fourth control signal received by the second selection sub-circuit at the fourth control terminal.
  • the voltage of the control signal is a low voltage
  • the second voltage controls the storage function of the second capacitor in the sub-circuit, stores the fourth control signal of low voltage, and controls the voltage of the control electrode of the fourth transistor in the second selection sub-circuit to be a low voltage, controls the second
  • the fourth control signal that the fourth transistor in the selection sub-circuit responds to is a low voltage, and at this time, the voltage of the control electrode of the fourth transistor is a low voltage, so that the fourth transistor is turned off, and the voltage of the power supply voltage terminal will not be transmitted to the second output.
  • the second control signal line can transmit the second control signal to the second control terminal coupled thereto within a short period of time, and the second transistor in the first selection sub-circuit responds to the second control signal signal (eg, a low level voltage), the second transistor is turned off, the first capacitor in the first voltage control sub-circuit stores the second control signal, and the first capacitor can provide the second control signal to the second transistor, so that The second transistor maintains an off state.
  • the second control signal line does not need to continuously transmit the second control signal to the second control terminal, that is, the second control signal line can stop supplying power to the second control terminal, thereby reducing the hardware transient of the display device. power consumption.
  • the fourth control signal line can transmit the fourth control signal to the fourth control terminal coupled thereto within a short period of time, and the fourth transistor in the second selection sub-circuit responds to the fourth control signal ( For example, a low level voltage), the fourth transistor is turned off, the second capacitor in the second voltage control sub-circuit stores the fourth control signal, and the second capacitor can provide the fourth control signal to the fourth transistor, so that the fourth The transistor remains off.
  • the fourth control signal line does not need to continuously transmit the fourth control signal to the fourth control terminal, that is, the fourth control signal line can stop supplying power to the fourth control terminal, thereby reducing the hardware transient of the display device. power consumption.
  • the display device 200 further includes at least one data signal transmission channel 211 .
  • a multiplexing circuit is coupled to the source driver through a data transmission channel.
  • the multiplexer is coupled to the source driver through three data transmission channels.
  • an output port of the source driver 210 is coupled to an input signal terminal IN of the multiplexing circuit 10 through a data transmission channel 211 . Therefore, the number of output ports of the source driver 210 is reduced, and the number of the data transmission channels 211 to which the source driver 210 is coupled with the multiplexing circuit 10 is reduced.
  • the source driver is bound to the base substrate of the display panel and coupled to the multiplexing circuit.
  • the display device further includes an ADC (Analog to Digital Converter).
  • the ADC is coupled to a plurality of sense lines.
  • the ADC is configured to sense the signal from the sense line.
  • the ADC samples the sensing line to sense the sensing line.
  • the threshold voltage of the drive transistor of a pixel circuit For example, referring to FIG. 15 , within a preset time u before the end of each sensing line sensing the threshold voltage of the driving transistor of one pixel circuit, the ADC responds to the sensing control signal Spr_L, eg, the voltage of the sensing control signal Spr_L For a high voltage, the ADC detects the voltage of the signal on the sense line.
  • the ADC senses the threshold voltage of the driving transistor in the corresponding pixel circuit sensed on each sensing line, and compensates the threshold voltage to the corresponding pixel circuit through the source driver.
  • the above-mentioned preset time is the time for the ADC to sense the signal from each sensing line, and the length of the preset time can be designed according to the actual situation, which is not limited here.
  • the display device may superimpose the sensed threshold voltage and the display data signal of the pixel circuit to obtain a superimposed data signal, and input the superimposed signal into the pixel circuit.
  • the actual threshold voltage of the driving transistor is internally compensated by the superimposed data signal, and the mobility (K) of the driving transistor can also be detected during the blanking phase (Blank).
  • the multiplexing circuit includes a first selection sub-circuit and a second selection sub-circuit.
  • the first selection sub-circuit is coupled to the first control terminal, the second control terminal, the input signal terminal, the power supply voltage terminal and the first output terminal.
  • the second selection sub-circuit is coupled to the third control terminal, the fourth control terminal, the input signal terminal, the power supply voltage terminal and the second output terminal.
  • a method for driving a multiplexing circuit includes: a first selector circuit transmits an input signal received at an input signal end to a first output end in response to a first control signal received at a first control end; a second selector circuit The circuit transmits the voltage of the supply voltage terminal to the second output terminal in response to the fourth control signal received at the fourth control terminal.
  • the first selection sub-circuit transmits the voltage of the power supply voltage terminal to the first output terminal in response to the second control signal received at the second control terminal; the second selection sub-circuit is responsive to the third control signal received at the third control terminal signal that transmits the input signal received at the input signal terminal to the second output terminal.
  • the above-mentioned driving method of the multiplexing circuit has the same beneficial effects as the above-mentioned multiplexing circuit, which will not be repeated here.
  • the multiplexer includes a plurality of multiplexing circuits, each multiplexing circuit includes a first selection sub-circuit and a second selection sub-circuit, the first selection sub-circuit is connected to the first control terminal and the second control terminal. , the input signal terminal, the power supply voltage terminal and the first output terminal are coupled; the second selection sub-circuit is coupled with the third control terminal, the fourth control terminal, the input signal terminal, the power supply voltage terminal and the second output terminal.
  • the input signal terminals of the multiplexing circuits are different, the first output terminals are different, and the second output terminals are different.
  • the driving method of the multiplexer including:
  • the first selection sub-circuit in each multiplexing circuit transmits the input signal received at the input signal terminal to which it is coupled to the second control signal to which it is coupled in response to the first control signal received at the first control terminal.
  • an output terminal; the second selection sub-circuit in each multiplexing circuit transmits the voltage of the power supply voltage terminal to the second output terminal to which it is coupled in response to the fourth control signal received at the fourth control terminal.
  • the first selection sub-circuit in each multiplexing circuit transmits the voltage of the supply voltage terminal to the first output terminal to which it is coupled in response to the second control signal received at the second control terminal; each multiplexing circuit The second selection subcircuit in the circuit transmits the input signal received at the input signal terminal to which it is coupled to the second output terminal to which it is coupled in response to the third control signal received at the third control terminal.
  • the above-mentioned driving method of the multiplexer has the same beneficial effects as the above-mentioned multiplexer, which will not be repeated here.
  • each pixel in a display panel in a display device includes a plurality of sub-pixels, each sub-pixel includes a pixel circuit, and the pixel circuit includes a driving transistor.
  • the display panel also includes a plurality of sensing lines. A plurality of pixels coupled to a multiplexer in a display panel are coupled to one sensing line, that is, a pixel circuit in each sub-pixel of a plurality of pixels to which the multiplexer is coupled is coupled to one sensing line coupled.
  • the driving method of the display device includes:
  • the source driver provides input signals to each of the multiplexing circuits in the multiplexer in the display panel.
  • the input signals received by the multiplexing circuits in the multiplexer are not identical.
  • one of the multiplexing circuits receives a high-voltage (high-level) input signal
  • the remaining multiplexing circuits receive a low-voltage (low-level) input signal, in this case, a high voltage
  • the threshold voltages of the drive transistors of the pixel circuits of the sub-pixels in the pixels to which the multiplexing circuit of the input signal is coupled can be sensed by the sense lines.
  • the first selection sub-circuit in the multiplexing circuit in the multiplexer transmits the input signal received at the input signal terminal to which it is coupled to the input signal terminal to which it is coupled in response to the first control signal received at the first control terminal.
  • the first output terminal is coupled;
  • the second selection sub-circuit in the multiplexing circuit in the multiplexer is responsive to the fourth control signal received at the fourth control terminal, and transmits the voltage of the power supply voltage terminal to its coupled connected to the second output terminal.
  • the sensing line senses the threshold voltage of the driving transistor of the pixel circuit in the sub-pixel in the pixel to which the first output terminal is coupled.
  • one sensing line senses the threshold voltage of the driving transistor of one pixel circuit at the same time. That is, for the threshold voltages of the driving transistors in the pixel circuits to which the first output ends of the multiple multiplexing circuits in the multiplexer are coupled, one sensing line senses at different times respectively.
  • the first output terminal of one multiplexing circuit in the multiplexer outputs a high voltage signal
  • the first output terminals of the other multiplexing circuits output low voltage signals.
  • a threshold voltage of a driving transistor in a pixel circuit in a pixel coupled to an output terminal is sensed.
  • the output signals of the second output terminal of one multiplexing circuit and the first output terminals and the second output terminals of the other multiplexing circuits are all low-voltage signals. In this way, the accuracy of the sensing threshold voltage of the sensing line will not be affected.
  • the first selection subcircuit in the multiplexing circuit in the multiplexer transmits the voltage of the power supply voltage terminal to the first output terminal to which it is coupled in response to the second control signal received at the second control terminal;
  • the second selection sub-circuit in the multiplexing circuit in the way selector transmits the input signal received at the input signal terminal to which it is coupled to the third control signal received at the third control terminal coupled to the second output.
  • the sensing line senses the threshold voltage of the driving transistor of the pixel circuit in the sub-pixel in the pixel to which the second output terminal is coupled.
  • one sensing line senses at different times respectively.
  • the second output terminal of one multiplexing circuit in the multiplexer outputs a high voltage signal
  • the second output terminals of the other multiplexing circuits output low voltage signals.
  • the threshold voltage of the driving transistor in the pixel circuit in the pixel to which the two output terminals are coupled is sensed.
  • the first output terminal of one multiplexing circuit and the output signals of the first output terminal and the second output terminal of the other multiplexing circuits are all low-voltage signals. In this way, the accuracy of the sensing threshold voltage of the sensing line will not be affected.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种多路选择电路(10)，包括：第一选择子电路(11)和第二选择子电路(12)。第一选择子电路(11)响应于在第一控制端(MUX1)接收的第一控制信号，将在输入信号端(IN)处接收的输入信号传输至第一输出端(OUT1)；响应于在第二控制端处(MUX2)接收的第二控制信号，将电源电压端(S)的电压传输至第一输出端(OUT1)。第二选择子电路(12)响应于在第三控制端(MUX3)处接收的第三控制信号，将在输入信号端(IN)处接收的输入信号传输至第二输出端(OUT2)；响应于在第四控制端(MUX4)处接收的第四控制信号，将电源电压端(S)的电压传输至第二输出端(OUT2)。

Description

多路选择电路、多路选择器、驱动方法、显示面板、显示装置
本申请要求于2020年10月21日提交的、申请号为202011133273.5的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种多路选择电路、多路选择器、驱动方法、显示面板、显示装置。
背景技术
自发光器件具有亮度高、发光颜色连续可调、成本低、响应速度快、能耗小、驱动电压低、工作温度范围宽、生产工艺简单、发光效率高等优点，而广泛应用于各种具有高分辨率彩色屏幕的终端显示产品。
发明内容
一方面，提供一种多路选择电路。所述多路选择电路包括第一选择子电路和第二选择子电路。所述第一选择子电路与第一控制端、第二控制端、输入信号端、电源电压端和第一输出端耦接。所述第二选择子电路与第三控制端、第四控制端、所述输入信号端、所述电源电压端和第二输出端耦接。所述第一选择子电路被配置为响应于在所述第一控制端接收的第一控制信号，将在所述输入信号端处接收的输入信号传输至所述第一输出端；及，响应于在所述第二控制端处接收的第二控制信号，将所述电源电压端的电压传输至所述第一输出端。所述第二选择子电路被配置为响应于在所述第三控制端处接收的第三控制信号，将在所述输入信号端处接收的输入信号传输至所述第二输出端；及，响应于在所述第四控制端处接收的第四控制信号，将所述电源电压端的电压传输至所述第二输出端。
在一些实施例中，所述第一选择子电路包括第一晶体管和第二晶体管。所述第一晶体管的控制极与所述第一控制端耦接，所述第一晶体管的第一极与所述输入信号端耦接，所述第一晶体管的第二极与所述第一输出端耦接。所述第二晶体管的控制极与所述第二控制端耦接，所述第二晶体管的第一极与所述电源电压端耦接，所述第二晶体管的第二极与所述第一输出端耦接。
在一些实施例中，所述第二选择子电路包括第三晶体管和第四晶体管。所述第三晶体管的控制极与所述第一控制端耦接，所述第三晶体管的第一极与所述输入信号端耦接，所述第三晶体管的第二极与所述第二输出端耦接。所述第四晶体管的控制极与所述第二控制端耦接，所述第四晶体管的第一极与所述电源电压端耦接，所述第四晶体管的第二极与所述第二输出端耦接。
在一些实施例中，所述多路选择电路还包括第一电压控制子电路。所述第一电压控制子电路与所述电源电压端、所述第二控制端和所述第一选择子电路耦接。所述第一电压控制子电路被配置为，根据所述电源电压端的电压和在所述第二控制端处接收的第二控制信号，控制所述第一选择子电路在所述第二控制端处接收的第二控制信号的电压。
在一些实施例中，所述第一电压控制子电路包括第一电容器。所述第一电容器的第一端与所述电源电压端耦接，所述第一电容器的第二端与所述第二控制端和所述第一选择子电路耦接。
在一些实施例中，所述多路选择电路还包括第二电压控制子电路。所述第二电压控制子电路与所述电源电压端、所述第四控制端和所述第二选择子电路耦接。所述第二电压控制子电路被配置为，根据所述电源电压端的电压和在所述第四控制端处接收的第四控制信号，控制所述第二选择子电路在所述第四控制端处接收的第四控制信号的电压。
在一些实施例中，所述第二电压控制子电路包括第二电容器。所述第二电容器的第一端与所述电源电压端耦接，所述第二电容器的第二端与所述第四控制端耦接。
另一方面，提供一种多路选择电路。所述多路选择电路包括第一晶体管、第二晶体管、第三晶体管和第四晶体管。所述第一晶体管的控制极与第一控制端耦接，所述第一晶体管的第一极与输入信号端耦接，所述第一晶体管的第二极与第一输出端耦接。所述第二晶体管的控制极与第二控制端耦接，所述第二晶体管的第一极与电源电压端耦接，所述第二晶体管的第二极与所述第一输出端耦接。所述第三晶体管的控制极与所述第一控制端耦接，所述第三晶体管的第一极与所述输入信号端耦接，所述第三晶体管的第二极与第二输出端耦接。所述第四晶体管的控制极与所述第二控制端耦接，所述第四晶体管的第一极与所述电源电压端耦接，所述第四晶体管的第二极与所述第二输出端耦接。
又一方面，提供一种多路选择器。所述多路选择器包括：多个如上述任一实施例所述的多路选择电路。多个所述多路选择电路的输入信号端不同，第一输出端不同，第二输出端不同。
在一些实施例中，多个所述多路选择电路的数量为三个。
又一方面，提供一种显示面板。所述显示面板包括多个像素和至少一个如上述任一实施例所述的多路选择器。每个多路选择器与多个像素耦接。
在一些实施例中，所述多个像素呈阵列排布。所述多路选择器与两列像 素耦接。所述多路选择器中的每个多路选择电路的第一输出端与所述两列像素中的一列像素耦接，所述多路选择器中的每个多路选择电路的第二输出端与所述两列像素中的另一列像素耦接。
在一些实施例中，所述多路选择器耦接的两列像素相邻。
在一些实施例中，每个像素包括多个子像素。在每个多路选择器中，每个多路选择电路的第一输出端和第二输出端分别与不同像素中的发光颜色相同的子像素耦接。
在一些实施例中，所述显示面板还包括多条感测线。所述多路选择器所耦接的多个像素与一条感测线耦接。
又一方面，提供一种显示装置。所述显示装置包括上述任一实施例所述的显示面板和源极驱动器。所述源极驱动器与所述显示面板中的至少一个多路选择器耦接。
又一方面，提供一种如上述任一项所述的多路选择电路的驱动方法。所述驱动方法包括：第一选择子电路响应于在第一控制端接收的第一控制信号，将在输入信号端处接收的输入信号传输至第一输出端；第二选择子电路响应于在第四控制端处接收的第四控制信号，将电源电压端的电压传输至第二输出端；所述第一选择子电路响应于在第二控制端处接收的第二控制信号，将电源电压端的电压传输至所述第一输出端；所述第二选择子电路响应于在第三控制端处接收的第三控制信号，将在所述输入信号端处接收的输入信号传输至所述第二输出端。
又一方面，提供一种多路选择器的驱动方法。所述多路选择器包括多个多路选择电路；每个多路选择电路包括第一选择子电路和第二选择子电路；所述第一选择子电路与第一控制端、第二控制端、输入信号端、电源电压端和第一输出端耦接；所述第二选择子电路与第三控制端、第四控制端、所述输入信号端、所述电源电压端和第二输出端耦接；所述多个多路选择电路的输入信号端不同，第一输出端不同，第二输出端不同。所述驱动方法包括：每个多路选择电路中的第一选择子电路响应于在所述第一控制端接收的第一控制信号，将在其所耦接的输入信号端处接收的输入信号传输至其所耦接的第一输出端；每个多路选择电路中的第二选择子电路响应于在所述第四控制端处接收的第四控制信号，将所述电源电压端的电压传输至其所耦接的第二输出端；每个多路选择电路中的第一选择子电路响应于在所述第二控制端处接收的第二控制信号，将所述电源电压端的电压传输至其所耦接的第一输出端；每个多路选择电路中的第二选择子电路响应于在所述第三控制端处接收 的第三控制信号，将在其所耦接的输入信号端处接收的输入信号传输至其所耦接的第二输出端。
又一方面，提供一种如上述任一项所述的显示装置的驱动方法。所述显示装置中的显示面板中的每个像素包括多个子像素；每个子像素包括像素电路；所述像素电路包括驱动晶体管；所述显示面板还包括多条感测线；所述显示面板中的多路选择器所耦接的多个像素与一条感测线耦接。所述显示装置的驱动方法包括：源极驱动器向所述显示面板中的多路选择器中的各多路选择电路提供输入信号。所述多路选择器中的多路选择电路中的第一选择子电路响应于在第一控制端接收的第一控制信号，将在其所耦接的输入信号端处接收的输入信号传输至其所耦接的第一输出端；所述多路选择器中的多路选择电路中的第二选择子电路响应于在第四控制端处接收的第四控制信号，将电源电压端的电压传输至其所耦接的第二输出端。所述感测线感测所述第一输出端所耦接的像素中子像素中的像素电路的驱动晶体管的阈值电压。所述多路选择器中的多路选择电路中的第一选择子电路响应于在第二控制端处接收的第二控制信号，将所述电源电压端的电压传输至其所耦接的第一输出端；所述多路选择器中的多路选择电路中的第二选择子电路响应于在第三控制端处接收的第三控制信号，将在其所耦接的输入信号端处接收的输入信号传输至其所耦接的第二输出端。所述感测线感测所述第二输出端所耦接的像素中子像素中的像素电路的驱动晶体管的阈值电压。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，然而，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开的实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的一种显示装置的结构图；
图2为根据一些实施例的一种子像素的示意图；
图3为根据一些实施例的一种像素电路的电路图；
图4为根据一些实施例的一种多路选择电路的示意图；
图5为根据一些实施例的一种显示装置的示意图；
图6为根据一些实施例的一种多路选择电路的电路图；
图7为根据一些实施例的另一种多路选择电路的示意图；
图8为根据一些实施例的另一种多路选择电路的电路图；
图9为根据一些实施例的一种多路选择器的示意图；
图10为根据一些实施例的另一种多路选择器的电路图；
图11为根据一些实施例的另一种多路选择器的电路图；
图12A为根据一些实施例的另一种显示装置的示意图；
图12B为根据一些实施例的多路选择器与像素的连接关系图；
图13A为根据一些实施例的一种多路选择电路的驱动时序图；
图13B为根据一些实施例的另一种多路选择电路的驱动时序图；
图14A和图14B为根据一些实施例的一种多路选择电路的仿真信号图；
图15为根据一些实施例的多路选择器的一种驱动时序图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，然而，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术 语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本公开的实施例提供一种显示装置。示例性地，该显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。更明确地说，显示装置可以是多种电子装置中的一种，所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。本公开的实施例对上述显示装置的具体形式不做特殊限制。
在一些实施例中，如图1所示，显示装置200包括显示面板100。显示面板100具有显示区AA和周边区S。其中，周边区S至少位于显示区AA外一侧。
其中，显示面板100包括设置于显示区AA中的多个像素P。示例性地，多个像素P可以呈阵列排布。例如，沿图1中X方向排列成一排的像素P称为同一像素，沿图1中Y方向排列成一排的像素P称为同一列像素。
在一些实施例中，如图1所示，每个像素P包括多个子像素Q。示例性地，多个子像素包括第一颜色子像素、第二颜色子像素和第三颜色子像素；例如，第一颜色、第二颜色和第三颜色为三基色；例如，第一颜色、第二颜色和第三颜色分别为红色、绿色和蓝色；即，多个子像素包括红色子像素、绿色子像素和蓝色子像素。
如图2所示，每个子像素Q包括像素电路101和发光器件L。其中，像素电路101与发光器件L耦接。
示例性地，发光器件L可以采用有机OLED或者发光二极管(Light Emitting Diode，LED)。在这种情况下，文中所述的工作时长可以被理解为发光器件L的发光时长；发光器件L的第一极和第二极分别为发光二极管的阳极和阴极。
需要说明的是，本公开的实施例对像素电路的具体结构不作限定，可以根据实际情况进行设计。示例性地，像素电路由薄膜晶体管(Thin Film Transistor，简称TFT)、电容(Capacitor，简称C)等电子器件组成。例如，像素电路可以包括两个薄膜晶体管(一个开关晶体管和一个驱动晶体管)和一个电容，构成2T1C结构；当然，像素电路还可以包括两个以上的薄膜晶体管(多个开关晶体管和一个驱动晶体管)和至少一个电容，例如参考图3，像素电路可以包括电容和三个晶体管(两个开关晶体管和一个驱动晶体管)构成3T1C结构。
在一些实施例中，如图1所示，显示面板100还包括多条栅线GL和多条数据线DL。示例性地，多条栅线GL沿图1中的X方向延伸，多条数据线DL沿图1中的Y方向延伸。栅线GL被配置为传输扫描信号，数据线DL被配置为传输数据信号。示例性地，每个像素电路101与至少一条栅线GL和一条数据线DL耦接，栅线GL和数据线DL向像素电路101提供工作信号，以使像素电路101驱动发光器件L发光。示例性地，每行像素电路与两条栅线耦接，其中一条栅线向像素电路传输第一扫描信号(G1)，另一条栅线向像素电路传输第二扫描信号(G2)。
在一些实施例中，如图1所示，显示面板100还包括多条感测线SL。示例性地，多条感测线SL沿图1中的Y方向延伸。其中，像素电路101与感测线SL耦接。
例如，如图3所示，一个开关晶体管M1的控制极(栅极)用于接收第一扫描信号G1。该开关晶体管M1的第一极与数据线DL耦接以接收数据线DL上传输的数据信号Vdata。开关晶体管M1的第二极与驱动晶体管M2的控制 极耦接，驱动晶体管M2的第二极与第一电压端V1耦接以接收第一电压VDD(高电压)，驱动晶体管M2的第一极(源极)与发光器件L的第一极耦接，发光器件L的第二极与第二电压端V2耦接。存储电容Cst的第一端与开关晶体管M1的第二极和驱动晶体管M2的控制极耦接，存储电容Cst的第二端与驱动晶体管M2的第一极和发光器件L的第一极耦接。感测晶体管M3(即另一个开关晶体管)的控制极与用于接收第二扫描信号G2。感测晶体管M3的第一极与存储电容Cst的第二端、驱动晶体管M2的第二极和发光器件L的第一极耦接，感测晶体管M3的第二极与感测线SL耦接。感测线SL与检测电路(未示出)耦接。在此情况下，在驱动晶体管M2导通的情况下，经由感测晶体管M3对感测线放电，使得驱动晶体管M2的第二极的电压改变。
由此，当驱动晶体管M2导通之后，经由感测晶体管M3对于检测电路放电或者对经由感测晶体管M3对感测线上设置的电容或寄生电容充电，使得驱动晶体管M2的源极电压Vs改变。当驱动晶体管M2的源极电压Vs等于驱动晶体管M2的栅极电压Vg与驱动晶体管的阈值电压Vth的差值时，驱动晶体管M2将会截止，驱动晶体管M2的源极电压Vs不再改变。此种情况下，可以在驱动晶体管M2截止后，经由导通的感测晶体管M3从驱动晶体管M2的源极获取截止后的源极电压(也即驱动晶体管M2截止后的源极电压Vb)。在获取截止源极电压Vb之后，可以获取驱动晶体管M2的阈值电压(也即，Vth＝Vdata-Vb)。由此，可以基于每个像素电路中驱动晶体管的阈值电压对像素电路的待显示的数据信号(数据电压)进行补偿，并且使用补偿后的数据信号驱动像素电路，由此可以实现针对显示面板各个子像素的阈值电压的补偿功能。例如，补偿后的数据信号Vdata_C可以使用以下的表达式表示：Vdata_C＝Vdata+Vth。
示例性地，一条感测线与多个像素电路耦接。例如，相邻两列像素中的像素电路可以与一条感测线耦接。例如，在每个像素包括三个子像素的情况下，对于一行像素，一条感测线可以分别与相邻两列像素中的六个子像素中的像素电路耦接，以检测各像素电路中的驱动晶体管的阈值电压。
在一些实施例中，如图1所示，显示装置200还包括源极驱动器(即源极驱动IC(Source IC))210。源极驱动器210与显示面板100邦定，源极驱动器210被配置为向显示面板100提供信号。例如，该信号可以是数据信号；例如，显示面板100中的多条数据线DL可以传输数据信号。示例性地，参考图1，源极驱动器210可以采用COF(Chip On Film，覆晶薄膜)工艺，即，将源极驱动器210设置在FPC(Flexible Printed Circuit Board，柔性线路板)上， 通过FPC与显示面板100邦定。
对于高分辨率的显示装置，显示面板中的像素电路的数量相对较多，显示面板中的为像素电路提供工作信号的信号线(例如栅线和数据线)的数量也相对较多，与信号线耦接的驱动器(例如为数据线提供数据信号的源极驱动器)需要的引脚(Pin)或输出端口的数量也会变多，例如，源极驱动器的输出端口与数据线一一对应耦接，使得源极驱动器的输出端口数量增加，这样会导致生产成本增加，且占用面积增加，在显示面板的邦定(Bonding)区中的版图空间受到限制，容易导致产品良率降低。
本公开的实施例提供一种多路选择电路10，如图4所示，多路选择电路10包括第一选择子电路11和第二选择子电路12。
第一选择子电路11与第一控制端MUX1、第二控制端MUX2、输入信号端IN、电源电压端S和第一输出端OUT1耦接。第二选择子电路12与第三控制端MUX3、第四控制端MUX4、输入信号端IN、电源电压端S和第二输出端OUT2耦接。
第一选择子电路11被配置为响应于在第一控制端MUX1处接收的第一控制信号，将在输入信号端IN处接收的输入信号传输至第一输出端OUT1；及，响应于在第二控制端MUX2处接收的第二控制信号，将电源电压端S的电压传输至第一输出端OUT1。
第二选择子电路12被配置为响应于在第三控制端MUX3处接收的第三控制信号，将在输入信号端IN处接收的输入信号传输至第二输出端OUT2；及，响应于在第四控制端MUX4处接收的第四控制信号，将电源电压端S的电压传输至第二输出端OUT2。
可以理解的是，如图5所示，显示面板100还包括第一控制信号线M_G1、第二控制信号线M_G2、第三控制信号线M_G3、第四控制信号线M_G4和电源电压线V_S，其中，多路选择电路10的第一控制端MUX1与第一控制信号线M_G1耦接，第二控制端MUX2与第二控制信号线M_G2耦接，第三控制端MUX3与第三控制信号线M_G3耦接，第四控制端MUX4与第四控制信号线M_G4耦接，电源电压端S与电源电压线V_S耦接。
示例性地，电源电压端S被配置为传输直流电压，例如直流低电压。例如，电源电压端S的电压与发光器件L的第二极所耦接的第二电压端V2的第二电压VSS(低电压)相同，即，电源电压端S的电压等于第二电压VSS。
示例性地，电源电压端与第二电压端为同一电压端。这样，电源电压端的电压与第二电压端的第二电压可以由相同的信号线传输，电源电压端和第 二电压端耦接相同的信号线，简化了显示面板的布线。
示例性地，第一输出端OUT1和第二输出端OUT2分别与不同的像素电路耦接，该不同的像素电路所在的子像素出射相同颜色的光。例如，参考图5，一个多路选择电路10的第一输出端OUT1通过一条数据线DL与一列像素中的第一颜色子像素Q R耦接，第二输出端OUT2通过另一条数据线DL与另一列像素中的第一颜色子像素Q R耦接；一个多路选择电路10的第一输出端OUT1通过一条数据线DL与一列像素中的第二颜色子像素Q G耦接，第二输出端OUT2通过另一条数据线DL与另一列像素中的第二颜色子像素Q G耦接；一个多路选择电路10的第一输出端OUT1通过一条数据线DL与一列像素中的第三颜色子像素Q B耦接，第二输出端OUT2通过另一条数据线DL与另一列像素中的第三颜色子像素Q B耦接。
可以理解的是，源极驱动器的一个输出端口与一个多路选择电路的输入信号端耦接，通过多路选择电路的第一输出端和第二输出端分别于两条数据线耦接，即，源极驱动器的一个输出端口可以向两条数据线输出信号，从而减少了源极驱动器的输出端口的数量，并减少了源极驱动器与显示面板邦定的引脚的数量，简化显示面板的邦定区的版图设计，降低生产成本，提高显示效果。
其中，多路选择电路10的第一输出端OUT1耦接的像素电路和第二输出端OUT2耦接的像素电路与同一条感测线耦接。并且，一条感测线分时检测其所耦接的多个像素电路的阈值电压(即驱动晶体管的阈值电压)。例如，多路选择电路10的第一输出端OUT1耦接一列像素中的第一颜色子像素，第二输出端OUT2耦接另一列像素中的第一颜色子像素，且一列像素中的第一颜色子像素和另一列像素中的第一颜色子像素与一条感测线耦接，该感测线可以在检测一列像素中的第一颜色子像素中的像素电路的阈值电压之后，检测另一列像素中的第一颜色子像素中的像素电路的阈值电压。
在感测线检测第一输出端OUT1耦接的一列像素中的第一颜色子像素中的像素电路的阈值电压情况下，第一输出端OUT1耦接的一列像素中的第一颜色子像素中的像素电路接收在输入信号端IN处接收的输入信号，第二输出端OUT2耦接另一列像素中的第一颜色子像素中的像素电路不会接收该输入信号，因此，一列像素中的第一颜色子像素中的像素电路耦接的数据线传输的信号为该输入信号，另一列像素中的第一颜色子像素中的像素电路的数据线不会传输该输入信号。一些实施例中，如果该数据线上无信号传输，那么数据线的信号会因电位不受控(例如处于浮置(Floating)状态)而存在噪声干 扰，导致与第二输出端OUT2耦接的子像素错误开启，影响感测线检测与第一输出端OUT1耦接的子像素中的像素电路的阈值电压的精确度。
因此，在感测线检测第一输出端OUT1耦接的一列像素中的第一颜色子像素中的像素电路的阈值电压情况下，第一输出端OUT1耦接的一列像素中的第一颜色子像素中的像素电路接收在输入信号端IN处接收的输入信号，第二输出端OUT2耦接的另一列像素中的第一颜色子像素中的像素电路接收电源电压端S的电压，另一列像素中的第一颜色子像素中的像素电路耦接的数据线传输的信号为电源电压端的电压，这样可以避免与第二输出端OUT2的输出端耦接的数据线的信号因电位不受控而导致数据线的信号存在噪声干扰，使得与第二输出端OUT2耦接的子像素错误开启，影响感测线检测与第一输出端OUT1耦接的子像素中的像素电路的阈值电压的精确度，从而提高了感测数据的准确性，提高了显示效果。
同样的，在感测线检测第二输出端OUT2耦接的另一列像素中的第一颜色子像素中的像素电路的阈值电压情况下，第二输出端OUT2耦接的另一列像素中的第一颜色子像素中的像素电路接收在输入信号端IN处接收的输入信号，第一输出端OUT1耦接的一列像素中的第一颜色子像素中的像素电路接收电源电压端S的电压，一列像素中的第一颜色子像素中的像素电路耦接的数据线传输的信号为电源电压端的电压，这样可以避免与第一输出端OUT1的输出端耦接的数据线的信号因电位不受控而导致数据线的信号存在噪声干扰，使得与第一输出端OUT1耦接的子像素错误开启，影响感测线检测与第二输出端OUT2耦接的子像素中的像素电路的阈值电压的精确度，从而提高了感测数据的准确性，提高了显示效果。
因此，本公开的实施例提供的多路选择电路，第一选择子电路响应于在第一控制端处接收的第一控制信号，将在输入信号端处接收的输入信号传输至第一输出端；及，响应于在第二控制端处接收的第二控制信号，将电源电压端的电压传输至第一输出端。第二选择子电路响应于在第三控制端处接收的第三控制信号，将在输入信号端处接收的输入信号传输至第二输出端；及，响应于在第四控制端处接收的第四控制信号，将电源电压端的电压传输至第二输出端。这样，在感测线检测第一输出端耦接的子像素中的像素电路的阈值电压的情况下，第二输出端耦接的数据线的信号的电压为电源电压端的电压；在感测线检测第二输出端耦接的子像素中的像素电路的阈值电压的情况下，第一输出端耦接的数据线的信号的电压为电源电压端的电压。因此，可以避免在检测多路选择电路的一个输出端所耦接的子像素中的像素电路的阈 值电压的过程中，多路选择电路的其余输出端所耦接的数据线的信号因电位不受控而存在噪声干扰，导致子像素错误开启，影响感测线检测的精确度，从而提高了感测数据的准确性，提高了显示效果。
示例性地，如图6所示，第一选择子电路11包括第一晶体管T1和第二晶体管T2。
其中，第一晶体管T1的控制极与第一控制端MUX1耦接，第一晶体管T1的第一极与输入信号端IN耦接，第一晶体管T1的第二极与第一输出端OUT1耦接。
第二晶体管T2的控制极与第二控制端MUX2耦接，第二晶体管T2的第一极与电源电压端S耦接，第二晶体管T2的第二极与第一输出端OUT1耦接。
示例性地，如图6所示，第二选择子电路12包括第三晶体管T3和第四晶体管T4。
其中，第三晶体管T3的控制极与第三控制端MUX3耦接，第三晶体管T3的第一极与输入信号端IN耦接，第三晶体管T3的第二极与第二输出端OUT2耦接。
第四晶体管T4的控制极与第四控制端MUX4耦接，第四晶体管T4的第一极与电源电压端S耦接，第四晶体管T4的第二极与第二输出端OUT2耦接。
在一些实施例中，如图7所示，多路选择电路10还包括第一电压控制子电路13。第一电压控制子电路13与电源电压端S、第二控制端MUX2和第一选择子电路11耦接。第一电压控制子电路13被配置为根据电源电压端S的电压和在第二控制端MUX2处接收的第二控制信号，控制第一选择子电路11在第二控制端MUX2处接收的第二控制信号的电压。在此情况下，可以通过第一电压控制子电路13控制第一选择子电路11在第二控制端MUX2处接收的第二控制信号的电压，这样在显示阶段，第一选择子电路11在第二控制端MUX2处接收的第二控制信号的电压由第一电压控制子电路13提供，而不由第二控制端MUX2所耦接的信号线提供，使得显示装置无需长时间给第二控制端MUX2所耦接的信号线通电，从而降低显示装置的功耗。
示例性地，如图8所示，第一电压控制子电路13包括第一电容器C1。其中，第一电容器C1的第一端与电源电压端S耦接，第一电容器C1的第二端与第二控制端MUX2和第一选择子电路11耦接。
示例性地，在第一选择子电路11包括第二晶体管T2的情况下，第一电容器C1的第二端与第二晶体管T2的控制极耦接。
在一些实施例中，如图7所示，多路选择电路10还包括第二电压控制子 电路14。第二电压控制子电路14与电源电压端S、第四控制端MUX4和第二选择子电路12耦接。第二电压控制子电路14被配置为根据电源电压端S的电压和在第四控制端MUX4处接收的第四控制信号，控制第二选择子电路12在第四控制端MUX4处接收的第四控制信号的电压。在此情况下，可以通过第二电压控制子电路14控制第二选择子电路12在第四控制端MUX4处接收的第四控制信号的电压，这样在显示阶段，第二选择子电路12在第四控制端MUX4处接收的第四控制信号的电压由第二电压控制子电路14提供，而不由第四控制端MUX4所耦接的信号线提供，使得显示装置无需长时间给第四控制端MUX4所耦接的信号线通电，从而降低显示装置的功耗。
示例性地，如图8所示，第二电压控制子电路14包括第二电容器C2。其中，第二电容器C2的第一端与电源电压端S耦接，第二电容器C2的第二端与第四控制端MUX4和第二选择子电路12耦接。
示例性地，在第二选择子电路12包括第四晶体管T4的情况下，第二电容器C2的第二端与第四晶体管T4的控制极耦接。
本公开的实施例提供一种多路选择电路。如图6所示，多路选择电路10包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4。
其中，第一晶体管T1的控制极与第一控制端MUX1耦接，第一晶体管T1的第一极与输入信号端IN耦接，第一晶体管T1的第二极与第一输出端OUT1耦接。
第二晶体管T2的控制极与第二控制端MUX2耦接，第二晶体管T2的第一极与电源电压端S耦接，第二晶体管T2的第二极与第一输出端OUT1耦接。
第三晶体管T3的控制极与第三控制端MUX3耦接，第三晶体管T3的第一极与输入信号端IN耦接，第三晶体管T3的第二极与第二输出端OUT2耦接。
第四晶体管T4的控制极与第四控制端MUX4耦接，第四晶体管T4的第一极与电源电压端S耦接，第四晶体管T4的第二极与第二输出端OUT2耦接。
需要说明的是，本公开的实施例提供的多路选择电路中所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，TFT)、场效应晶体管(Field Effect Transistor，FET)或其他特性相同的开关器件，本公开的实施例对此并不设限。
在一些实施例中，多路选择电路所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的 第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例提供的多路选择电路中，各个子电路的具体实现方式不局限于上面描述的方式，其可以为任意使用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可。上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不适用上述各个子电路中的一个或多个，基于前述各个子电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
本公开的实施例提供一种多路选择器，多路选择器包括多个多路选择电路。多个多路选择电路为多个上述任一实施例中的多路选择电路。例如，参考图9至图11，多路选择器110包括多个多路选择电路(10A、10B和10C)。例如，多个多路选择电路的数量为三个。
其中，多路选择器110中的多个多路选择电路10的输入信号端IN不同，第一输出端OUT1不同，第二输出端OUT2不同。例如，多路选择器110中的多个多路选择电路10的输入信号端IN出接收的输入信号不同；例如，多路选择器110中的每个多路选择电路10的输入信号端IN所耦接的数据传输通道不同。多路选择器110中的多个多路选择电路10的第一输出端OUT1所耦接的子像素不同，即，多路选择器110中的多个多路选择电路10的第一输出端OUT1所耦接的子像素的发光颜色不同；多路选择器110中的多个多路选择电路10的第二输出端OUT2所耦接的子像素不同，即，多路选择器110中的多个多路选择电路10的第二输出端OUT2所耦接的子像素的发光颜色不同；但是每个多路选择电路10的第一输出端OUT1和第二输出端OUT2耦接的子像素发光颜色相同。
在一些实施例中，显示面板还包括至少一个多路选择器。每个多路选择器与多个像素耦接。
示例性地，多路选择器与多个像素中的像素电路耦接。例如，多个像素可以为至少两个像素。例如，多路选择器与相邻两列像素耦接。例如，多路选择器与奇数列像素和偶数列像素耦接。例如，多路选择器中的每个多路选择电路的第一输出端与奇数列像素耦接，多路选择器中的每个多路选择电路的第二输出端与偶数列像素耦接。
示例性地，每个像素包括多个子像素；在每个多路选择器中，每个多路选择电路的第一输出端和第二输出端分别与不同像素中的发光颜色相同的子 像素耦接。
例如，每个像素包括三个子像素，例如多路选择器中的多个多路选择电路为三个多路选择电路，每个多路选择电路分别与多个像素中发出相同颜色光的子像素中的像素电路耦接。例如，参考图12A，多个像素分别为至少一个像素P O和至少一个像素P E，至少一个像素P O处于像素排布的奇数列像素，至少一个像素P E处于像素排布的偶数列。
示例性地，参考图12A和图12B，多个像素中的像素P O中的三个子像素分别为第一颜色子像素Q R_O、第二颜色子像素Q G_O和第三颜色子像素Q B_O，多个像素中的像素P E中的三个子像素分别为第一颜色子像素Q R_E、第二颜色子像素Q G_E和第三颜色子像素Q B_E。多路选择器110中的多个多路选择电路10分别为多路选择电路10A、多路选择电路10B和多路选择电路10C，多路选择电路10A与像素P O中的第一颜色子像素Q R_O和像素P E中的第一颜色子像素Q R_E耦接，即，多路选择电路10A的第一输出端OUT1A与第一颜色子像素Q R_O耦接，多路选择电路10A的第二输出端OUT2A与第一颜色子像素Q R_E耦接；多路选择电路10A的第一输出端OUT1A与一列第一颜色子像素Q R_O耦接，多路选择电路10A的第二输出端OUT2A与一列第一颜色子像素Q R_E耦接；多路选择电路10B与像素P O中的第二颜色子像素Q G_O和像素P E中的第二颜色子像素Q G_E耦接，即，多路选择电路10B的第一输出端OUT1B与第二颜色子像素Q G_E耦接，多路选择电路10B的第二输出端OUT2B与第二颜色子像素Q G_E耦接；多路选择电路10B的第一输出端OUT1B与一列第二颜色子像素Q G_E耦接，多路选择电路10B的第二输出端OUT2B与一列第二颜色子像素Q G_E耦接；多路选择电路10C与像素P O中的第三颜色子像素Q B_O和像素P E中的第三颜色子像素Q B_E耦接，即，多路选择电路10C的第一输出端OUT1C与第三颜色子像素Q B_E耦接，多路选择电路10C的第二输出端OUT2C与第三颜色子像素Q B_E耦接；多路选择电路10C的第一输出端OUT1C与一列第三颜色子像素Q B_E耦接，多路选择电路10C的第二输出端OUT2C与一列第三颜色子像素Q B_E耦接。
其中，多路选择电路在输入信号端接收的输入信号与该多路选择电路的第一输出端和第二输出端所耦接的子像素需要显示的灰阶有关。例如，多路选择电路10A在输入信号端INA处接收的输入信号可以是第一颜色数据信号，以使第一颜色子像素Q R_O和第一颜色子像素Q R_E接收第一颜色数据信号后显示第一颜色子像素对应的灰阶；多路选择电路10B在输入信号端INB处接收的输入信号可以是第二颜色数据信号，以使第二颜色子像素Q G_O和第二 颜色子像素Q G_E接收第二颜色数据信号后显示第二颜色子像素对应的灰阶；多路选择电路10C在输入信号端INC处接收的输入信号可以是第三颜色数据信号，以使第三颜色子像素Q B_O和第三颜色子像素Q B_E接收第三颜色数据信号后显示第三颜色子像素对应的灰阶。
以下，参考图13A和图13B中的时序，对多路选择电路的工作情况进行举例说明。其中，多路选择电路中的各个晶体管均为N型晶体管。
在第一阶段(P1)，多路选择电路中的第一选择子电路响应于在第一控制端处接收的第一控制信号，将在输入信号端处接收的输入信号传输至第一输出端。多路选择电路中的第二选择子电路响应于在第三控制端处接收的第三控制信号，将在输入信号端处接收的输入信号传输至第二输出端。示例性地，在此阶段，输入信号端处接收的输入信号为参考信号，例如，参考信号的电压为0V。
例如，参考图4，多路选择电路10中的第一选择子电路11响应于在第一控制端MUX1处接收的第一控制信号，将在输入信号端IN处接收的输入信号传输至第一输出端OUT1。多路选择电路10中的第二选择子电路12响应于在第三控制端MUX3处接收的第三控制信号，将在输入信号端IN处接收的输入信号传输至第二输出端OUT2。
例如，参考图6，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端IN处接收的低电压的输入信号传输至第一输出端OUT1，第一输出端OUT1的输出信号为低电压信号；第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信号端IN处接收的低电压的输入信号传输至第二输出端OUT2，第二输出端OUT2的输出信号为低电压信号。在此情况下，与第一输出端OUT1和第二输出端OUT2耦接的数据线上传输的信号为低电压信号，与第一输出端OUT1和第二输出端OUT2耦接的各个子像素均被复位。
需要说明的是，在显示面板包括n行像素，每个子像素对应一个像素电路的情况下，在第一阶段，对第一行至第n行的子像素进行逐行扫描，即，对第一行至第n行的子像素进行逐行复位，实现全屏复位。例如，在第一阶段，第一行至第n行的子像素依次逐行接收第一扫描信号G1和第二扫描信号G2(例如，第一行子像素接收第一扫描信号G1(1)和第二扫描信号G2(1)，第n行子像素接收第一扫描信号G1(n)和第二扫描信号G2(n))，将多路选择电路输出的信号写入对应的子像素中的像素电路。
示例性地，在第一阶段(P1)，对于第一行像素，在第一扫描信号G1(1)和 第二扫描信号G2(1)为高电平的情况下，参考图3，像素电路中的开关晶体管M1响应于高电压的第一扫描信号，开关晶体管M1导通，将多路选择电路的第一输出端OUT1输出的低电压信号写入驱动晶体管M2的控制极，对驱动晶体管M2进行复位，感测晶体管M3响应于高电压的第二扫描信号，感测晶体管M3导通，将多路选择电路的第二输出端OUT2输出的低电压信号写入发光器件L的第一极，对发光器件L进行复位，实现对子像素的复位。需要说明的是，其余行子像素中的像素电路工作情况与第一行子像素中的像素电路的工作情况类似，在此不作赘述。其中，在对第一行至第n行的子像素逐行复位完毕后，进入第二阶段。
需要说明的是，在第一阶段，第一控制信号和第三控制信号可以为时钟信号(参考图13A)，且第一控制信号和第三控制信号互为反转信号，例如，在第一控制信号为高电压信号的情况下，第三控制信号为低电压信号，在第一控制信号为低电压信号的情况下，第三控制信号为高电压信号。这样，多路选择电路10中的第一选择子电路11和第二选择子电路12可以交替工作，例如，第一选择子电路11和第二选择子电路12可以交替输出低电压信号，即，第一输出端OUT1和第二输出端OUT2交替输出低电压信号。或者，第一控制信号和第三控制信号可以为相同的直流信号(参考图13B)，例如，第一控制信号和第三控制信号同为直流高电压信号。这样，多路选择电路10中的第一选择子电路11和第二选择子电路12可以同时工作，例如，第一选择子电路11和第二选择子电路12可以同时输出低电压信号，即，第一输出端OUT1和第二输出端OUT2同时输出低电压信号。
在第二阶段(P2)中的第一时段(R1)，多路选择电路中的第一选择子电路响应于在第一控制端处接收的第一控制信号，将在输入信号端处接收的输入信号传输至第一输出端。多路选择电路中的第二选择子电路响应于在第四控制端处接收的第四控制信号，将电源电压端的电压传输至第二输出端。
例如，参考图4，多路选择电路10中的第一选择子电路11响应于在第一控制端MUX1处接收的第一控制信号，将在输入信号端IN处接收的输入信号传输至第一输出端OUT1。多路选择电路10中的第二选择子电路12响应于在第四控制端MUX4处接收的第四控制信号，将电源电压端S的电压传输至第二输出端OUT2。
例如，参考图6，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端IN处接收的高电压的输入信号传输至第一输出端OUT1，第一输出端OUT1的输出信号为高电压信号；第四晶体管T4响 应于高电压的第四控制信号，第四晶体管T4导通，将电源电压端S的低电压传输至第二输出端OUT2，第二输出端OUT2的输出信号为低电压信号。
在此情况下，与第一输出端OUT1耦接的数据线上传输高电压信号，与第二输出端OUT2耦接的数据线上传输的信号为低电压信号。这样，与第一输出端OUT1耦接的子像素中的像素电路写入为高电压信号，即，像素电路中的开关晶体管(例如，第二行像素中的像素电路中的开关晶体管响应于高电压的第一扫描信号G1(2)，开关晶体管导通)将高电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为高电压，驱动晶体管会被导通；感测晶体管(例如，第二行像素中的像素电路中的感测晶体管响应于高电压的第二扫描信号G2(2))处于导通状态，感测线通过感测晶体管检测驱动晶体管的源极的电压，以感测与第一输出端OUT1耦接的子像素中的像素电路中的驱动晶体管的阈值电压。并且，与第二输出端OUT2耦接的子像素的像素电路写入为低电压信号，即，像素电路中的开关晶体管将低电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为低电压，驱动晶体管均被处于截止状态，与第二输出端OUT2耦接的子像素的像素电路中的驱动晶体管的阈值电压，不会影响感测与第一输出端OUT1耦接的子像素中的像素电路中的驱动晶体管的阈值电压。因此，在感测线可以检测与第一输出端OUT1耦接的子像素中的像素电路中的驱动晶体管的阈值电压的过程中，可以避免与第二输出端OUT2耦接的子像素因电位不受控状态(例如Floating)而导致信号存在噪声干扰，使得与第二输出端OUT2耦接的子像素错误开启，影响感测线可以检测与第一输出端OUT1耦接的子像素中的像素电路中的驱动晶体管的阈值电压的精确度，从而提高了感测数据的准确性，提高了显示效果。
在第二阶段(P2)中的第二时段(R2)，多路选择电路中的第一选择子电路响应于在第二控制端处接收的第二控制信号，将电源电压端的电压传输至第一输出端。多路选择电路中的第二选择子电路响应于在第三控制端处接收的第三控制信号，将在输入信号端处接收的输入信号传输至第二输出端。
例如，参考图4，多路选择电路10中的第一选择子电路11响应于在第二控制端MUX2处接收的第二控制信号，将电源电压端S的电压传输至第一输出端OUT1。多路选择电路10中的第二选择子电路12响应于在第三控制端MUX3处接收的第三控制信号，将在输入信号端IN处接收的输入信号传输至第二输出端OUT2。
例如，参考图6，第二晶体管T2响应于高电压的第二控制信号，第二晶 体管T2导通，将电源电压端的低电压传输至第一输出端OUT1，第一输出端OUT1的输出信号为低电压信号；第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信号端IN处接收的高电压的输入信号传输至第二输出端OUT2，第二输出端OUT2的输出信号为高电压信号。
在此情况下，与第一输出端OUT1耦接的数据线上传输低电压信号，与第二输出端OUT2耦接的数据线上传输的信号为高电压信号。这样，与第二输出端OUT2耦接的子像素中的像素电路写入为高电压信号，即，像素电路中的开关晶体管将高电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为高电压，驱动晶体管会被导通；感测晶体管处于导通状态，感测线通过感测晶体管检测驱动晶体管的源极的电压，以感测与第二输出端OUT2耦接的子像素中的像素电路中的驱动晶体管的阈值电压。并且，与第一输出端OUT1耦接的子像素的像素电路写入为低电压信号，即，像素电路中的开关晶体管将低电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为低电压，驱动晶体管均被处于截止状态，与第一输出端OUT1耦接的子像素的像素电路中的驱动晶体管的阈值电压，不会影响感测与第二输出端OUT2耦接的子像素中的像素电路中的驱动晶体管的阈值电压。因此，在感测线可以检测与第二输出端OUT2耦接的子像素中的像素电路中的驱动晶体管的阈值电压的过程中，可以避免与第一输出端OUT1耦接的子像素因电位不受控状态(例如Floating)而导致信号存在噪声干扰，使得与第一输出端OUT1耦接的子像素错误开启，影响感测线可以检测与第二输出端OUT2耦接的子像素中的像素电路中的驱动晶体管的阈值电压的精确度，从而提高了感测数据的准确性，提高了显示效果。
需要说明的是，多路选择电路的第一输出端所耦接的子像素和第二输出端所耦接的子像素分别位于不同列的像素中。例如，多路选择电路10的第一输出端OUT1可以与奇数列像素中的单色子像素耦接，多路选择电路10的第二输出端OUT2与可以偶数列像素中对应相同颜色的子像素耦接，例如，第一输出端OUT1可以与奇数列像素中的第一颜色子像素耦接，第二输出端OUT2与可以偶数列像素中的第一颜色子像素耦接。另外，多路选择电路耦接的各子像素中的像素电路可以与一条感测线耦接，这样，一条感测线可以分时感测与多路选择电路耦接的各子像素中的像素电路中的驱动晶体管的阈值电压。
示例性地，对于多路选择电路，在第一阶段，多路选择电路的第一输出端和第二输出端输出低电压信号，将第一输出端耦接的数据线和第二输出端 耦接的数据线上的信号均复位。在第二阶段，感测线分别感测第一输出端耦接的子像素中的像素电路的阈值电压和第二输出端耦接的子像素中的像素电路的阈值电压。
例如，在感测多路选择电路的第一输出端耦接的子像素中的像素电路的阈值电压的情况下，多路选择电路的第一输出端输出高电压信号(例如电压为3V)，使得第一输出端耦接的数据线传输的信号的电压为高电压。如果多路选择电路的第二输出端无输出信号，即第二输出端耦接的数据线上无信号，处于Floating状态，那么由于数据线所耦接的晶体管存在漏电，导致第二输出端的电压抬升，例如，如图14A所示，第二输出端OUT2的电压由0V抬升至约0.4V，之后又由于数据线的信号噪声干扰，导致第二输出端的电压进一步抬升，例如，如图14A所示，第二输出端OUT2的电压由0.4V抬升至约0.6V。这样，如果在感测阈值电压的过程中，例如感测时间约为几十毫秒(ms)，噪声会不断累积，导致第二输出端耦接的数据线上的信号达到较大的电压，从而导致第二输出端耦接的像素电路中的驱动晶体管错误打开，对感测线进行充电，影响感测第一输出端耦接的像素电路中的阈值电压的准确性。
因此，本公开的实施例的多路选择电路在感测多路选择电路的第一输出端耦接的子像素中的像素电路的阈值电压的过程中，给第二输出端耦接的数据线上传输信号(数据线上传输的信号的电压为电源电压端的电压)，例如，如图14B所示，第二输出端OUT2的电压为0V，则第二输出端OUT2耦接的数据线上的信号的电压为0V，这样可以避免第二输出端耦接的数据线的信号受到干扰，降低噪声，提高电路的抗干扰性能，避免第二输出端耦接的像素电路中的驱动晶体管打开，从而提高了感测阈值电压的准确性。
以下，参考图15中的时序，对多路选择器的工作情况进行举例说明。其中，多路选择器中的各个多路选择电路中的晶体管均为N型晶体管。
示例性地，一个多路选择器可以与两列像素耦接，例如，两列像素分别为一列奇数列像素和一列偶数列像素，例如，多路选择器耦接的奇数列像素和偶数列像素相邻。例如，可以通过一条感测线检测多路选择器耦接的各列像素中每个子像素中的像素电路的阈值电压。示例性地，每个像素包括三个子像素，三个子像素分别为第一颜色子像素、第二颜色子像素和第三颜色子像素；例如，参考图12A，多路选择器110中的多个多路选择电路有三个，三个多路选择电路分别为多路选择电路10A、多路选择电路10B和多路选择电路10C，多路选择电路10A的第一输出端OUT1A、多路选择电路10B的第一输出端OUT1B和多路选择电路10C的第一输出端OUT1C分别与奇数列像 素中的第一颜色子像素、第二颜色子像素和第三颜色子像素耦接，多路选择电路10A的第二输出端OUT2A、多路选择电路10B的第二输出端OUT2B和多路选择电路10C的第二输出端OUT2C分别与偶数列像素中的第一颜色子像素、第二颜色子像素和第三颜色子像素耦接。
在此情况下，在第一阶段，对于多路选择器中的各多路选择电路，其中的第一选择子电路响应于在第一控制端处接收的第一控制信号，将在输入信号端处接收的输入信号传输至第一输出端。各多路选择电路中的第二选择子电路响应于在第三控制端处接收的第三控制信号，将在输入信号端处接收的输入信号传输至第二输出端。示例性地，在此阶段，输入信号端处接收的输入信号为参考信号，例如，参考信号的电压为0V。
例如，参考图9，在多路选择器110中，多路选择电路10A中的第一选择子电路11A响应于在第一控制端MUX1处接收的第一控制信号，将在输入信号端INA处接收的输入信号传输至第一输出端OUT1A。多路选择电路10A中的第二选择子电路12A响应于在第三控制端MUX3处接收的第三控制信号，将在输入信号端INA处接收的输入信号传输至第二输出端OUT2A。多路选择电路10B中的第一选择子电路11B响应于在第一控制端MUX1处接收的第一控制信号，将在输入信号端INB处接收的输入信号传输至第一输出端OUT1B。多路选择电路10B中的第二选择子电路12B响应于在第三控制端MUX3处接收的第三控制信号，将在输入信号端INB处接收的输入信号传输至第二输出端OUT2B。多路选择电路10C中的第一选择子电路11C响应于在第一控制端MUX1处接收的第一控制信号，将在输入信号端INC处接收的输入信号传输至第一输出端OUT1C。多路选择电路10C中的第二选择子电路12C响应于在第三控制端MUX3处接收的第三控制信号，将在输入信号端INC处接收的输入信号传输至第二输出端OUT2C。
例如，参考图10，在多路选择电路10A中，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端INA处接收的低电压的输入信号传输至第一输出端OUT1A，第一输出端OUT1A的输出信号为低电压信号；第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信号端INA处接收的低电压的输入信号传输至第二输出端OUT2A，第二输出端OUT2A的输出信号为低电压信号。在此情况下，与第一输出端OUT1A和第二输出端OUT2A耦接的数据线上传输的信号为低电压信号，与第一输出端OUT1A和第二输出端OUT2A耦接的各个子像素均被复位。
在多路选择电路10B中，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端INB处接收的低电压的输入信号传输至第一输出端OUT1B，第一输出端OUT1B的输出信号为低电压信号；第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信号端INB处接收的低电压的输入信号传输至第二输出端OUT2B，第二输出端OUT2B的输出信号为低电压信号。在此情况下，与第一输出端OUT1B和第二输出端OUT2B耦接的数据线上传输的信号为低电压信号，与第一输出端OUT1B和第二输出端OUT2B耦接的各个子像素均被复位。
在多路选择电路10C中，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端INC处接收的低电压的输入信号传输至第一输出端OUT1C，第一输出端OUT1C的输出信号为低电压信号；第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信号端INC处接收的低电压的输入信号传输至第二输出端OUT2C，第二输出端OUT2C的输出信号为低电压信号。在此情况下，与第一输出端OUT1C和第二输出端OUT2C耦接的数据线上传输的信号为低电压信号，与第一输出端OUT1C和第二输出端OUT2C耦接的各个子像素均被复位。
需要说明的是，在第一阶段，第一控制信号和第三控制信号可以互为反转信号，或者，第一控制信号和第三控制信号可以为相同的直流信号，例如，第一控制信号和第三控制信号同为直流高电压信号。
可以理解的是，在第一阶段，显示面板中的各行子像素逐行进行复位。对于每行子像素，在第一扫描信号和第二扫描信号为高电平的情况下，像素电路中的开关晶体管响应于高电压的第一扫描信号，开关晶体管导通，将多路选择器中对应的多路选择电路的第一输出端输出的低电压信号，写入对应的像素电路中的驱动晶体管的控制极，对驱动晶体管进行复位，对应的感测晶体管响应于高电压的第二扫描信号，感测晶体管导通，将多路选择器中对应的多路选择电路的第二输出端输出的低电压信号写入发光器件的第一极，对发光器件进行复位，实现对子像素的复位。这样，在第一阶段，显示面板实现全屏复位，此时显示面板不显示(例如处于关机状态)。
在第二阶段的第一时段，对于多路选择器中的多路选择电路，其中的多路选择电路中的第一选择子电路响应于在第一控制端处接收的第一控制信号，将在输入信号端处接收的输入信号传输至第一输出端。各多路选择电路中的第二选择子电路响应于在第四控制端处接收的第四控制信号，将电源电压端的电压传输至第二输出端。
例如，参考图9，在多路选择器110中，多路选择电路10A中的第一选择子电路11A响应于在第一控制端MUX1处接收的第一控制信号，将在输入信号端INA处接收的输入信号传输至第一输出端OUT1A。多路选择电路10A中的第二选择子电路12A响应于在第四控制端MUX4处接收的第四控制信号，将电源电压端S的电压传输至第二输出端OUT2A。多路选择电路10B中的第一选择子电路11B响应于在第一控制端MUX1处接收的第一控制信号，将在输入信号端INB处接收的输入信号传输至第一输出端OUT1B。多路选择电路10B中的第二选择子电路12B响应于在第四控制端MUX4处接收的第四控制信号，将电源电压端S的电压传输至第二输出端OUT2B。多路选择电路10C中的第一选择子电路11C响应于在第一控制端MUX1处接收的第一控制信号，将在输入信号端INC处接收的输入信号传输至第一输出端OUT1C。多路选择电路10C中的第二选择子电路12C响应于在第四控制端MUX4处接收的第四控制信号，将电源电压端S的电压传输至第二输出端OUT2C。
例如，参考图10，在多路选择电路10A中，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端INA处接收的高电压的输入信号传输至第一输出端OUT1A，第一输出端OUT1A的输出信号为高电压信号；第四晶体管T4响应于高电压的第四控制信号，第四晶体管T4导通，将电源电压端S的低电压传输至第二输出端OUT2A，第二输出端OUT2A的输出信号为低电压信号。在多路选择电路10B中，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端INB处接收的低电压的输入信号(例如参考电压)传输至第一输出端OUT1B，第一输出端OUT1B的输出信号为低电压信号；第四晶体管T4响应于高电压的第四控制信号，第四晶体管T4导通，将电源电压端S的低电压传输至第二输出端OUT2B，第二输出端OUT2B的输出信号为低电压信号。在多路选择电路10C中，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端INC处接收的低电压的输入信号(例如参考电压)传输至第一输出端OUT1C，第一输出端OUT1C的输出信号为低电压信号；第四晶体管T4响应于高电压的第四控制信号，第四晶体管T4导通，将电源电压端S的低电压传输至第二输出端OUT2C，第二输出端OUT2C的输出信号为低电压信号。
在此情况下，在多路选择器110中，多路选择电路10A的第一输出端OUT1A所耦接的数据线上传输高电压信号，其余的输出端所耦接的数据线上传输的信号均为低电压信号。这样，多路选择电路10A的第一输出端OUT1A 所耦接的子像素中的像素电路写入为高电压信号，即，像素电路中的开关晶体管(例如，第二行像素中的像素电路中的开关晶体管响应于高电压的第一扫描信号G1(2)，开关晶体管导通)将高电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为高电压，驱动晶体管会被导通；感测晶体管(例如，第二行像素中的像素电路中的感测晶体管响应于高电压的第二扫描信号G2(2))处于导通状态，感测线通过感测晶体管检测驱动晶体管的源极的电压，以感测与多路选择电路10A的第一输出端OUT1A耦接的子像素中的像素电路中的驱动晶体管的阈值电压。并且，其余的输出端所耦接的子像素的像素电路写入为低电压信号，即，像素电路中的开关晶体管将低电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为低电压，驱动晶体管均被处于截止状态，其余的输出端所耦接的子像素的像素电路中的驱动晶体管的阈值电压，不会影响感测与多路选择电路10A的第一输出端OUT1A耦接的子像素中的像素电路中的驱动晶体管的阈值电压。因此，在感测线可以检测与多路选择电路10A的第一输出端OUT1A所耦接的子像素(例如奇数列像素中的第一颜色子像素)中的像素电路中的驱动晶体管的阈值电压的过程中，可以避免与其余的输出端耦接的子像素因电位不受控状态(例如Floating)而导致信号存在噪声干扰，使得与其余的输出端耦接的子像素错误开启，影响感测线可以检测与多路选择电路10A的第一输出端OUT1A耦接的子像素中的像素电路中的驱动晶体管的阈值电压的精确度，从而提高了感测数据的准确性，提高了显示效果。
需要说明的是，在感测线耦接多个像素电路的情况下，多个像素电路中的驱动晶体管的阈值电压需要分时感测，例如，一条感测线耦接相邻两列像素中的各个像素电路，感测线在不同时刻感测各个像素电路中的驱动晶体管的阈值电压。例如，对于每条感测线，可以先感测其所耦接的奇数列像素中的第一颜色子像素、第二颜色子像素和第三颜色子像素中的阈值电压，之后感测其所耦接的偶数列像素中的第一颜色子像素、第二颜色子像素和第三颜色子像素中的阈值电压。示例性地，显示面板中的各个像素逐行进行感测，对于一行像素，感测线逐列感测各子像素中的像素电路对应的阈值电压。
示例性地，感测与多路选择电路10A的第一输出端OUT1A所耦接的子像素中的像素电路中的驱动晶体管的阈值电压，即为感测奇数列像素中的第一颜色子像素中的像素电路的阈值电压。
示例性地，参考图10，在多路选择电路10A中，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端INA处接收的 低电压的输入信号(例如参考电压)传输至第一输出端OUT1A，第一输出端OUT1A的输出信号为低电压信号；第四晶体管T4响应于高电压的第四控制信号，第四晶体管T4导通，将电源电压端S的低电压传输至第二输出端OUT2A，第二输出端OUT2A的输出信号为低电压信号。在多路选择电路10B中，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端INB处接收的高电压的输入信号传输至第一输出端OUT1B，第一输出端OUT1B的输出信号为高电压信号；第四晶体管T4响应于高电压的第四控制信号，第四晶体管T4导通，将电源电压端S的低电压传输至第二输出端OUT2B，第二输出端OUT2B的输出信号为低电压信号。在多路选择电路10C中，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端INC处接收的低电压的输入信号(例如参考电压)传输至第一输出端OUT1C，第一输出端OUT1C的输出信号为低电压信号；第四晶体管T4响应于高电压的第四控制信号，第四晶体管T4导通，将电源电压端S的低电压传输至第二输出端OUT2C，第二输出端OUT2C的输出信号为低电压信号。
在此情况下，在多路选择器110中，多路选择电路10B的第一输出端OUT1B所耦接的数据线上传输高电压信号，其余的输出端所耦接的数据线上传输的信号均为低电压信号。这样，多路选择电路10B的第一输出端OUT1B所耦接的子像素中的像素电路写入为高电压信号，即，像素电路中的开关晶体管将高电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为高电压，驱动晶体管会被导通；感测晶体管处于导通状态，感测线通过感测晶体管检测驱动晶体管的源极的电压，以感测与多路选择电路10B的第一输出端OUT1B耦接的子像素中的像素电路中的驱动晶体管的阈值电压。并且，其余的输出端所耦接的子像素的像素电路写入为低电压信号，即，像素电路中的开关晶体管将低电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为低电压，驱动晶体管均被处于截止状态，其余的输出端所耦接的子像素的像素电路中的驱动晶体管的阈值电压，不会影响感测与多路选择电路10B的第一输出端OUT1B耦接的子像素中的像素电路中的驱动晶体管的阈值电压。因此，在感测线可以检测与多路选择电路10B的第一输出端OUT1B所耦接的子像素(例如奇数列像素中的第二颜色子像素)中的像素电路中的驱动晶体管的阈值电压的过程中，可以避免与其余的输出端耦接的子像素因电位不受控状态(例如Floating)而导致信号存在噪声干扰，使得与其余的输出端耦接的子像素错误开启，影响感测线可以检 测与多路选择电路10B的第一输出端OUT1B耦接的子像素中的像素电路中的驱动晶体管的阈值电压的精确度，从而提高了感测数据的准确性，提高了显示效果。
示例性地，参考图10，在多路选择电路10A中，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端INA处接收的低电压的输入信号(例如参考电压)传输至第一输出端OUT1A，第一输出端OUT1A的输出信号为低电压信号；第四晶体管T4响应于高电压的第四控制信号，第四晶体管T4导通，将电源电压端S的低电压传输至第二输出端OUT2A，第二输出端OUT2A的输出信号为低电压信号。在多路选择电路10B中，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端INB处接收的低电压的输入信号(例如参考电压)传输至第一输出端OUT1B，第一输出端OUT1B的输出信号为低电压信号；第四晶体管T4响应于高电压的第四控制信号，第四晶体管T4导通，将电源电压端S的低电压传输至第二输出端OUT2B，第二输出端OUT2B的输出信号为低电压信号。在多路选择电路10C中，第一晶体管T1响应于高电压的第一控制信号，第一晶体管T1导通，将在输入信号端INC处接收的高电压的输入信号传输至第一输出端OUT1C，第一输出端OUT1C的输出信号为高电压信号；第四晶体管T4响应于高电压的第四控制信号，第四晶体管T4导通，将电源电压端S的低电压传输至第二输出端OUT2C，第二输出端OUT2C的输出信号为低电压信号。
在此情况下，在多路选择器110中，多路选择电路10C的第一输出端OUT1C所耦接的数据线上传输高电压信号，其余的输出端所耦接的数据线上传输的信号均为低电压信号。这样，多路选择电路10C的第一输出端OUT1C所耦接的子像素中的像素电路写入为高电压信号，即，像素电路中的开关晶体管将高电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为高电压，驱动晶体管会被导通；感测晶体管处于导通状态，感测线通过感测晶体管检测驱动晶体管的源极的电压，以感测与多路选择电路10C的第一输出端OUT1C耦接的子像素中的像素电路中的驱动晶体管的阈值电压。并且，其余的输出端所耦接的子像素的像素电路写入为低电压信号，即，像素电路中的开关晶体管将低电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为低电压，驱动晶体管均被处于截止状态，其余的输出端所耦接的子像素的像素电路中的驱动晶体管的阈值电压，不会影响感测与多路选择电路10C的第一输出端OUT1C耦接的子像素中的像 素电路中的驱动晶体管的阈值电压。因此，在感测线可以检测与多路选择电路10C的第一输出端OUT1C所耦接的子像素(例如奇数列像素中的第三颜色子像素)中的像素电路中的驱动晶体管的阈值电压的过程中，可以避免与其余的输出端耦接的子像素因电位不受控状态(例如Floating)而导致信号存在噪声干扰，使得与其余的输出端耦接的子像素错误开启，影响感测线可以检测与多路选择电路10C的第一输出端OUT1C耦接的子像素中的像素电路中的驱动晶体管的阈值电压的精确度，从而提高了感测数据的准确性，提高了显示效果。
在此基础上，在第二阶段中的第二时段，多路选择电路中的第一选择子电路响应于在第二控制端处接收的第二控制信号，将电源电压端的电压传输至第一输出端。多路选择电路中的第二选择子电路响应于在第三控制端处接收的第三控制信号，将在输入信号端处接收的输入信号传输至第二输出端。
例如，参考图9，在多路选择器110中，多路选择电路10A中的第一选择子电路11A响应于在第二控制端MUX2处接收的第二控制信号，将电源电压端S的电压传输至第一输出端OUT1A。多路选择电路10A中的第二选择子电路12A响应于在第三控制端MUX3处接收的第三控制信号，将在输入信号端INA处接收的输入信号传输至第二输出端OUT2A。多路选择电路10B中的第一选择子电路11B响应于在第二控制端MUX2处接收的第二控制信号，将电源电压端S的电压传输至第一输出端OUT1B。多路选择电路10B中的第二选择子电路12B响应于在第三控制端MUX3处接收的第三控制信号，将在输入信号端INB处接收的输入信号传输至第二输出端OUT2B。多路选择电路10C中的第一选择子电路11C响应于在第二控制端MUX2处接收的第二控制信号，将电源电压端S的电压传输至第一输出端OUT1C。多路选择电路10C中的第二选择子电路12C响应于在第三控制端MUX3处接收的第三控制信号，将在输入信号端INC处接收的输入信号传输至第二输出端OUT2C。
例如，参考图10，在多路选择电路10A中，第二晶体管T2响应于高电压的第二控制信号，第二晶体管T2导通，将电源电压端S的低电压传输至第一输出端OUT1A，第一输出端OUT1A的输出信号为低电压信号；第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信号端INA处接收的高电压的输入信号传输至第二输出端OUT2A，第二输出端OUT2A的输出信号为高电压信号。在多路选择电路10B中，第二晶体管T2响应于高电压的第二控制信号，第二晶体管T1导通，将电源电压端S的低电压传输至第一输出端OUT1B，第一输出端OUT1B的输出信号为低电压信号； 第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信号端INB处接收的低电压的输入信号传输至第二输出端OUT2B，第二输出端OUT2B的输出信号为低电压信号。在多路选择电路10C中，第二晶体管T2响应于高电压的第二控制信号，第二晶体管T2导通，将电源电压端S的低电压传输至第一输出端OUT1C，第一输出端OUT1C的输出信号为低电压信号；第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信号端INB处接收的低电压的输入信号传输至第二输出端OUT2C，第二输出端OUT2C的输出信号为低电压信号。
在此情况下，在多路选择器110中，多路选择电路10A的第二输出端OUT2A所耦接的数据线上传输高电压信号，其余的输出端所耦接的数据线上传输的信号均为低电压信号。这样，多路选择电路10A的第二输出端OUT2A所耦接的子像素中的像素电路写入为高电压信号，即，像素电路中的开关晶体管将高电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为高电压，驱动晶体管会被导通；感测晶体管处于导通状态，感测线通过感测晶体管检测驱动晶体管的源极的电压，以感测与多路选择电路10A的第二输出端OUT2A耦接的子像素中的像素电路中的驱动晶体管的阈值电压。并且，其余的输出端所耦接的子像素的像素电路写入为低电压信号，即，像素电路中的开关晶体管将低电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为低电压，驱动晶体管均被处于截止状态，其余的输出端所耦接的子像素的像素电路中的驱动晶体管的阈值电压，不会影响感测与多路选择电路10A的第二输出端OUT2A耦接的子像素中的像素电路中的驱动晶体管的阈值电压。因此，在感测线可以检测与多路选择电路10A的第二输出端OUT2A所耦接的子像素(例如偶数列像素中的第一颜色子像素)中的像素电路中的驱动晶体管的阈值电压的过程中，可以避免与其余的输出端耦接的子像素因电位不受控状态(例如Floating)而导致信号存在噪声干扰，使得与其余的输出端耦接的子像素错误开启，影响感测线可以检测与多路选择电路10A的第二输出端OUT2A耦接的子像素中的像素电路中的驱动晶体管的阈值电压的精确度，从而提高了感测数据的准确性，提高了显示效果。
示例性地，参考图10，在多路选择电路10A中，第二晶体管T2响应于高电压的第二控制信号，第二晶体管T2导通，将电源电压端S的低电压传输至第一输出端OUT1A，第一输出端OUT1A的输出信号为低电压信号；第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信 号端INA处接收的低电压的输入信号传输至第二输出端OUT2A，第二输出端OUT2A的输出信号为低电压信号。在多路选择电路10B中，第二晶体管T2响应于高电压的第二控制信号，第二晶体管T1导通，将电源电压端S的低电压传输至第一输出端OUT1B，第一输出端OUT1B的输出信号为低电压信号；第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信号端INB处接收的高电压的输入信号传输至第二输出端OUT2B，第二输出端OUT2B的输出信号为高电压信号。在多路选择电路10C中，第二晶体管T2响应于高电压的第二控制信号，第二晶体管T2导通，将电源电压端S的低电压传输至第一输出端OUT1C，第一输出端OUT1C的输出信号为低电压信号；第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信号端INB处接收的低电压的输入信号传输至第二输出端OUT2C，第二输出端OUT2C的输出信号为低电压信号。
在此情况下，在多路选择器110中，多路选择电路10B的第二输出端OUT2B所耦接的数据线上传输高电压信号，其余的输出端所耦接的数据线上传输的信号均为低电压信号。这样，多路选择电路10B的第二输出端OUT2B所耦接的子像素中的像素电路写入为高电压信号，即，像素电路中的开关晶体管将高电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为高电压，驱动晶体管会被导通；感测晶体管处于导通状态，感测线通过感测晶体管检测驱动晶体管的源极的电压，以感测与多路选择电路10B的第二输出端OUT2B耦接的子像素中的像素电路中的驱动晶体管的阈值电压。并且，其余的输出端所耦接的子像素的像素电路写入为低电压信号，即，像素电路中的开关晶体管将低电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为低电压，驱动晶体管均被处于截止状态，其余的输出端所耦接的子像素的像素电路中的驱动晶体管的阈值电压，不会影响感测与多路选择电路10B的第二输出端OUT2B耦接的子像素中的像素电路中的驱动晶体管的阈值电压。因此，在感测线可以检测与多路选择电路10B的第二输出端OUT2B所耦接的子像素(例如偶数列像素中的第二颜色子像素)中的像素电路中的驱动晶体管的阈值电压的过程中，可以避免与其余的输出端耦接的子像素因电位不受控状态(例如Floating)而导致信号存在噪声干扰，使得与其余的输出端耦接的子像素错误开启，影响感测线可以检测与多路选择电路10B的第二输出端OUT2B耦接的子像素中的像素电路中的驱动晶体管的阈值电压的精确度，从而提高了感测数据的准确性，提高了显示效果。
示例性地，参考图10，在多路选择电路10A中，第二晶体管T2响应于高电压的第二控制信号，第二晶体管T2导通，将电源电压端S的低电压传输至第一输出端OUT1A，第一输出端OUT1A的输出信号为低电压信号；第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信号端INA处接收的低电压的输入信号传输至第二输出端OUT2A，第二输出端OUT2A的输出信号为低电压信号。在多路选择电路10B中，第二晶体管T2响应于高电压的第二控制信号，第二晶体管T1导通，将电源电压端S的低电压传输至第一输出端OUT1B，第一输出端OUT1B的输出信号为低电压信号；第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信号端INB处接收的低电压的输入信号传输至第二输出端OUT2B，第二输出端OUT2B的输出信号为低电压信号。在多路选择电路10C中，第二晶体管T2响应于高电压的第二控制信号，第二晶体管T2导通，将电源电压端S的低电压传输至第一输出端OUT1C，第一输出端OUT1C的输出信号为低电压信号；第三晶体管T3响应于高电压的第三控制信号，第三晶体管T3导通，将在输入信号端INB处接收的高电压的输入信号传输至第二输出端OUT2C，第二输出端OUT2C的输出信号为高电压信号。
在此情况下，在多路选择器110中，多路选择电路10C的第二输出端OUT2C所耦接的数据线上传输高电压信号，其余的输出端所耦接的数据线上传输的信号均为低电压信号。这样，多路选择电路10C的第二输出端OUT2C所耦接的子像素中的像素电路写入为高电压信号，即，像素电路中的开关晶体管将高电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为高电压，驱动晶体管会被导通；感测晶体管处于导通状态，感测线通过感测晶体管检测驱动晶体管的源极的电压，以感测与多路选择电路10C的第二输出端OUT2C耦接的子像素中的像素电路中的驱动晶体管的阈值电压。并且，其余的输出端所耦接的子像素的像素电路写入为低电压信号，即，像素电路中的开关晶体管将低电压信号写入驱动晶体管的控制极(即栅极)，使得驱动晶体管的栅极的电压为低电压，驱动晶体管均被处于截止状态，其余的输出端所耦接的子像素的像素电路中的驱动晶体管的阈值电压，不会影响感测与多路选择电路10C的第二输出端OUT2C耦接的子像素中的像素电路中的驱动晶体管的阈值电压。因此，在感测线可以检测与多路选择电路10C的第二输出端OUT2C所耦接的子像素(例如偶数列像素中的第三颜色子像素)中的像素电路中的驱动晶体管的阈值电压的过程中，可以避免与其余的输出端耦接的子像素因电位不受控状态(例如Floating)而导致信号存在 噪声干扰，使得与其余的输出端耦接的子像素错误开启，影响感测线可以检测与多路选择电路10C的第二输出端OUT2C耦接的子像素中的像素电路中的驱动晶体管的阈值电压的精确度，从而提高了感测数据的准确性，提高了显示效果。
需要说明的是，在每条感测线感测一个像素电路的驱动晶体管的阈值电压的结束时刻与该感测线感测下一个像素电路的驱动晶体管的阈值电压的开始时刻之间，需要对该感测线进行复位。例如在对感测线进行复位时，感测线在感测一行像素中奇数列像素中的第一颜色子像素结束时刻至感测一行奇数列像素中的第二颜色子像素开始之时刻之间(例如图15中的时间段w)，对感测线进行复位，例如，对于第二行像素，第一扫描信号G1(2)和第二扫描信号G2(2)持续为高电压信号，像素电路中的开关晶体管和感测晶体管导通，输入信号为低电压信号(即复位信号)，数据线上的信号为低电压信号，此时感测线上的信号均为低电压信号。
在此基础上，在一些实施例中，在显示面板的显示阶段，显示面板中的数据线上传输显示所需的数据信号。此时，多路选择电路不会将电源电压端的电压输出，即，第一输出端和第二输出端均不会输出电源电压端的电压。示例性地，在显示阶段，第一选择子电路中的第二晶体管响应于第二控制信号(例如低电压信号)，第二晶体管截止，第二晶体管不会将电源电压端的电压传输至第一输出端，第二选择子电路中的第四晶体管响应于第四控制信号(例如低电压信号)，第四晶体管截止，第四晶体管不会将电源电压端的电压传输至第二输出端。在此阶段，第一选择子电路中的第一晶体管响应于第一控制信号(例如高电压信号)，第一晶体管导通，并将输入信号端的输入信号传输至第一输出端，第二选择子电路中的第三晶体管响应于第三控制信号(例如高电压信号)，第三晶体管导通，并将输入信号端的输入信号传输至第二输出端。这样，多路选择电路的第一输出端和第二输出端耦接的数据线上均传输在输入信号端接收的输入信号，以使像素电路写入对应的输入信号，驱动发光器件显示不同的灰阶。
在此情况下，第一电压控制子电路根据电源电压端的电压和在第二控制端处接收的第二控制信号，控制第一选择子电路在第二控制端处接收的第二控制信号的电压。例如，电源电压端的电压为低电压，第一电压控制子电路根据在第二控制端处接收的低电压的第二控制信号，可以控制第一选择子电路在第二控制端处接收的第二控制信号的电压为低电压。例如，第一电压控制子电路中的第一电容器的存储作用，存储低电压的第二控制信号，并控制 第一选择子电路中的第二晶体管的控制极的电压为低电压，控制第一选择子电路中的第二晶体管响应的第二控制信号为低电压，此时，第二晶体管的控制极的电压为低电压，使得第二晶体管截止，不会将电源电压端的电压传输至第一输出端。相应的，第二电压控制子电路根据电源电压端的电压和在第四控制端处接收的第四控制信号，控制第二选择子电路在第四控制端处接收的第四控制信号的电压。例如，电源电压端的电压为低电压，根据在第四控制端处接收的低电压的第四控制信号，第二电压控制子电路控制可以第二选择子电路在第四控制端处接收的第四控制信号的电压为低电压。例如，第二电压控制子电路中的第二电容器的存储作用，存储低电压的第四控制信号，并控制第二选择子电路中的第四晶体管的控制极的电压为低电压，控制第二选择子电路中的第四晶体管响应的第四控制信号为低电压，此时，第四晶体管的控制极的电压为低电压，使得第四晶体管截止，不会将电源电压端的电压传输至第二输出端。
在此基础上，在显示阶段，第二控制信号线可以在较短时间段内向其耦接的第二控制端传输第二控制信号，第一选择子电路中的第二晶体管响应该第二控制信号(例如低电平电压)，第二晶体管截止，第一电压控制子电路中的第一电容器存储该第二控制信号，并且，第一电容器可以向第二晶体管提供该第二控制信号，使得第二晶体管维持截止状态。这样，在显示阶段，第二控制信号线不用持续向第二控制端传输第二控制信号，即，第二控制信号线可以停止向第二控制端给电，从而可以降低显示装置的硬件瞬态功耗。相应的，在显示阶段，第四控制信号线可以在较短时间段内向其耦接的第四控制端传输第四控制信号，第二选择子电路中的第四晶体管响应该第四控制信号(例如低电平电压)，第四晶体管截止，第二电压控制子电路中的第二电容器存储该第四控制信号，并且，第二电容器可以向第四晶体管提供该第四控制信号，使得第四晶体管维持截止状态。这样，在显示阶段，第四控制信号线不用持续向第四控制端传输第四控制信号，即，第四控制信号线可以停止向第四控制端给电，从而可以降低显示装置的硬件瞬态功耗。
需要说明的是，为了描述方便，本公开的实施例将一些信号端(或控制端、电压端)、一些信号端传输的信号、以及一些信号端所耦接的信号线均采用相同符号表示，但各自的属性不相同。
在本公开的一些实施例中，如图5和图12A所示，显示装置200还包括至少一个数据信号传输通道211。示例性地，一个多路选择电路通过一个数据传输通道与源极驱动器耦接。示例性地，在多路选择器包括三个多路选择电 路的情况下，多路选择器通过三个数据传输通道与源极驱动器耦接。
可以理解的是，源极驱动器210的一个输出端口通过一个数据传输通道211与一个多路选择电路10的输入信号端IN耦接。因此，减少了源极驱动器210的输出端口的数量，减少了源极驱动器210与多路选择电路10耦接的数据传输通道211的数量。
示例性地，源极驱动器与显示面板的衬底基板绑定，并与多路选择电路耦接。
需要说明的是，上述的多路选择电路也可以集成在源极驱动器内部，有益效果与源极驱动器的有益效果相同，此处不再赘述。
在一些实施例中，显示装置还包括ADC(Analog to Digital Converter，模数转换器)。ADC与多条感测线耦接。ADC被配置为感测来自感测线的信号。
可以理解的是，在每条感测线感测一个像素电路的驱动晶体管的阈值电压的结束前的预设时间内，ADC对该感测线进行采样，以感测到该感测线感测的一个像素电路的驱动晶体管的阈值电压。例如，参考图15，在每条感测线感测一个像素电路的驱动晶体管的阈值电压的结束前的预设时间u内，ADC响应于感测控制信号Spr_L，例如感测控制信号Spr_L的电压为高电压，ADC检测感测线上的信号的电压。这样，ADC感测到每条感测线上感测的对应的像素电路中的驱动晶体管的阈值电压，并通过源极驱动器将阈值电压补偿至对应的像素电路中。需要说明的是，上述的预设时间为ADC感测来自每条感测线的信号的时间，该预设时间的长短可以根据实际情况进行设计，在此不作限定。
此外，显示装置除了可以在显示面板关机状态感测驱动晶体管的阈值电压，还可以在消隐期间(Blank)实时感测驱动晶体管的K值(例如K＝W/L×C×u，W/L为驱动晶体管的宽长比，C为沟道绝缘层电容，u为沟道载流子迁移率)。
示例性地，显示装置可以将感测得到的阈值电压与像素电路的显示数据信号进行叠加以得到一叠加数据信号，并将叠加信号输入至像素电路中，在每一帧时间内，像素电路根据叠加数据信号对驱动晶体管的实际阈值电压进行内部补偿，另外，还可以在消隐阶段(Blank)侦测驱动晶体管的迁移率(K)。
本公开的实施例提供一种多路选择电路的驱动方法，多路选择电路采用上述任一实施例中的多路选择电路。示例性地，多路选择电路包括第一选择子电路和第二选择子电路。第一选择子电路与第一控制端、第二控制端、输入信号端、电源电压端和第一输出端耦接。第二选择子电路与第三控制端、 第四控制端、输入信号端、电源电压端和第二输出端耦接。
多路选择电路的驱动方法，包括：第一选择子电路响应于在第一控制端接收的第一控制信号，将在输入信号端处接收的输入信号传输至第一输出端；第二选择子电路响应于在第四控制端处接收的第四控制信号，将电源电压端的电压传输至第二输出端。第一选择子电路响应于在第二控制端处接收的第二控制信号，将电源电压端的电压传输至第一输出端；第二选择子电路响应于在第三控制端处接收的第三控制信号，将在输入信号端处接收的输入信号传输至第二输出端。
需要说明的是，上述的多路选择电路的驱动方法与上述的多路选择电路的有益效果相同，此处不再赘述。
本公开的实施例提供一种多路选择器的驱动方法，采用上述任一实施例中的多路选择器。示例性地，多路选择器包括多个多路选择电路，每个多路选择电路包括第一选择子电路和第二选择子电路，第一选择子电路与第一控制端、第二控制端、输入信号端、电源电压端和第一输出端耦接；第二选择子电路与第三控制端、第四控制端、输入信号端、电源电压端和第二输出端耦接。多个多路选择电路的输入信号端不同，第一输出端不同，第二输出端不同。
多路选择器的驱动方法，包括：
每个多路选择电路中的第一选择子电路响应于在第一控制端接收的第一控制信号，将在其所耦接的输入信号端处接收的输入信号传输至其所耦接的第一输出端；每个多路选择电路中的第二选择子电路响应于在第四控制端处接收的第四控制信号，将电源电压端的电压传输至其所耦接的第二输出端。
每个多路选择电路中的第一选择子电路响应于在第二控制端处接收的第二控制信号，将电源电压端的电压传输至其所耦接的第一输出端；每个多路选择电路中的第二选择子电路响应于在第三控制端处接收的第三控制信号，将在其所耦接的输入信号端处接收的输入信号传输至其所耦接的第二输出端。
需要说明的是，上述的多路选择器的驱动方法与上述的多路选择器的有益效果相同，此处不再赘述。
本公开的实施例提供一种显示装置的驱动方法，采用上述任一实施例中的显示装置。示例性地，显示装置中的显示面板中的每个像素包括多个子像素，每个子像素包括像素电路，像素电路包括驱动晶体管。显示面板还包括多条感测线。显示面板中的多路选择器所耦接的多个像素与一条感测线耦接， 即，多路选择器所耦接的多个像素中的每个子像素中的像素电路与一条感测线耦接。
显示装置的驱动方法包括：
源极驱动器向显示面板中的多路选择器中的各多路选择电路提供输入信号。
其中，多路选择器中的各多路选择电路接收的输入信号不完全相同。例如，多路选择电路中的一个多路选择电路接收高电压(高电平)的输入信号，其余多路选择电路接收低电压(低电平)的输入信号，在此情况下，接收高电压的输入信号的多路选择电路所耦接的像素中的子像素的像素电路的驱动晶体管的阈值电压可以被感测线感测。
多路选择器中的多路选择电路中的第一选择子电路响应于在第一控制端接收的第一控制信号，将在其所耦接的输入信号端处接收的输入信号传输至其所耦接的第一输出端；多路选择器中的多路选择电路中的第二选择子电路响应于在第四控制端处接收的第四控制信号，将电源电压端的电压传输至其所耦接的第二输出端。
感测线感测第一输出端所耦接的像素中子像素中的像素电路的驱动晶体管的阈值电压。
需要说明的是，一条感测线在同一时刻感测一个像素电路的驱动晶体管的阈值电压。也即，对于多路选择器中的多个多路选电路的第一输出端所耦接的像素电路中的驱动晶体管的阈值电压，一条感测线分别在不同的时刻进行感测。
例如，多路选择器中的一个多路选择电路的第一输出端输出高电压信号，其余多路选择电路的第一输出端输出低电压信号，感测线对该一个多路选择电路的第一输出端所耦接的像素中的像素电路中的驱动晶体管的阈值电压进行感测。此时，一个多路选择电路的第二输出端以及其余多路选电路的第一输出端和第二输出端的输出信号均为低电压信号。这样，不会影响感测线感测阈值电压的准确性。
多路选择器中的多路选择电路中的第一选择子电路响应于在第二控制端处接收的第二控制信号，将电源电压端的电压传输至其所耦接的第一输出端；多路选择器中的多路选择电路中的第二选择子电路响应于在第三控制端处接收的第三控制信号，将在其所耦接的输入信号端处接收的输入信号传输至其所耦接的第二输出端。
感测线感测第二输出端所耦接的像素中子像素中的像素电路的驱动晶体 管的阈值电压。
可以理解的是，对于多路选择器中的多个多路选电路的第二输出端所耦接的像素电路中的驱动晶体管的阈值电压，一条感测线分别在不同的时刻进行感测。
例如，多路选择器中的一个多路选择电路的第二输出端输出高电压信号，其余多路选择电路的第二输出端输出低电压信号，感测线对该一个多路选择电路的第二输出端所耦接的像素中的像素电路中的驱动晶体管的阈值电压进行感测。此时，一个多路选择电路的第一输出端以及其余多路选电路的第一输出端和第二输出端的输出信号均为低电压信号。这样，不会影响感测线感测阈值电压的准确性。
需要说明的是，上述的显示装置的驱动方法与上述的显示装置的有益效果相同，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种多路选择电路，包括：
    第一选择子电路，与第一控制端、第二控制端、输入信号端、电源电压端和第一输出端耦接；其中，所述第一选择子电路被配置为，响应于在所述第一控制端接收的第一控制信号，将在所述输入信号端处接收的输入信号传输至所述第一输出端；及，响应于在所述第二控制端处接收的第二控制信号，将所述电源电压端的电压传输至所述第一输出端；和
    第二选择子电路，与第三控制端、第四控制端、所述输入信号端、所述电源电压端和第二输出端耦接；其中，所述第二选择子电路被配置为，响应于在所述第三控制端处接收的第三控制信号，将在所述输入信号端处接收的输入信号传输至所述第二输出端；及，响应于在所述第四控制端处接收的第四控制信号，将所述电源电压端的电压传输至所述第二输出端。
  2. 根据权利要求1所述的多路选择电路，其中，所述第一选择子电路包括：
    第一晶体管，其中，所述第一晶体管的控制极与所述第一控制端耦接，所述第一晶体管的第一极与所述输入信号端耦接，所述第一晶体管的第二极与所述第一输出端耦接；和
    第二晶体管，其中，所述第二晶体管的控制极与所述第二控制端耦接，所述第二晶体管的第一极与所述电源电压端耦接，所述第二晶体管的第二极与所述第一输出端耦接。
  3. 根据权利要求1或2所述的多路选择电路，其中，所述第二选择子电路包括：
    第三晶体管，其中，所述第三晶体管的控制极与所述第一控制端耦接，所述第三晶体管的第一极与所述输入信号端耦接，所述第三晶体管的第二极与所述第二输出端耦接；和
    第四晶体管，其中，所述第四晶体管的控制极与所述第二控制端耦接，所述第四晶体管的第一极与所述电源电压端耦接，所述第四晶体管的第二极与所述第二输出端耦接。
  4. 根据权利要求1～3中任一项所述的多路选择电路，还包括第一电压控制子电路，与所述电源电压端、所述第二控制端和所述第一选择子电路耦接；其中，所述第一电压控制子电路被配置为，根据所述电源电压端的电压和在所述第二控制端处接收的第二控制信号，控制所述第一选择子电路在所述第二控制端处接收的第二控制信号的电压。
  5. 根据权利要求4所述的多路选择电路，其中，所述第一电压控制子电路包括第一电容器；所述第一电容器的第一端与所述电源电压端耦接，所述第一电容器的第二端与所述第二控制端和所述第一选择子电路耦接。
  6. 根据权利要求1～5中任一项所述的多路选择电路，还包括第二电压控制子电路，与所述电源电压端、所述第四控制端和所述第二选择子电路耦接；其中，所述第二电压控制子电路被配置为，根据所述电源电压端的电压和在所述第四控制端处接收的第四控制信号，控制所述第二选择子电路在所述第四控制端处接收的第四控制信号的电压。
  7. 根据权利要求6所述的多路选择电路，其中，所述第二电压控制子电路包括第二电容器；所述第二电容器的第一端与所述电源电压端耦接，所述第二电容器的第二端与所述第四控制端耦接。
  8. 一种多路选择电路，包括：
    第一晶体管，其中，所述第一晶体管的控制极与第一控制端耦接，所述第一晶体管的第一极与输入信号端耦接，所述第一晶体管的第二极与第一输出端耦接；
    第二晶体管，其中，所述第二晶体管的控制极与第二控制端耦接，所述第二晶体管的第一极与电源电压端耦接，所述第二晶体管的第二极与所述第一输出端耦接；
    第三晶体管，其中，所述第三晶体管的控制极与所述第一控制端耦接，所述第三晶体管的第一极与所述输入信号端耦接，所述第三晶体管的第二极与第二输出端耦接；和
    第四晶体管，其中，所述第四晶体管的控制极与所述第二控制端耦接，所述第四晶体管的第一极与所述电源电压端耦接，所述第四晶体管的第二极与所述第二输出端耦接。
  9. 一种多路选择器，包括：多个如权利要求1～8中任一项所述的多路选择电路；其中，多个所述多路选择电路的输入信号端不同，第一输出端不同，第二输出端不同。
  10. 根据权利要求9所述的多路选择器，其中，多个所述多路选择电路的数量为三个。
  11. 一种显示面板，包括：
    多个像素；和
    至少一个如权利要求9或10所述的多路选择器；其中，每个多路选择器与多个像素耦接。
  12. 根据权利要求11所述的显示面板，其中，所述多个像素呈阵列排布；
    所述多路选择器与两列像素耦接；所述多路选择器中的每个多路选择电路的第一输出端与所述两列像素中的一列像素耦接，所述多路选择器中的每个多路选择电路的第二输出端与所述两列像素中的另一列像素耦接。
  13. 根据权利要求12所述的显示面板，其中，所述多路选择器耦接的两列像素相邻。
  14. 根据权利要求11～13中任一项所述的显示面板，其中，每个像素包括多个子像素；在每个多路选择器中，每个多路选择电路的第一输出端和第二输出端分别与不同像素中的发光颜色相同的子像素耦接。
  15. 根据权利要求11～14中任一项所述的显示面板，还包括多条感测线；其中，所述多路选择器所耦接的多个像素与一条感测线耦接。
  16. 一种显示装置，包括：
    如权利要求11～15中任一项所述的显示面板；和
    源极驱动器；其中，所述源极驱动器与所述显示面板中的至少一个多路选择器耦接。
  17. 一种如权利要求1～7中任一项所述的多路选择电路的驱动方法，包括：
    第一选择子电路响应于在第一控制端接收的第一控制信号，将在输入信号端处接收的输入信号传输至第一输出端；
    第二选择子电路响应于在第四控制端处接收的第四控制信号，将电源电压端的电压传输至第二输出端；
    所述第一选择子电路响应于在第二控制端处接收的第二控制信号，将电源电压端的电压传输至所述第一输出端；以及
    所述第二选择子电路响应于在第三控制端处接收的第三控制信号，将在所述输入信号端处接收的输入信号传输至所述第二输出端。
  18. 一种多路选择器的驱动方法，其中，所述多路选择器包括多个多路选择电路；每个多路选择电路包括第一选择子电路和第二选择子电路；所述第一选择子电路与第一控制端、第二控制端、输入信号端、电源电压端和第一输出端耦接；所述第二选择子电路与第三控制端、第四控制端、所述输入信号端、所述电源电压端和第二输出端耦接；所述多个多路选择电路的输入信号端不同，第一输出端不同，第二输出端不同；所述驱动方法包括：
    每个多路选择电路中的第一选择子电路响应于在所述第一控制端接收的第一控制信号，将在其所耦接的输入信号端处接收的输入信号传输至其所耦 接的第一输出端；
    每个多路选择电路中的第二选择子电路响应于在所述第四控制端处接收的第四控制信号，将所述电源电压端的电压传输至其所耦接的第二输出端；
    每个多路选择电路中的第一选择子电路响应于在所述第二控制端处接收的第二控制信号，将所述电源电压端的电压传输至其所耦接的第一输出端；以及
    每个多路选择电路中的第二选择子电路响应于在所述第三控制端处接收的第三控制信号，将在其所耦接的输入信号端处接收的输入信号传输至其所耦接的第二输出端。
  19. 一种如权利要求16所述的显示装置的驱动方法，其中，所述显示装置中的显示面板中的每个像素包括多个子像素；每个子像素包括像素电路；所述像素电路包括驱动晶体管；所述显示面板还包括多条感测线；所述显示面板中的多路选择器所耦接的多个像素与一条感测线耦接；所述显示装置的驱动方法包括：
    源极驱动器向所述显示面板中的多路选择器中的各多路选择电路提供输入信号；
    所述多路选择器中的多路选择电路中的第一选择子电路响应于在第一控制端接收的第一控制信号，将在其所耦接的输入信号端处接收的输入信号传输至其所耦接的第一输出端；
    所述多路选择器中的多路选择电路中的第二选择子电路响应于在第四控制端处接收的第四控制信号，将电源电压端的电压传输至其所耦接的第二输出端；
    所述感测线感测所述第一输出端所耦接的像素中子像素中的像素电路的驱动晶体管的阈值电压；
    所述多路选择器中的多路选择电路中的第一选择子电路响应于在第二控制端处接收的第二控制信号，将所述电源电压端的电压传输至其所耦接的第一输出端；
    所述多路选择器中的多路选择电路中的第二选择子电路响应于在第三控制端处接收的第三控制信号，将在其所耦接的输入信号端处接收的输入信号传输至其所耦接的第二输出端；
    所述感测线感测所述第二输出端所耦接的像素中子像素中的像素电路的驱动晶体管的阈值电压。
PCT/CN2021/116327 2020-10-21 2021-09-02 多路选择电路、多路选择器、驱动方法、显示面板、显示装置 WO2022083313A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/793,536 US11769445B2 (en) 2020-10-21 2021-09-02 Multiplexer circuit, multiplexer, driving method, display panel, and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011133273.5A CN112201198A (zh) 2020-10-21 2020-10-21 多路选择电路、多路选择器、驱动方法、显示面板及装置
CN202011133273.5 2020-10-21

Publications (1)

Publication Number Publication Date
WO2022083313A1 true WO2022083313A1 (zh) 2022-04-28

Family

ID=74010532

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/116327 WO2022083313A1 (zh) 2020-10-21 2021-09-02 多路选择电路、多路选择器、驱动方法、显示面板、显示装置

Country Status (3)

Country Link
US (1) US11769445B2 (zh)
CN (1) CN112201198A (zh)
WO (1) WO2022083313A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112201198A (zh) 2020-10-21 2021-01-08 合肥京东方卓印科技有限公司 多路选择电路、多路选择器、驱动方法、显示面板及装置
CN114283719B (zh) * 2021-12-31 2023-07-14 湖北长江新型显示产业创新中心有限公司 开关控制电路及其驱动方法、显示装置
WO2023225861A1 (zh) * 2022-05-24 2023-11-30 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
KR20240000026A (ko) * 2022-06-22 2024-01-02 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170118341A (ko) * 2016-04-15 2017-10-25 엘지디스플레이 주식회사 유기발광 표시장치 및 그의 구동 방법
CN110706636A (zh) * 2019-03-11 2020-01-17 友达光电股份有限公司 移位暂存电路及栅极驱动器
CN110853556A (zh) * 2018-12-14 2020-02-28 友达光电股份有限公司 脉冲产生电路
CN111243530A (zh) * 2018-11-28 2020-06-05 乐金显示有限公司 数据驱动器和包括数据驱动器的有机发光显示装置
US20200233522A1 (en) * 2016-08-31 2020-07-23 Lg Display Co., Ltd. Display Panel Having Built-In Touchscreen, Display Device Having Built-In Touch Screen, Integrated Driving Circuit, and Driving Method
CN112201198A (zh) * 2020-10-21 2021-01-08 合肥京东方卓印科技有限公司 多路选择电路、多路选择器、驱动方法、显示面板及装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100602361B1 (ko) * 2004-09-22 2006-07-19 삼성에스디아이 주식회사 디멀티플렉서 및 이를 이용한 발광 표시장치와 그의구동방법
CA2637343A1 (en) * 2008-07-29 2010-01-29 Ignis Innovation Inc. Improving the display source driver
KR101597037B1 (ko) * 2014-06-26 2016-02-24 엘지디스플레이 주식회사 구동소자의 전기적 특성 편차를 보상할 수 있는 유기발광 표시장치
CN105185326B (zh) * 2015-08-12 2017-10-17 深圳市华星光电技术有限公司 一种液晶显示面板及其驱动电路
CN105761675B (zh) * 2016-05-18 2018-03-20 上海天马微电子有限公司 有机发光显示面板及其驱动方法、有机发光显示装置
KR102369624B1 (ko) 2017-06-30 2022-03-03 엘지디스플레이 주식회사 표시패널과 이를 이용한 전계 발광 표시장치

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170118341A (ko) * 2016-04-15 2017-10-25 엘지디스플레이 주식회사 유기발광 표시장치 및 그의 구동 방법
US20200233522A1 (en) * 2016-08-31 2020-07-23 Lg Display Co., Ltd. Display Panel Having Built-In Touchscreen, Display Device Having Built-In Touch Screen, Integrated Driving Circuit, and Driving Method
CN111243530A (zh) * 2018-11-28 2020-06-05 乐金显示有限公司 数据驱动器和包括数据驱动器的有机发光显示装置
CN110853556A (zh) * 2018-12-14 2020-02-28 友达光电股份有限公司 脉冲产生电路
CN110706636A (zh) * 2019-03-11 2020-01-17 友达光电股份有限公司 移位暂存电路及栅极驱动器
CN112201198A (zh) * 2020-10-21 2021-01-08 合肥京东方卓印科技有限公司 多路选择电路、多路选择器、驱动方法、显示面板及装置

Also Published As

Publication number Publication date
CN112201198A (zh) 2021-01-08
US11769445B2 (en) 2023-09-26
US20230079091A1 (en) 2023-03-16

Similar Documents

Publication Publication Date Title
US11881164B2 (en) Pixel circuit and driving method thereof, and display panel
US20220284851A1 (en) Pixel circuit and driving method thereof, display panel
WO2022083313A1 (zh) 多路选择电路、多路选择器、驱动方法、显示面板、显示装置
US20240062721A1 (en) Pixel Circuit and Driving Method Thereof, and Display Panel
CN109872692B (zh) 像素电路及其驱动方法、显示装置
US11881178B2 (en) Light emitting display device and method of driving same
US20230145805A1 (en) Display device, display panel, and display driving method
CN114220389A (zh) 像素驱动电路及其驱动方法、显示面板及装置
CN107665668B (zh) 显示装置
KR20200034477A (ko) 전계 발광 표시장치
US20230143178A1 (en) Display device and data driving circuit
US11783774B2 (en) Display device, driving circuit and display driving method
US11862086B2 (en) Pixel circuit and display device including the same
CN114927102B (zh) 像素驱动电路及其驱动方法、显示面板、显示装置
US12008965B2 (en) Display panel and display device using the same
WO2022094738A1 (zh) 像素电路及驱动方法、显示面板、显示装置
KR20210080960A (ko) 게이트 구동 회로 및 이를 포함하는 발광 표시 장치
KR20210085346A (ko) 표시 장치 및 보상 방법
US11922866B1 (en) Pixel, display device, and driving method of the display device
CN114708837B (zh) 像素驱动电路及其驱动方法、显示面板、显示装置
US11763755B2 (en) Light emitting display device and driving method of the same
US12027080B1 (en) Display device, display panel, and subpixel circuit
US20230186854A1 (en) Display Device
US11854480B2 (en) Pixel circuit, method for driving pixel circuit and display device
US20240221636A1 (en) Display Device and Method of Driving the Same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21881732

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21881732

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 25.01.2024)