WO2022073604A1

WO2022073604A1 - Forming semiconductor devices for non-hermetic environments

Info

Publication number: WO2022073604A1
Application number: PCT/EP2020/078108
Authority: WO
Inventors: Malcolm PATE; Samir RIHANI; Bo Ruan; Wei Liu; Xin Chen
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2020-10-07
Filing date: 2020-10-07
Publication date: 2022-04-14
Also published as: CN116325388A

Abstract

Described herein is a method (700) for forming an optical device (600) from a semiconductor wafer (401), the optical device having a facet (602, 603) at one end of an optical waveguide (601). The method comprises: etching (701) the wafer to form an etched section (402), the etched section having a side wall (403) and a base, the side wall of the etched section defining the facet; and applying (702) a coating (604) to the wafer (401). This may allow for a cost- efficient way of forming a semiconductor device that may operate in non-hermetic environments, with a conformal coating across the top surface of the chip and the facet(s).

Description

FORMING SEMICONDUCTOR DEVICES FOR NON-HERMETIC ENVIRONMENTS

FIELD OF THE INVENTION

This invention relates to semiconductor devices that may be manufactured for use in challenging environments.

BACKGROUND

Standard lasers, electroabsorption modulated lasers (EML), Mach-Zehnder modulators and waveguide photodetectors are widely used in telecommunications applications. These devices have waveguide structures and generally have front and rear facets.

A typical distributed feedback (DFB) laser structure comprises an optical waveguide having facets at opposite ends of the waveguide. A high-reflection (HR) coating may be applied to the rear facet. The rear facet acts as a rear reflector and the front facet can act as a front reflector. A HR coating or an anti-reflection (AR) coating may be applied to the front facet. Light exits the laser cavity at the front facet. The laser cavity generally comprises an active layer interposed between layers of p- and n-type semiconductor material. The waveguide of the laser comprises a material with a refractive index n greater than that of the surrounding substrate. Light is emitted from the end of the waveguide at the front face of the laser.

The HR facet may boost the output power. The AR facet may help to reduce optical reflection and may improve the output power. Generally, the top surface of the laser has no extra coating, apart from the top metal contacts for the laser. An atomic layer deposition (ALD) coating layer can be applied after bonding to the carrier.

A typical EML structure comprises a DFB coupled to an electroabsorption modulator (EAM). The EAM section is normally butt-coupled to the DFB laser section. A HR-coated facet on the DFB section can boost the output power. An AR-coated facet on the EAM section can reduce the optical reflection. Electrically, the DFB and EAM sections are isolated by ion-implantation or etching.

There are demands for such devices to be used in a non-hermetic environment, where conditions can reach 85% humidity and 85°C temperature. For example, data center applications. However, the “gold box“ packaging normally required in such applications is generally expensive and time consuming to manufacture. Under 85% humidity and 85°C conditions, the characteristics of a laser or EML can quickly change. EAM absorption characteristics may change, and laser characteristic can also change if the device is not protected properly. Figure 1 (a) shows the change in output power with time when an EML device has no top surface protection.

For such devices to effectively operate in a non-hermetic environment, they are generally protected by various schemes. Among them, ALD can be used to deposit coatings on the facets, and also on top of the chip surface. Alternatively, after the chip is bonded onto the carrier, ALD can be used to deposit various layers to protect the Chip-on-Carrier (COC).

Generally the ALD layer is deposited on the wafer to cover the top surface. Using an ALD layer for AR/HR facet coating is difficult, as the deposition process may take approximately 3 hours to deposit a 20 nm thick coating. A normal AR coating for a 1300 nm range laser is approximately 800 nm thick, so this method is not suitable for mass production. Furthermore, the ALD layer is very dense, and results in a higher stress on the chip/device, which can cause other reliability failure modes.

Another known scheme involves depositing an ALD layer on the top surface of the chip, and using properly designed non-hermetic AR/HR coatings to protect the facets. In this scheme, the joints between facets and top surface need to be protected properly, as any imperfections at the joints may be subject to water ingression, which is particularly true if a mechanical method is used to cleave the bars to form the facets.

With a top surface coated with SiO₂, using plasma-enhanced chemical vapour deposition (PECVD) or physical vapour deposition (PVD), the EML characteristics change may be smaller and the device may last longer, as shown in Figure 1 (b). However, the PECVD or PVD coating may not be conformal and can have pin holes on the surface, as shown in Figure 2. As shown in Figure 3, such chips may fail and in this event may undergo water ingression. The weakest part is the joints between the top ALD coating and the AR/HR coatings.

It is also desirable for the device to be able to withstand a 85°C/85% humidity environment for 2000 to 5000 hours. This demands the cleaved facet quality to be very high and the joints between the top surface and the AR/HR coatings to be well protected, which is difficult to guarantee during mass production, if a standard bar-cleaving method is used. It is desirable to develop of new method of producing such devices that allows them to operate in non-hermetic or similar environments at reduced cost.

SUMMARY

According to one aspect there is provided a method for forming an optical device from a semiconductor wafer, the optical device having a facet at one end of an optical waveguide, the method comprising: etching the wafer to form an etched section, the etched section having a side wall and a base, the side wall of the etched section defining the facet; and applying a coating to the wafer.

This may allow for a cost-efficient way of forming a semiconductor device that may operate in non-hermetic environments, with a conformal coating across the top surface of the chip and the facets.

The method may further comprise applying stress to the wafer such that it cleaves, with the cleavage being along the base of the etched section. The cleavage may be initiated at the base of the etched section. The wafer may be cleaved into bars. Cleaving the wafer along the base of the etched section may prevent damage being caused to the facet and the coating.

The coating may be applied to an upper surface of the wafer and the facet. This may allow for the coating to conform to the upper surface and the facets to produce a conformal, continuous coating across the whole wafer.

The coating may form a continuous layer between the upper surface and the facet. This may allow the device to operate in a non-hermetic environment.

The coating may be applied to the upper surface and the facet simultaneously. This may be efficient for producing the device by allowing the coating to be applied to the whole wafer and may allow a continuous coating to be formed.

The step of applying a coating to the wafer may comprise applying a coating to the whole of the upper surface of the wafer. This may allow the coating to be applied to multiple chips that are formed from one wafer simultaneously, prior to cleaving the wafer into separate bars comprising the chips. The coating may be a hermetic coating. This may allow the device to operate in 85% humidity and 85°C temperature conditions. The hermetic coating may be substantially air and/or water tight. Thus, the coating provides a seal from the outside and parts of the device beneath the coating can be protected in damp and/or humid environments.

The hermetic coating may form part of an anti-reflection coating or a high-reflection coating. This may prevent cracking and water ingression between coatings.

The method may further comprise applying an anti-reflection coating or a high-reflection coating to the facet. This may allow each of the facets to be separately coated as appropriate.

The step of applying the coating to the wafer may be performed using an atomic layer deposition process. This may be a convenient method that provides the necessary coating properties for the device to be used in a non-hermetic environment.

The coating thickness may be between 10 nm to 250 nm. This may provide an appropriate amount of protection to the device in its working environment.

The coating may comprise one or more of AI₂O₃, SiN, Ta₂O₅, and SiO₂. Such coating materials may provide protection to the device in its working environment.

The base may be located deeper into the wafer than the facet. This may prevent damage to the facet during cleaving of the wafer into bars, each bar comprising one or more semiconductor devices.

The step of etching the wafer may be performed using a dry etch or a dry plus wet etch process. Such processes may be convenient for performing the etching step on the semiconductor wafer.

The depth of the side wall of the etched section may be between 1.0 pm to 10.0 pm. This may provide a suitable dimension for the facet.

The side wall may be perpendicular to the longitudinal axis of the waveguide. This may allow the side wall to effectively act as a facet during operation of the device.

The step of applying stress to the wafer such that it cleaves may form a semiconductor chip comprising the device. A single wafer may be cleaved into multiple chips. Thus, the upper surfaces and facets of multiple chips or devices may be simultaneously coated before cleaving the wafer into the separate chips or devices.

According to another aspect there is provided a semiconductor device formed by the method described above, wherein the device is a Fabry Perot laser, a DFB laser, a DBR laser, a tunable laser, an electroabsorption modulated laser, a Mach-Zehnder modulator or a waveguide photodetector. The method may therefore be used to manufacture a range of optical devices.

The semiconductor device may be configured to operate in a non-hermetic environment. This is desirable for applications such as data centres.

According to a further aspect there is provided an optical device formed on a semiconductor wafer having upper, lower and lateral surfaces, the optical device having an optical waveguide, a facet defined at an end of the optical waveguide and a cleavage surface incorporating the facet, the cleavage surface intersecting the upper, lower and lateral surfaces and comprising a fracture initiation zone offset from the upper, lower and lateral surfaces and spatially offset from the facet.

BRIEF DESCRIPTION OF THE FIGURES

The present invention will now be described by way of example with reference to the accompanying drawings.

In the drawings:

Figure 1 (a) shows the percentage change in output power with time when an EML device has no top surface protection.

Figure 1 (b) shows the percentage change in output power with time when an EML device has a top surface coated with SiO₂ using PECVD or PVD.

Figure 2 shows defects that can occur in a coated device.

Figure 3 shows an example of a chip where the protective coating has failed. Figure 4(a) shows a Scanning Electron Microscopy (SEM) image of wafer having an etched section as described herein.

Figure 4(b) shows an SEM image of the cross section of the etched section.

Figure 5 shows a coating applied to the top surface of a device and a facet.

Figure 6(a) shows a schematic illustration of the top view of an EML formed by the method described herein.

Figure 6(b) shows a schematic illustration of the cross-section of an EML formed by the method described herein.

Figure 6(c) shows an SEM image of the cross-section of the rear facet of an EML with a hermetic ALD coating and multiple HR coating layers formed by the method described herein.

Figure 7 shows an example of a method of forming an optical device from a semiconductor wafer.

DETAILED DESCRIPTION

The method described herein uses a combination of on-wafer etching and on-wafer coating to produce an optical device that is suitable for operation in a non-hermetic environment.

Figure 4(a) shows an SEM image of a semiconductor wafer, shown generally at 401. The semiconductor wafer may be made from one or more semiconductor materials including, but not limited to, InP, GaAs, Si and GaN/AIN. The semiconductor wafer has upper, lower and lateral surfaces.

An etching process is used at the wafer level to form at least one facet of the optical device. An etched section, shown generally at 402 in Figure 4(a), is formed on the wafer. The wafer can be etched using, for example, a dry etch or dry plus wet etch process. Multiple etched sections can be formed on the wafer. This can allow multiple devices to be formed from one wafer. The etching process is therefore performed before cleaving the wafer into bars. The etched facet is located at one end of the waveguide of the device. The waveguide of the device comprises a material with a refractive index n greater than that of the surrounding material. Light travels along the waveguide. The device preferably comprises facets at opposite ends of the waveguide. During operation, light is emitted from the device at the front facet. The rear facet receives the incoming light signal and can act as a rear reflector.

The etched section comprises a side wall 403. The side wall may be parallel to the lateral surface of the wafer. The side wall of the etched section defines a facet of the semiconductor device that is formed from the wafer. The facet is preferably perpendicular to the longitudinal axis of the waveguide of the device. The etch depth of the facet (corresponding to the height of the side wall) is preferably between 1.0-10.0 pm. The etched section may also comprise a second side wall, indicated at 404 in Figure 4(b), opposite to the first side wall. The second side wall is preferably parallel to the first side wall. The second side wall may define a facet of a further semiconductor device that is formed when the wafer is cleaved into bars. Each bar comprises one or more semiconductor device chips. An etched section comprising two side walls may therefore be formed at the interface between two areas of the wafer that are to be formed into two separate devices or chips.

The etched section also comprises a base. The base is preferably formed by the etching process at the same time and/or in the same etching step as the side wall(s). The base and the side wall(s) may be formed by a process other than etching (i.e. another suitable material removal process).

The base is located deeper into the wafer than the facet (and therefore than the side wall(s)). The base of the etched section preferably has a maximum depth that extends over less than 10% of the total plan area of the base. The maximum depth may be defined by a base wall or line that is not parallel with the upper surface of the wafer.

Conveniently, part of the base is offset from the facet parallel to a major plane of the wafer and/or perpendicular to the facet. In the example shown in Figures 4(a) and 4(b) the base is defined by a pair of walls 405, 406 which abut respective side walls 403, 404 and converge at an edge 407 which is deeper into the wafer than the deepest edges of the facets. The base may be tapered. In the examples shown in Figures 4(a) and 4(b), the base of the etched section is generally V-shaped in cross-section. The base comprises and/or is defined by two base portions 405, 406 that intersect at a vertex 407. The base portions 405, 406 may be walls. The base portions 405, 406 are planar and intersect along a linear region 407 at the deepest part (the maximum depth) of the base. The line of that region preferably extends parallel to the plane of one or both of the side walls 403, 404. The linear region of maximum depth is located deeper into the wafer than the facet. The V-shape of the base of the etched section can assist the mechanical cleaving of the wafer to bars by initiating cleavage of the wafer away from the facet. This helps to avoid damage to the facet and the coating in the region of the facet and the areas of the joints between the facet and the upper surface. Put another way, the side walls 403, 404 lie on either side of a channel in the wafer. The base region defined by walls 405, 406 defines the base of that channel. By virtue of the base region, the deepest part of the channel (407) is spatially offset from the facet as defined by side wall 403. Furthermore, the deepest part of the channel is defined by a sharply angled edge where the walls 405, 406 meet. These features each mean that when the wafer is subject to stress, e.g. a suitable bending stress across the channel, cleavage of the wafer will typically be initiated at a point offset from the facet 403 and extend through the depth of the wafer in a direction away from the facet 403. This can make it easier to cleave the wafer without risk of damage to the facet 403.

Alternatively, the base may be U-shaped. The base may have a region, or point, where the distance between the deepest point (the region or point of maximum depth) of the base and the lower surface of the wafer is smaller than at regions closer to the facet, i.e. the wafer is thinner in this point or region, such that cleavage is initiated at the thinnest part of the base.

The base may have other suitable shapes or profiles.

The base therefore comprises a portion at which cleavage is preferentially initiated upon the application of stress to the base of the etched section, as will be described in more detail below. This portion is remote from the facet, such that the facet and the coating applied to it, as described in more detail below, is not damaged by the cleaving process.

After the etched section(s) is/are formed in the wafer, a coating is applied to the wafer. The coating is applied to the whole wafer, such that if the wafer has multiple etched sections, the coating will cover the top surface of the wafer and each of the side walls (defining the facets of the semiconductor devices being manufactured from the wafer) and the base of an etched section. The coating can therefore be applied to the whole wafer in one step, as opposed to being applied to individual parts of the wafer separately.

The coating is preferably a hermetic coating. This is a coating that is substantially air and/or watertight. Thus, the coating provides a seal from the outside and parts of the device beneath the coating can be protected in damp and/or humid environments. Additionally, a hermetic HR or AR coating may be applied over the hermetic coating, either before or after cleaving the wafer into bars, as will be described in more detail below.

Once coated in such a way, the device may operate in a non-hermetic environment and it is not necessary for the device to be packaged into a “gold box”. The chip itself can withstand damp conditions, high temperatures, pollution, etc.

In a preferred embodiment, the coating is applied to the wafer using Atomic Layer Deposition (ALD). ALD is a chemical gas phase thin film deposition method based on sequential, selfsaturating surface reactions. Two or more precursor chemicals, each containing different elements of the materials being deposited, are introduced to the substrate surface separately, one at a time. Each precursor saturates the surface, forming a monolayer of material. The resulting film is very dense, extremely conformal with no pinholes, making it an ideal method to deposit surface coatings for improved hermetic sealing.

The coating is applied at the wafer level after the etching process used to form the facet(s). The coating process, such as ALD, is used to deposit a thin layer of material, or a combination of materials. The coating material may include, but is not limited to, one or more of AI₂O₃, SiN, Ta₂O₅, and SiO₂. Conveniently, the coating layer thickness may be between 10 nm to 250 nm. When using ALD, the ALD layer is preferably between approximately 10 to 100 nm thick to minimize the stress caused to the wafer and to protect the surface of the device from water ingression during operation.

The coating is therefore applied to the upper surface of the wafer and the facet(s) simultaneously and, as indicated in Figure 5, the coating 501 forms a continuous layer between the upper surface 502 and the facet 503.

After etching and coating, the wafer is cleaved into bars, each bar comprising at least one semiconductor device. Stress is applied to the wafer such that it cleaves, with the cleavage being preferentially initiated at the base of the etched section. The cleavage is along the base of the etched section.

In the preferred implementation shown in Figures 4(a) and 4(b), the V-shape of the base formed during the etched facet process can assist the mechanical cleaving of the wafer into bars by concentrating stress at the vertex 407 where the base portions 405, 406 meet. The cleavage therefore occurs along the line that defines the deepest part of the base. During the cleaving process, the facet is not impacted, i.e. no mechanical force is applied directly to the facet, which minimizes possible damage to the facet. Therefore, as the base is remote from the facet, the facets may not be impacted by stresses during cleaving.

Because the cleavage is initiated away from the facet, and extends along the base of the etched section, there are no weak points in the coating for water ingression in the vicinity of the facet. The coating and the facet are relatively undisturbed during bar cleaving because the wafer is cleaved along the base of the etched section, which is remote from the facet.

After cleaving, the optical device comprises a cleavage surface that intersects the upper, lower and lateral surfaces of the wafer and comprises a fracture initiation zone offset from the upper, lower and lateral surfaces of the wafer and spatially offset from the facet.

After the application of the ALD hermetic coating and after cleaving, properly designed hermetic AR or HR coatings can be applied to the facets by conventional coating methods to further protect the chip under non-hermetic conditions. The design of such AR or HR coatings may take into account the impact of the thin ALD layer of the reflective properties of the coating.

Alternatively, the AR or HR coatings (or further AR/HR coatings) can be applied on the wafer after the hermetic coating and before cleaving the wafer into bars. The AR/HR coating may be applied to the upper surface of the wafer and the facet(s). The AR/HR coating may form a continuous layer between the upper surface and the facet. The AR/HR coating may be applied to the upper surface and the facet simultaneously. The AR/HR coating may also be applied to the base of the etched section.

The hermetic ALD layer previously applied to the facets can be further protected by the AR or HR coating.

The device formed by the method described herein may have a second facet at an opposite end of the waveguide to the first facet described above. The second facet may be defined by a side wall of a second etched section. The second facet may have a coating applied to it during the coating of the wafer. Stress may be applied to the wafer such that it cleaves along the base of the second etched section. This may form a bar comprising a semiconductor device wherein each facet at an opposite end of the waveguide has been formed via the method described herein. Each of the facets may optionally have a further coating applied to it. For example, the facet at the emissive face (front facet) of the semiconductor device may be further coated with an AR coating and the facet at which light enters the device (rear facet) may be coated with a HR coating, as described above.

It is preferable that both facets of the device are formed by etching as described herein, so that a coating can then be applied that is continuous across the top surface of the wafer and both the front facet and rear facet of the device. Using this etched facet process, the facets are already formed before bar cleaving, which avoids using a mechanical cleaving process to form the facets.

Alternatively, the method may further comprise forming a second facet at an opposite end of the waveguide using conventional cleaving. Thus, only one facet of the device (i.e. either the rear or front facet) may be formed by the etching process described above.

Figures 6(a) to 6(c) show an example of an EML formed using the method described herein. The EML comprises a DFB laser optically coupled to an EAM, with an isolation region in between. The waveguide of the device is indicated at 601. The waveguide of the device comprises a material with a refractive index n greater than that of the surrounding substrate. The rear (HR) facet is shown at 602 and the front (AR) facet is shown at 603. Light is emitted from the end of the waveguide at the front facet 603 of the device. The DFB and EAM each comprise an active layer of multiple quantum well material (MQW1/2) interposed between layers of p- and n-type semiconductor material. The layers are elongated in a direction extending between the rear facet and the front facet. The DFB laser additionally comprises a Bragg grating.

The ALD coating is shown at 604. As described above, the coating layer deposition is performed during wafer processing, before bar cleaving. The coating is applied to the top surface of the wafer and also to the etch-formed facets 602, 603. Thus, a continuous, conformal, dense and hermetic thin ALD layer 604 covers the upper surface of the chip and the facets.

This may conveniently eliminate points of weakness in the coating. This may allow the coating to be water tight. Furthermore, only a thin ALD layer is needed. Therefore, the deposition time is manageable and stress can be minimized.

After bar cleaving the ALD coating 604 is integrated with the hermetic HR and AR coatings, shown at 605 and 606 respectively. The ALD layer(s) therefore form part of the HR and AR coatings. Figure 6(c) shows an SEM image of the cross-section of the rear facet 602 of an EML with a hermetic ALD coating 604 and multiple HR coating layers 605.

As a result of the hermetic coating applied across the top surface and the facets, and optionally additional AR/HR coatings applied to at least the facets of the device and optionally the top surface, the device is well protected against a damp/hot environment. In some implementations, the top surface and surface joints can withstand a 85°C/85% humidity environment for at least 2000-5000 hours.

Figure 7 shows an example of a method 700 for forming an optical device from a semiconductor wafer, the optical device having a facet at one end of an optical waveguide. At step 701 , the method comprises etching the wafer to form an etched section, the etched section having a side wall and a base, the side wall of the etched section defining the facet. At step 702, the method comprises applying a coating to the wafer. The wafer can then be cleaved along the base of the etched section to form bars, each bar comprising a respective semiconductor device.

In such way, hermetic ALD layers can be deposited which not only cover the top surface of the device, but also the front facet and/or back facet.

After cleaving the wafer into bars, by adjusting the coating designs, the ALD layer can be integrated with the AR/HR coatings (as appropriate), and the devices are well protected against damp and hot environments. The ALD layers can form part of the HR or AR coatings. As the ALD layer is conformal, the joints between the top surface and the facets do not act as a weak point. However, if required, the ALD layer can be etched away in an area for gold wire bonding on the chip.

The method described herein allows the cleaved facet quality to be high, and the joints between the top surface and the facet coatings to be well protected. The described combination of on-wafer etching to form the facet and on-wafer ALD coating may result in a chip that can withstand 85% humidity and 85°C temperature for greater than 2000 hours.

The method may be used to fabricate a range of optical semiconductor devices, such as Fabry Perot lasers, DFB lasers, DBR lasers, tunable lasers, electroabsorption modulated lasers, Mach-Zehnder modulators and waveguide photodetectors. Such devices may effectively operate under non-hermetic conditions and may be more reliable. The semiconductor chip can work as chip-on-board and there is no need for a “gold box” package, allowing for a low- cost solution in non-hermetic environments. The process is suitable for mass production and may allow many devices to be coated on a wafer in a single step. The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

Claims

1. A method (700) for forming an optical device (600) from a semiconductor wafer (401), the optical device having a facet (602, 603) at one end of an optical waveguide (601), the method comprising: etching (701) the wafer to form an etched section (402), the etched section having a side wall (403) and a base, the side wall of the etched section defining the facet; and applying (702) a coating (604) to the wafer (401).

2. The method as claimed in claim 1 , the method further comprising applying stress to the wafer (401) such that it cleaves, with the cleavage being along the base of the etched section (402).

3. The method as claimed in claim 1 or claim 2, wherein the coating (604) is applied to an upper surface of the wafer (401) and the facet (602, 603).

4. The method as claimed in claim 3, wherein the coating (604) forms a continuous layer between the upper surface and the facet.

5. The method as claimed in claim 3 or claim 4, wherein the coating (604) is applied to the upper surface and the facet simultaneously.

6. The method as claimed in any of claims 3 to 5, wherein applying a coating (604) to the wafer (401) comprises applying a coating to the whole of the upper surface of the wafer.

7. The method as claimed in any preceding claim, wherein the coating (604) is a hermetic coating.

8. The method as claimed in claim 7, wherein the hermetic coating (604) forms part of an antireflection coating or a high-reflection coating (605).

9. The method as claimed in claim 7 or claim 8, wherein the method further comprises applying an anti-reflection coating or a high-reflection coating (605) to the facet.

10. The method as claimed in any preceding claim, wherein the step of applying the coating (604) to the wafer is performed using an atomic layer deposition process.

11. The method as claimed in any preceding claim, wherein the coating thickness is between

10 nm to 250 nm.

12. The method as claimed in any preceding claim, wherein the coating (604) comprises one or more of AI₂O₃, SiN, Ta₂O₅, and SiO₂.

13. The method as claimed in any preceding claim, wherein the base is located deeper into the wafer (401) than the facet (602, 603).

14. The method as claimed in any preceding claim, wherein the step of etching (701) the wafer (401) is performed using a dry etch or a dry plus wet etch process.

15. The method as claimed in any preceding claim, wherein the depth of the side wall (403) of the etched section (402) is between 1.0 pm to 10.0 pm.

16. The method as claimed in any preceding claim, wherein the side wall (403) is perpendicular to the longitudinal axis of the waveguide.

17. The method as claimed in any preceding claim, wherein applying stress to the wafer (401) such that it cleaves forms a semiconductor chip comprising the device.

18. A semiconductor device formed by the method of any preceding claim, wherein the device is a Fabry Perot laser, a DFB laser, a DBR laser, a tunable laser, an electroabsorption modulated laser, a Mach-Zehnder modulator or a waveguide photodetector.

19. The semiconductor device as claimed in any preceding claim, wherein the device is configured to operate in a non-hermetic environment.

20. An optical device (600) formed on a semiconductor wafer (401) having upper, lower and lateral surfaces, the optical device having an optical waveguide (601), a facet (602, 603) defined at an end of the optical waveguide and a cleavage surface incorporating the facet, the cleavage surface intersecting the upper, lower and lateral surfaces and comprising a fracture initiation zone offset from the upper, lower and lateral surfaces and spatially offset from the facet.