WO2022070862A1 - Module à hautes fréquences et dispositif de communication - Google Patents

Module à hautes fréquences et dispositif de communication Download PDF

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Publication number
WO2022070862A1
WO2022070862A1 PCT/JP2021/033534 JP2021033534W WO2022070862A1 WO 2022070862 A1 WO2022070862 A1 WO 2022070862A1 JP 2021033534 W JP2021033534 W JP 2021033534W WO 2022070862 A1 WO2022070862 A1 WO 2022070862A1
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WIPO (PCT)
Prior art keywords
main surface
inductor
transmission
high frequency
covering portion
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PCT/JP2021/033534
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English (en)
Japanese (ja)
Inventor
基嗣 津田
隼人 中村
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株式会社村田製作所
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Publication of WO2022070862A1 publication Critical patent/WO2022070862A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving

Definitions

  • the present invention relates to a high frequency module and a communication device.
  • Patent Document 1 describes a switch plexa (antenna switch) arranged between a plurality of transmitters (transmission path) and a plurality of receivers (reception path), and the plurality of transmitters and the plurality of receivers and an antenna. ), And the circuit configuration of the transceiver (transmitting / receiving circuit) including.
  • Each of the plurality of transmitters has a transmission circuit, a PA (transmission power amplifier), and an output circuit.
  • Each of the plurality of receivers has a receiving circuit, an LNA (received low noise amplifier), and an input circuit.
  • the output circuit includes a transmit filter, an impedance matching circuit, a duplexer, and the like.
  • the input circuit includes a receive filter, an impedance matching circuit, a duplexer, and the like.
  • the transceiver (transmission / reception circuit) disclosed in Patent Document 1 is composed of a high-frequency module mounted on a mobile communication device, it is arranged in each of the transmission path, the reception path, and the transmission / reception path including the antenna switch. It is assumed that at least two of the inductors are magnetically coupled. In this case, the harmonic component of the high-output transmission signal amplified by the PA (transmission power amplifier) may be superimposed on the transmission signal, and the quality of the transmission signal may deteriorate. In addition, the isolation between transmission and reception is reduced by the magnetic field coupling, and unnecessary waves such as the harmonics or intermodulation distortion between the transmission signal and other high-frequency signals flow into the reception path and the reception sensitivity deteriorates. In some cases.
  • an object of the present invention is to provide a high frequency module and a communication device in which quality deterioration of a transmission signal or a reception signal is suppressed.
  • the high-frequency module covers a module substrate having a main surface, a first inductor and a second inductor arranged on the main surface, and at least a part of the main surface, the first inductor, and the second inductor. It is placed between the sealing member, the metal layer that covers the surface of the sealing member and is set to the ground potential, and the first inductor and the second inductor on the main surface when the module substrate is viewed in a plan view.
  • the chip capacitor includes a first electrode terminal in contact with a metal layer, a second electrode terminal, a first main surface parallel to the main surface, and a second surface opposite the first main surface.
  • a main surface and a main body having a first side surface and a second side surface opposite to the first side surface connecting the first main surface and the second main surface, and inside the main body, from the first side surface to the main surface. It has a first internal electrode extending parallel to the main body and a second internal electrode extending parallel to the main surface from the second side surface and overlapping the first internal electrode in the plan view of the main surface.
  • the electrode terminal is connected to the first internal electrode and is connected to the first side surface covering portion that covers at least a part of the first side surface and the first side surface covering portion, and at least a part of the first main surface.
  • a second side surface covering portion having a first main surface covering portion covering the second side surface covering portion, and a second electrode terminal connected to the second internal electrode and covering at least a part of the second side surface, and a second side surface covering portion.
  • the first main surface covering portion is connected to the second main surface covering portion and covers at least a part of the second main surface, and the first main surface covering portion is connected to the second main surface covering portion in the plan view of the main surface. overlapping.
  • the communication device is a high frequency module according to the above aspect, which transmits a high frequency signal between an RF signal processing circuit that processes high frequency signals transmitted and received by an antenna and an RF signal processing circuit. And.
  • the present invention it is possible to provide a high frequency module and a communication device in which quality deterioration of a transmission signal or a reception signal is suppressed.
  • FIG. 1 is a circuit configuration diagram of a high frequency module and a communication device according to an embodiment.
  • FIG. 2 is a plan view of the high frequency module according to the embodiment.
  • FIG. 3 is a cross-sectional view of the high frequency module according to the embodiment.
  • FIG. 4 is a cross-sectional view, a top view, a bottom view, a right side view, and a left side view showing a first example of the chip capacitor of the high frequency module according to the embodiment.
  • FIG. 5 is a cross-sectional view, a top view, a bottom view, a right side view, and a left side view showing a second example of the chip capacitor of the high frequency module according to the embodiment.
  • FIG. 6 is a cross-sectional view, a top view, a bottom view, a right side view, and a left side view showing a third example of the chip capacitor of the high frequency module according to the embodiment.
  • each figure is a schematic diagram and is not necessarily exactly illustrated. Therefore, for example, the scales and the like do not always match in each figure. Further, in each figure, substantially the same configuration is designated by the same reference numeral, and duplicate description will be omitted or simplified.
  • the terms “upper” and “lower” do not refer to the upward direction (vertically upward) and the downward direction (vertically downward) in absolute spatial recognition, but are based on the stacking order in the laminated configuration. It is used as a term defined by the relative positional relationship. For this reason, for example, the “top surface” or “top surface” of a part or member is not only a surface on the vertically upper side but also a surface on the vertically lower side or a surface orthogonal to the horizontal direction in an actual usage mode. It can be various aspects such as.
  • the "top surface” of a part or member means the uppermost surface of the part or member.
  • the x-axis, y-axis, and z-axis indicate the three axes of the three-dimensional Cartesian coordinate system.
  • Each of the x-axis and the y-axis is a direction parallel to the first side of the rectangle and the second side orthogonal to the first side when the plan view shape of the module substrate is rectangular.
  • the z-axis is the thickness direction of the module substrate.
  • the "thickness direction" of the module substrate means the direction perpendicular to the main surface of the module substrate.
  • connection includes not only the case of being directly connected by a connection terminal and / or a wiring conductor, but also the case of being electrically connected via another circuit element.
  • connected between A and B means that both A and B are connected between A and B.
  • planar view of the module board means that an object is projected orthographically projected from the positive side of the z-axis onto the xy plane.
  • the component is arranged on the substrate means that the component is arranged on the substrate in a state of being in contact with the substrate and is arranged above the substrate without contacting the substrate (for example,).
  • the component is laminated on another component placed on the board), and a part or all of the component is embedded and placed in the board.
  • the component is arranged on the main surface of the board means that the component is arranged on the main surface in a state of being in contact with the main surface of the board, and the component is mainly arranged without contacting the main surface.
  • A is arranged between B and C means that at least one of a plurality of line segments connecting an arbitrary point in B and an arbitrary point in C passes through A. means.
  • ordinal numbers such as “first” and “second” do not mean the number or order of components unless otherwise specified, and avoid confusion of the same kind of components and distinguish them. It is used for the purpose of
  • the "transmission path” is a transmission line composed of a wiring for transmitting a high frequency transmission signal, an electrode directly connected to the wiring, and a wiring or a terminal directly connected to the electrode.
  • the "reception path” means a transmission line composed of a wiring for transmitting a high-frequency reception signal, an electrode directly connected to the wiring, and the wiring or a terminal directly connected to the electrode.
  • the "transmission / reception path” is a transmission composed of a wiring for transmitting both a high-frequency transmission signal and a high-frequency reception signal, an electrode directly connected to the wiring, and a terminal directly connected to the wiring or the electrode. It means that it is a railroad.
  • FIG. 1 is a circuit configuration diagram of a high frequency module 1 and a communication device 5 according to an embodiment.
  • the communication device 5 is a device used in a communication system, and is a mobile terminal such as a smartphone and a tablet computer. As shown in FIG. 1, the communication device 5 according to the present embodiment includes a high frequency module 1, an antenna 2, an RF signal processing circuit (RFIC) 3, and a baseband signal processing circuit (BBIC) 4. ..
  • RFIC RF signal processing circuit
  • BBIC baseband signal processing circuit
  • the high frequency module 1 transmits a high frequency signal between the antenna 2 and the RFIC 3.
  • the internal configuration of the high frequency module 1 will be described later.
  • the antenna 2 is connected to the antenna connection terminal 100 of the high frequency module 1, transmits a high frequency signal (transmitted signal) output from the high frequency module 1, and receives a high frequency signal (received signal) from the outside to receive the high frequency signal (received signal). Output to.
  • RFIC 3 is an example of a signal processing circuit that processes high frequency signals transmitted and received by the antenna 2. Specifically, the RFIC 3 processes the high frequency reception signal input via the reception path of the high frequency module 1 by down-conversion or the like, and outputs the reception signal generated by the signal processing to the BBIC 4. Further, the RFIC 3 processes the transmission signal input from the BBIC 4 by up-conversion or the like, and outputs the high frequency transmission signal generated by the signal processing to the transmission path of the high frequency module 1. Further, the RFIC 3 has a control unit for controlling a switch, an amplifier and the like included in the high frequency module 1. A part or all of the function of the RFIC 3 as a control unit may be mounted outside the RFIC 3, or may be mounted on, for example, the BBIC 4 or the high frequency module 1.
  • the BBIC 4 is a baseband signal processing circuit that processes signals using an intermediate frequency band having a lower frequency than the high frequency signal transmitted by the high frequency module 1.
  • the signal processed by the BBIC 4 for example, an image signal for displaying an image and / or an audio signal for a call via a speaker is used.
  • the antenna 2 and the BBIC 4 are not essential components.
  • the high frequency module 1 includes a power amplifier 11, a low noise amplifier 21, switches 51 to 53, and duplexers 61 and 62. Further, the high frequency module 1 includes inductors 31L, 32L, 41L, 70L, 71L and 72L, and capacitors 31C, 71C and 72C. Further, the high frequency module 1 includes an antenna connection terminal 100, a transmission input terminal 111, and a reception / output terminal 121.
  • the antenna connection terminal 100 is connected to the antenna 2.
  • the transmission input terminal 111 is a terminal for receiving a transmission signal from the outside (RFIC3) of the high frequency module 1.
  • the transmission input terminal 111 is a terminal for receiving transmission signals of communication bands A and B from RFIC3.
  • the reception output terminal 121 is a terminal for supplying a received signal to the outside (RFIC3) of the high frequency module 1.
  • the reception output terminal 121 is a terminal for providing the reception signals of the communication bands A and B to the RFIC 3.
  • the communication band means a frequency band defined in advance by a standardization body or the like (for example, 3GPP (3rd Generation Partnership Project) and IEEE (Institute of Electrical and Electronics Engineers)) for a communication system.
  • a standardization body or the like for example, 3GPP (3rd Generation Partnership Project) and IEEE (Institute of Electrical and Electronics Engineers) for a communication system.
  • the communication system means a communication system constructed by using wireless access technology (RAT: RadioAccess Technology).
  • RAT RadioAccess Technology
  • the communication system for example, a 5GNR (5th Generation New Radio) system, an LTE (Long Term Evolution) system, a WLAN (Wireless Local Area Network) system, and the like can be used, but the communication system is not limited thereto.
  • the high frequency module 1 is provided with a transmission path for transmitting a transmission signal, a reception path for transmitting a reception signal, and a transmission / reception path for transmitting both the transmission signal and the reception signal.
  • transmission paths AT and BT, reception paths AR and BR, and transmission / reception paths ATR, BTR and CTR are provided.
  • the transmission path AT is a path for transmitting the transmission signal of the communication band A, and is a signal path connecting the transmission input terminal 111 and the common terminal of the duplexer 61.
  • the transmission path BT is a path for transmitting the transmission signal of the communication band B, and is a signal path connecting the transmission input terminal 111 and the common terminal of the duplexer 62.
  • the transmission path AT and BT are shared between the transmission input terminal 111 and the switch 52.
  • the reception path AR is a path for transmitting the reception signal of the communication band A, and is a signal path connecting the reception output terminal 121 and the common terminal of the duplexer 61.
  • the reception path BR is a signal path that transmits the reception signal of the communication band B and connects the reception output terminal 121 and the common terminal of the duplexer 62.
  • the reception paths AR and BR are shared between the reception output terminal 121 and the switch 53.
  • the transmission / reception path ATR is a path for transmitting the transmission signal and the reception signal of the communication band A, and is a signal path connecting the common terminal of the duplexer 61 and the switch 51.
  • the transmission / reception path BTR is a path for transmitting the transmission signal and the reception signal of the communication band B, and is a signal path connecting the common terminal of the duplexer 62 and the switch 51.
  • the transmission / reception path CTR is a path for transmitting the transmission signal and the reception signal of the communication band A, and the transmission signal and the reception signal of the communication band B, and is a signal path connecting the antenna connection terminal 100 and the switch 51.
  • the power amplifier 11 is an example of an amplifier that amplifies a high frequency signal, and is a transmission amplifier that amplifies the transmission signals of the communication band A and the communication band B.
  • the power amplifier 11 is arranged in the transmission paths AT and BT.
  • the input terminal of the power amplifier 11 is connected to the transmission input terminal 111 via the inductor 32L.
  • the output terminal of the power amplifier 11 is connected to the inductor 31L and the capacitor 31C.
  • the configuration of the power amplifier 11 is not particularly limited.
  • the power amplifier 11 may have a single-stage configuration or a multi-stage configuration.
  • the power amplifier 11 may have a plurality of cascade-connected amplification elements.
  • the power amplifier 11 may convert a high frequency signal into a balanced signal and amplify it.
  • Such a power amplifier 11 may be referred to as a differential amplifier.
  • the balanced signal means a set of signals having opposite phases.
  • the balanced signal is sometimes referred to as a differential signal.
  • the low noise amplifier 21 is an example of an amplifier that amplifies a high frequency signal, and is a reception amplifier that amplifies the reception signals of the communication band A and the communication band B with low noise.
  • the low noise amplifier 21 is arranged in the reception paths AR and BR.
  • the input terminal of the low noise amplifier 21 is connected to the inductor 41L.
  • the output terminal of the low noise amplifier 21 is connected to the reception output terminal 121.
  • the configuration of the low noise amplifier 21 is not particularly limited.
  • the low noise amplifier 21 may have a single-stage configuration or a multi-stage configuration.
  • the power amplifier 11 and the low noise amplifier 21 are composed of, for example, a Si-based CMOS or a field effect transistor (FET) or a heterobipolar transistor (HBT) made of GaAs as a material.
  • FET field effect transistor
  • HBT heterobipolar transistor
  • Duplexer 61 is an example of a filter having a pass band including a communication band A.
  • the duplexer 61 passes the high frequency signal of the communication band A.
  • the duplexer 61 transmits the transmission signal and the reception signal of the communication band A by a frequency division duplex (FDD) method.
  • the duplexer 61 includes a transmit filter 61T and a receive filter 61R.
  • the transmission filter 61T is arranged in the transmission path AT, and among the transmission signals amplified by the power amplifier 11, the transmission signal in the transmission band of the communication band A is passed.
  • the transmission filter 61T has a pass band including an uplink operating band of the communication band A.
  • One end of the transmission filter 61T is connected to the antenna connection terminal 100 via the inductor 71L, the switch 51 and the inductor 70L.
  • the other end of the transmission filter 61T is connected to the output terminal of the power amplifier 11 via the switch 52 and the inductor 31L.
  • the uplink operation band means a part of the communication band designated for the uplink.
  • the uplink operation band means the transmission band.
  • the reception filter 61R is arranged in the reception path AR, and among the reception signals input from the antenna connection terminal 100, the reception signal in the reception band of the communication band A is passed.
  • the reception filter 61R has a pass band including a downlink operating band of the communication band A.
  • One end of the receive filter 61R is connected to the antenna connection terminal 100 via the inductor 71L, the switch 51 and the inductor 70L.
  • the other end of the receive filter 61R is connected to the input terminal of the low noise amplifier 21 via the switch 53 and the inductor 41L.
  • the downlink operation band means a part of the communication band designated for the downlink.
  • the downlink operation band means the reception band.
  • Duplexer 62 is an example of a filter having a pass band including a communication band B.
  • the duplexer 62 passes the high frequency signal of the communication band B.
  • the duplexer 62 transmits the transmission signal and the reception signal of the communication band B by the FDD method.
  • the duplexer 62 includes a transmit filter 62T and a receive filter 62R.
  • the transmission filter 62T is arranged in the transmission path BT, and among the transmission signals amplified by the power amplifier 11, the transmission signal in the transmission band of the communication band B is passed.
  • the transmission filter 62T has a pass band including the uplink operation band of the communication band B.
  • One end of the transmission filter 62T is connected to the antenna connection terminal 100 via the inductor 72L, the switch 51 and the inductor 70L.
  • the other end of the transmission filter 62T is connected to the output terminal of the power amplifier 11 via the switch 52 and the inductor 31L.
  • the reception filter 62R is arranged in the reception path BR, and among the reception signals input from the antenna connection terminal 100, the reception signal in the reception band of the communication band B is passed.
  • the reception filter 62R has a pass band including the downlink operation band of the communication band B.
  • One end of the receive filter 62R is connected to the antenna connection terminal 100 via the inductor 72L, the switch 51 and the inductor 70L.
  • the other end of the receive filter 62R is connected to the input terminal of the low noise amplifier 21 via the switch 53 and the inductor 41L.
  • the transmission filters 61T and 62T, and the reception filters 61R and 62R are, for example, a surface acoustic wave filter using SAW (Surface Acoustic Wave), a surface acoustic wave filter using BAW (Bulk Acoustic Wave), an LC resonance filter and a dielectric filter. However, it is not limited to these.
  • Each of the duplexers 61 and 62 may be one filter (TDD filter) transmitted by a time division duplex (TDD: Time Division Duplex) method. That is, each of the communication bands A and B may be a communication band for TDD. In this case, between the first TDD filter and the switch 51 instead of the duplexer 61, and at least one between the first TDD filter and the switches 52 and 53, and the second TDD filter and the switch 51 instead of the duplexer 62. A switch for switching between transmission and reception is arranged between the second TDD filter and at least one of the switches 52 and 53. Also, only one of the duplexers 61 and 62 may be a TDD filter.
  • a switch for switching between transmission and reception is arranged between the TDD filter and the switch 51, and at least one of the TDD filter and the switches 52 and 53. ..
  • the switch 51 is connected between the antenna connection terminal 100 and each of the duplexers 61 and 62.
  • the switch 51 is also referred to as an antenna switch.
  • the switch 51 has terminals 511 to 513.
  • the terminal 511 is a common terminal connected to the antenna connection terminal 100 via the inductor 70L.
  • the terminal 512 is a selection terminal connected to the transmission filter 61T and the reception filter 61R via the inductor 71L.
  • the terminal 513 is a selection terminal connected to the transmission filter 62T and the reception filter 62R via the inductor 72L.
  • the switch 51 can connect either one of the terminals 512 and 513 to the terminal 511, for example, based on the control signal from the RFIC 3. As a result, the switch 51 switches between (a) the connection between the antenna connection terminal 100 and the transmission filter 61T and the reception filter 61R, and (b) the connection between the antenna connection terminal 100 and the transmission filter 62T and the reception filter 62R.
  • the switch 51 is, for example, a SPDT (Single Pole Double Throw) type switch circuit.
  • the switch 51 may be a multi-connection type switch circuit capable of simultaneously executing the above connections (a) and (b).
  • the switch 52 is connected between each of the duplexers 61 and 62 and the power amplifier 11. Specifically, the switch 52 has terminals 521 to 523.
  • the terminal 521 is a common terminal connected to the output terminal of the power amplifier 11 via the inductor 31L.
  • the terminal 522 is a selection terminal connected to the transmission filter 61T.
  • Terminal 523 is a selection terminal connected to the transmission filter 62T.
  • the switch 52 can connect either one of the terminals 522 and 523 to the terminal 521, for example, based on the control signal from the RFIC 3. As a result, the switch 52 switches between the connection of the power amplifier 11 and the transmission filter 61T and the connection of the power amplifier 11 and the transmission filter 62T.
  • the switch 52 is, for example, a SPDT type switch circuit.
  • the switch 53 is connected between each of the duplexers 61 and 62 and the low noise amplifier 21. Specifically, the switch 53 has terminals 531 to 533.
  • the terminal 531 is a common terminal connected to the input terminal of the low noise amplifier 21 via the inductor 41L.
  • Terminal 532 is a selection terminal connected to the reception filter 61R.
  • Terminal 533 is a selection terminal connected to the reception filter 62R.
  • the switch 53 can connect either one of the terminals 532 and 533 to the terminal 531 based on, for example, a control signal from the RFIC 3. As a result, the switch 53 switches between the connection of the low noise amplifier 21 and the reception filter 61R and the connection of the low noise amplifier 21 and the reception filter 62R.
  • the switch 53 is, for example, a SPDT type switch circuit.
  • the inductor 31L is an example of the first inductor and is arranged in the transmission paths AT and BT.
  • the inductor 31L is at least a part of a matching circuit arranged between the switch 52 and the power amplifier 11, and impedance matching is performed between the power amplifier 11 and each of the transmission filters 61T and 62T.
  • the inductor 31L is connected to the output terminal of the power amplifier 11. Although the inductor 31L is arranged in series with the transmission path AT and BT, it may be connected in series between the transmission path AT and BT and the ground.
  • the capacitor 31C is a shunt capacitor connected in series between the transmission path AT and BT and the ground.
  • the capacitor 31C is connected to the output terminal of the power amplifier 11.
  • the capacitor 31C is provided to remove the harmonic component of the transmission signal generated by the power amplifier 11. Further, the capacitor 31C, together with the inductor 31L, constitutes a matching circuit for impedance matching between the power amplifier 11 and each of the transmission filters 61T and 62T.
  • the inductor 32L is an example of the first inductor or the second inductor, and is arranged in the transmission paths AT and BT.
  • the inductor 32L is at least a part of a matching circuit arranged between the power amplifier 11 and the transmission / input terminal 111, and impedance matching is performed between the power amplifier 11 and the transmission / input terminal 111.
  • the inductor 32L is connected to the input terminal of the power amplifier 11. Although the inductor 32L is arranged in series with the transmission path AT and BT, it may be connected in series between the transmission path AT and BT and the ground.
  • the inductor 41L is an example of the first inductor or the second inductor, and is arranged in the reception paths AR and BR.
  • the inductor 41L is at least a part of a matching circuit arranged between the switch 53 and the low noise amplifier 21, and performs impedance matching between the low noise amplifier 21 and each of the reception filters 61R and 62R.
  • the inductor 41L is connected to the input terminal of the low noise amplifier 21.
  • the inductor 41L is arranged in series with the reception path AR and BR, it may be connected between the reception path AR and BR and ground.
  • the inductor 70L is an example of the second inductor and is arranged in the transmission / reception path CTR.
  • the inductor 70L is at least a part of a matching circuit arranged between the antenna connection terminal 100 and the switch 51, and has impedance matching between the antenna 2 and the switch 51, the duplexers 61 and 62.
  • the inductor 70L is arranged in series with the transmission / reception path CTR, it may be connected in series between the transmission / reception path CTR and the ground.
  • the inductor 71L is an example of the second inductor and is arranged in the transmission / reception path ATR.
  • the inductor 71L is at least a part of a matching circuit arranged between the duplexer 61 and the switch 51, and has impedance matching between the duplexer 61 and the switch 51.
  • the inductor 71L is arranged in series with the transmission / reception path ATR, it may be connected in series between the transmission / reception path ATR and ground.
  • the capacitor 71C is a shunt capacitor connected in series between the transmission / reception path ATR and the ground.
  • the capacitor 71C is connected to one end of the transmission filter 61T (specifically, a common terminal of the duplexer 61).
  • the capacitor 71C is provided to remove the harmonic component of the transmission signal generated by the power amplifier 11. Further, the capacitor 71C, together with the inductor 71L, constitutes a matching circuit for impedance matching between the duplexer 61 and the switch 51.
  • the inductor 72L is an example of the second inductor and is arranged in the transmission / reception path BTR.
  • the inductor 72L is at least a part of a matching circuit arranged between the duplexer 62 and the switch 51, and has impedance matching between the duplexer 62 and the switch 51.
  • the inductor 72L is arranged in series with the transmission / reception path BTR, it may be connected in series between the transmission / reception path BTR and ground.
  • the capacitor 72C is a shunt capacitor connected in series between the transmission / reception path BTR and the ground.
  • the capacitor 72C is connected to one end of the transmission filter 62T (specifically, a common terminal of the duplexer 62).
  • the capacitor 72C is provided to remove the harmonic component of the transmission signal generated by the power amplifier 11. Further, the capacitor 72C, together with the inductor 72L, constitutes a matching circuit for impedance matching between the duplexer 62 and the switch 51.
  • a matching circuit may be provided in at least one of the output terminals 121.
  • the matching circuit includes an inductor, but may also include a capacitor.
  • the inductors 31L, 32L, 41L, 70L, 71L and 72L may not be provided.
  • one or more inductors may be provided in each of the two paths of the transmission paths AT and BT, the reception paths AR and BR, and the transmission / reception paths ATR, BTR, and CTR.
  • a capacitor (shunt capacitor) having one end connected to ground is connected to at least one of transmission paths AT and BT, reception paths AR and BR, and transmission / reception paths ATR, BTR, and CTR, and the other end is connected. It suffices if it is provided so as to be used.
  • the other end of the shunt capacitor may be connected to any of the inductors 32L, 41L and 70L.
  • the other end of the shunt capacitor includes a path connecting the transmission filter 61T and the switch 52, a path connecting the transmission filter 62T and the switch 52, a path connecting the reception filter 61R and the switch 53, and the reception filter 62R and the switch 53. It may be connected to either a connecting path or a path connecting the low noise amplifier 21 and the reception output terminal 121.
  • the power amplifier 11, the inductors 31L and 32L, the capacitors 31C, the switch 52, and the transmission filter 61T are the first transmissions that output the transmission signal of the communication band A toward the antenna connection terminal 100.
  • the power amplifier 11, the inductors 31L and 32L, the capacitor 31C, the switch 52, and the transmission filter 62T constitute a second transmission circuit that outputs a transmission signal of the communication band B toward the antenna connection terminal 100.
  • the low noise amplifier 21, the inductor 41L, the switch 53, and the reception filter 61R constitute a first reception circuit for inputting a reception signal of the communication band A from the antenna 2 via the antenna connection terminal 100. Further, the low noise amplifier 21, the inductor 41L, the switch 53, and the reception filter 62R constitute a second reception circuit for inputting a reception signal of the communication band B from the antenna 2 via the antenna connection terminal 100.
  • the high frequency module 1 has (1) transmission / reception of high frequency signals of communication band A, (2) transmission / reception of high frequency signals of communication band B, and (3) transmission / reception of high frequency signals of communication band A. It is possible to execute at least one of simultaneous transmission, simultaneous reception, and simultaneous transmission / reception of the high frequency signal and the high frequency signal of the communication band B.
  • the transmission circuit and the reception circuit may not be connected to the antenna connection terminal 100 via the switch 51, and the transmission circuit and the reception circuit may be connected to the antenna connection terminal 100 via different terminals. It may be connected to the antenna 2.
  • the circuit configuration of the high frequency module 1 according to the present embodiment at least two paths of the transmission path, the reception path, and the transmission / reception path, each inductor arranged in the two paths, a shunt capacitor, and the like. It suffices to have.
  • the high frequency module 1 may have either a first transmission circuit or a second transmission circuit.
  • the high frequency module 1 may have either a first receiving circuit or a second receiving circuit.
  • the high frequency module 1 having the above circuit configuration, when at least two of the inductors arranged in the transmission paths AT and BT, the reception paths AR and BR, and the transmission / reception paths ATR, BTR, and CTR are magnetically coupled, power is generated.
  • the harmonic component of the high-output transmission signal amplified by the amplifier 11 may be superimposed on the transmission signal, and the quality of the transmission signal may deteriorate.
  • the isolation between transmission and reception is reduced by the magnetic field coupling, and unnecessary waves such as the harmonics or intermodulation distortion between the transmission signal and other high-frequency signals flow into the reception path and the reception sensitivity deteriorates. In some cases.
  • the high frequency module 1 according to the present embodiment has a configuration for suppressing the magnetic field coupling.
  • a configuration specifically, component arrangement of the high frequency module 1 for suppressing the magnetic field coupling of the high frequency module 1 according to the present embodiment will be described.
  • FIG. 2 is a plan view of the high frequency module 1 according to the present embodiment.
  • FIG. 3 is a cross-sectional view of the high frequency module 1 according to the present embodiment.
  • FIG. 3 represents a cross section taken along line III-III of FIG.
  • the module substrate 91 is not shaded to represent the cross section.
  • the high frequency module 1 includes a module substrate 91, a resin member 92, a metal shield layer 95, and an external connection terminal 150. Further, the high frequency module 1 includes chip capacitors 200 to 202.
  • the chip capacitors 200 to 202 are circuit components including the capacitors 31C, 71C and 72C shown in FIG. 1, respectively.
  • the module board 91 has a main surface 91a and a main surface 91b on the opposite side of the main surface 91a.
  • the module substrate 91 has a rectangular shape in a plan view, but the shape of the module substrate 91 is not limited to this.
  • Examples of the module substrate 91 include a low-temperature co-fired ceramics (LTCC: Low Temperature Co-fired Ceramics) substrate having a laminated structure of a plurality of dielectric layers, a high-temperature co-fired ceramics (HTCC: High Temperature Co-fired Ceramics) substrate, and the like.
  • LTCC Low Temperature Co-fired Ceramics
  • HTCC High Temperature Co-fired Ceramics
  • a board having a built-in component, a board having a redistribution layer (RDL: Redistribution Layer), a printed circuit board, or the like can be used, but is not limited thereto.
  • RDL Redistribution Layer
  • the main surface 91a may be referred to as an upper surface or a surface. As shown in FIG. 2, all the parts (excluding terminals) constituting the circuit shown in FIG. 1 are arranged on the main surface 91a. Specifically, on the main surface 91a, a power amplifier 11, a low noise amplifier 21, switches 51 to 53, duplexers 61 and 62, inductors 31L, 32L, 41L, 70L, 71L and 72L, and a capacitor 31C , 71C and 72C are arranged. Chip capacitors 200 to 202 are arranged on the main surface 91a. The specific configuration of the chip capacitors 200 to 202 will be described later.
  • the low noise amplifier 21 and the switch 53 may be included in one semiconductor integrated circuit.
  • a semiconductor integrated circuit is an electronic component having an electronic circuit formed on the surface and inside of a semiconductor chip (also called a die).
  • the semiconductor integrated circuit is composed of, for example, CMOS, and may be specifically configured by an SOI process. This makes it possible to manufacture semiconductor integrated circuits at low cost.
  • the semiconductor integrated circuit may be composed of at least one of GaAs, SiGe and GaN. This makes it possible to realize a high-quality semiconductor integrated circuit.
  • the main surface 91b may be referred to as the lower surface or the back surface.
  • a plurality of external connection terminals 150 are arranged on the main surface 91b.
  • the plurality of external connection terminals 150 include a ground terminal in addition to the antenna connection terminal 100, the transmission input terminal 111, and the reception output terminal 121 shown in FIG. Each of the plurality of external connection terminals 150 is connected to an input / output terminal and / or a ground terminal on the mother board arranged on the negative side of the z-axis of the high frequency module 1.
  • the plurality of external connection terminals 150 are, for example, flat electrodes formed on the main surface 91b, but may be bump electrodes. Alternatively, the plurality of external connection terminals 150 may be post electrodes that penetrate the resin member that covers the main surface 91b.
  • the resin member 92 is an example of a sealing member, is arranged on the main surface 91a of the module substrate 91, and covers the main surface 91a. Specifically, the resin member 92 is provided so as to cover the side surface and the top surface of each component arranged on the main surface 91a. For example, the resin member 92 covers the inductors 31L, 32L, 41L, 70L, 71L and 72L, the switches 51 to 53, and the top surface of the low noise amplifier 21.
  • the plurality of parts arranged on the main surface 91a include parts whose top surface is not covered by the resin member 92.
  • the top surface of each of the power amplifier 11 and the chip capacitor 200 is not covered with the resin member 92.
  • the top surface of the power amplifier 11 and the chip capacitor 200 is in contact with the metal shield layer 95.
  • the top surface of each of the duplexers 61 and 62 may be in contact with the metal shield layer 95.
  • the metal shield layer 95 covers the surface of the resin member 92. Specifically, the metal shield layer 95 covers the top surface and side surfaces of the resin member 92 and the top surface of the component whose top surface is not covered by the resin member 92. For example, the metal shield layer 95 contacts and covers each of the top surface of the power amplifier 11 and the top surface of the chip capacitor 200.
  • the metal shield layer 95 is, for example, a metal thin film formed by a sputtering method.
  • the metal shield layer 95 is set to the ground potential. Specifically, the metal shield layer 95 is set to the ground potential by being connected to the ground terminal and the ground electrode provided on the module substrate 91. As a result, it is possible to prevent external noise from entering the circuit components constituting the high frequency module 1.
  • the metal shield layer 95 is in contact with each of the chip capacitors 200 to 202. Therefore, the terminals of the chip capacitors 200 to 202 are set to the ground potential. As a result, the chip capacitors 200 to 202 can each function as a shield member that suppresses magnetic field coupling between other components.
  • Chip capacitor Next, the structure, arrangement, and function of the chip capacitors 200 to 202 will be described.
  • FIG. 4 is a diagram showing a chip capacitor 200 of the high frequency module 1 according to the present embodiment.
  • FIGS. 4A to 4E are a cross-sectional view, a top view, a bottom view, a right side view, and a left side view of the chip capacitor 200, respectively.
  • FIG. 4A shows a cross section of FIG. 4B on the IVa-IVa line.
  • the electrode terminals 240 and 250 are shaded with dots, respectively.
  • the chip capacitor 200 includes a main body 210, internal electrodes 220 and 230, and electrode terminals 240 and 250.
  • the main body 210 has a laminated structure of a plurality of dielectric layers.
  • the plurality of dielectric layers are formed using, for example, a ceramic material, but the present invention is not limited thereto.
  • internal electrodes 220 and 230 are provided with one or more dielectric layers interposed therebetween.
  • the shape of the main body 210 is, for example, a rectangular parallelepiped. As shown in FIG. 4, the main body 210 has main surfaces 211 and 212 and side surfaces 213 and 214. The shape of the main body 210 may be a cube, or another prism or cylinder.
  • the main surface 211 is an example of the first main surface, and is the top surface (upper surface) of the main body 210.
  • the main surface 212 is an example of the second main surface, and is the surface opposite to the main surface 211. Specifically, the main surface 212 is the lower surface of the main body 210.
  • the main surfaces 211 and 212 are parallel to each other.
  • Side surface 213 is an example of the first side surface.
  • the side surface 214 is an example of the second side surface, and is the surface opposite to the side surface 213.
  • the side surfaces 213 and 214 connect the main surface 211 and the main surface 212, respectively.
  • the sides 213 and 214 are parallel to each other.
  • the internal electrode 220 is an example of the first internal electrode, and extends parallel to the main surface 211 from the side surface 213 inside the main body 210.
  • the internal electrode 230 is an example of the second internal electrode, and extends from the side surface 214 to the main surface 211 inside the main body 210.
  • the internal electrode 230 overlaps the internal electrode 220 in a plan view.
  • the internal electrodes 220 and 230 are parallel to each other and form a parallel plate electrode.
  • the internal electrodes 220 and 230 are each formed of a conductive material such as metal.
  • the internal electrode 220 is connected to the electrode terminal 240.
  • the internal electrode 230 is connected to the electrode terminal 250.
  • the internal electrode 220 is set to the ground potential. That is, since one of the parallel plate electrodes is set to the ground potential, the capacitor 71C included in the chip capacitor 200 becomes a shunt capacitor.
  • the chip capacitor 200 has two pairs of parallel plate electrodes. Each of the two pairs of parallel plate electrodes constitutes a capacitor (capacitor) and is connected in parallel to each other. Thereby, the capacity value of the chip capacitor 200 can be increased.
  • Each of the plurality of internal electrodes 220 is connected to the electrode terminal 240.
  • the plurality of internal electrodes 230 are connected to the electrode terminals 250.
  • the number of parallel plate electrodes included in the chip capacitor 200 may be only one or three or more.
  • the electrode terminal 240 is an example of the first electrode terminal.
  • the electrode terminal 240 has a main surface covering portion 241 and a side surface covering portion 242.
  • the main surface covering portion 241 is connected to the side surface covering portion 242. Therefore, as shown in FIG. 4A, the cross-sectional shape of the electrode terminal 240 is L-shaped.
  • the electrode terminal 240 is formed by using a conductive material such as metal.
  • the main surface covering portion 241 is an example of the first main surface covering portion, and covers at least a part of the main surface 211 of the main body 210.
  • the main surface covering portion 241 does not cover a region of the main surface 211 having a predetermined width from the connection portion between the main surface 211 and the side surface 214.
  • the main surface 211 has an exposed region 211a having a width w1.
  • the exposed region 211a is a portion of the main surface 211 that is not covered by the main surface covering portion 241.
  • the shape of the exposed region 211a is rectangular, but is not particularly limited. In FIG.
  • the boundary line between the exposed region 211a and the side surface covering portion 252 corresponds to the connection portion (one side of the rectangular parallelepiped) between the main surface 211 and the side surface 214.
  • the connection portion between the main surface 211 and the side surface 214 is exposed without being covered by any of the electrode terminals 240 and 250.
  • the side surface covering portion 242 is an example of the first side surface covering portion, and covers at least a part of the side surface 213 of the main body 210.
  • the side surface covering portion 242 is connected to the internal electrode 220.
  • the thickness d2 of the side surface covering portion 242 is thicker than the thickness d1 of the main surface covering portion 241.
  • the side surface covering portion 242 does not cover a region having a predetermined width from the connection portion between the side surface 213 and the main surface 212 in the side surface 213.
  • the side surface 213 has an exposed region 213a having a width w3.
  • the exposed region 213a is a portion of the side surface 213 that is not covered by the side surface covering portion 242.
  • the shape of the exposed region 213a is rectangular, but is not particularly limited.
  • the boundary line between the exposed region 213a and the main surface covering portion 251 corresponds to the connecting portion (one side of the rectangular parallelepiped) between the side surface 213 and the main surface 212.
  • the connection portion between the side surface 213 and the main surface 212 is exposed without being covered by any of the electrode terminals 240 and 250.
  • the electrode terminal 250 is an example of the second electrode terminal.
  • the electrode terminal 250 has a main surface covering portion 251 and a side surface covering portion 252.
  • the main surface covering portion 251 is connected to the side surface covering portion 252. Therefore, as shown in FIG. 4A, the cross-sectional shape of the electrode terminal 250 is L-shaped.
  • the electrode terminal 250 is formed by using a conductive material such as metal.
  • the main surface covering portion 251 is an example of the second main surface covering portion, and covers at least a part of the main surface 212 of the main body 210.
  • the main surface covering portion 251 does not cover a region having a predetermined width from the connection portion between the main surface 212 and the side surface 213 of the main surface 212.
  • the main surface 212 has an exposed region 212a having a width w2.
  • the exposed region 212a is a portion of the main surface 212 that is not covered by the main surface covering portion 251.
  • the shape of the exposed region 212a is rectangular, but is not particularly limited.
  • the boundary line between the exposed region 212a and the side surface covering portion 242 corresponds to the connection portion (one side of the rectangular parallelepiped) between the main surface 212 and the side surface 213.
  • the side surface covering portion 252 is an example of the second side surface covering portion, and covers at least a part of the side surface 214 of the main body 210.
  • the side surface covering portion 252 is connected to the internal electrode 230.
  • the thickness d4 of the side surface covering portion 252 is thicker than the thickness d3 of the main surface covering portion 251.
  • the side surface covering portion 252 does not cover a region having a predetermined width from the connection portion between the side surface 214 and the main surface 211 of the side surface 214.
  • the side surface 214 has an exposed region 214a having a width w4.
  • the exposed region 214a is a portion of the side surface 214 that is not covered by the side surface covering portion 252.
  • the shape of the exposed region 214a is rectangular, but is not particularly limited.
  • the boundary line between the exposed region 214a and the main surface covering portion 241 corresponds to the connection portion (one side of the rectangular parallelepiped) between the side surface 214 and the main surface 211.
  • the main surface covering portion 241 overlaps with the main surface covering portion 251 in a plan view.
  • the main surface covering portion 241 covers more than half of the main surface 211.
  • the main surface covering portion 251 covers more than half of the main surface 212.
  • the chip capacitor 200 can be easily mounted on the module board 91.
  • electrical connection between each of the main surface covering portions 241 and 251 and the conductive pattern of the metal shield layer 95 or the module substrate 91 can be easily and satisfactorily performed.
  • the widths of the exposed regions 211a to 214a do not have to be constant.
  • the width w1 of the exposed region 211a does not have to be a constant value.
  • the boundary line between the exposed region 211a and the main surface covering portion 241 may be a curved line or a straight line inclined obliquely with respect to one side of the main surface 211. The same applies to the widths w2, w3 and w4.
  • the chip capacitor 200 is arranged on the main surface 91a of the module board 91. Specifically, the chip capacitor 200 is arranged so that the main surfaces 211 and 212 of the main body 210 are parallel to the main surface 91a of the module substrate 91, that is, horizontally. Therefore, both the internal electrodes 220 and 230 provided inside the chip capacitor 200 are parallel to the main surface 91a of the module substrate 91.
  • the side surfaces 213 and 214 of the main body 210 of the chip capacitor 200 are perpendicular to the main surface 91a of the module board 91.
  • the side surface covering portion 242 of the electrode terminal 240 and the side surface covering portion 252 of the electrode terminal 250 are also perpendicular to the main surface 91a.
  • the electrode terminal 250 of the chip capacitor 200 is in contact with a conductive pattern (not shown) provided on the main surface 91a of the module substrate 91.
  • Conductive patterns are part of transmit, receive and transmit / receive paths.
  • the conductive pattern in contact with the electrode terminals 250 is a part of the transmission / reception path ATR.
  • the electrode terminal 240 of the chip capacitor 200 is in contact with the metal shield layer 95. Specifically, the upper surface of the main surface covering portion 241 of the electrode terminal 240 is in contact with the back surface of the metal shield layer 95. Since the metal shield layer 95 is set to the ground potential, the electrode terminal 240 of the chip capacitor 200 is also set to the ground potential. That is, the chip capacitor 200 constitutes a shunt capacitor (for example, the capacitor 71C shown in FIG. 1) having one end connected to the ground.
  • the upper surface of the main surface covering portion 241 and the top surface (upper surface) of the resin member 92 are flush with each other, but the present invention is not limited to this.
  • the resin member 92 is formed so as to cover the upper surface of the chip capacitor 200 (that is, the upper surface of the main surface covering portion 241), and then a recess is provided in the resin member 92 by irradiating the resin member 92 with the main surface covering portion.
  • the upper surface of the 241 may be exposed to the bottom of the recess.
  • the metal shield layer 95 is formed along the inner surface of the recess.
  • the side surface covering portion 242 is provided so as to extend from the metal shield layer 95 toward the main surface 91a of the module substrate 91. Since the side surface 213 of the main body 210 is perpendicular to the main surface 91a, the side surface covering portion 242 is a metal wall provided perpendicular to the main surface 91a. Since the exposed region 213a is provided as shown in FIG. 4, the side surface covering portion 242 is not in contact with the main surface 91a.
  • the side surface covering portion 242 Since the side surface covering portion 242 is set to the ground potential, it has a shielding function. Specifically, the side surface covering portion 242 can suppress magnetic field coupling between other components, and can suppress quality deterioration of the transmission signal or the reception signal. As described above, in the present embodiment, the chip capacitor 200 also functions as a shield member that suppresses magnetic field coupling. That is, the chip capacitor 200 has not only a function of removing harmonic components of a transmission signal but also a function of suppressing magnetic field coupling.
  • the thickness d2 of the side surface covering portion 242 is thicker than the thickness d1 of the main surface covering portion 241. Thereby, the shielding function by the side surface covering portion 242 can be enhanced.
  • the chip capacitor 200 is arranged between two inductors included in the high frequency module 1 in a plan view.
  • One of the two inductors is arranged in one of the transmit path, the receive path and the transmit / receive path, and the other of the two inductors is arranged in the above one of the transmit path, the receive path and the transmit path. It is located on no route.
  • the chip capacitor 200 including the capacitor 71C is arranged between the inductor 31L arranged in the transmission path AT and BT and the inductor 70L arranged in the transmission / reception path CTR.
  • the chip capacitor 200 can suppress the magnetic field coupling between the inductor 31L and the inductor 70L.
  • the chip capacitor 202 including the capacitor 72C is arranged between the inductor 72L arranged in the transmission / reception path BTR and the inductor 41L arranged in the reception path AR and BR.
  • the chip capacitor 202 can suppress the magnetic field coupling between the inductor 72L and the inductor 41L. For example, it is possible to suppress the transmission signal passing through the inductor 72L from wrapping around through the inductor 41L and affecting the received signal.
  • a part of the chip capacitors 200 and 202 is arranged between the inductor 31L arranged in the transmission path AT and BT and the inductor 41L arranged in the reception path AR and BR.
  • the chip capacitors 200 and 202 can suppress the magnetic field coupling between the inductor 31L and the inductor 41L. Therefore, the isolation between transmission and reception can be enhanced.
  • both of the two inductors sandwiching the chip capacitor may be inductors arranged in the transmission path.
  • the chip capacitor 201 including the capacitor 31C is arranged between the inductor 31L arranged in the transmission path AT and BT and the inductor 32L arranged in the transmission path AT and BT.
  • the chip capacitor 201 can suppress the magnetic field coupling between the inductor 31L and the inductor 32L. By suppressing the signal wraparound between the input and output of the power amplifier 11, the oscillation of the power amplifier 11 can be suppressed.
  • both of the two inductors sandwiching the chip capacitor may be inductors arranged in the receiving path.
  • the chip capacitor may be arranged between the inductor connected to the output terminal of the low noise amplifier 21 and the inductor 41L in plan view. ..
  • the capacitor included in the chip capacitor in this case may be any of the capacitors 31C, 71C and 72C.
  • the chip capacitor may include a capacitor connected to the receive path AR or BR.
  • each of the chip capacitors 200 to 202 can suppress the magnetic field coupling between the plurality of inductors.
  • the arrangement of the inductor and the chip capacitor shown in FIG. 2 is only an example, and is not particularly limited.
  • at least one of the chip capacitors 200 to 202 may be arranged between the inductor 31L and the inductor 41L.
  • At least one of the chip capacitors 200 to 202 may be arranged between the inductor 32L and the inductor 41L.
  • the short circuit between the electrode terminal 240 and the electrode terminal 250 can be suppressed by providing the exposed regions 211a to 214a.
  • the exposed area 212a And 213a can prevent the protruding solder from coming into contact with the side surface covering portion 242 of the electrode terminal 240.
  • the resin member 92 so as to cover the exposed regions 211a and 214a, it is possible to prevent the metal shield layer 95 from coming into contact with the side surface covering portion 252 of the electrode terminal 250. In this way, a short circuit between the electrode terminal 240 and the electrode terminal 250 can be suppressed.
  • the exposed areas 211a to 214a may not be provided.
  • the exposed areas 213a and 214a may not be provided.
  • FIG. 5 is a diagram showing a chip capacitor 200A of the high frequency module 1 according to the present embodiment.
  • FIGS. 5A to 5E are a cross-sectional view, a top view, a bottom view, a right side view, and a left side view of the chip capacitor 200A, respectively.
  • FIG. 5A shows a cross section of FIG. 5B on the Va—Va line.
  • the electrode terminals 240A and 250A are shaded with dots, respectively.
  • the side surface covering portion 242A of the electrode terminal 240A covers the entire side surface 213 of the main body 210. Further, the side surface covering portion 252A of the electrode terminal 250A covers the entire side surface 214 of the main body 210.
  • the gap between the side surface covering portion 242A and the main surface 91a becomes narrow. Therefore, the shielding function of the side surface covering portion 242A can be further enhanced.
  • the exposed areas 211a and 212a may not be provided.
  • FIG. 6 is a diagram showing a chip capacitor 200B of the high frequency module 1 according to the present embodiment.
  • FIGS. 6A to 6E are a cross-sectional view, a top view, a bottom view, a right side view, and a left side view of the chip capacitor 200B, respectively.
  • FIG. 6A shows a cross section of FIG. 6B on the VIa-VIa line.
  • the electrode terminals 240B and 250B are shaded with dots, respectively.
  • the main surface covering portion 241B of the electrode terminal 240B covers the entire main surface 211 of the main body 210. Further, the main surface covering portion 251B of the electrode terminal 250B covers the entire main surface 212 of the main body 210.
  • the high frequency module 1 includes the module substrate 91 having the main surface 91a, the first inductor and the second inductor arranged on the main surface 91a, the main surface 91a, the first inductor, and the main surface 91a.
  • a resin member 92 that covers at least a part of the second inductor, a metal shield layer 95 that covers the surface of the resin member 92 and is set to a ground potential, and a case where the module substrate 91 is viewed in a plan view on the main surface 91a.
  • a chip capacitor arranged between the first inductor and the second inductor is provided.
  • the chip capacitor has an electrode terminal 240 in contact with the metal shield layer 95, an electrode terminal 250, a main body 210 having main surfaces 211 and 212, and side surfaces 213 and 214, and inside the main body 210, the side surface 213 to the main surface 211. It has an internal electrode 220 extending parallel to the main body 210, and an internal electrode 230 extending parallel to the main surface 211 from the side surface 214 and overlapping the internal electrode 220 in a plan view.
  • the electrode terminal 240 is connected to the internal electrode 220 and is connected to the side surface covering portion 242 that covers at least a part of the side surface 213, and is connected to the side surface covering portion 242 and covers at least a part of the main surface 211. It has a portion 241 and.
  • the electrode terminal 250 is connected to the internal electrode 230 and is connected to the side surface covering portion 252 that covers at least a part of the side surface 214, and is connected to the side surface covering portion 252 and covers at least a part of the main surface 212. It has a portion 251 and.
  • the main surface covering portion 241 overlaps with the main surface covering portion 251 in a plan view.
  • the first inductor and the second inductor are arranged so as to sandwich the chip capacitor having the electrode terminal 240 set to the ground potential, so that the magnetic field coupling between the first inductor and the second inductor is suppressed. Can be done. Since the wraparound of the signal due to the magnetic field coupling can be suppressed, it is possible to suppress the deterioration of the quality due to the mixing of unnecessary signals with the transmitted signal or the received signal.
  • the chip capacitor can be provided with a function of removing harmonic components of a transmission signal.
  • the electrode terminal 240 of the chip capacitor including the capacitor essential in the circuit configuration of the high frequency module 1 also functions as a shield that suppresses electromagnetic field coupling.
  • one chip capacitor can realize not only a shield function that suppresses electromagnetic field coupling but also a predetermined function in the circuit configuration, so that it is not necessary to provide dedicated parts and members for each, and high frequency is used. It can also contribute to the miniaturization of module 1.
  • the first inductor is arranged in any of the transmission path, the reception path, and the transmission / reception path.
  • the second inductor is arranged in one of the two paths of the transmission path, the reception path, and the transmission / reception path, excluding the path in which the first inductor is arranged.
  • the first inductor may be arranged in the transmission path, and the second inductor may be arranged in the reception path.
  • the first inductor may be arranged in the transmission path
  • the second inductor may be arranged in the transmission / reception path.
  • the first inductor may be arranged in the receiving path, and the second inductor may be arranged in the transmitting / receiving path.
  • the chip capacitor may be connected in series between the transmission path and the ground.
  • the chip capacitor can remove the harmonic component transmitted through the transmission path. That is, the chip capacitor has not only the function of suppressing the magnetic field coupling between the two inductors but also the function of removing harmonics.
  • the high frequency module 1 may include a power amplifier 11 for amplifying a transmission signal, and a chip capacitor may be connected to an output terminal of the power amplifier 11.
  • the harmonic component of the transmission signal is likely to be generated in the power amplifier 11, so that the harmonic component can be efficiently removed by the chip capacitor connected to the output terminal of the power amplifier 11.
  • the high frequency module 1 may include a transmission filter through which a transmission signal is passed, and a chip capacitor may be connected to one end of the transmission filter.
  • the harmonic component that could not be removed by the transmission filter can be removed by the chip capacitor.
  • the high frequency module 1 may include an amplifier for amplifying a high frequency signal, the first inductor may be connected to the output terminal of the amplifier, and the second inductor may be connected to the input terminal of the amplifier.
  • the amplifier may be a power amplifier that amplifies a transmission signal that is a high-frequency signal.
  • the chip capacitor may be connected to the output terminal of the power amplifier 11.
  • one of the two inductors and the chip capacitor are electrically connected, and the wiring length required for the connection can be shortened.
  • the wiring length required for the connection can be shortened.
  • the side surface covering portion 242 does not cover a region having a predetermined width from the connection portion between the side surface 213 and the main surface 212 of the side surface 213, and the side surface covering portion 252 is the side surface 214 of the side surface 214. It does not cover the area of the predetermined width from the connection portion with the main surface 211.
  • the main surface covering portion 241 does not cover a region having a predetermined width from the connection portion between the main surface 211 and the side surface 214 in the main surface 211, and the main surface covering portion 251 is in the main surface 212.
  • the area of a predetermined width is not covered from the connection portion between the main surface 212 and the side surface 213.
  • the thickness d2 of the side surface covering portion 242 is thicker than the thickness d1 of the main surface covering portion 241.
  • the thickness d4 of the side surface covering portion 252 is thicker than the thickness d3 of the main surface covering portion 251.
  • the communication device 5 includes an RFIC 3 for processing a high frequency signal transmitted / received by the antenna 2 and a high frequency module 1 for transmitting a high frequency signal between the antenna 2 and the RFIC 3.
  • the thickness of the main surface covering portion and the thickness of the side covering portion may be the same.
  • the thickness of the main surface covering portion may be thicker than the thickness of the side surface covering portion.
  • the first electrode terminal and the second electrode terminal of the chip capacitor may have different shapes.
  • the chip capacitor may have any one of the electrode terminals 240, 240A and 240B and one of the electrode terminals 250, 250A and 250B.
  • the high frequency module may have only one chip capacitor.
  • the capacitor not included in the chip capacitor may be formed by utilizing the wiring pattern of the module board 91 or the integrated circuit element. Further, a plurality of capacitors may be provided in one chip capacitor.
  • each circuit component constituting the high frequency module is arranged on only one of the main surfaces of the module board 91, but each circuit component is distributed and arranged on the two main surfaces of the module board 91. May be. That is, each circuit component may be mounted on the module board 91 on one side or on both sides.
  • the chip capacitor may be located inside the circumscribed rectangle or circumscribed circle that circumscribes the first inductor and the second inductor. In this case, even if the chip capacitor is not located between the first inductor and the second inductor, it is possible to block a part of the magnetic field radially emitted from each of the first inductor and the second inductor. That is, the chip capacitor can suppress the magnetic field coupling between the first inductor and the second inductor.
  • the present invention can be widely used in communication devices such as mobile phones as a high frequency module arranged in a multi-band compatible front end portion.
  • High frequency module 2 Antenna 3 RFIC 4 BBIC 5 Communication device 11 Power amplifier 21 Low noise amplifier 31C, 71C, 72C Capacitor 31L, 32L, 41L, 70L, 71L, 72L Inductor 51, 52, 53 Switch 61, 62 Duplexer 61R, 62R Receive filter 61T, 62T Transmission filter 91 module Substrate 91a, 91b, 211, 212 Main surface 92 Resin member 95 Metal shield layer 100 Antenna connection terminal 111 Transmission input terminal 121 Reception output terminal 150 External connection terminal 200, 200A, 200B, 201, 202 Chip capacitor 210 Main body 211a, 212a, 213a, 214a Exposed area 213, 214 Side surface 220, 230 Internal electrodes 240, 240A, 240B, 250, 250A, 250B Electrode terminals 241, 241B, 251, 251B Main surface covering part 242, 242A, 252, 252A Side covering part 511, 512, 5

Abstract

L'invention concerne un module à hautes fréquences (1) comportant : un substrat de module (91) présentant une surface principale (91a) ; un premier inducteur et un second inducteur, disposés sur la surface principale (91a) ; un élément en résine (92) ; une couche de blindage métallique (95), recouvrant une surface de l'élément en résine (92) ; et un condensateur à puce (200), disposé entre le premier inducteur et le second inducteur. Le condensateur à puce (200) comprend : une borne d'électrode (240), en contact avec la couche de blindage métallique (95) ; une borne d'électrode (250) ; un corps (210) ; et une électrode interne (220, 230), disposée à l'intérieur du corps (210). La borne d'électrode (240) contient une partie de revêtement (242) de surface latérale, recouvrant au moins une partie de la surface latérale (213) ; et une partie de revêtement (241) de surface principale, recouvrant au moins une partie de la surface principale (211). La borne d'électrode (250) contient une partie de revêtement (252) de surface latérale, recouvrant au moins une partie de la surface latérale (214) et une partie de revêtement (251) de surface principale, recouvrant au moins une partie de la surface principale (212).
PCT/JP2021/033534 2020-09-30 2021-09-13 Module à hautes fréquences et dispositif de communication WO2022070862A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55169839U (fr) * 1979-05-24 1980-12-05
JPH0855752A (ja) * 1994-08-10 1996-02-27 Taiyo Yuden Co Ltd 積層コンデンサの実装方法及び積層コンデンサ
JP2003234595A (ja) * 2003-02-07 2003-08-22 Denso Corp 電磁波シールド型半導体装置
WO2017169547A1 (fr) * 2016-03-31 2017-10-05 株式会社村田製作所 Module à haute fréquence
JP2019153611A (ja) * 2018-02-28 2019-09-12 株式会社村田製作所 モジュール

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55169839U (fr) * 1979-05-24 1980-12-05
JPH0855752A (ja) * 1994-08-10 1996-02-27 Taiyo Yuden Co Ltd 積層コンデンサの実装方法及び積層コンデンサ
JP2003234595A (ja) * 2003-02-07 2003-08-22 Denso Corp 電磁波シールド型半導体装置
WO2017169547A1 (fr) * 2016-03-31 2017-10-05 株式会社村田製作所 Module à haute fréquence
JP2019153611A (ja) * 2018-02-28 2019-09-12 株式会社村田製作所 モジュール

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