WO2022067589A1 - 一种芯片封装和电子设备 - Google Patents

一种芯片封装和电子设备 Download PDF

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Publication number
WO2022067589A1
WO2022067589A1 PCT/CN2020/119111 CN2020119111W WO2022067589A1 WO 2022067589 A1 WO2022067589 A1 WO 2022067589A1 CN 2020119111 W CN2020119111 W CN 2020119111W WO 2022067589 A1 WO2022067589 A1 WO 2022067589A1
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WO
WIPO (PCT)
Prior art keywords
heat dissipation
dissipation cover
silicon wafer
substrate
chip package
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Application number
PCT/CN2020/119111
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English (en)
French (fr)
Inventor
孙世虎
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202080104020.7A priority Critical patent/CN116157905A/zh
Priority to PCT/CN2020/119111 priority patent/WO2022067589A1/zh
Publication of WO2022067589A1 publication Critical patent/WO2022067589A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons

Definitions

  • the present application relates to the field of electronic technology, and in particular, to a chip package and an electronic device.
  • a silicon wafer 01 is mounted on a substrate 02 , in order to increase the heat dissipation effect, a heat dissipation cover 03 is provided above the silicon wafer 01 , and the heat dissipation cover 03 is covered above the silicon wafer 01 , The two sides are connected to the substrate 02 to encapsulate the silicon wafer 01 .
  • the heat dissipation cover 03 is in contact with the silicon wafer 01 to dissipate the heat of the silicon wafer 01, thereby achieving the purpose of improving the heat dissipation effect.
  • the heat dissipation cover 03 is attached to the upper surface of the silicon wafer 01, and the thickness of the heat dissipation cover 03 itself is relatively thick, so that the size of the packaged chip is further increased. And when the package size becomes smaller, the quality of the heat dissipation cover 03 itself increases, which leads to an increase in the contact surface pressure with the substrate 02, and then a series of problems may occur, such as: the surface of the substrate 02 is warped, the resistance-capacitance space is limited, the reliability is reduced, and the packaging issues such as rising costs. Therefore, the chip of the related art cannot solve the heat dissipation problem of the thin and light chip in a small package size.
  • the embodiments of the present application provide a chip package and an electronic device, which can solve the problem of heat dissipation of thin and light chips in a small package size.
  • an embodiment of the present application provides a chip package, including:
  • a silicon wafer wherein the silicon wafer is arranged on one side of the substrate;
  • a heat dissipation cover wherein the heat dissipation cover is connected to the substrate, the heat dissipation cover and the silicon wafer are arranged on the same side of the substrate, the heat dissipation cover is provided with an opening along the thickness direction of the substrate, the silicon wafer is arranged in the opening, the heat dissipation cover at least partially surrounds the silicon wafer, and the silicon wafer is less than or equal to the height of the cooling cover.
  • the heat dissipation cover is provided with an opening along the thickness direction of the substrate, and the silicon chip is arranged in the opening, the installation of the heat dissipation cover can avoid the position of the silicon chip, and the silicon chip and the heat dissipation cover will not be stacked. Together, the heat dissipation cover does not extend to the part of the silicon wafer on the side away from the substrate, so the strength and thickness of this part are not considered.
  • the height of the heat dissipation cover only needs to be slightly greater than or even equal to the height of the silicon wafer, so as to ensure that the silicon wafer can be protected from wear. Therefore, compared with the related technology chip packaging solution, the heat dissipation cover can be reduced in thickness and can be adapted to small package size chips. Manufacture of packages.
  • the heat dissipation cover at least partially surrounds the silicon wafer, which ensures the heat dissipation effect of the heat dissipation cover on the silicon wafer. Therefore, the heat dissipation problem of thin and light chips with small package size can be solved.
  • the height of the silicon wafer is less than or equal to the height of the heat dissipation cover to ensure that the surface of the side of the silicon wafer away from the substrate is not higher than the side of the heat dissipation cover away from the substrate, which is conducive to protecting the silicon wafer and improving the heat dissipation of the heat dissipation cover to the silicon wafer. .
  • the height of the silicon wafer refers to the distance from the side surface of the silicon wafer away from the substrate to the substrate, including the thickness of the silicon wafer and the solder fillet gap between the silicon wafer and the substrate;
  • the height of the heat dissipation cover refers to the distance from the heat dissipation cover to the substrate.
  • the distance from one side surface of the substrate to the substrate includes the thickness of the heat dissipation cover and the thickness generated by the connection of the heat dissipation cover to the substrate (for example, the thickness of the adhesive layer).
  • the height of the silicon wafer is less than or equal to the height of the heat dissipation cover, which can also be interpreted as the upper surface of the silicon wafer is lower than or equal to the height of the heat dissipation cover. Flush with the top surface of the heat dissipation cover.
  • the substrate is provided with electronic components, a surface of the heat dissipation cover on one side close to the substrate is recessed to form a groove, and the electronic components are located in the groove.
  • other electronic components may be arranged on the substrate, such as some passive components, that is, capacitors, resistors and inductors. These electronic components are also arranged on the substrate, which also affects the thickness of the chip package, that is, may interfere with the heat dissipation cover and affect the overall thickness of the chip package. Therefore, in order to allow the heat dissipation cover to avoid these electronic components, a side surface close to the substrate is recessed, and a groove is formed, and the electronic components are located in the groove.
  • the projection of the outline of the opening completely covers the silicon wafer. This can ensure that the silicon chip can be located in the opening, so that the overall thickness of the chip package can be reduced to a certain extent.
  • the contour of the opening is consistent with the contour of the silicon wafer. That is, along the thickness direction of the substrate, the shape of the opening is the same as that of the silicon wafer.
  • the opening can be as large as the silicon wafer. At this time, the silicon wafer is just inside the opening, and the sidewall of the silicon wafer is attached to the sidewall of the opening.
  • the opening can also be slightly larger than the silicon wafer. At this time, the sidewall of the silicon wafer is There is a certain gap between it and the side wall of the opening, and the distance of the gap can be uniform around the circumference of the silicon wafer.
  • the outline of the opening is consistent with the outline of the silicon wafer, which is convenient for manufacture and assembly, and the opening can be made as small as possible under the condition that the silicon wafer can be located in it, so that the edge of the heat dissipation cover can be kept away from the edge of the silicon wafer.
  • the distance can be very close, and the layout area of the heat dissipation cover can be larger in a limited space, which is beneficial to improve the heat dissipation effect of the silicon chip.
  • the opening is located in the middle of the heat dissipation cover, and the heat dissipation cover surrounds the silicon wafer.
  • the opening can be arranged on the side of the heat dissipation cover or in the middle of the heat dissipation cover. That is to say, when looking down or looking up at the heat dissipation cover from the thickness direction of the heat dissipation cover, taking the heat dissipation cover as a rectangle as an example, the opening is arranged on the side of the heat dissipation cover, and the heat dissipation cover is approximately in the shape of a "concave" shape, and the opening is arranged on the heat dissipation cover. When in the middle of the cover, the heat dissipation cover presents a "back" shape.
  • the opening is arranged in the middle of the heat dissipation cover.
  • the heat dissipation cover provided with the opening is an annular structure, and the silicon wafer is located at the opening of the annular structure. , that is, the heat dissipation cover surrounds the silicon wafer.
  • the heat dissipation cover is arranged around the silicon wafer, that is, the pins of the heat dissipation cover are fixed on the circumference of the silicon wafer to surround the silicon wafer. In this way, the connection between the heat dissipation cover and the substrate can also prevent the substrate from warping.
  • a cross section of the heat dissipation cover along the thickness direction of the substrate is a rectangle.
  • the heat dissipation cover is a plate-like structure. After the opening is opened in the middle of the heat dissipation cover, the silicon chip is placed in the opening. If no other components are required to be avoided, at this time, the cross section of the annular heat dissipation cover along the thickness direction of the substrate is rectangular to ensure heat dissipation. The thickness of the cover is uniform.
  • the groove is provided at the edge of the heat dissipation cover, and the cross section of the heat dissipation cover along the thickness direction of the substrate is stepped or "T" shaped.
  • the grooves need to be arranged according to the positions of the electronic components.
  • the grooves can be arranged on the edge of the heat dissipation cover or in the middle of the heat dissipation cover, and the grooves can be multiple small-sized grooves, or long grooves, etc.
  • the solution that the groove is arranged in the middle of the heat dissipation cover will reduce the strength of the middle part of the heat dissipation cover, the heat dissipation cover is easy to be damaged, and it is not easy to manufacture. Therefore, the grooves are provided at the edge of the heat dissipation cover.
  • the groove is designed as close to the opening as possible.
  • the cross section in the direction is stepped; when the grooves are provided on both sides of the heat dissipation cover, the cross section of the heat dissipation cover along the thickness direction of the substrate is a "T" shape.
  • the bottom surface of the groove forms an obtuse angle with the side wall.
  • the bottom surface of the groove is perpendicular to the side wall.
  • the groove of the stepped heat dissipation cover avoids electronic components.
  • the bottom surface of the groove and the side wall form an obtuse angle or the bottom surface of the groove is perpendicular to the side wall.
  • the bottom surface of the groove is perpendicular to the side wall, which is an approximately vertical state. Due to the influence of the structure and process, the vertical is vertical with a certain error value.
  • the heat dissipation cover is provided with a connection hole, and the connection hole is used to connect the heat dissipation cover to a system-level heat sink disposed on a surface of the silicon chip away from the substrate.
  • the chip package will be installed in a corresponding carrier to achieve the required functions.
  • the carrier can be a printed circuit board (PCB), etc., and a system-level heat sink is generally installed on the chip package.
  • the system-level radiator is connected to the PCB board.
  • a connection hole is provided on the heat dissipation cover, and the system-level radiator can be directly connected to the heat dissipation cover to facilitate assembly. .
  • connection holes are arranged to avoid the grooves.
  • the thickness of the heat dissipation cover is relatively small at the places corresponding to the grooves, and the structural strength here is not high. If a connecting hole is provided at the groove of the heat dissipation cover, the structural strength of the heat dissipation cover will be further reduced. Therefore, the connection holes are arranged to avoid the grooves to ensure the strength of the heat dissipation cover.
  • the chip package can be conveniently connected with other carriers through the connection holes.
  • connection holes are through holes or blind holes.
  • connection holes can be through holes or blind holes, and different types of holes correspond to different installation requirements.
  • the front end of the fastener fitted in the through hole can penetrate through the heat dissipation cover to make the connection more tightly; however, there may be problems such as taking up a large space and affecting the structural strength.
  • connection holes are blind holes
  • the fasteners arranged in the blind holes do not need to penetrate the heat dissipation cover, the fasteners do not need to occupy additional space, and the impact on the structural strength of the heat dissipation cover is relatively small; however, the stability of the connection is A solution without through-holes is better.
  • a thread is provided in the connection hole.
  • a thread can be provided in the connecting hole.
  • connection holes there are multiple connection holes, and the multiple connection holes are evenly distributed on the heat dissipation cover.
  • the substrate and the heat dissipation cover are bonded.
  • the substrate and the heat dissipation cover are bonded through an adhesive layer, and the adhesive layer is composed of an adhesive.
  • embodiments of the present application provide an electronic device, a printed circuit board (PCB), and the chip package according to any one of the first aspect, where the chip package is electrically connected to the printed circuit board.
  • PCB printed circuit board
  • the electronic device includes the chip package of the first aspect, the heat dissipation problem of a thin and light chip with a small package size can be solved.
  • the electronic device in this embodiment of the present application may be a server, a base station, or a computer, or the like.
  • FIG. 1 is a schematic diagram of a chip package of the related art
  • FIG. 2 is a schematic side cross-sectional structural diagram of a heat dissipation cover of a chip package according to an embodiment of the present application
  • FIG. 3 is a schematic top-view structural diagram of the opening of the heat dissipation cover of the chip package according to the embodiment of the present application being disposed on the side;
  • FIG. 4 is a schematic top-view structural diagram of an opening of a heat dissipation cover of a chip package provided in the middle according to an embodiment of the present application;
  • FIG. 5 is a schematic cross-sectional structural schematic diagram of a side view of a heat dissipation cover of a chip package according to an embodiment of the present application
  • FIG. 6 is a schematic bottom view of the structure of the groove of the heat dissipation cover of the chip package provided near the opening according to the embodiment of the present application;
  • FIG. 7 is a schematic structural diagram in which the cross section of the heat dissipation cover of the chip package according to the embodiment of the present application is stepped and the sidewall and bottom surface of the groove are obtuse angles;
  • FIG. 8 is a schematic side cross-sectional structural diagram of the groove of the heat dissipation cover of the chip package provided in the middle of the embodiment of the present application;
  • FIG. 9 is a schematic side cross-sectional structural diagram of a heat dissipation cover of a chip package according to an embodiment of the present application in a “T” shape;
  • FIG. 10 is a schematic side cross-sectional structural diagram of a chip package provided with a connection hole according to an embodiment of the present application.
  • FIG. 11 is a schematic side cross-sectional structural diagram of a connection hole provided in a chip package provided with a screw thread according to an embodiment of the present application.
  • orientation terms such as “upper”, “lower”, “left” and “right” are defined relative to the orientation in which the components in the drawings are schematically placed, and it should be understood that these directional terms are Relative notions, they are used for relative description and clarification, which may vary accordingly depending on the orientation in which components are placed in the figures.
  • connection should be understood in a broad sense.
  • connection may be a fixed connection, a detachable connection, or an integrated body; it may be directly connected, or Can be indirectly connected through an intermediary.
  • the embodiment of the present application provides an electronic device, which may include a server or a base station, as well as a mobile phone (mobile phone), a tablet computer (pad), a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (virtual reality) , VR) terminal equipment, augmented reality (AR) terminal equipment and other equipment.
  • a server or a base station as well as a mobile phone (mobile phone), a tablet computer (pad), a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (virtual reality) , VR) terminal equipment, augmented reality (AR) terminal equipment and other equipment.
  • Electronic equipment requires the transmission of circuit signals and data processing, etc., which will use chip packaging that can process data.
  • FIG. 2 is a cross-sectional view of the chip package, including a substrate 100 , a silicon wafer 200 disposed on the substrate 100 , and a heat dissipation cover 301 disposed on the substrate 100 .
  • the heat dissipation cover 301 can solve the heat dissipation problem of thin and light chips with small package size.
  • the substrate 100 and the heat dissipation cover 301 may be connected by bonding.
  • the substrate 100 and the heat dissipation cover 301 are bonded by an adhesive layer 400 , wherein the adhesive layer 400 may be composed of an adhesive.
  • the chip package will be installed on the corresponding carrier to achieve the required functions.
  • the carrier can be a PCB (Printed Circuit Board, printed circuit board), etc., and a system-level heat sink is generally set on the chip package. Typically, system level heat sinks are attached to the PCB board.
  • the structure in which the chip package is connected to the PCB board may be a ball grid array (BGA) structure.
  • BGA ball grid array
  • connection structure may be a microbump ( ⁇ bump) 201 structure.
  • the following describes how the heat dissipation cover 301 of the chip package provided by the embodiment of the present application solves the heat dissipation problem of a thin and light chip with a small package size.
  • the chip package provided by the embodiment of the present application includes:
  • the silicon wafer 200 wherein the silicon wafer 200 is arranged on one side of the substrate 100;
  • the heat dissipation cover 301 wherein the heat dissipation cover 301 is connected to the substrate 100, the heat dissipation cover 301 and the silicon wafer 200 are arranged on the same side of the substrate 100, the heat dissipation cover 301 is provided with an opening 302 along the thickness direction of the substrate 100, and the silicon wafer 200 is arranged in the opening 302,
  • the heat dissipation cover 301 at least partially surrounds the silicon wafer 200 , and the height of the silicon wafer 200 is less than or equal to the height of the heat dissipation cover 301 .
  • the heat dissipation cover 301 has an opening 302 along the thickness direction of the substrate 100 , and the silicon wafer 200 is arranged in the opening 302 , the heat dissipation cover 301 can be installed to avoid the silicon wafer 200 . position, the silicon wafer 200 and the heat dissipation cover 301 will not be stacked together. Compared with the chip packaging solution of the related art, the heat dissipation cover 301 does not extend to the part of the silicon wafer 200 away from the substrate, so the strength and thickness issue.
  • the height of the heat dissipation cover 301 only needs to be slightly greater than or even equal to the height of the silicon wafer 200 to ensure that the silicon wafer 200 can be protected from being worn. Therefore, the heat dissipation cover 301 can be reduced in thickness and can be adapted to the manufacture of chip packages with small package sizes.
  • the heat dissipation cover 301 at least partially surrounds the silicon wafer 200 , which ensures the heat dissipation effect of the heat dissipation cover 301 on the silicon wafer 200 . Therefore, the heat dissipation problem of thin and light chips with small package size can be solved.
  • the height of the silicon wafer 200 is less than or equal to the height of the heat dissipation cover 301 to ensure that the surface of the side of the silicon wafer 200 away from the substrate 100 is not higher than the side of the heat dissipation cover 301 away from the substrate 100, which is beneficial to protect the silicon wafer 200, and has It is beneficial to improve the heat dissipation of the heat dissipation cover 301 to the silicon wafer 200 .
  • the height of the silicon wafer 200 refers to the distance from the side surface of the silicon wafer 200 away from the substrate 100 to the substrate 100 .
  • the distance m shown in FIG. 2 it includes the thickness of the silicon wafer 200 and the The thickness of the micro-bumps 201 between the silicon wafer 200 and the substrate 100, etc.
  • the height of the heat dissipation cover 301 refers to the distance from the surface of the heat dissipation cover 301 away from the substrate 100 to the substrate 100, referring to the distance of n shown in FIG. 2, It includes the thickness of the heat dissipation cover 301 and the thickness generated by the connection of the heat dissipation cover 301 to the substrate 100 (for example, the thickness of the adhesive layer 400 ).
  • the chip package is generally mounted on a PCB during use, and a system-level heat sink is connected to the chip package to dissipate heat from the chip package.
  • the system level heat sink may be close to the surface of the chip package away from the PCB board, that is, the system level heat sink may be close to the side of the silicon wafer 200 and the heat dissipation cover 301 in the chip package away from the substrate 100 .
  • the system-level heat sink will be in close contact with the silicon wafer 200 , which may wear or crush the silicon wafer 200 .
  • the height n of the heat dissipation cover 301 is slightly larger than the height m of the silicon wafer 200, which ensures that the silicon wafer 200 can be protected from being worn, wherein the difference between the height n of the heat dissipation cover 301 and the height m of the silicon wafer 200 is b, the height of b, regardless of the strength of the heat dissipation cover 301, can be infinitely close to or equal to zero, so as to obtain a greater reduction in the thickness of the chip package.
  • the height of the silicon wafer 200 is less than or equal to the height of the heat dissipation cover 301 , which can also be explained
  • the upper surface of the silicon wafer 200 is lower than or flush with the upper surface of the heat dissipation cover 301 .
  • the projection of the outline of the opening 302 completely covers the silicon wafer 200 . In this way, it can be ensured that the silicon chip 200 can be located in the opening 302, so that the overall thickness of the package of the chip 200 can be reduced to a certain extent.
  • the contour of the opening 302 is consistent with the contour of the silicon wafer 200 . That is, along the thickness direction of the substrate 100 , the shape of the opening 302 is the same as that of the silicon wafer 200 .
  • the opening 302 can be as large as the silicon wafer 200.
  • the silicon wafer 200 is just located in the opening 302, and the sidewall of the silicon wafer 200 is attached to the sidewall of the opening 302; the opening 302 can also be slightly larger than the silicon wafer 200.
  • there is a certain gap between the side wall of the silicon wafer 200 and the side wall of the opening 302 and the distance of the gap can be uniform throughout the circumference of the silicon wafer 200 .
  • the outline of the opening 302 is consistent with the outline of the silicon wafer 200, which is convenient for manufacture and assembly, and the opening 302 can be made as small as possible under the condition that the silicon wafer 200 can be located therein, so that the heat dissipation cover 301 can be made as small as possible.
  • the distance between the edge and the silicon wafer 200 can be very close, and the layout area of the heat dissipation cover 301 can be larger in a limited space, which is beneficial to improve the heat dissipation effect of the silicon wafer 200 .
  • the heat dissipation cover 301 at least partially surrounds the silicon wafer 200 , which means that the heat dissipation cover 301 is arranged all around the silicon wafer 200 , or at least partially is arranged with the heat dissipation cover 301 .
  • FIG. 2 is a cross-sectional view of the chip package. It can be seen that heat dissipation covers 301 are arranged on both sides of the silicon wafer 200 .
  • the cross section in the thickness direction of the heat dissipation cover 301 is rectangular. After the opening 302 is opened in the middle of the heat dissipation cover 301 , the silicon wafer 200 is arranged in the opening 302 . If it is not necessary to avoid other components, at this time, the cross section of the annular heat dissipation cover 301 in the thickness direction is rectangular to ensure the thickness of the heat dissipation cover 301 evenly.
  • the opening 302 may be disposed on the side of the heat dissipation cover 301 , or may be disposed in the middle of the heat dissipation cover 301 .
  • 3 and 4 which are top views of the heat dissipation cover 301 of the chip package, taking the heat dissipation cover 301 as a rectangle as an example, when the heat dissipation cover 301 is viewed from the thickness direction of the heat dissipation cover 301 or viewed from the bottom, the opening 302 is shown in FIG. 3 .
  • the heat dissipation cover 301 Opened on the side of the heat dissipation cover 301, if the heat dissipation cover 301 is assembled with the silicon wafer 200 at this time, at least the right side of the silicon wafer 200 as shown in FIG. 200. As shown in FIG. 4 , the opening 302 is disposed in the middle of the heat dissipation cover 301 . At this time, if the heat dissipation cover 301 is assembled with the silicon wafer 200 , the heat dissipation cover 301 is arranged around the silicon wafer 200 , that is, the heat dissipation cover 301 completely surrounds the silicon wafer 200 . .
  • the opening 302 is disposed in the middle of the heat dissipation cover 301 , so that the heat dissipation cover 301 surrounds the silicon wafer 200 , and the heat dissipation cover 301 is arranged around the silicon wafer 200 to facilitate heat dissipation of the silicon wafer 200 .
  • the opening 302 is located in the middle of the heat dissipation cover 301 .
  • the heat dissipation cover 301 surrounds the silicon wafer 200 .
  • the heat dissipation cover 301 is arranged around the silicon wafer 200, that is, the pins of the heat dissipation cover 301 are fixed on the circumference of the silicon wafer 200 to surround the silicon wafer 200. In this way, the connection between the heat dissipation cover 301 and the substrate 100 can also be prevented.
  • the substrate 100 warps when the silicon wafer 200 is soldered.
  • other electronic components 500 may be disposed on the substrate 100 in addition to the silicon wafer 200 , such as some passive components, ie, capacitors, resistors, inductors, and the like. These electronic components 500 are also disposed on the substrate 100, which will also affect the thickness of the chip package after packaging, that is, may interfere with the heat dissipation cover 301 and affect the overall thickness of the chip package. Therefore, in order to allow the heat dissipation cover 301 to avoid these electronic components 500 , referring to FIG. 5 , a schematic side cross-sectional view of the heat dissipation cover 301 of the chip package with the grooves 303 is shown.
  • the electronic components 500 are provided on the substrate 100 , and the heat dissipation cover 301 is close to the substrate.
  • One side surface of 100 is concave, a groove 303 is formed, and the electronic component 500 is located in the groove 303 .
  • FIG. 6 which is a schematic bottom view of the structure of the heat dissipation cover 301 provided with the groove 303 , the specific structure of the stepped heat dissipation cover 301 can be seen from the side of the heat dissipation cover 301 close to the substrate 100 .
  • the groove 303 of the stepped heat dissipation cover 301 avoids the electronic components 500 .
  • the specific stepped shapes can be various, for example, the bottom surface of the groove 303 and the side wall are obtuse angles or the bottom surface of the groove 303 is perpendicular to the side wall.
  • the bottom surface of the groove 303 is perpendicular to the side wall; referring to FIG. 7 , the bottom surface and the side wall of the groove 303 form an obtuse angle.
  • the bottom surface of the groove 303 is perpendicular to the sidewall, which is an approximately vertical state. Due to the influence of the structure and the process, the vertical is the vertical with a certain error value.
  • the positions of the electronic components 500 arranged on the substrate 100 have various position schemes, and the grooves 303 need to be arranged according to the positions of the electronic components 500 .
  • the groove 303 may be disposed at the edge of the heat dissipation cover 301 or near the opening 302.
  • the groove 303 is disposed at the heat dissipation cover 301 close to the opening 302; It may be arranged at other positions of the heat dissipation cover 301, such as the solution shown in FIG. 8 .
  • the grooves 303 can be a plurality of small-sized grooves 303, or can be long grooves 303, etc., wherein, the solution of the grooves 303 being arranged on the edge of the heat dissipation cover 301 is convenient for production, manufacture and assembly, and is not suitable for the heat dissipation cover. 301 has a lower overall strength impact. Therefore, the grooves 303 are provided at the edge of the heat dissipation cover 301 .
  • the groove 303 is designed as close to the opening 302 as possible, so that the cross section in the thickness direction of the heat dissipation cover 301 is stepped or "T" shaped.
  • FIG. 5 and FIG. 7 it is a scheme that the groove 303 is arranged at the position of the heat dissipation cover 301 near the opening 302 , and the cross section of the heat dissipation cover along the thickness direction of the substrate is stepped; referring to FIG. 9 , the concave
  • the cross section of the heat dissipation cover along the thickness direction of the substrate is a "T" shape.
  • the chip package will be installed on the corresponding carrier to achieve the required functions.
  • the carrier can be a PCB (Printed Circuit Board, printed circuit board), etc., and a system-level heat sink is generally set on the chip package.
  • the system-level heat sink is connected to the PCB board.
  • the heat dissipation cover 301 is provided with a connection hole 304 , and the connection hole 304 is used to connect the heat dissipation cover 301 It is connected to a system-level heat sink disposed on the surface of the silicon wafer 200 away from the substrate 100 .
  • a connection hole is provided on the heat dissipation cover 301, and the system-level heat sink can be directly connected to the heat dissipation cover, which is convenient for assembly.
  • connection holes 304 when the connection holes 304 are provided on the heat dissipation cover 301 , the connection holes 304 may be arranged to avoid the grooves 303 .
  • the thickness of the heat dissipation cover 301 corresponding to the grooves 303 is relatively small, and the structural strength here is not high. If the connection holes 304 are provided at the grooves 303 of the heat dissipation cover 301 , the structural strength there will be further reduced, thereby affecting the connection between the chip and other carriers. Therefore, the connection holes 304 are arranged to avoid the grooves 303 to ensure the strength of the connection holes 304 .
  • connection holes 304 may be through holes; or, referring to FIG. 10 , the connection holes 304 may be blind holes, and different forms of holes correspond to different installation requirements.
  • the connecting hole 304 is a through hole
  • the front end of the fastener fitted in the through hole can penetrate through the heat dissipation cover 301 to make the connection more tightly; however, there may be problems such as taking up a large space and affecting the structural strength.
  • connection holes 304 are blind holes
  • the fasteners arranged in the blind holes do not need to penetrate the heat dissipation cover 301 , the fasteners do not occupy additional space, and the impact on the structural strength of the heat dissipation cover 301 is relatively small; however, the connection The stability is not as good as the through-hole solution.
  • a thread may be provided in the connection hole 304 .
  • connection holes 304 may be evenly distributed on the heat dissipation cover 301 .

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Abstract

本申请实施例提供一种芯片封装和电子设备，涉及电子技术领域，可以解决小封装尺寸下轻薄芯片的散热问题。该芯片包括：基板；硅片，其中硅片设置在基板一侧；散热盖，其中散热盖与基板连接，散热盖与硅片设置于基板的同一侧，散热盖沿基板厚度方向开设有开口，硅片设置于开口中，散热盖至少部分环绕硅片，且硅片的高度小于或等于散热盖的高度。本申请实施例提供的芯片封装将硅片产生的大部分热量通过环绕硅片的散热盖从周围散出。

Description

一种芯片封装和电子设备 技术领域
本申请涉及电子技术领域，尤其涉及一种芯片封装和电子设备。
背景技术
随着科技的发展和工艺技术的提高，芯片的封装制造中，单位芯片面积内的晶体管的数量不断增加，进而芯片的发展趋势为单位面积下功耗增加。同时，为了满足更多应用要求，芯片及封装内部还会集成更多的模块及器件，这样，一方面芯片及封装尺寸不断增加，另一方面，对芯片的散热要求更高。为了提高散热效果，一般采用在基板表面贴装散热盖的方式。
参照图1，为相关技术的一种芯片封装，硅片01安装在基板02上，为了增加散热效果，硅片01的上方设有散热盖03，散热盖03盖设在硅片01的上方，且两侧与基板02连接，将硅片01封装起来。散热盖03与硅片01接触，以将硅片01的热量导出，进而达到提高散热效果的目的。
但是，相关技术的芯片封装中，散热盖03贴在硅片01的上表面，且散热盖03本身的厚度较厚，这样，使芯片封装后的尺寸进一步增加。且当封装尺寸变小时，散热盖03自身质量上升导致与基板02的接触面压力上升，进而可能发生一系列的问题，例如：基板02表面翘曲，阻容空间受限，可靠性下降，封装成本上升等问题。因此，相关技术的芯片无法解决小封装尺寸下轻薄芯片的散热问题。
发明内容
本申请的实施例提供一种芯片封装和电子设备，可以解决小封装尺寸下轻薄芯片的散热问题。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请实施例提供一种芯片封装，包括：
基板；
硅片，其中硅片设置在基板一侧；
散热盖，其中散热盖与基板连接，散热盖与硅片设置在基板的同一侧，散热盖沿基板厚度方向开设有开口，硅片设置于开口中，散热盖至少部分环绕硅片，且硅片的高度小于或等于散热盖的高度。
本申请实施例提供的芯片封装，由于散热盖沿基板厚度方向开设有开口，硅片设置在开口中，这样，使得散热盖的安装可以避开硅片的位置，硅片和散热盖不会层叠在一起，散热盖没有延伸至硅片远离基板的一侧的部分，因此不用考虑该部分的强度和厚度问题。散热盖的高度只要略微大于甚至等于硅片的高度，保证能够保护硅片不被磨损即可，因此，相比相关技术芯片封装的方案，散热盖可以在厚度上缩减可以适应小封装尺寸的芯片封装的制造。
同时，散热盖至少部分环绕硅片，保证了散热盖对硅片的散热作用，因此，可以 解决小封装尺寸下轻薄芯片的散热问题。
硅片的高度小于或等于散热盖的高度，保证硅片远离基板的一侧表面不会高于散热盖远离基板的一侧，有利于保护硅片，且有利于提高散热盖对硅片的散热。
需要说明的是，硅片的高度指硅片远离基板的一侧表面到基板的距离，其中包括硅片的厚度以及硅片和基板之间的焊脚间隙等；散热盖的高度指散热盖远离基板的一侧表面到基板的距离，其中包括散热盖的厚度以及散热盖与基板连接产生的厚度(例如粘接胶层的厚度)。当以基板的厚度方向为参考，基板设置硅片的一侧为上方，另外一侧为下方时，硅片的高度小于或等于散热盖的高度，也可以解释为硅片的上表面低于或平齐于散热盖的上表面。
在第一方面的第一种可能的实现方式中，基板上设有电子元件，散热盖靠近基板的一侧表面凹陷，形成有凹槽，电子元件位于凹槽中。在基板上除了硅片可能还会设置其他电子元件，例如一些被动元件，即，电容、电阻和电感等。而这些电子元件也设置在基板上，也会影响芯片封装的厚度，即，也可能会与散热盖干涉，影响芯片封装的整体厚度。因此，为了可以让散热盖避开这些电子元件，靠近基板的一侧表面凹陷，形成有凹槽，电子元件位于凹槽中。
在第一方面的第二种可能的实现方式中，沿基板的厚度方向，开口的轮廓的投影完全覆盖硅片。这样可以保证硅片能够位于开口内，以使芯片封装的整体厚度有一定程度的缩减。
在第一方面的第三种可能的实现方式中，开口的轮廓与硅片的轮廓一致。即，沿基板的厚度方向上，开口的形状与硅片的形状是一样的。开口可以与硅片一样大，此时，硅片刚好位于开口内，且硅片的侧壁与开口的侧壁贴合；开口也可以略微比硅片大一点，此时，硅片的侧壁和开口的侧壁之间具有一定的间隙，在硅片的一周，该间隙的距离可以是均匀的。
因此，开口的轮廓与硅片的轮廓一致，这样方便制造和装配，且开口在保证硅片可以位于其内的情况下，可以尽量做得很小，既可以使散热盖的边缘距离硅片的距离可以很近，又可以在有限的空间内使散热盖布局的面积更大，进而有利于提高硅片的散热效果。
在第一方面的第四种可能的实现方式中，开口位于散热盖的中部，散热盖环绕硅片。
开口可以设置在散热盖的侧边，也可以设置在散热盖的中部。也就是说，从散热盖的厚度方向俯视或者仰视散热盖时，以散热盖为矩形为例，开口设置在散热盖的侧边，散热盖近似呈现“凹”字型的形状，开口设置在散热盖的中部时，散热盖呈现“回”字型的形状。为了使硅片的周围都布局有散热盖，提高硅片的散热效果，开口设置在散热盖的中部，这样，设置有开口的散热盖为一个环形的结构，硅片则处于该环形结构的开口处，即散热盖环绕硅片。
另外，散热盖设置在硅片的一周围，即散热盖的引脚固定在硅片的一周，将硅片包围起来，这样，散热盖与基板的连接，还可以防止基板发生翘曲。
在第一方面的第五种可能的实现方式中，散热盖沿基板的厚度方向的截面为矩形。散热盖为板状结构，在散热盖的中部开设了开口后，硅片设置在开口，如果不需要再 避让其他部件，此时，环形的散热盖沿基板的厚度方向的截面为矩形，保证散热盖的厚度均匀。
在第一方面的第六种可能的实现方式中，凹槽设置在散热盖的边缘处，散热盖沿基板的厚度方向的截面为阶梯形或“T”字形。
基板上设置的电子元件的位置具有多种不同的位置方案，凹槽需要根据电子元件的位置来设置。对于散热盖来说，凹槽可以是设置在散热盖的边缘，也可以是设置在散热盖的中部，而且凹槽可以是多个小尺寸的凹槽，也可以是长槽等，其中，凹槽设置在散热盖中部的方案会使散热盖的中部的强度降低，散热盖容易损坏，而且不容易生产制造。因此，凹槽设置在散热盖的边缘处。
因此，为了方便散热盖的加工和安装，保证散热盖本身的结构强度，将凹槽尽量设计在靠近开口的位置，这样，当凹槽开设在散热盖的一侧时，散热盖沿基板的厚度方向的截面为阶梯形；当凹槽开设在散热盖的两侧时，散热盖沿基板的厚度方向的截面为“T”字形。
在第一方面的第七种可能的实现方式中，凹槽的底面与侧壁呈钝角。
在第一方面的第八种可能的实现方式中，凹槽的底面与侧壁垂直。呈阶梯形的散热盖的凹槽处避让了电子元件，具体的阶梯形装可以有多种，例如凹槽的底面与侧壁呈钝角或者凹槽的底面与侧壁垂直。
需要说明的是，凹槽的底面与侧壁垂直，是一个近似垂直的状态，受架构和工艺影响，垂直是具有一定误差值的垂直。
在第一方面的第九种可能的实现方式中，散热盖上设有连接孔，连接孔用于将散热盖与设置在硅片远离基板的表面的系统级散热器连接。芯片封装会安装在对应的载体中，实现所需的功能，载体可以为印制电路板(printed circuit board，PCB)等，而芯片封装上一般会设置系统级散热器。通常，系统级散热器会与PCB板连接，在此处，为了方便芯片封装与系统级散热器连接，在散热盖上设有连接孔，可以将系统级散热器直接与散热盖连接，方便装配。
在第一方面的第十种可能的实现方式中，连接孔避开凹槽设置。散热盖上设置了凹槽后，对应凹槽的地方散热盖的厚度较小，此处的结构强度不高。如果在散热盖的凹槽处设置连接孔，会进一步降低散热盖的结构强度。因此，将连接孔避开凹槽设置，保证散热盖的强度。
另外，通过连接孔可以将芯片封装与其他载体方便地连接。
在第一方面的第十一种可能的实现方式中，连接孔为通孔或盲孔。连接孔的形式也有很多种，例如，连接孔可以为通孔或者盲孔，不同形式的孔对应不同的安装要求。例如，连接孔为通孔的方案中，配合设置在通孔内的紧固件的前端可以贯穿散热盖，使得连接更加紧密；但是，可能存在占用空间大，影响结构强度等问题。连接孔为盲孔的方案中，配合设置在盲孔内的紧固件不用贯穿散热盖，紧固件不用额外占用空间，且对散热盖的结构强度影响相对较小；但是，连接的稳固性没有通孔的方案好。
在第一方面的第十二种可能的实现方式中，连接孔内设有螺纹。为了方便连接孔与紧固件的配合，连接孔内可以设置螺纹。
在第一方面的第十三种可能的实现方式中，连接孔为多个，且多个连接孔均匀分 布在散热盖上。
在第一方面的第十四种可能的实现方式中，基板和散热盖粘接。
在第一方面的第十五种可能的实现方式中，基板和散热盖的粘接是通过一个粘接层来粘接的，而粘接层由胶黏剂构成。
第二方面，本申请实施例提供一种电子设备，印制电路板(printed circuit board，PCB)以及如第一方面的任一项中的芯片封装，芯片封装与印制电路板电连接。
本申请实施例的电子设备，由于包括了第一方面的芯片封装，因此，可以解决小封装尺寸下轻薄芯片的散热问题。
本申请实施例的电子设备，可以是服务器、基站或者电脑等。
附图说明
图1为相关技术的芯片封装的示意图；
图2为本申请实施例的芯片封装的散热盖的侧视截面结构示意图；
图3为本申请实施例的芯片封装的散热盖的开口设置在侧边的俯视结构示意图；
图4为本申请实施例的芯片封装的散热盖的开口设置在中部的俯视结构示意图；
图5为本申请实施例的芯片封装的散热盖设置凹槽的侧视截面结构示意图；
图6为本申请实施例的芯片封装的散热盖的凹槽设置在靠近开口处的仰视结构示意图；
图7为本申请实施例的芯片封装的散热盖的截面为阶梯形且凹槽的侧壁和底面呈钝角的结构示意图；
图8为本申请实施例的芯片封装的散热盖的凹槽设置在中部的侧视截面结构示意图；
图9为本申请实施例的芯片封装的散热盖的截面为“T”字形的侧视截面结构示意图；
图10为本申请实施例的芯片封装上设置连接孔的侧视截面结构示意图；
图11为本申请实施例的芯片封装上设置的连接孔内设有螺纹的侧视截面结构示意图。
附图标记：
01-硅片；02-基板；03-散热盖；100-基板；200-硅片；201-微凸块；301-散热盖；302-开口；303-凹槽；304-连接孔；400-粘接层；500-电子元件；600-焊球。
具体实施方式
在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请中，“上”、“下”、“左”以及“右”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。
需要说明的是，本申请实施例中，“示例性的”或者“例如”等词用于表示作例 子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请实施例提供一种的电子设备，可以包括是服务器或基站，以及手机(mobile phone)、平板电脑(pad)、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality AR)终端设备等设备。
电子设备需要电路信号的传输和数据处理等，这就会用到可以处理数据的芯片封装。
为了满足更多应用要求，一方面，芯片封装内部还会集成更多的模块及器件，芯片封装尺寸不断增加；另一方面，随着工艺技术的提升和电子设备的尺寸缩减，芯片封装尺寸要求越来越小。这样，需要考虑如何解决小封装尺寸下轻薄芯片封装的散热问题。
本申请实施例提供一种芯片封装，如图2所示，为芯片封装的剖视图，包括基板100，基板100上设有硅片200，基板100上设有散热盖301。
其中，散热盖301可以解决小封装尺寸下轻薄芯片的散热问题。
参照图2基板100和散热盖301可以通过粘接连接。
具体的，参照图2基板100和散热盖301的粘接是通过一个粘接层400来粘接的，其中，粘接层400可以由胶黏剂构成。
芯片封装会安装在对应的载体上，实现所需的功能，载体可以为PCB(Printed Circuit Board，印制电路板)等，而芯片封装上一般会设置系统级散热器。通常，系统级散热器会与PCB板连接。
芯片封装与PCB板连接的结构可以是球阵列(ball grid array，BGA)的结构，参照图2，芯片封装的基板100远离硅片200的一侧设有焊球600。
在芯片封装中，硅片200与基板100通过连接结构连接，参照图2，该连接结构可以为微凸块(μbump)201的结构。
下面介绍本申请实施例提供的芯片封装的散热盖301是如何解决小封装尺寸下轻薄芯片的散热问题的。
参照图2，本申请实施例提供的芯片封装，包括：
基板100；
硅片200，其中硅片200设置在基板100一侧；
散热盖301，其中散热盖301与基板100连接，散热盖301与硅片200设置在基板100的同一侧，散热盖301沿基板100厚度方向开设有开口302，硅片200设置于开口302中，散热盖301至少部分环绕硅片200，且硅片200的高度小于或等于散热盖301的高度。
本申请实施例提供的芯片封装，参照图2，由于散热盖301沿基板100厚度方向开设有开口302，硅片200设置在开口302中，这样，使得散热盖301的安装可以避开硅片200的位置，硅片200和散热盖301不会层叠在一起，相比相关技术芯片封装的方案，散热盖301没有延伸至硅片200远离基板的一侧的部分，因此不用考虑该部 分的强度和厚度问题。散热盖301的高度只要略微大于甚至等于硅片200的高度，保证能够保护硅片200不被磨损即可，因此，散热盖301可以在厚度上缩减，可以适应小封装尺寸的芯片封装的制造。
同时，散热盖301至少部分环绕硅片200，保证了散热盖301对硅片200的散热作用，因此，可以解决小封装尺寸下轻薄芯片的散热问题。
另外，硅片200的高度小于或等于散热盖301的高度，保证硅片200远离基板100的一侧表面不会高于散热盖301远离基板100的一侧，有利于保护硅片200，且有利于提高散热盖301对硅片200的散热。
需要说明的是，参照图2，硅片200的高度指硅片200远离基板100的一侧表面到基板100的距离，参照图2中所示的m的距离，其中包括硅片200的厚度以及硅片200和基板100之间的微凸块201的厚度等；散热盖301的高度指散热盖301远离基板100的一侧表面到基板100的距离，参照图2中所示的n的距离，其中包括散热盖301的厚度以及散热盖301与基板100连接产生的厚度(例如粘接层400的厚度)。
芯片封装在使用的过程中一般安装在PCB板上，而芯片封装上会连接系统级散热器，以对芯片封装处进行散热。在此情况下，系统级散热器可能会紧贴在芯片封装远离PCB板的表面，即，系统级散热器可能会紧贴芯片封装中的硅片200和散热盖301远离基板100的一侧。在这种情况下，参照图2，如果散热盖301的高度n小于硅片200的高度m，那么系统级散热器就会与硅片200紧贴，可能会磨损或压坏硅片200，因此，参照图2，散热盖301的高度n略微大于硅片200的高度m，保证了能够保护硅片200不被磨损，其中，散热盖301的高度n和硅片200的高度m的差值为b，b的高度不用考虑散热盖301的强度问题，可以无限接近于零或者等于零，以获得芯片封装的厚度较大的缩减。
参照图2，当以基板100的厚度方向为参考，基板100设置硅片200的一侧为上方，另外一侧为下方时，硅片200的高度小于或等于散热盖301的高度，也可以解释为硅片200的上表面低于或平齐于散热盖301的上表面。
沿基板100的厚度方向，开口302的轮廓的投影完全覆盖硅片200。这样可以保证硅片200能够位于开口302内，以使芯片200封装的整体厚度有一定程度的缩减。
开口302的轮廓与硅片200的轮廓一致。即，沿基板100的厚度方向上，开口302的形状与硅片200的形状是一样的。开口302可以与硅片200一样大，此时，硅片200刚好位于开口302内，且硅片200的侧壁与开口302的侧壁贴合；开口302也可以略微比硅片200大一点，此时，硅片200的侧壁和开口302的侧壁之间具有一定的间隙，在硅片200的一周，该间隙的距离可以是均匀的。
因此，开口302的轮廓与硅片200的轮廓一致，这样方便制造和装配，且开口302在保证硅片200可以位于其内的情况下，可以尽量做得很小，既可以使散热盖301的边缘距离硅片200的距离可以很近，又可以在有限的空间内使散热盖301布局的面积更大，进而有利于提高硅片200的散热效果。
需要说明的是，散热盖301至少部分环绕硅片200，指的是，在硅片200的一周围都布局有散热盖301，或者至少部分布局有散热盖301。图2为芯片封装的剖视图，可以看出在硅片200的两侧均布局有散热盖301。
参照图2，散热盖301的厚度方向的截面为矩形。在散热盖301的中部开设了开口302后，硅片200设置在开口302，如果不需要再避让其他部件，此时，环形的散热盖301的厚度方向的截面为矩形，保证散热盖301的厚度均匀。
开口302可以设置在散热盖301的侧边，也可以设置在散热盖301的中部。参照图3和图4，为以散热盖301为矩形为例，芯片封装的散热盖301的俯视图，从散热盖301的厚度方向俯视或者仰视散热盖301时，图3中所示的是开口302开设在散热盖301的侧边，此时如果散热盖301与硅片200装配，硅片200至少有图3中所示的右侧是没有布局散热盖301的，即散热盖301部分环绕硅片200。图4所示的是开口302设置在散热盖301的中部，此时如果散热盖301与硅片200装配，硅片200的一周围都布局有散热盖301，即散热盖301完全环绕硅片200。
相比较来说，开口302设置在散热盖301的中部，使得散热盖301环绕硅片200，使硅片200的周围都布局有散热盖301，方便硅片200的散热。
因此，参照图4，开口302位于散热盖301的中部，在此情况下，散热盖301与硅片200装配后，散热盖301环绕硅片200。
另外，散热盖301设置在硅片200的一周围，即散热盖301的引脚固定在硅片200的一周，将硅片200包围起来，这样，散热盖301与基板100的连接，还可以防止基板100在焊接硅片200的时候发生翘曲。
参照图5，在基板100上除了硅片200可能还会设置其他电子元件500，例如一些被动元件，即，电容、电阻和电感等。而这些电子元件500也设置在基板100上，也会影响芯片封装后的厚度，即，也可能会与散热盖301干涉，影响芯片封装的整体厚度。因此，为了可以让散热盖301避开这些电子元件500，参照图5为芯片封装的散热盖301设置了凹槽303的侧视截面示意图，基板上100设有电子元件500，散热盖301靠近基板100的一侧表面凹陷，形成有凹槽303，电子元件500位于凹槽303中。参照图6，为散热盖301设置了凹槽303的仰视结构示意图，可以从散热盖301靠近基板100的一侧看到阶梯形的散热盖301的具体结构。
呈阶梯形的散热盖301的凹槽303处避让了电子元件500，具体的阶梯形状可以有多种，例如凹槽303的底面与侧壁呈钝角或者凹槽303的底面与侧壁垂直。
示例的，参照图5和图6，凹槽303的底面与侧壁垂直；参照图7，凹槽303的底面与侧壁呈钝角。
需要说明的是，凹槽303的底面与侧壁垂直，是一个近似垂直的状态，受架构和工艺影响，垂直是具有一定误差值的垂直。
基板100上设置的电子元件500的位置具有多种不同的位置方案，凹槽303需要根据电子元件500的位置来设置。对于散热盖301来说，凹槽303可以是设置在散热盖301的边缘或者靠近开口302处，例如图5和图7所示的方案为凹槽303设置在散热盖301靠近开口302处；也可以是设置在散热盖301的其他位置，例如图8所示的方案。而且凹槽303可以是多个小尺寸的凹槽303，也可以是长条装的凹槽303等，其中，凹槽303设置在散热盖301边缘的方案方便生产制造和装配，且对散热盖301的整体强度影响较低。因此，凹槽303设置在散热盖301的边缘处。
为了方便散热盖301的加工和安装，将凹槽303尽量设计在靠近开口302的位置， 这样，在散热盖301的厚度方向的截面为阶梯形或“T”字形，示例的，当凹槽开设在散热盖的一侧时，参照图5和图7，为为凹槽303设置在散热盖301靠近开口302处的方案，散热盖沿基板的厚度方向的截面为阶梯形；参照图9，凹槽303在散热盖301的边缘和靠近开口302处都设置时，散热盖沿基板的厚度方向的截面为“T”字形。
芯片封装会安装在对应的载体上，实现所需的功能，载体可以为PCB(Printed Circuit Board，印制电路板)等，而芯片封装上一般会设置系统级散热器。通常，系统级散热器会与PCB板连接，在此处，为了方便芯片封装与系统级散热器连接，参照图10，散热盖301上设有连接孔304，连接孔304用于将散热盖301与设置在硅片200远离基板100的表面的系统级散热器连接。在散热盖301上设有连接孔，可以将系统级散热器直接与散热盖连接，方便装配。
参照图10，在散热盖301上设置连接孔304时，可以将连接孔304避开凹槽303设置。散热盖301上设置了凹槽303后，对应凹槽303的地方散热盖301的厚度较小，此处的结构强度不高。如果在散热盖301的凹槽303处设置连接孔304，会进一步降低该处的结构强度，进而影响芯片与其他载体的连接。因此，将连接孔304避开凹槽303设置，保证连接孔304的强度。
连接孔304的形式也有很多种，例如，连接孔304可以为通孔；或者，参照图10，连接孔304可以为盲孔，进而不同形式的孔对应不同的安装要求。例如，连接孔304为通孔的方案中，配合设置在通孔内的紧固件的前端可以贯穿散热盖301，使得连接更加紧密；但是，可能存在占用空间大，影响结构强度等问题。连接孔304为盲孔的方案中，配合设置在盲孔内的紧固件不用贯穿散热盖301，紧固件不用额外占用空间，且对散热盖301的结构强度影响相对较小；但是，连接的稳固性没有通孔的方案好。
进一步的，参照图11，为了方便连接孔304与紧固件的配合，连接孔304内可以设置螺纹。
当然，为了使芯片封装的散热盖301与系统级散热器连接更稳固，连接孔304可以为多个，进一步的，多个连接孔304可以均匀分布在散热盖301上。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (14)

  1. 一种芯片封装，其特征在于，包括：
    基板；
    硅片，其中所述硅片设置在所述基板一侧；
    散热盖，其中所述散热盖与所述基板连接，所述散热盖与所述硅片设置于所述基板的同一侧，所述散热盖沿所述基板厚度方向开设有开口，所述硅片设置于所述开口中，所述散热盖至少部分环绕所述硅片，且所述硅片的高度小于或等于所述散热盖的高度。
  2. 根据权利要求1所述的芯片封装，其特征在于，所述基板上设有电子元件，所述散热盖靠近所述基板的一侧表面凹陷，形成有凹槽，所述电子元件位于所述凹槽中。
  3. 根据权利要求1所述的芯片封装，其特征在于，沿所述基板的厚度方向，所述开口的轮廓的投影完全覆盖所述硅片的投影。
  4. 根据权利要求1～3中任一项所述的芯片封装，其特征在于，所述开口的轮廓与所述硅片的轮廓一致。
  5. 根据权利要求1～4中任一项所述的芯片封装，其特征在于，所述开口位于所述散热盖的中部，所述散热盖环绕所述硅片。
  6. 根据权利要求1所述的芯片封装，其特征在于，所述散热盖沿所述基板的厚度方向的截面为矩形。
  7. 根据权利要求2～5中任一项所述的芯片封装，其特征在于，所述凹槽设置在所述散热盖的边缘处，所述散热盖沿所述基板的厚度方向的截面为阶梯形或“T”字形。
  8. 根据权利要求7所述的芯片封装，其特征在于，所述凹槽的底面与侧壁呈钝角。
  9. 根据权利要求7所述的芯片封装，其特征在于，所述凹槽的底面与侧壁垂直。
  10. 根据权利要求7～9中任一项所述的芯片封装，其特征在于，所述散热盖上设有连接孔，所述连接孔用于将所述散热盖与设置在所述硅片远离基板的表面的系统级散热器连接。
  11. 根据权利要求10所述的芯片封装，其特征在于，所述连接孔避开所述凹槽设置。
  12. 根据权利要求10或11所述的芯片封装，其特征在于，所述连接孔为通孔或盲孔。
  13. 根据权利要求1～12中任一项所述的芯片封装，其特征在于，所述基板和所述散热盖粘接。
  14. 一种电子设备，其特征在于，包括印制电路板以及如权利要求1～13中任一项所述的芯片封装，所述芯片封装与所述印制电路板电连接。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050255646A1 (en) * 2003-06-30 2005-11-17 Intel Corporation Heatsink device and method
CN101101880A (zh) * 2006-07-03 2008-01-09 矽品精密工业股份有限公司 散热型封装结构及其制法
CN101335216A (zh) * 2007-06-27 2008-12-31 矽品精密工业股份有限公司 散热型封装结构及其制法
CN102956584A (zh) * 2011-08-18 2013-03-06 新光电气工业株式会社 半导体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050255646A1 (en) * 2003-06-30 2005-11-17 Intel Corporation Heatsink device and method
CN101101880A (zh) * 2006-07-03 2008-01-09 矽品精密工业股份有限公司 散热型封装结构及其制法
CN101335216A (zh) * 2007-06-27 2008-12-31 矽品精密工业股份有限公司 散热型封装结构及其制法
CN102956584A (zh) * 2011-08-18 2013-03-06 新光电气工业株式会社 半导体装置

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