WO2022064314A1 - Display system - Google Patents

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Publication number
WO2022064314A1
WO2022064314A1 PCT/IB2021/058287 IB2021058287W WO2022064314A1 WO 2022064314 A1 WO2022064314 A1 WO 2022064314A1 IB 2021058287 W IB2021058287 W IB 2021058287W WO 2022064314 A1 WO2022064314 A1 WO 2022064314A1
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Prior art keywords
signal
transistor
display
circuit
wiring
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PCT/IB2021/058287
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French (fr)
Japanese (ja)
Inventor
楠紘慈
吉本智史
熱海知昭
川島進
渡邉一徳
Original Assignee
株式会社半導体エネルギー研究所
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Publication of WO2022064314A1 publication Critical patent/WO2022064314A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • One aspect of the present invention relates to a display system.
  • one aspect of the present invention is not limited to the above technical fields.
  • the technical fields of one aspect of the present invention include semiconductor devices, display devices, light emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices (for example, touch sensors, etc.), input / output devices (for example, touch panels, etc.). ), Their driving method, or their manufacturing method can be given as an example.
  • the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics.
  • Display devices liquid crystal display devices, light emission display devices, etc.
  • projection devices lighting devices, electro-optic devices, power storage devices, storage devices, semiconductor circuits, image pickup devices, electronic devices, and the like may be said to be semiconductor devices.
  • they may be said to have semiconductor devices.
  • display devices with a large number of pixels such as full high definition (number of pixels 1920 ⁇ 1080), 4K (number of pixels 3840 ⁇ 2160 or 4096 ⁇ 2160, etc.), and 8K (number of pixels 7680 ⁇ 4320 or 8192 ⁇ 4320, etc.) are popular.
  • full high definition number of pixels 1920 ⁇ 1080
  • 4K number of pixels 3840 ⁇ 2160 or 4096 ⁇ 2160, etc.
  • 8K number of pixels 7680 ⁇ 4320 or 8192 ⁇ 4320, etc.
  • a flat panel display represented by a liquid crystal display and an organic EL display is widely used.
  • Silicon is mainly used as the semiconductor material of the transistors constituting these display devices, but in recent years, a technique of using a transistor using a metal oxide as a pixel of the display device has also been developed.
  • Patent Document 1 discloses a technique of using amorphous silicon as a semiconductor material for a transistor.
  • Patent Document 2 and Patent Document 3 disclose a technique of using a metal oxide as a semiconductor material of a transistor.
  • the number of pixels of the display device increases, the number of transistors and display elements of the display device increases, so that the variation in the characteristics of the transistor and the variation in the characteristics of the display element become remarkable.
  • One aspect of the present invention is to provide a display system with high display quality.
  • One aspect of the present invention is to provide a display system having low power consumption.
  • One aspect of the present invention is to provide a display system having a high resolution.
  • One of the problems of one aspect of the present invention is to provide a display system in which display unevenness is reduced.
  • One aspect of the present invention is to provide a display system having a large display area.
  • One aspect of the present invention is to provide a display system that can operate at a high frame frequency.
  • One aspect of the present invention is a display system having a processing unit, a display unit, and a storage unit.
  • the storage unit has correction data.
  • the first image signal and correction data are supplied to the processing unit.
  • the processing unit has a function of generating a second image signal by using the first image signal.
  • the processing unit has a function of generating a correction signal based on the correction data.
  • the display unit has pixels, and the pixels have a display element and a storage circuit. Further, a second image signal and a correction signal are supplied to the pixels.
  • the storage circuit has a function of holding a correction signal.
  • the storage unit includes a capacitive element having a ferroelectric layer and a transistor electrically connected to the capacitive element.
  • another aspect of the present invention is a display system having a processing unit, a display unit, and a storage unit.
  • the storage unit has correction data.
  • the first image signal and correction data are supplied to the processing unit.
  • the processing unit has a function of generating a second image signal by using the first image signal.
  • the processing unit has a function of generating a correction signal by using the first image signal and the correction data.
  • the display unit has pixels, and the pixels have a display element and a storage circuit. A second image signal and a correction signal are supplied to the pixels.
  • the storage circuit has a function of holding a correction signal.
  • the storage unit includes a capacitive element having a ferroelectric layer and a transistor electrically connected to the capacitive element.
  • another aspect of the present invention is a display system having a processing unit, a display unit, and a storage unit.
  • the storage unit has correction data.
  • the display unit has a first circuit and pixels.
  • the first circuit has a function of generating a first signal.
  • a first image signal, a first signal, and correction data are supplied to the processing unit.
  • the processing unit has a function of generating a second image signal by using the first image signal.
  • the processing unit has a function of generating a correction signal by using the first signal and the correction data.
  • the pixel has a display element and a storage circuit. A second image signal and a correction signal are supplied to the pixels.
  • the storage circuit has a function of holding a correction signal.
  • the storage unit includes a capacitive element having a ferroelectric layer and a transistor electrically connected to the capacitive element.
  • the processing unit generates one or both of the second image signal and the correction signal by using the neural network.
  • the processing unit preferably has a neural network circuit.
  • the ferroelectric layer preferably has an oxide containing one or both of hafnium and zirconium.
  • the concentration of at least one of hydrogen, hydrocarbon, and carbon contained in the ferroelectric layer is 5 ⁇ 10 20 atoms / cm 3 or less, or 1 ⁇ 10 20 atoms in SIMS analysis. It is preferably / cm 3 or less.
  • the transistor has silicon in the channel forming region.
  • the transistor preferably has an oxide semiconductor in the channel forming region.
  • a display system with high resolution can be provided. According to one aspect of the present invention, it is possible to provide a display system having high display quality. According to one aspect of the present invention, it is possible to provide a display system having low power consumption. According to one aspect of the present invention, it is possible to provide a display system in which display unevenness is reduced. According to one aspect of the present invention, it is possible to provide a display system having a large display area. According to one aspect of the present invention, it is possible to provide a display system capable of operating at a high frame frequency.
  • FIG. 1A and 1B are diagrams showing an example of a display system.
  • 2A and 2B are diagrams illustrating up-conversion.
  • FIG. 3 is a diagram illustrating a comparative example of up-conversion.
  • 4A, 4B, and 4C are diagrams showing an example of a display system.
  • 5A, 5B, 5C, 5D, 5E, and 5F are diagrams showing an example of a display system.
  • FIG. 6 is a block diagram showing an example of the display unit.
  • 7A, 7C, and 7D are circuit diagrams of the display device.
  • FIG. 7B is a timing chart.
  • 8A and 8B are diagrams showing an example of a display system.
  • FIG. 9 is a block diagram showing an example of the display unit.
  • FIG. 9 is a block diagram showing an example of the display unit.
  • FIG. 10A is a block diagram showing an example of a storage device.
  • FIG. 10B is a perspective view showing an example of a storage device.
  • FIG. 11A is a circuit diagram showing an example of a memory cell.
  • FIG. 11B is a graph showing an example of the hysteresis characteristics of the ferroelectric layer.
  • FIG. 12 is a timing chart showing an example of a memory cell driving method.
  • 13A1, 13B1 and 13C1 are circuit diagrams showing an example of a ferroelectric memory.
  • 13A2, 13B2, and 13C2 to 13C4 are cross-sectional views showing an example of a ferroelectric memory.
  • 14A to 14C are cross-sectional views showing an example of a method for manufacturing a capacitive element.
  • FIG. 10A is a block diagram showing an example of a storage device.
  • FIG. 10B is a perspective view showing an example of a storage device.
  • FIG. 11A is a circuit diagram showing an example of
  • FIG. 15 is a model diagram illustrating the crystal structure of hafnium oxide.
  • FIG. 16 is a diagram showing an example of a film formation sequence of a metal oxide film.
  • FIG. 17A is a cross-sectional view showing an example of a metal oxide film manufacturing apparatus.
  • FIG. 17B is a model diagram of the crystal structure of HfZrOX .
  • 18A and 18B are diagrams illustrating a configuration example of a neural network.
  • FIG. 19 is a diagram illustrating a configuration example of a semiconductor device.
  • FIG. 20 is a diagram illustrating a configuration example of a memory cell.
  • 21A, 21B, 21C, 21D, and 21E are diagrams showing an example of pixels.
  • FIG. 22 is a diagram showing an example of a display device.
  • FIG. 23 is a diagram showing an example of a display device.
  • 24A, 24B, 24C, 24D, 24E, and 24F are diagrams showing an example of an electronic device.
  • membrane and the word “layer” can be interchanged with each other in some cases or depending on the situation.
  • conductive layer can be changed to the term “conductive film”.
  • insulating film can be changed to the term “insulating layer”.
  • the display system of the present embodiment has a function of generating a correction signal, a function of generating an image signal using data received from the outside, and a function of displaying an image using the correction signal and the image signal. , Have.
  • the display system of the present embodiment has a processing unit and a display unit.
  • the processing unit has a function of generating a correction signal and a function of generating an image signal using data received from the outside.
  • the display unit includes a display element and a storage circuit.
  • the storage circuit has a function of holding a correction signal.
  • the storage circuit has a function of adding a correction signal to the image signal.
  • the correction signal is added to the image signal by capacitive coupling and supplied to the display element. Therefore, the display unit can display an image using the correction signal and the image signal.
  • the display system can perform various image processing on the data received from the outside. However, especially in the case of up-converting the resolution, the amount of calculation performed by the processing unit becomes enormous. Therefore, the display system of one aspect of the present invention generates a correction signal and an image signal in the processing unit.
  • the image signal generated by performing image processing on the data received from the outside is a signal including data having the same resolution as the data received from the outside. Then, the image is up-converted by adding the separately generated correction signal to the image signal.
  • it is possible to reduce the amount of calculation in the processing unit reduce the power consumption, reduce the circuit scale, suppress the display delay, and the like.
  • the processing unit may generate a correction signal in real time using data received from the outside, or may read the correction data stored in the recording medium and generate a correction signal based on the correction data. good. By supplying the correction signal based on the correction data to the display unit regardless of the data received from the outside, it is possible to reduce the amount of calculation in the processing unit.
  • the correction signal can be used for purposes other than up-conversion.
  • the correction signal can be used to correct display unevenness caused by variations in the characteristics of the transistors of the pixels. In this way, by using the correction signal, it is possible to reduce the load on the processing unit related to the generation of the image signal.
  • the display system of one aspect of the present invention has a storage unit in addition to the processing unit.
  • the storage unit has a function of holding various data handled by the display system.
  • a ferroelectric layer containing one or both of hafnium and zirconium in the dielectric layer can be used as a storage unit possessed by the processing unit.
  • the storage unit can have both high data retention characteristics and high rewrite resistance. As a result, high-speed processing is possible and a highly reliable display system can be realized.
  • FIG. 1A shows a block diagram of the display system 100A.
  • the display system 100A has a control unit 151, a storage unit 152, a processing unit 153, an input / output unit 154, a communication unit 155, and a display unit 156.
  • it may have a touch sensor, a touch sensor control unit, a battery, a battery controller, a power receiving unit, an antenna, an image pickup unit, a vibration unit, and the like.
  • the control unit 151, the storage unit 152, the processing unit 153, the input / output unit 154, the communication unit 155, the display unit 156, and the like are electrically connected to each other via the bus line 157.
  • the communication unit 155 supplies the image signal S1 based on the data received from the outside to the processing unit 153.
  • the processing unit 153 performs image processing on the data included in the image signal S1 to generate the image signal S2.
  • the image signal S2 is supplied from the processing unit 153 to the display unit 156.
  • the processing unit 153 has a function of generating an image signal S2 by using artificial intelligence (AI: Artificial Intelligence). Thereby, the display quality in the display unit 156 can be improved.
  • AI Artificial Intelligence
  • Artificial intelligence is a computer that imitates human intelligence.
  • an artificial neural network (ANN: Artificial Neural Network) can be used.
  • An artificial neural network is a circuit that imitates a neural network composed of neurons and synapses, and an artificial neural network is a kind of artificial intelligence.
  • neural network When the term "neural network” is used in the present specification and the like, it particularly refers to an artificial neural network.
  • FIG. 1A and 1B show an example in which the processing unit 153 has a neural network 159.
  • Examples of image processing performed on the data included in the image signal S1 include noise reduction processing, gradation conversion processing, color tone correction processing, and luminance correction processing.
  • the color tone correction process and the luminance correction process can be performed by using gamma correction or the like.
  • the processing unit 153 may have a function of executing interpolation processing between frames accompanying the up-conversion of the frame frequency.
  • Noise reduction processing includes removal of various noises such as mosquito noise that occurs around contours such as characters, block noise that occurs in high-speed moving images, random noise that causes flicker, and dot noise that occurs due to resolution up-conversion. ..
  • the gradation conversion process is a process of converting the gradation indicated by the image data of the image signal S1 into the gradation corresponding to the output characteristics of the display unit 156. For example, when increasing the number of gradations, it is possible to perform a process of smoothing the histogram by interpolating and assigning gradation values corresponding to each pixel to an image input with a small number of gradations. In addition, high dynamic range (HDR) processing that widens the dynamic range is also included in the gradation conversion processing.
  • HDR high dynamic range
  • the color tone correction process is a process for correcting the color tone of an image.
  • the luminance correction process is a process for correcting the brightness (luminance contrast) of an image. For example, the brightness or color tone of the image displayed on the display unit 156 is corrected so as to be optimum according to the type, brightness, color purity, and the like of the space in which the display unit 156 is provided.
  • the interpolation process between frames is a process of generating an image of a frame (interpolation frame) that does not originally exist when the frame frequency of the image to be displayed is increased.
  • an image of an interpolated frame to be inserted between two images is generated from the difference between two images.
  • the frame frequency of the image data is 60 Hz
  • the frame frequency of the image signal output to the display unit 156 is doubled to 120 Hz, quadrupled to 240 Hz, or 8 by generating a plurality of interpolated frames. It can be doubled to 480 Hz or the like.
  • correction data W1 is supplied to the processing unit 153 from the storage unit 152.
  • the processing unit 153 generates a correction signal W2 based on the correction data W1.
  • the correction signal W2 is supplied from the processing unit 153 to the display unit 156.
  • the correction data W1 is preferably data generated in advance using artificial intelligence.
  • the image signal S2 When the image signal S2 is generated without up-converting the image signal S1 and the correction signal W2 is not used, when the low resolution image data is to be displayed on the high resolution display unit 156, the same image is displayed on a plurality of pixels.
  • the signal will be supplied.
  • the number of pixels of the 8K4K display device is four times the number of pixels of the 4K2K display device (3840 ⁇ 2160). That is, when the image data of the 4K2K display device is simply displayed on the 8K4K display device, the image signal supplied to one pixel of the 4K2K display device is supplied to the four pixels of the 8K4K display device. Become.
  • FIG. 3 is a diagram illustrating an image displayed in four pixels in the horizontal and vertical directions in the comparative example.
  • all four pixels display an image using the image signal S1
  • the image signals S1a to S1c are supplied to each pixel to improve the resolution. can do.
  • the image signals S2a to S2c are supplied to each pixel.
  • a correction signal can be added to the image signal. Therefore, as shown in FIG. 2A, the image signal S1 is subjected to image processing without up-converting the image signal S1 to generate the image signal S2. As a result, the amount of calculation for image processing can be reduced and the power consumption can be reduced. Then, the same image signal S2 is supplied to the four pixels.
  • the correction signals W2a to W2c are supplied to each pixel.
  • the method for generating the correction signals W2a to W2c is not limited.
  • the correction data W1 stored in the storage unit 152 may be read out to generate a correction signal W2 based on the correction data W1.
  • the correction signal W2 may be generated in real time using the image signal S1 (see FIG. 4B and the like).
  • the correction signal W2 is generated in real time, the quality of up-conversion can be improved, which is preferable. Even in this case, the amount of calculation in the generation of the image signal S2 can be reduced.
  • each correction signal is added to the image signal S2, and new image signals S2a to S2c are generated.
  • the pixels can display the original image signal S1 up-converted.
  • FIG. 4A shows a block diagram of the display system 100B.
  • the processing unit 153 may have a plurality of neural networks.
  • the processing unit 153 has a neural network 159a and a neural network 159b.
  • the communication unit 155 can supply the image signal S1 based on the data received from the outside to the processing unit 153.
  • the processing unit 153 performs image processing on the data included in the image signal S1 using the neural network 159a, and generates the image signal S2. Further, the processing unit 153 generates the correction signal W2 by using the data included in the neural network 159b and the image signal S1.
  • the image signal S2 and the correction signal W2 are supplied from the processing unit 153 to the display unit 156.
  • the display system 100B uses the image signal S1 to generate the correction signal W2, higher quality up-conversion can be realized as compared with the display system 100A.
  • a highly accurate correction signal W2 can be generated by using a deep neural network in which a huge number of images are learned as teacher data.
  • the correction signal W2 can be used for interpolation processing between pixels due to resolution up-conversion.
  • the interpolation process between pixels is a process of interpolating data that does not originally exist when the resolution is up-converted. For example, refer to the color data of the pixels around the pixel as the color data of the pixel to be newly interpolated (for example, the gradation value corresponding to each color of red (R), green (G), and blue (B)). Then, the data is interpolated so that the data is a color that is an intermediate color between them.
  • the processing unit 153 performs image processing on the image signal S1 without up-converting the image signal S1 to generate the image signal S2. This makes it possible to reduce the amount of image processing calculation even when the correction signal W2 is generated in real time. Further, by generating the image signal S2 and the correction signal W2 in parallel, the display delay can be suppressed.
  • FIG. 4B shows an example in which only the image signal S1 is supplied to the neural network 159b.
  • FIG. 4C shows an example in which the correction data W1 is supplied to the neural network 159b in addition to the image signal S1.
  • the neural network 159 may be used only for the generation of the image signal S2, or as shown in FIG. 5B.
  • the neural network 159 may be used only for the generation of the correction signal W2.
  • the signal generation without using the neural network 159 may be performed by another method using artificial intelligence, or may be performed by a method not using artificial intelligence. As shown in FIGS. 5C and 5D, the same applies to the case where the correction signal W2 is generated by using the image signal S1 and the correction data W1.
  • one neural network 159 may be used to simultaneously generate the image signal S2 and the correction signal W2. At this time, both the data of the image signal S2 and the data of the correction signal W2 are output from the output layer of the neural network.
  • the data of the image signal S1 is input to the input layer of the neural network in FIG. 5E.
  • Both the data of the image signal S1 and the correction data W1 are input to the input layer of the neural network in FIG. 5F.
  • the resolution of the data contained in the image signal is not changed by image processing, and a new image signal is generated by the pixel to which the correction signal is supplied in addition to the image signal, thereby increasing the resolution of the image.
  • Reduction of calculation amount, reduction of power consumption, reduction of circuit scale, suppression of display delay, and the like can be realized. Therefore, it is possible to realize a display system having high resolution or high display quality. Furthermore, it is possible to increase the size of the display system and reduce the power consumption.
  • the operation for generating a new image signal with pixels can be performed in a small number of steps, it can be realized even in a display device having a large number of pixels and a short horizontal period. can do. Therefore, it is possible to realize a display system that can operate at a high frame frequency.
  • the display system 100A will be described as an example, but the same configuration can be applied to the display system 100B.
  • Control unit 151 has a function of controlling the operation of the entire display system 100A.
  • the control unit 151 controls the operations of the storage unit 152, the processing unit 153, the input / output unit 154, the communication unit 155, the display unit 156, and the like.
  • the storage unit 152 it is preferable to apply a storage device having a ferroelectric memory as a storage element. Since the ferroelectric memory can realize an element configuration consisting of a small number of elements, it is possible to realize a storage device having a large storage capacity by miniaturizing and increasing the density of the ferroelectric memory.
  • the ferroelectric memory is non-volatile and can retain data for a long period of time.
  • the frequency of refreshing can be reduced, so that the power consumption of the display system according to one aspect of the present invention can be reduced.
  • the ferroelectric memory included in the display system of one aspect of the present invention includes, for example, a capacitive element having a ferroelectric layer and a transistor electrically connected to the capacitive element.
  • FeRAM Feoelectric Random Access Memory
  • FeRAM Feoelectric Random Access Memory
  • a capacitive element ferroelectric capacitor
  • the FeRAM has features such as miniaturization, high-speed operation, and high rewrite resistance.
  • the FeRAM has a 1-transistor, 1-capacitor type element configuration similar to a DRAM (Dynamic RAM), and can be increased in density. By miniaturizing and increasing the density of FeRAM, it is possible to realize a storage device having a large storage capacity.
  • the ferroelectric layer of the ferroelectric memory preferably has an oxide having one or both of hafnium and zirconium.
  • the concentration of at least one of hydrogen, hydrocarbon, and carbon contained in the ferroelectric layer is preferably 5 ⁇ 10 20 atoms / cm 3 or less in SIMS analysis, and is preferably 1 ⁇ 10 20 atoms / cm 3 or less. Is more preferable.
  • the ferroelectric layer it is preferable to use a chlorine-based material that does not contain hydrocarbons as a precursor. This makes it possible to reduce the concentrations of hydrogen, hydrocarbons, and carbon contained in the ferroelectric layer, respectively. Further, the ferroelectric layer may contain chlorine.
  • a transistor having an oxide semiconductor in the channel forming region can be used. Since the OS transistor has a high withstand voltage, a high voltage can be applied even if the transistor is miniaturized.
  • a transistor (Si transistor) having silicon in the channel forming region can be used for the ferroelectric memory such as FeRAM and FeFET. Since the Si transistor has a small variation in electrical characteristics, it is possible to realize a storage device having high reliability and a small variation in electrical characteristics between cells.
  • the semiconductor device of one aspect of the present invention can stop a circuit that does not need to be operated by power gating. This makes it possible to reduce the power consumption of the semiconductor device. In power gating, since the power supply is stopped, the effect of eliminating the power during standby is achieved. Specifically, power gating is possible on one or both of the CPU and the GPU.
  • the display system of one aspect of the present invention is a FeRAM, a FeFET having one transistor, and at least one of an FTJ (Ferroelectric Tunnel Junction) memory having at least one ferroelectric capacitor or a tunnel junction element.
  • FTJ Ferroelectric Tunnel Junction
  • the ferroelectric field effect transistor is a non-volatile storage element (ferroelectric memory) manufactured by using a ferroelectric layer for at least a part (for example, a gate insulating layer) of the insulating layer of the transistor.
  • FeFET has features such as low power consumption, high-speed operation, and non-destructive readout. Further, the FeFET has a one-transistor type element configuration, and high density can be achieved. This makes it possible to realize a storage device having a large storage capacity.
  • the ferroelectric tunnel junction (FTJ) memory is a non-volatile storage element (ferroelectric memory) using a tunnel junction, which is manufactured by using a capacitive element (ferroelectric capacitor) having a ferroelectric layer.
  • the FTJ memory has features such as a small occupied area, high-speed operation, and non-destructive reading. Further, the FTJ memory utilizes a tunnel junction and has an element configuration having a function as a capacitance and a function as a diode, and can be increased in density. This makes it possible to realize a storage device having a large storage capacity. It can be said that the FTJ memory has a tunnel junction element having a ferroelectric layer.
  • the ferroelectric memory which is a non-volatile storage element, not only to the storage unit 152 but also to all the storage devices of the display system. Power consumption can be dramatically reduced by using ferroelectric memory for all or more than half of the storage elements of the display system.
  • the display system of the present embodiment may have one or both of other volatile storage elements and non-volatile storage elements. Further, in the display system of the present embodiment, it is preferable that the memory configured by the volatile storage element such as the DRAM or the cache memory is replaced with the ferroelectric memory.
  • a storage device to which a non-volatile storage element such as a flash memory, an MRAM (Magnetoristive Random Access Memory), a PRAM (Phase change RAM), or a ReRAM (Resistive RAM) is applied, or a DRAM, or A storage device or the like to which a volatile storage element such as SRAM (Static RAM) is applied may be used.
  • a recording media drive such as a hard disk drive (HDD: Hard Disk Drive) or a solid state drive (SSD: Solid State Drive) may be used.
  • a storage device such as an HDD or SSD that can be attached / detached by a connector via an input / output unit 154, or a media drive of a recording medium such as a flash memory, a Blu-ray disc, or a DVD can also be used as the storage unit 152.
  • the storage unit 152 may not be built in the display system 100A, and a storage device placed outside the display system 100A may be used as the storage unit 152. In that case, the storage unit 152 is connected to the display system 100A via the input / output unit 154.
  • the configuration may be such that data is exchanged by wireless communication via the communication unit 155.
  • the storage unit 152 stores the program, algorithm, weighting coefficient, etc. used in the processing unit 153. Further, the storage unit 152 stores video information and the like to be displayed on the display unit 156. Further, the correction data W1 may be stored in the storage unit 152.
  • the processing unit 153 has a function of performing an operation related to the operation of the entire display system 100A, and for example, a central processing unit (CPU: Central Processing Unit) or the like can be used.
  • CPU Central Processing Unit
  • processing unit 153 in addition to the CPU, other microprocessors such as a DSP (Digital Signal Processor) and a GPU (Graphics Processing Unit) can be used alone or in combination. Further, these microprocessors may be realized by a PLD (Programmable Logic Device) such as FPGA (Field Programmable Gate Array) or FPGA (Field Programmable Analog Array).
  • PLD Programmable Logic Device
  • FPGA Field Programmable Gate Array
  • FPGA Field Programmable Analog Array
  • the processing unit 153 has a neural network 159 (also referred to as NN159 in the figure).
  • the neural network 159 may be configured by software.
  • the processing unit 153 performs various data processing, program control, and the like by interpreting and executing instructions from various programs by the processor.
  • the program that can be executed by the processor may be stored in the memory area of the processor or may be stored in the storage unit 152.
  • a cache memory can be used as the memory area of the processor.
  • SRAM may be used as the cache memory, but it is particularly preferable to use a storage element to which the above-mentioned ferroelectric substance is applied. Since the storage element is a non-volatile storage element, the power required for data retention can be significantly reduced as compared with the case where SRAM is used. Therefore, not only the power consumption of the display system can be reduced, but also the heat generation of the display system can be suppressed. For example, it is possible to eliminate one or more of the heat sink and the cooling fan for cooling the processor of the system and the like.
  • the processing unit 153 may have a main memory.
  • the main memory can be configured to include a volatile memory such as a RAM (Random Access Memory) or a non-volatile memory such as a ROM (Read Only Memory).
  • a volatile memory such as a RAM (Random Access Memory) or a non-volatile memory such as a ROM (Read Only Memory).
  • the RAM provided in the main memory for example, FeRAM or DRAM is used, and the memory space is virtually allocated and used as the work space of the processing unit 153.
  • the operating system, application program, program module, program data, etc. stored in the storage unit 152 are loaded into the RAM for execution. These data, programs, or program modules loaded into the RAM are directly accessed and operated by the processing unit 153.
  • the ROM can store BIOS (Basic Input / Output System) or firmware that does not require rewriting.
  • BIOS Basic Input / Output System
  • a mask ROM an OTPROM (One Time Program Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), or the like can be used.
  • EPROM include UV-EPROM (Ultra-Violet Erasable Project Only Memory), EEPROM (Electrically Erasable Erasable Memory), etc., which enables erasure of stored data by irradiation with ultraviolet rays.
  • a non-volatile storage element may be used as the ROM.
  • the above-mentioned FeRAM has extremely high data retention characteristics, and therefore can be applied to ROM.
  • a calculation circuit composed of a transistor containing silicon or an oxide semiconductor in the channel forming region is suitable.
  • an arithmetic circuit composed of a transistor containing silicon (amorphous silicon, low temperature polysilicon, or single crystal silicon) or an oxide semiconductor in the channel forming region is suitable.
  • a transistor containing an oxide semiconductor is suitable as the transistor constituting the product-sum calculation circuit.
  • Examples of the input / output unit 154 include an external port to which an input component can be connected.
  • the input / output unit 154 is electrically connected to the processing unit 153 via the bus line 157.
  • the external port can be configured to be connected to an external device such as a computer or a printer via a cable, for example.
  • an external device such as a computer or a printer via a cable, for example.
  • a USB terminal or the like.
  • the external port it may have a LAN (Local Area Network) connection terminal, a digital broadcast reception terminal, a terminal for connecting an AC adapter, and the like.
  • a transceiver for optical communication using infrared rays, visible light, ultraviolet rays, or the like may be provided as well as wired.
  • the communication unit 155 controls a control signal for connecting the display system 100A to the computer network in response to a command from the control unit 151, and transmits the signal to the computer network.
  • An antenna may be provided in the display system 100A, and communication may be performed via the antenna.
  • the display system 100A can be connected to a computer network for communication. Further, when a plurality of different communication methods are used, a plurality of antennas may be provided depending on the communication method.
  • a high frequency circuit may be provided in the communication unit 155 to transmit and receive RF signals.
  • the high frequency circuit is a circuit for mutually converting an electromagnetic signal and an electric signal in the frequency band specified by the legislation of each country and wirelessly communicating with other communication devices using the electromagnetic signal. A few tens of kHz to a few tens of GHz are generally used as a practical frequency band.
  • the high-frequency circuit has a circuit unit corresponding to a plurality of frequency bands, and the circuit unit can be configured to include an amplifier (amplifier), a mixer, a filter, a DSP, an RF transceiver, and the like.
  • the communication unit 155 may have a function of connecting the display system 100A to the telephone line.
  • the communication unit 155 controls a connection signal for connecting the display system 100A to the telephone line in response to a command from the control unit 151, and transmits the signal to the telephone line. do.
  • the communication unit 155 may have a tuner that generates an image signal to be output to the display unit 156 from the received broadcast radio wave.
  • the tuner can be configured to include a demodulation circuit, an AD conversion circuit (analog-digital conversion circuit), a decoder circuit, and the like.
  • the demodulation circuit has a function of demodulating the input signal.
  • the AD conversion circuit has a function of converting a demodulated analog signal into a digital signal.
  • the decoder circuit has a function of decoding video data included in a digital signal and generating an image signal.
  • the decoder may be configured to have a dividing circuit and a plurality of processors.
  • the division circuit has a function of spatially and temporally dividing the input video data and outputting it to each processor.
  • the plurality of processors decode the input video data and generate an image signal.
  • the decoder circuit for decoding the compressed data has a processor having extremely high-speed processing capability.
  • the decoder circuit is preferably configured to include a plurality of processors capable of parallel processing of 4 or more, preferably 8 or more, and more preferably 16 or more. Further, the decoder may have a circuit for separating a video signal included in the input signal and other signals (character information, program information, authentication information, etc.).
  • broadcast radio waves that can be received by the communication unit 155 include terrestrial waves and radio waves transmitted from satellites. Further, as broadcast radio waves that can be received by the communication unit 155, there are analog broadcasting, digital broadcasting, and the like, and there are video and audio, or audio-only broadcasting. For example, it is possible to receive broadcast radio waves transmitted in a specific frequency band within the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz). Further, for example, by using a plurality of data received in a plurality of frequency bands, the transfer rate can be increased and more information can be obtained. As a result, an image having a resolution exceeding full high-definition can be displayed on the display unit 156. For example, it is possible to display an image having a resolution of 4K, 8K, 16K, or higher.
  • the tuner may be configured to generate an image signal by using the broadcast data transmitted by the data transmission technology via the computer network. At this time, if the received signal is a digital signal, the tuner does not have to have a demodulation circuit and an AD conversion circuit.
  • the image signal acquired by the communication unit 155 can be stored in the storage unit 152.
  • the input / output unit 154 or the communication unit 155 may have a function of acquiring correction data.
  • the correction data generated by the external device can be acquired and stored in the storage unit 152.
  • the correction data of the display system can be updated at any time to improve the display quality.
  • Display unit 156 Various display devices and display elements can be applied to the display unit 156.
  • a light emitting display device, a liquid crystal display device, or the like can be used.
  • an EL (Electroluminescence) element organic EL element, an inorganic EL element, or an EL element containing an organic substance and an inorganic substance
  • an LED Light Emitting Diode
  • the liquid crystal display device can use a liquid crystal element as the display element.
  • FIG. 6 shows an example of a block diagram of the display unit 156.
  • the display unit 156 has a plurality of pixels 10, a scanning line driving circuit 12, and a signal line driving circuit 13.
  • the plurality of pixels 10 are provided in a matrix.
  • a shift register circuit For the scanning line drive circuit 12 and the signal line drive circuit 13, for example, a shift register circuit can be used.
  • the image signal S2 and the correction signal W2 are supplied from the processing unit 153 to the signal line drive circuit 13.
  • the processing unit 153 uses the supplied image signal S1 (and correction data W1) to generate the image signal S2 and the correction signal W2.
  • FIG. 7A shows a circuit diagram of the pixel 10.
  • the pixel 10 has a transistor M1, a transistor M2, a capacitance C1, and a circuit 41. Further, wiring SL1, wiring SL2, wiring GL1, and wiring GL2 are connected to the pixel 10.
  • the gate is connected to the wiring GL1, one of the source and drain is connected to the wiring SL1, and the other is connected to one electrode of the capacitance C1.
  • the transistor M2 connects the gate to the wiring GL2, one of the source and the drain to the wiring SL2, the other to the other electrode of the capacitance C1, and the circuit 41, respectively.
  • the circuit 41 is a circuit including at least one display element.
  • Various elements can be used as the display element, but typically an organic EL element, a light emitting element such as an LED, a liquid crystal element, a MEMS (Micro Electro Mechanical Systems) element, or the like can be applied.
  • LEDs there are macro LEDs (also called giant LEDs), mini LEDs, micro LEDs, etc., from large ones.
  • an LED chip having a side size of more than 1 mm is called a macro LED
  • an LED chip larger than 100 ⁇ m and 1 mm or less is called a mini LED
  • an LED chip having a side size of 100 ⁇ m or less is called a micro LED.
  • a micro LED it is particularly preferable to use a micro LED as the LED element applied to the pixel. By using a micro LED, an extremely high-definition display device can be realized.
  • the node connecting the transistor M1 and the capacitance C1 is referred to as a node N1
  • the node connecting the transistor M2 and the circuit 41 is referred to as a node N2.
  • the pixel 10 can hold the potential of the node N1 by turning off the transistor M1. Further, by turning off the transistor M2, the potential of the node N2 can be maintained. Further, by writing a predetermined potential to the node N1 via the transistor M1 with the transistor M2 turned off, the potential of the node N2 is corresponding to the displacement of the potential of the node N1 by the capacitive coupling via the capacitance C1. Can be changed.
  • an oxide semiconductor is applied to one or both of the transistor M1 and the transistor M2, and a transistor having a significantly low leakage current (off current) in the off state can be applied. Therefore, the potential of the node N1 or the node N2 can be maintained for a long period of time due to the extremely low off current.
  • a transistor to which a semiconductor such as silicon is applied may be used.
  • FIG. 7B is a timing chart relating to the operation of the pixel 10.
  • the effects of various resistances such as wiring resistance, parasitic capacitance such as transistors or wiring, and threshold voltage of transistors are not considered here.
  • one frame period is divided into a period T1 and a period T2.
  • the period T1 is a period for writing the potential to the node N2
  • the period T2 is a period for writing the potential to the node N1.
  • the potential V ref is given to the node N1 from the wiring SL1 via the transistor M1. Further, the node N2 is given a first data potential V w from the wiring SL2 via the transistor M2. Therefore, the potential difference V w ⁇ V ref is held in the capacitance C1.
  • the wiring GL1 is given a potential for turning on the transistor M1, and the wiring GL2 is given a potential for turning off the transistor M2. Further, a second data potential V data is supplied to the wiring SL1.
  • a predetermined constant potential may be applied to the wiring SL2, or the wiring SL2 may be in a floating state.
  • a second data potential V data is given to the node N1 from the wiring SL1 via the transistor M1.
  • the potential of the node N2 changes by the potential dV according to the second data potential V data . That is, the potential obtained by adding the first data potential V w and the potential dV is input to the circuit 41.
  • FIG. 7B shows that the potential dV is a positive value, it may be a negative value. That is, the second data potential V data may be lower than the potential V ref .
  • the potential dV is generally determined by the capacitance value of the capacitance C1 and the capacitance value of the circuit 41.
  • the potential dV becomes a potential close to the second data potential V data .
  • the pixel 10 can generate a potential to be supplied to the circuit 41 including the display element by combining two types of data signals, it is possible to correct the gradation in the pixel 10.
  • the pixel 10 can also generate a potential exceeding the maximum potential that can be supplied by the source driver connected to the wiring SL1 and the wiring SL2.
  • HDR high dynamic range
  • a liquid crystal element is used, overdrive drive and the like can be realized.
  • the pixel 10LC shown in FIG. 7C has a circuit 41LC.
  • the circuit 41LC has a liquid crystal element LC and a capacitance C2.
  • one electrode is connected to one electrode of the node N2 and the capacitance C2, and the other electrode is connected to the wiring to which the potential V com2 is given.
  • the capacitance C2 is connected to a wiring in which the other electrode is given the potential V com1 .
  • Capacity C2 functions as a holding capacity.
  • the capacity C2 can be omitted if it is unnecessary.
  • the pixel 10LC can supply a high voltage to the liquid crystal element LC, for example, it is possible to realize a high-speed display by overdrive driving, or to apply a liquid crystal material having a high driving voltage. Further, by supplying the correction signal to the wiring SL1 or the wiring SL2, the gradation can be corrected according to the operating temperature, the deterioration state of the liquid crystal element LC, and the like.
  • the pixel 10EL shown in FIG. 7D has a circuit 41EL.
  • the circuit 41EL has a light emitting element EL, a transistor M3, and a capacitance C2.
  • the gate is connected to one electrode of the node N2 and the capacitance C2, one of the source and the drain is connected to the wiring to which the potential VH is given, and the other is connected to one electrode of the light emitting element EL.
  • the capacitance C2 connects the other electrode to a wiring to which the potential V com is given.
  • the light emitting element EL is connected to a wiring in which the other electrode is given the potential VL .
  • the transistor M3 has a function of controlling the current supplied to the light emitting element EL.
  • the capacity C2 functions as a holding capacity. The capacity C2 can be omitted if it is unnecessary.
  • the transistor M3 may be connected to the cathode side. At that time, the values of the potential V H and the potential VL can be changed as appropriate.
  • the pixel 10EL can pass a large current through the light emitting element EL, so that HDR display can be realized, for example. Further, by supplying the correction signal to the wiring SL1 or the wiring SL2, it is possible to correct the variation in the electrical characteristics of one or both of the transistor M3 and the light emitting element EL.
  • circuit is not limited to the circuit illustrated in FIGS. 7C and 7D, and a transistor or a capacitance may be added separately.
  • the writing operation of the correction signal (first data potential V w ) and the input operation of the image signal (second data potential V data ) may be continuously performed, but the correction signal is written to all the pixels. It is preferable to perform the image signal input operation later.
  • the display system of one aspect of the present invention can generate an up-converted image in pixels.
  • the image signal supplied to the pixels is an image signal having a low resolution, and the same image signal may be supplied to a plurality of pixels.
  • the same image signal may be supplied to four pixels in the horizontal and vertical directions.
  • the same image signal may be supplied to each of the signal lines connected to each pixel, but it is preferable to electrically connect the signal lines that supply the same image signal. This makes it possible to speed up the operation of writing the image signal.
  • the processing unit 153 may generate the correction signal W2 by using the signal W3 supplied from the display unit 156. For example, the electrical characteristics of the transistor possessed by the pixel are acquired, and the signal W3 based on the electrical characteristics is supplied to the processing unit 153. By generating the correction signal W2 using the signal W3, it is possible to suppress display unevenness of the display unit 156.
  • FIG. 8A shows an example of generating a correction signal W2 using only the signal W3.
  • FIG. 8B shows an example in which the correction signal W2 is generated by using the correction data W1 supplied from the storage unit 152 in addition to the signal W3.
  • the correction data W1 supplied from the storage unit 152 in addition to the signal W3.
  • FIG. 9 shows an example of a block diagram of the display unit 156.
  • the display unit 156 has a plurality of pixels 10d, a scanning line drive circuit 12, a signal line drive circuit 13, and a circuit 15.
  • the plurality of pixels 10d are provided in a matrix.
  • a shift register circuit can be used for the circuit 15, for example.
  • the wiring 16 can be sequentially selected by the circuit 15 and the output value (signal W3) thereof can be input to the processing unit 153.
  • the image signal S1 is supplied to the processing unit 153. Further, the correction data W1 may be supplied to the processing unit 153. Further, as described above, the signal W3 is supplied to the processing unit 153 from the circuit 15.
  • the pixel 10d and the circuit 15 are electrically connected via the wiring 16.
  • the wiring 16 is a wiring for outputting information on electrical characteristics of the transistor or display element in the pixel 10d as a potential or a current.
  • the processing unit 153 has a function of generating an image signal S2 and a correction signal W2.
  • the pixel 10d can also perform an operation of correcting the variation in the characteristics of the transistor.
  • the variation in the threshold voltage of the drive transistor that supplies current to the EL element has a large effect on the display quality. Therefore, the pixel is made to hold a signal for correcting the threshold voltage of the drive transistor, and the image signal is used. By adding it, the display quality can be improved.
  • the signal W3 can be a signal including information on the current value flowing through the transistor when an arbitrary voltage as a reference is written to the pixel 10d.
  • the processing unit 153 reads and analyzes the information of the current value included in the signal W3, and generates a correction signal W2 to be stored in each pixel with the transistor whose current value is the average value or the median value as a reference.
  • the correction signal W2 is input to the signal line drive circuit 13 and written to each pixel.
  • the circuit having the function of reading the current value and the circuit having the function of generating the correction signal W2 may be different from each other.
  • the threshold voltage of the transistor may fluctuate greatly over a long period of time, but the fluctuation in a short period of time is extremely small. Therefore, the operation of generating the correction signal and writing to the pixel does not have to be performed for each frame, and may be performed at the time of turning on the power or at the end of the operation. Alternatively, the operation time of the display unit 156 may be recorded, and the operation may be performed at regular intervals in units of days, weeks, months, years, and the like.
  • both the threshold voltage correction and the up-conversion operation can be performed. You can also do it.
  • the correction signal W2 may be generated by another method.
  • a grayscale display may be performed, and the correction signal W2 may be generated based on data obtained by reading the brightness of the display with a luminance meter, data obtained by reading a photograph of the display, and the like. It is preferable to use inference using a neural network to generate the correction signal W2.
  • the display system of the present embodiment has a processing unit and a display unit, the processing unit can generate an image signal and a correction signal, and the display unit is a storage circuit provided in a pixel. Therefore, the correction signal can be held. Then, the display unit can display an image by using the correction signal and the image signal. For example, the resolution of an image can be converted by adding a correction signal to the image signal. Since the resolution of the data included in the image signal generated by the image processing does not have to be changed from the resolution of the data input from the outside, the calculation amount of the image processing can be reduced and the power consumption can be reduced.
  • This embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.
  • FIG. 10A shows an example of the configuration of the storage device.
  • the storage device 1400 has a peripheral circuit 1411 and a memory cell array 1470.
  • the peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
  • the column circuit 1430 includes, for example, a column decoder, a bit line driver circuit, a precharge circuit, a sense amplifier, a write circuit, and the like.
  • the precharge circuit has a function of precharging the wiring.
  • the sense amplifier has a function of amplifying a data signal read from a memory cell.
  • the wiring is the wiring connected to the memory cell of the memory cell array 1470, and will be described in detail later.
  • the amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440.
  • the row circuit 1420 has, for example, a row decoder, a word line driver circuit, and the like, and the row to be accessed can be selected.
  • the storage device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 as power supply voltages from the outside. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside.
  • the address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.
  • the control logic circuit 1460 processes the control signals (CE, WE, RE) input from the outside to generate the control signal of the row decoder and the control signal of the column decoder.
  • the control signal CE is a chip enable signal
  • the control signal WE is a write enable signal
  • the control signal RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.
  • the memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings.
  • the number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one column, and the like. Further, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one row, and the like.
  • FIG. 10A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane
  • the present embodiment is not limited to this.
  • the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411.
  • a sense amplifier may be provided so as to overlap under the memory cell array 1470.
  • the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in the present embodiment are not limited to the above.
  • the arrangement or function of these circuits and the wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.
  • the storage device of one aspect of the present invention has a high operating speed and can retain data for a long period of time. Further, the storage device of one aspect of the present invention has high rewrite resistance.
  • FIG. 11A shows a configuration example of the above-mentioned memory cell MC.
  • the memory cell MC has a transistor Tr and a capacitance Fe. Further, FIG. 11A also shows a sense amplifier circuit SA.
  • the transistor Tr may or may not have a back gate in addition to the gate. Further, in FIG. 11A, the transistor Tr is an n-channel type transistor, but a p-channel type transistor may be used. Hereinafter, the description will be made assuming that the transistor Tr or the like is an n-channel type transistor, but the following description can be referred to even if the transistor Tr or the like is a p-channel type by appropriately reversing the magnitude relationship of the potentials.
  • One of the source and drain of the transistor Tr is electrically connected to one electrode of the capacitance Fe.
  • the other of the source or drain of the transistor Tr is electrically connected to the wiring BL.
  • the gate of the transistor Tr is electrically connected to the wiring WL.
  • the other electrode of the capacitance Fe is electrically connected to the wiring PL.
  • the wiring BL is electrically connected to the sense amplifier circuit SA.
  • the wiring WL has a function as a word line, and the on / off of the transistor Tr can be controlled by controlling the potential of the wiring WL. For example, by setting the potential of the wiring WL to a high potential, the transistor Tr can be turned on, and by setting the potential of the wiring WL to a low potential, the transistor Tr can be turned off.
  • the wiring WL is electrically connected to the word line driver circuit included in the row circuit 1420, and the potential of the wiring WL can be controlled by the word line driver circuit.
  • the wiring BL has a function as a bit line, data is written to the memory cell MC via the wiring BL, and data held in the memory cell MC is read out via the wiring BL.
  • the sense amplifier circuit SA is provided in the bit line driver circuit of the column circuit 1430.
  • the potential Vref can be supplied to the sense amplifier circuit SA, and the signal EN can be supplied.
  • the sense amplifier circuit SA has a function of amplifying data read from, for example, a memory cell MC. For example, it has a function of amplifying data read from the memory cell MC based on the difference between the potential of the wiring BL and Vref.
  • the signal EN can be an enable signal that controls whether or not to activate the sense amplifier circuit SA.
  • the signal EN can be, for example, a binary digital signal. For example, when the potential of the signal EN is high, the sense amplifier circuit SA can be in the activated state, and when the potential of the signal EN is low, the sense amplifier circuit SA can be in the deactivated state. can do. When the sense amplifier circuit SA is in the activated state, for example, the data read from the memory cell MC is amplified. On the other hand, when the sense amplifier circuit SA is in the deactivated state, the amplification is not performed.
  • the wiring PL has a function as a plate wire, and the potential of the wiring PL can be the potential of the other electrode of the capacitance Fe.
  • the wiring PL is electrically connected to the plate wire driver circuit, and the potential of the wiring PL can be controlled by the plate wire driver circuit.
  • the plate wire driver circuit may be provided in the row circuit 1420 or the column circuit 1430.
  • the transistor Tr it is preferable to apply a transistor (OS transistor) having an oxide semiconductor in the channel forming region.
  • the OS transistor has a characteristic of having a high withstand voltage. Therefore, by using the transistor Tr as an OS transistor, a high voltage can be applied to the transistor Tr even if the transistor Tr is miniaturized.
  • the occupied area of the memory cell MC can be reduced.
  • the occupied area per memory cell MC shown in FIG. 11A can be 1/3 to 1/6 of the occupied area per SRAM cell. Therefore, the memory cells MC can be arranged at a high density.
  • the storage device according to one aspect of the present invention can be a storage device having a large storage capacity.
  • a transistor Si transistor having silicon in the channel forming region as the transistor Tr.
  • a transistor using single crystal silicon The Si transistor has characteristics such as small variation in electrical characteristics, stable electrical characteristics, high field effect mobility, and easy miniaturization. Therefore, by using the transistor Tr as a Si transistor, it is possible to realize a memory cell MC that is extremely fine, highly reliable, and has little variation in electrical characteristics between cells. Further, by miniaturizing the Si transistor, the field effect mobility can be further increased, so that the read speed per memory cell MC can be increased.
  • the capacitive Fe can be a ferroelectric capacitor having an MFM (Metal-Ferroelectric-Metal) structure in which a ferroelectric layer is sandwiched between a pair of electrodes.
  • the ferroelectric layer has a material that exhibits ferroelectricity.
  • a non-volatile storage element can be formed by using a capacitive element (ferroelectric capacitor) using the material as a dielectric.
  • a non-volatile storage element using a ferroelectric capacitor may be referred to as a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, or the like.
  • a ferroelectric memory may have a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor may be electrically connected to one terminal of the ferroelectric capacitor.
  • hafnium oxide As a material capable of exhibiting ferroelectricity, for example, hafnium oxide, or a material having hafnium oxide and zirconium oxide can be used.
  • a material having hafnium oxide or hafnium oxide and zirconium oxide is preferable because it can exhibit ferroelectricity even when processed into a thin film of several nm. By thinning the ferroelectric layer, a storage device combined with a miniaturized transistor can be obtained.
  • FeRAM having a ferroelectric capacitor and a transistor is applied to the memory cell MC shown in FIG. 11A.
  • the memory cell MC shown in FIG. 11A has at least a capacitive element and a transistor for controlling charge / discharge of the capacitive element.
  • ferroelectric memory can be used for the memory cell MC.
  • the storage device of one aspect of the present invention can be manufactured by using one or more of the above-mentioned ferroelectric memories.
  • the circuit symbol of the capacitance for example, the capacitance Fe
  • the circuit symbol of the capacitance Fe having a material capable of having ferroelectricity as a dielectric is assumed to be a diagonal line added to the circuit symbol of the capacitance as shown in FIG. 11A. ..
  • the dielectric of the capacitance Fe has a hysteresis characteristic.
  • FIG. 11B is a graph showing an example of the hysteresis characteristic.
  • the horizontal axis indicates the voltage applied to the dielectric.
  • the voltage can be, for example, the difference between the potential of one electrode of the capacitance Fe and the potential of the other electrode of the capacitance Fe.
  • the vertical axis indicates the amount of polarization (also referred to as polarization) of the dielectric. If the value is positive, the negative charge is biased toward one electrode of the capacitance Fe, and the positive charge is the other electrode of the capacitance Fe. Indicates that it is biased to the side. On the other hand, when the amount of polarization is a negative value, it indicates that the negative charge is biased toward the other electrode side of the capacitance Fe and the positive charge is biased toward one electrode side of the capacitance Fe.
  • the voltage shown on the horizontal axis of the graph of FIG. 11B may be the difference between the potential of the other electrode of the capacitance Fe and the potential of one electrode of the capacitance Fe. Further, the amount of polarization shown on the vertical axis of the graph of FIG. 11B is set to a positive value when the negative charge is biased toward the other electrode side of the capacitance Fe and the positive charge is biased toward one electrode side of the capacitance Fe, and is negative. When the charge is biased to one electrode side of the capacitance Fe and the positive charge is biased to the other electrode side of the capacitance Fe, it may be a negative value.
  • the hysteresis characteristic of the dielectric can be represented by the curve 51 and the curve 52.
  • the voltage at the intersection of the curve 51 and the curve 52 be VSP and ⁇ VSP.
  • VSP and ⁇ VSP can be said to be saturated polarization voltages.
  • the voltage applied to the dielectric when the polarization amount of the dielectric changes along the curve 51 and the polarization amount of the dielectric is 0 is defined as Vc.
  • the voltage applied to the dielectric is ⁇ Vc.
  • Vc and -Vc can be said to be withstand voltage. It can be said that the value of Vc and the value of -Vc are values between -VSP and VSS.
  • the voltage applied to the dielectric of the capacitance Fe can be expressed by the difference between the potential of one electrode of the capacitance Fe and the potential of the other electrode of the capacitance Fe. Further, as described above, the other electrode of the capacitance Fe is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, it is possible to control the voltage applied to the dielectric material of the capacitance Fe.
  • the memory cell MC can hold binary data whose value can be represented by, for example, "0" or "1".
  • the data held in the memory cell MC can be determined, for example, by the amount of polarization of the dielectric contained in the capacitance Fe.
  • the amount of polarization of the dielectric contained in the capacitance Fe is a positive value, it can be assumed that the memory cell MC holds data having a value of “1”.
  • the polarization amount of the dielectric contained in the capacitance Fe is a negative value, it can be assumed that the data having a value of "0" is held in the memory cell MC.
  • the polarization amount of the dielectric contained in the capacitance Fe is a positive value
  • the data having a value of "0" is held in the memory cell MC, and when the value is negative, the memory cell MC is used.
  • Data having a value of "1" may be held in the data.
  • the voltage applied to the dielectric of the capacitance Fe indicates the difference between the potential of one electrode of the capacitance Fe and the potential of the other electrode (wiring PL) of the capacitance Fe.
  • the data written in the memory cell MC and read out from the memory cell MC is binary data whose value can be represented by "0" or "1".
  • the polarization amount of the dielectric contained in the capacitance Fe is a negative value, it is assumed that the data having a value of "0" is held in the memory cell MC, and when the value is positive, the memory cell MC has. It is assumed that the data having a value of "1" is held.
  • the transistor Tr is an n-channel type transistor.
  • FIG. 12 is a timing chart showing an example of the driving method of the memory cell MC shown in FIG. 11A.
  • “H” indicates a high potential and “L” indicates a low potential.
  • the time T01 to the time T36 are shown as the period during which the memory cell MC is driven.
  • the data whose value is "0" is read from the memory cell MC.
  • the data having a value of "0” is written to the memory cell MC.
  • the data having a value of "1” is written to the memory cell MC.
  • the data is written back to the memory cell MC.
  • the data having a value "0” is written to the memory cell MC.
  • GND can be, for example, a ground potential.
  • the GND does not necessarily have to be the ground potential as long as the memory cell MC or the like can be driven so as to satisfy the gist of one aspect of the present invention.
  • the potential of the wiring WL is set to a high potential.
  • the transistor Tr is turned on, so that one electrode of the capacitance Fe and the wiring BL are conducted.
  • the potential of the wiring PL is Vw.
  • Vw is VSP or higher.
  • the potential of the wiring BL is held in the polarization amount of the dielectric of the capacitance Fe at the start time of time T02, that is, in the memory cell MC due to the capacitive coupling via the capacitance Fe. It rises according to the data being made.
  • Vw is a potential higher than VSS and GND is a ground potential. Further, the potentials supplied to the wiring PL and the wiring BL will be described with Vw as a high potential and GND as a low potential. Further, Vref is described as a potential between Vw and GND.
  • the data held in the memory cell MC can be read out and input to the sense amplifier circuit SA via the wiring BL.
  • the potential of the signal EN is set to a high potential.
  • the sense amplifier circuit SA is activated, and the data read from the memory cell MC is amplified based on the difference between the potential of the wiring BL and Vref.
  • the potential of the wiring BL is lower than Vref. Therefore, the potential of the wiring BL becomes GND, which is a low potential, and the data whose value is “0” read from the memory cell MC is amplified.
  • the transistor Tr since the transistor Tr is in the ON state at time T03 to time T04, the voltage applied to the dielectric of the capacitance Fe is ⁇ Vw. Therefore, as shown in FIG. 11B, the amount of polarization of the dielectric of the capacitance Fe remains negative, and the data having a value of “0” is continuously held in the memory cell MC.
  • the potential of the wiring PL is set to GND.
  • the transistor Tr is in the ON state and the potential of the wiring BL is GND, so that the potential applied to the dielectric of the capacitance Fe is 0V. Since the amount of polarization of the dielectric of the capacitance Fe changes along the curve 51 shown in FIG. 11B, the amount of polarization of the dielectric of the capacitance Fe remains negative even if the potential applied to the dielectric of the capacitance Fe is 0V. Is. Therefore, the data having a value of "0" is continuously held in the memory cell MC.
  • the potential of the signal EN is set to a low potential.
  • the sense amplifier circuit SA becomes inactive.
  • the potential of the wiring WL is set to a low potential. As a result, the transistor Tr is turned off.
  • the potential of the wiring WL, the potential of the wiring PL, and the potential of the signal EN at time T11 to time T21 may be the same as the potential of the wiring WL, the potential of the wiring PL, and the potential of the signal EN at time T01 to time T11. can.
  • the potential of the wiring BL becomes GND, which is a low potential, and the data read from the memory cell MC and having a value of "0" is amplified.
  • the potential of the wiring BL is set to Vw. Since the transistor Tr is in the ON state, the potential of one electrode of the capacitance Fe is Vw.
  • the potential of the signal EN By setting the potential of the signal EN to a low potential at time T15 to time T16, the potential of the wiring BL becomes GND, which is a low potential.
  • the transistor Tr is in the ON state and the potential of the wiring PL is GND, so that the potential applied to the dielectric of the capacitance Fe is 0V. Since the amount of polarization of the dielectric of the capacitance Fe changes along the curve 52 shown in FIG. 11B, the amount of polarization of the dielectric of the capacitance Fe remains positive even if the potential applied to the dielectric of the capacitance Fe is 0V. Is. Therefore, the data whose value is "1" is held in the memory cell MC.
  • the potential of the wiring WL, the potential of the wiring PL, and the potential of the signal EN at the time T21 to the time T31 shall be the same as the potential of the wiring WL, the potential of the wiring PL, and the potential of the signal EN at the time T11 to the time T21 and the like. Can be done.
  • the sense amplifier circuit SA is activated, and the data read from the memory cell MC is amplified based on the difference between the potential of the wiring BL and Vref.
  • the potential of the wiring BL is higher than Vref. Therefore, the potential of the wiring BL becomes Vw, which is a high potential, and the data with the value “1” read from the memory cell MC is amplified.
  • the potential of the signal EN By setting the potential of the signal EN to a low potential at time T25 to time T26, the potential of the wiring BL becomes GND, which is a low potential. As a result, the potential applied to the dielectric of the capacitance Fe becomes 0 V, but the polarization inversion does not occur, and the data having a value of “1” is continuously held in the memory cell MC.
  • the potential of the wiring WL, the potential of the wiring PL, and the potential of the signal EN after the time T31 to the time T36 are the same as the potential of the wiring WL, the potential of the wiring PL, and the potential of the signal EN at the time T21 to the time T31 and the like. be able to.
  • the potential of the wiring BL becomes Vw, which is a high potential, and the data with a value of "1" read from the memory cell MC is amplified.
  • the potential of the wiring BL is set to GND. Since the transistor Tr is in the ON state, the potential of one electrode of the capacitance Fe is GND.
  • the potential of the wiring PL is Vw. From the above, the voltage applied to the dielectric of the capacitance Fe becomes ⁇ Vw. As a result, as shown in FIG. 11B, the amount of polarization of the dielectric of the capacitive Fe becomes negative. Therefore, data having a value of "0" is written in the memory cell MC.
  • the above is an example of how to drive the memory cell MC.
  • This embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.
  • 13A1, 13B1 and 13C1 show circuit diagrams of the ferroelectric memory.
  • white circles represent terminals.
  • FIG. 13A1 shows a circuit diagram of FeRAM.
  • the circuit diagram shown in FIG. 13A1 has one transistor (also referred to as a field effect transistor or FET) and one capacitive element, and the capacitive element includes a material capable of exhibiting ferroelectricity.
  • the second embodiment and the fourth embodiment can be referred to.
  • FIG. 13B1 shows a circuit diagram of FeFET.
  • the circuit diagram shown in FIG. 13B1 has one transistor and includes a material capable of exhibiting ferroelectricity in the gate insulating film of the transistor.
  • FIG. 13C1 shows a circuit diagram of the FTJ memory.
  • the circuit diagram shown in FIG. 13C1 has one capacitive element and one diode, and the capacitive element contains a material capable of exhibiting ferroelectricity.
  • FIG. 13C1 one capacitive element and one diode are described separately, but the present invention is not limited to this.
  • one element has both the functions of one capacitive element and one diode, it is not necessary to separate the respective functions.
  • FIG. 13C1 an element configuration in which an insulator is provided between a pair of electrodes and a tunnel junction is used between the insulator and the electrodes can be used. .. Further, the circuit diagram shown in FIG. 13C1 can be regarded as an element configuration of one capacitor using a tunnel junction.
  • FIG. 13A2 is a cross-sectional view corresponding to the capacitive element of the FeRAM shown in FIG. 13A1.
  • FIG. 13A2 has a conductor 110, an insulator 130 on the conductor 110, and a conductor 120 on the insulator 130.
  • the conductor 110 functions as a lower electrode.
  • the conductor 120 functions as an upper electrode.
  • the insulator 130 preferably uses a material capable of exhibiting ferroelectricity.
  • the insulator 130 may be read as a dielectric or a ferroelectric substance.
  • the conductor 120 may be configured to be connected to the source or drain of the transistor.
  • FIG. 13B2 is a cross-sectional view corresponding to the FeFET shown in FIG. 13B1.
  • FIG. 13B2 has an oxide 230, an insulator 130 on the oxide 230, and a conductor 120 on the insulator 130.
  • Oxide 230 contains a channel forming region.
  • the oxide 230 may be replaced with a semiconductor such as silicon. That is, the FeFET may have an oxide semiconductor or silicon in the channel forming region.
  • the insulator 130 preferably uses a material capable of exhibiting ferroelectricity. Further, the laminated structure shown in FIG. 13B2 can be said to be different from the configuration in which the oxide 230 and the insulator 130, that is, a material capable of exhibiting ferroelectricity, are in contact with each other.
  • 13C2, 13C3, and 13C4 are cross-sectional views corresponding to the FTJ memory shown in FIG. 13C1, respectively.
  • FIG. 13C2 has a conductor 110, an insulator 115a on the conductor 110, an insulator 130 on the insulator 115a, and a conductor 120 on the insulator 130. It can be said that FIG. 13C2 has a structure having an insulator 115a between the conductor 110 of FIG. 13A2 and the insulator 130.
  • FIG. 13C3 has a conductor 110, an insulator 130 on the conductor 110, an insulator 115b on the insulator 130, and a conductor 120 on the insulator 115b.
  • FIG. 13C4 shows the conductor 110, the insulator 115a on the conductor 110, the insulator 130 on the insulator 115a, the insulator 115b on the insulator 130, and the conductor 120 on the insulator 115b. , Have.
  • the insulator 115a and the insulator 115b may have different configurations in at least one of the film type, the film quality, and the film thickness.
  • the insulator 115a and the insulator 115b may be of normal dielectric materials, respectively, and for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, and the like may be used. can. In particular, as the insulators 115a and 115b, silicon nitride films are preferable. Further, the insulator 115a and the insulator 115b can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, respectively.
  • the insulator 115a and the insulator 115b it is preferable to form a film by using the PEALD method.
  • a precursor containing halogens such as fluorine, chlorine, bromine and iodine.
  • plasma treatment is performed in an atmosphere in which a nitride such as N 2 , N 2 O, NH 3 , NO, NO 2 , and N 2 O 2 is introduced to obtain a high-quality silicon nitride film. Can be formed.
  • a ferroelectric device using a material capable of exhibiting ferroelectricity.
  • a capacitive element using a material capable of exhibiting ferroelectricity.
  • a transistor using a material capable of exhibiting ferroelectricity.
  • a capacitive element and a diode using a material capable of exhibiting ferroelectricity.
  • This embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.
  • the capacitive element of the present embodiment has a material capable of exhibiting ferroelectricity as a dielectric layer.
  • the capacitive element of the present embodiment can be used for the storage device exemplified in the second embodiment. Specifically, the capacitive element of this embodiment can be used as the capacitive Fe shown in FIG. 11A.
  • the conductor 110 is formed on a substrate (not shown).
  • the film formation of the conductor 110 is performed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, and an atomic layer deposition (PLD) method. It can be carried out by using a deposition (ALD: Atomic Layer Deposition) method or the like.
  • ALD Atomic Layer Deposition
  • the conductor 110 may be appropriately patterned by using a lithography method or the like.
  • the insulator 130 is formed on the conductor 110.
  • the film formation of the insulator 130 can be performed by using a sputtering method, a CVD method, an ALD method, or the like.
  • the insulator 130 can be formed on the conductor 110 with good coverage. As a result, it is possible to suppress the generation of a leak current between the upper electrode and the lower electrode of the capacitive element 100.
  • insulator 130 it is preferable to use a material capable of exhibiting ferroelectricity.
  • Materials that can exhibit strong dielectric property include hafnium oxide, zirconium oxide, hafnium oxide, and a material having zirconium oxide (HfZrOX ( X is a real number larger than 0)), hafnium oxide and element J1 (element here).
  • J1 is added with one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadrinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr) and the like.
  • Element J2 in the material and zirconium oxide is hafnium (Hf), silicon (Si), aluminum (Al), gadrinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr). ), Etc., and the material to which one or more) is added.
  • PbTiO X barium titanate strontium (BST), barium titanate, lead zirconate titanate (PZT), strontium bismuthate tantanate (SBT), bismuth ferrite (BFO), titanium
  • a piezoelectric ceramic having a perovskite structure such as barium acid acid may be used.
  • the material capable of exhibiting ferroelectricity for example, a mixture or compound containing a plurality of materials selected from the materials listed above can be used.
  • the insulator 130 may have a laminated structure composed of a plurality of materials selected from the materials listed above.
  • hafnium oxide, zirconium oxide, HfZrOX , a material in which element J1 is added to hafnium oxide, a material in which element J2 is added to zirconium oxide, and the like have crystal structures and characteristics depending not only on film forming conditions but also on various processes.
  • the above materials can be referred to as materials capable of exhibiting strong dielectric properties because they are subject to change.
  • the film thickness of the insulator 130 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, still more preferably 10 nm or less (typically 2 nm or more and 9 nm or less).
  • the capacitive element 100 can be combined with a miniaturized transistor to form a semiconductor device.
  • a layered material capable of exhibiting ferroelectricity may be referred to as a ferroelectric layer or a metal oxide film.
  • FIG. 15 is a model diagram illustrating the crystal structure of hafnium oxide (HfO 2 in this embodiment).
  • Hafnium oxide is known to have various crystal structures, for example, the cubic system (cubic, space group: Fm-3m) and the tetragonal system (tetragonal, space group: P42 2 / nmc) shown in FIG. ), Orthorhombic, space group: Pbc2 2 ), and monoclinic, space group: P2 1 / c.
  • each of the above-mentioned crystal structures can undergo a phase change. For example, by using a composite material in which hafnium oxide is doped with zirconium, the crystal structure of monoclinic hafnium oxide can be changed to an orthorhombic crystal structure.
  • the composite material When the above-mentioned composite material is formed by alternately forming hafnium oxide and zirconium oxide in a 1: 1 composition using the ALD method, the composite material has an orthorhombic crystal structure. Alternatively, the composite material has an amorphous structure. Then, by applying heat treatment or the like to the composite material, the amorphous structure can be made into an orthorhombic crystal structure. The crystal structure of the orthorhombic system may change to the crystal structure of the monoclinic system. When imparting strong dielectric property to the above-mentioned composite material, an orthorhombic crystal structure is preferable to a monoclinic crystal structure.
  • the crystal structure of the insulator 130 is not particularly limited.
  • the crystal structure of the insulator 130 may be one or more selected from a cubic system, a tetragonal system, an orthorhombic system, and a monoclinic system.
  • the insulator 130 may have an amorphous structure.
  • the insulator 130 may be a composite structure having an amorphous structure and a crystal structure.
  • the insulator 130 may be in a state in which a plurality of crystal structures are mixed. At this time, the insulator 130 can exhibit ferroelectricity by including at least the orthorhombic crystal structure in the insulator 130.
  • HfZrOX hafnium oxide and zirconium oxide
  • the insulator 130 when the insulator 130 is formed into a film by using the thermal ALD method, it is preferable to use a material containing no hydrocarbon (hydrocarbon, also referred to as HC) as a precursor. If the insulator 130 contains one or both of hydrogen and carbon, it may inhibit the crystallization of the insulator 130. Therefore, as described above, it is preferable to reduce the concentration of either one or both of hydrogen and carbon in the insulator 130 by using a precursor containing no hydrocarbon.
  • the precursor containing no hydrocarbon include chlorine-based materials.
  • HfZrOX hafnium oxide and zirconium oxide
  • HfCl 4 and / or ZrCl 4 can be used as the precursor.
  • H2O or O3 can be used as the oxidizing agent.
  • the oxidizing agent of the thermal ALD method it is preferable to use O3 rather than H2O because the hydrogen concentration in the membrane can be reduced.
  • the oxidizing agent of the thermal ALD method is not limited to this.
  • any one or a plurality selected from O 2 , O 3 , N 2 O, NO 2 , H 2 O, and H 2 O 2 can be used.
  • the conductor 120 is formed on the insulator 130.
  • the conductor 120 is arranged apart from the conductor 110 via the insulator 130.
  • the conductor 120 may have a laminated structure of a conductor 120a provided in contact with the insulator 130 and a conductor 120b provided in contact with the conductor 120a.
  • the conductor 120a is provided with a thin conductive film having a good covering property on the insulator 130.
  • the conductor 120b may be arranged so as to embed an opening on the conductor 120a.
  • the conductor 120a can be formed into a film by using an ALD method, a CVD method, or the like.
  • titanium nitride may be formed by using the thermal ALD method.
  • the film forming method of the conductor 120a is preferably a method of forming a film while heating the substrate, as in the thermal ALD method.
  • the film may be formed by setting the substrate temperature to room temperature or higher, preferably 300 ° C. or higher, more preferably 325 ° C. or higher, and further preferably 350 ° C. or higher.
  • the film may be formed by setting the substrate temperature to 500 ° C. or lower, preferably 450 ° C. or lower.
  • the film may be formed by setting the substrate temperature to about 400 ° C.
  • the conductor 120a By forming the conductor 120a in the temperature range as described above, insulation is performed without performing a high-temperature baking treatment (for example, a baking treatment having a heat treatment temperature of 400 ° C. or higher or 500 ° C. or higher) after the conductor 120a is formed.
  • the ferroelectricity can be imparted to the body 130, or the ferroelectricity of the insulator 130 can be enhanced. This makes it possible to easily manufacture a ferroelectric capacitor and improve the productivity of the semiconductor device.
  • the conductor 120a by using the ALD method, which causes relatively little damage to the substrate as described above, it is possible to prevent the crystal structure of the insulator 130 from being excessively destroyed, and the insulator 130 can be prevented from being excessively destroyed. Ferroelectricity can be increased.
  • the conductor 120a when the conductor 120a is formed by a sputtering method or the like, damage may enter the base film, here, the insulator 130.
  • the insulator 130 when a material having hafnium oxide and zirconium oxide (HfZrO X ) is used as the insulator 130 and the conductor 120a is formed by a sputtering method, the underlying film HfZrOX is damaged and the crystal structure of HfZrOX (representative). There is a possibility that the crystal structure such as the orthorhombic system) will collapse.
  • HfZrO X hafnium oxide and zirconium oxide
  • the insulator 130 (here, HfZrOX ) it is preferable to use a material that does not contain hydrogen or a material that has an extremely low hydrogen content.
  • the concentration of hydrogen contained in the insulator 130 is preferably 5 ⁇ 10 20 atoms / cm 3 or less, and more preferably 1 ⁇ 10 20 atoms / cm 3 or less.
  • the insulator 130 may become a film that does not contain hydrocarbons as a main component or has an extremely low content of hydrocarbons.
  • the concentration of the hydrocarbon contained in the insulator 130 is preferably 5 ⁇ 10 20 atoms / cm 3 or less, and more preferably 1 ⁇ 10 20 atoms / cm 3 or less.
  • the insulator 130 may be a film containing no carbon as a main component or having an extremely low carbon content.
  • the concentration of carbon contained in the insulator 130 is preferably 5 ⁇ 10 20 atoms / cm 3 or less, more preferably 1 ⁇ 10 20 atoms / cm 3 or less.
  • the insulator 130 it is preferable to use a material having an extremely low content of at least one of hydrogen, hydrocarbon, and carbon, but it is particularly important to extremely reduce the content of hydrogen and carbon. be. Hydrocarbons and carbon are heavier molecules or atoms than hydrogen and are difficult to remove in later steps. Therefore, it is preferable to thoroughly eliminate hydrocarbons and carbon when forming the insulator 130.
  • the insulator 130 is made of a material that does not contain at least one of hydrogen, hydrocarbon, and carbon, or has an extremely low content of at least one of hydrogen, hydrocarbon, and carbon. It is possible to improve the crystallinity of 130, and it is possible to form a structure having high strong dielectric property.
  • a film having high purity and intrinsic ferroelectricity by thoroughly removing at least one of impurities, here hydrogen, hydrocarbon, and carbon in the film of the insulator 130, here. It is possible to form a high-purity intrinsic capacitive element. It should be noted that the consistency of the manufacturing process between the capacitive element having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later is very high. Therefore, it is possible to provide a method for manufacturing a semiconductor device having high productivity.
  • a hydrocarbon-free precursor typically a chlorine-based precursor
  • an oxidizing agent typically, using the thermal ALD method
  • an oxidizing agent typically
  • Uses O 3 and to form a ferroelectric material.
  • the conductor 120b can be formed into a film by using a sputtering method, an ALD method, a CVD method, or the like.
  • tungsten may be formed by using a metal CVD method.
  • the capacitive element 100 having the insulator 130 between the conductor 110 and the conductor 120 shown in FIG. 14C can be manufactured.
  • the capacitive element 100 according to the present embodiment can enhance the ferroelectricity of the insulator 130 without performing a high-temperature baking treatment after the conductor 120a is formed. As a result, the process of manufacturing the ferroelectric capacitor can be reduced, so that the productivity of the ferroelectric capacitor and the semiconductor device including the ferroelectric capacitor can be improved.
  • the ALD method utilizes the self-regulating properties of atoms and allows atoms to be deposited layer by layer, so ultra-thin film formation is possible, film formation into structures with a high aspect ratio is possible, pinholes, etc. It has the effects of being able to form a film with few defects, being able to form a film with excellent coverage, and being able to form a film at a low temperature.
  • the ALD method is carried out by alternately introducing a first raw material gas (also called a precursor) and a second raw material gas (also called an oxidizing gas) for the reaction into the chamber and repeating the introduction of these raw material gases. Make a membrane. Further, when introducing the precursor or the oxidizing gas, N2 , Ar or the like may be introduced into the reaction chamber together with the precursor or the oxidizing gas as a carrier purge gas. By using the carrier purge gas, it is possible to suppress the adsorption of the precursor or oxidizing gas to the inside of the pipe and the inside of the valve, and to introduce the precursor or oxidizing gas into the reaction chamber (also called carrier gas). ..
  • the precursor or oxidizing gas remaining in the reaction chamber can be quickly exhausted (also referred to as purge gas). Since it has two roles of introduction (carrier) and exhaust (purge) in this way, it is sometimes called a carrier purge gas. Further, it is preferable to use the carrier purge gas because the uniformity of the formed film is improved.
  • FIG. 16 shows a film formation sequence of a film of a material exhibiting ferroelectricity (hereinafter referred to as a ferroelectric layer) using the ALD method.
  • a ferroelectric layer a film formation sequence of a film of a material exhibiting ferroelectricity (hereinafter referred to as a ferroelectric layer) using the ALD method.
  • the insulator 130 a film formation of a ferroelectric layer having hafnium oxide and zirconium oxide will be shown as an example.
  • a precursor containing hafnium and further containing one or more selected from chlorine, fluorine, bromine, iodine, and hydrogen can be used.
  • a precursor containing zirconium and further containing one or more selected from chlorine, fluorine, bromine, iodine, and hydrogen can be used.
  • HfCl 4 is used as the precursor 401 containing hafnium
  • ZrCl 4 is used as the precursor 402 containing zirconium.
  • the precursor 401 and the precursor 402 are formed by heating and gasifying a liquid raw material or a solid raw material.
  • the precursor 401 is formed from a solid raw material of HfCl 4
  • the precursor 402 is formed from a solid raw material of ZrCl 4 .
  • Impurities are preferably reduced in the precursor 401 and the precursor 402, and it is preferable that these solid raw materials also have reduced impurities.
  • examples of the impurities include Ba, Cd, Co, Cr, Cu, Fe, Ga, Li, Mg, Mn, Na, Ni, Sr, V, Zn and the like.
  • the above impurities are preferably less than 1000 wppb.
  • wppb is a unit in which the concentration of impurities converted by mass is expressed in parts per billion.
  • any one or a plurality selected from O 2 , O 3 , N 2 O, NO 2 , H 2 O, and H 2 O 2 can be used.
  • a gas containing H2O is used as the oxidizing gas 403.
  • the carrier purge gas 404 any one or a plurality selected from N2 , He, Ar, Kr, and Xe can be used.
  • N 2 is used as the carrier purge gas 404.
  • the carrier purge gas 404 is introduced into the reaction chamber.
  • the carrier purge gas 404 is always introduced during steps S01 to S08.
  • the oxidizing gas 403 is introduced into the reaction chamber (step S01).
  • the introduction of the oxidizing gas 403 is stopped, only the carrier purge gas 404 is used, and the oxidizing gas 403 remaining in the reaction chamber is purged (step S02).
  • the precursor 401 is introduced into the reaction chamber to keep the pressure in the reaction chamber constant (step S03). In this way, the precursor 401 is adsorbed on the surface to be formed.
  • the introduction of the precursor 401 is stopped, only the carrier purge gas 404 is used, and the precursor 401 remaining in the reaction chamber is purged (step S04).
  • the oxidizing gas 403 is introduced into the reaction chamber.
  • the precursor 401 is oxidized to form hafnium oxide (step S05).
  • the introduction of the oxidizing gas 403 is stopped, only the carrier purge gas 404 is used, and the oxidizing gas 403 remaining in the reaction chamber is purged (step S06).
  • the precursor 402 is introduced into the reaction chamber to keep the pressure in the reaction chamber constant (step S07). In this way, the precursor 402 is adsorbed on the oxygen layer of hafnium oxide.
  • the introduction of the precursor 402 is stopped, only the carrier purge gas 404 is used, and the precursor 402 remaining in the reaction chamber is purged (step S08).
  • the oxidizing gas 403 is introduced into the reaction chamber. By introducing the oxidizing gas 403, the precursor 402 is oxidized and zirconium oxide is formed on hafnium oxide.
  • steps S01 to S08 are set as one cycle, and the cycle is repeated until a desired film thickness is reached. It is preferable that steps S01 to S08 are performed in a temperature range of 250 ° C. or higher and 450 ° C. or lower, and more preferably in a temperature range of 350 ° C. or higher and 400 ° C. or lower.
  • the insulator 130 by forming a film using the ALD method, it is possible to form a layered crystal structure in which a hafnium layer, an oxygen layer, a zirconium layer, and an oxygen layer are repeated. Further, as described above, by forming a film using a precursor having reduced impurities, it is possible to prevent impurities from being mixed in during the film formation and hindering the formation of the layered crystal structure. As described above, by forming the insulator 130 into a layered crystal structure having high crystallinity, the insulator 130 can be given high ferroelectricity.
  • the insulator 130 does not necessarily exhibit ferroelectricity immediately after film formation. As described above, the insulator 130 may exhibit ferroelectricity not immediately after film formation but after forming the conductor 120 on the insulator 130.
  • FIG. 17A is a schematic view of the manufacturing apparatus 900 by the ALD method.
  • the manufacturing apparatus 900 has a reaction chamber 901, a gas introduction port 903, a reaction chamber inlet 904, an exhaust port 905, a wafer stage 907, and a shaft 908.
  • the wafer 950 is arranged on the wafer stage 907.
  • the reaction chamber 901 may be provided with a heater system for heating the inside of the reaction chamber 901, the precursor 401, the precursor 402, the oxidizing gas 403, and the carrier purge gas 404.
  • the wafer stage 907 may be provided with a heater system for heating the wafer 950.
  • the wafer stage 907 may be provided with a rotation mechanism that rotates horizontally with the shaft 908 as a rotation axis.
  • the precursor 401, the precursor 402, the oxidizing gas 403, and the carrier purge gas 404 are introduced into the gas inlet 903 at an appropriate timing and at an appropriate flow rate in front of the gas inlet.
  • Gas supply system is installed.
  • an exhaust system having a vacuum pump is installed at the end of the exhaust port 905.
  • the manufacturing device 900 shown in FIG. 17A is an ALD device called a cross-flow method.
  • the flow of the precursor 401, the precursor 402, the oxidizing gas 403, and the carrier purge gas 404 in the cross-flow method will be described below.
  • the precursor 401, the precursor 402, the oxidizing gas 403, and the carrier purge gas 404 flow from the gas inlet 903 to the reaction chamber 901 via the reaction chamber inlet 904, reach the wafer 950, and are exhausted through the exhaust port 905. .
  • the arrow shown in FIG. 17A schematically indicates the direction in which the gas flows.
  • step S05 for introducing the oxidizing gas 403 into the reaction chamber 901 shown in FIG. 16 the precursor 401 adsorbed on the wafer 950 is oxidized by the oxidizing gas 403 to form hafnium oxide. Due to the structure of the manufacturing apparatus 900 of the cross-flow method, the oxidizing gas 403 reaches the wafer 950 after being in contact with the heated reaction chamber member for a long time. Therefore, for example , when O3 is used as the oxidizing gas 403, the oxidizing gas 403 is decomposed by the reaction between the high temperature solid surface and the oxidizing gas 403 by the time it reaches the state, and the oxidizing power is lowered.
  • the film formation rate of hafnium oxide depends on the reach of the oxidizing gas from the reaction chamber inlet 904 to the wafer 950.
  • the peripheral portion of the wafer 950 reaches the oxidizing gas 403 first, so that the film thickness of hafnium oxide becomes thicker toward the peripheral portion of the wafer 950 and the central portion. Is thinner than the peripheral part.
  • the oxidation of the precursor 401 has been described as an example, but the same applies to the oxidation of the precursor 402.
  • hafnium oxide having excellent film thickness uniformity in the substrate surface can be formed.
  • the uniformity in the substrate surface is preferably ⁇ 1.5% or less, more preferably ⁇ 1.0% or less.
  • the inside of the substrate surface means the range of a square in which the length of one side of the size of the substrate is 5 inches.
  • RANGE maximum film thickness in the substrate surface-the minimum film thickness in the substrate surface
  • ⁇ PNU Percent Non Uniformity
  • the oxidizing gas 403 forms a layer of oxygen having excellent uniformity, so that a more regular layered crystal structure can be formed.
  • the insulator 130 by forming the insulator 130 into a highly regular, layered crystal structure, the insulator 130 can be given high ferroelectricity.
  • an insulator 130 made of a material exhibiting ferroelectricity can be formed.
  • the capacitive element 100 can be made into a ferroelectric capacitor.
  • FIG. 17B is a model diagram of the crystal structure of HfZrO X , here Hf 0.5 Zr 0.5 O 2 . Further, in FIG. 17B, the directions of the a-axis, the b-axis, and the c-axis are also shown.
  • FIG. 17B is a structure in which Zr is arranged in layers with respect to the optimized structure including the cell by the first-principles calculation regarding the orthorhombic structure (Pca2 1 ) of HfO 2 .
  • hafnium and zirconium are in a state of being bonded to each other via oxygen. This can be formed by alternately depositing hafnium and zirconium by the ALD method as in the film formation sequence shown in FIG.
  • the metal oxide of one aspect of the present invention can produce a crystal structure as shown in FIG. 17B by using the film forming sequence shown in FIG. 16 and the manufacturing apparatus shown in FIG. 17A.
  • the capacitive element containing a material capable of exhibiting ferroelectricity.
  • the capacitive element can be provided with good productivity.
  • the neural network NN can be composed of an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL.
  • the input layer IL, the output layer OL, and the intermediate layer HL each have one or more neurons (units).
  • the intermediate layer HL may be one layer or two or more layers.
  • a neural network having two or more layers of intermediate layers HL can also be called a DNN (deep neural network), and learning using a deep neural network can also be called deep learning.
  • Input data is input to each neuron in the input layer IL, the output signal of the anterior layer or posterior layer neuron is input to each neuron in the intermediate layer HL, and the output of the anterior layer neuron is input to each neuron in the output layer OL.
  • a signal is input.
  • each neuron may be connected to all neurons in the anterior and posterior layers (fully connected), or may be connected to some neurons.
  • FIG. 18B shows an example of an operation by a neuron.
  • two neurons in the presheaf layer that output a signal to the neuron N are shown.
  • the output x 1 of the presheaf neuron and the output x 2 of the presheaf neuron are input to the neuron N.
  • the sum of the multiplication result of the output x 1 and the weight w 1 (x 1 w 1 ) and the multiplication result of the output x 2 and the weight w 2 (x 2 w 2 ) is x 1 w 1 + x 2 w 2 .
  • the operation by the neuron includes the operation of adding the product of the output of the neuron in the previous layer and the weight, that is, the product-sum operation (x 1 w 1 + x 2 w 2 above).
  • This product-sum operation may be performed by software using a program or by hardware.
  • a product-sum calculation circuit can be used.
  • the product-sum calculation circuit a digital circuit or an analog circuit may be used.
  • an analog circuit is used for the product-sum calculation circuit, it is possible to improve the processing speed and reduce the power consumption by reducing the circuit scale of the product-sum calculation circuit or reducing the number of times the memory is accessed.
  • the product-sum calculation circuit may be composed of a transistor (also referred to as a “Si transistor”) containing silicon (single crystal silicon or the like) in the channel forming region, or an oxide semiconductor which is a kind of metal oxide in the channel forming region. It may be configured by a transistor (also referred to as “OS transistor”) containing. In particular, since the OS transistor has an extremely small off current, it is suitable as a transistor constituting the memory of the product-sum calculation circuit.
  • a product-sum calculation circuit may be configured by using both a Si transistor and an OS transistor.
  • FIG. 19 shows a configuration example of a semiconductor device MAC having a function of performing a neural network calculation.
  • the semiconductor device MAC has a function of performing a product-sum operation of the first data corresponding to the bond strength (weight) between neurons and the second data corresponding to the input data.
  • the first data and the second data can be analog data or multi-valued digital data (discrete data), respectively.
  • the semiconductor device MAC has a function of converting the data obtained by the product-sum operation by the activation function.
  • the semiconductor device MAC has a cell array CA, a current source circuit CS, a current mirror circuit CM, a circuit WDD, a circuit WLD, a circuit CLD, an offset circuit OFST, and an activation function circuit ACTV.
  • the cell array CA has a plurality of memory cells MC and a plurality of memory cells MCref.
  • memory cells MC MC [1,1] to MC [m, n]
  • the cell array CA is m rows and n columns (m, n are integers of 1 or more) and m memory cells MCref (m, n).
  • An example of the configuration having MCref [1] to MCref [m]) is shown.
  • the memory cell MC has a function of storing the first data.
  • the memory cell MCref has a function of storing reference data used for the product-sum operation.
  • the reference data can be analog data or multi-valued digital data.
  • the memory cells MC [i, j] (i is an integer of 1 or more and m or less, j is an integer of 1 or more and n or less) are wiring WL [i], wiring RW [i], wiring WD [j], and wiring BL. It is connected to [j]. Further, the memory cell MCref [i] is connected to the wiring WL [i], the wiring RW [i], the wiring WDref, and the wiring BLref.
  • I MC [i, j] the current flowing between the memory cell MC [i, j] and the wiring BL [j]
  • I MCref [i] the current flowing between the memory cell MCref [i] and the wiring BLref [i]
  • FIG. 20 shows a specific configuration example of the memory cell MC and the memory cell MCref.
  • FIG. 20 shows memory cells MC [1,1], MC [2,1] and memory cells MCref [1], MCref [2] as typical examples, but other memory cells MC and memory cells MCref are shown. Can also use a similar configuration.
  • the memory cell MC and the memory cell MCref each have a transistor Tr11, a transistor Tr12, and a capacitive element C11.
  • the transistor Tr11 and the transistor Tr12 are n-channel type transistors will be described.
  • the gate of the transistor Tr11 is connected to the wiring WL, one of the source or drain is connected to the gate of the transistor Tr12 and the first electrode of the capacitive element C11, and the other of the source or drain is connected to the wiring WD.
  • One of the source or drain of the transistor Tr12 is connected to the wiring BL, and the other of the source or drain is connected to the wiring VR.
  • the second electrode of the capacitive element C11 is connected to the wiring RW.
  • the wiring VR is a wiring having a function of supplying a predetermined potential.
  • a low power supply potential ground potential or the like
  • a node connected to one of the source and drain of the transistor Tr11, the gate of the transistor Tr12, and the first electrode of the capacitive element C11 is referred to as a node NM.
  • the node NMs of the memory cells MC [1,1] and MC [2,1] are referred to as nodes NM [1,1] and NM [2,1], respectively.
  • the memory cell MCref also has the same configuration as the memory cell MC.
  • the node NM and the node NMref each function as a holding node.
  • the first data is held in the node NM
  • the reference data is held in the node NMref.
  • currents I MC [1, 1] and I MC [2, 1] flow from the wiring BL [1] to the transistors Tr12 of the memory cells MC [1, 1] and MC [2, 1], respectively.
  • currents I MCref [1] and I MCref [2] flow from the wiring BLref to the transistors Tr12 of the memory cells MCref [1] and MCref [2], respectively.
  • the transistor Tr11 holds the potential of the node NM or the node NMref, it is preferable to use an OS transistor having an extremely small off current. As a result, the fluctuation of the potential of the node NM or the node NMref can be suppressed, and the calculation accuracy can be improved. Further, the frequency of the operation of refreshing the potential of the node NM or the node NMref can be suppressed low, and the power consumption can be reduced.
  • the transistor Tr12 is not particularly limited, and for example, a Si transistor or an OS transistor can be used.
  • an OS transistor is used for the transistor Tr12, the transistor Tr12 can be manufactured by using the same manufacturing apparatus as the transistor Tr11, and the manufacturing cost can be suppressed.
  • the transistor Tr12 may be an n-channel type or a p-channel type.
  • the current source circuit CS is connected to the wiring BL [1] to BL [n] and the wiring BLref.
  • the current source circuit CS has a function of supplying a current to the wiring BL [1] to BL [n] and the wiring BLref.
  • the current value supplied to the wiring BL [1] to BL [n] and the current value supplied to the wiring BLref may be different.
  • the current supplied from the current source circuit CS to the wiring BL [1] to BL [n] is referred to as IC
  • the current supplied from the current source circuit CS to the wiring BLref is referred to as ICRef .
  • the current mirror circuit CM has wiring IL [1] to IL [n] and wiring ILref.
  • the wiring IL [1] to IL [n] are connected to the wiring BL [1] to BL [n], respectively, and the wiring ILref is connected to the wiring BLref.
  • the connection points between the wiring IL [1] to IL [n] and the wiring BL [1] to BL [n] are referred to as nodes NP [1] to NP [n].
  • the connection point between the wiring ILref and the wiring BLref is referred to as a node NPref.
  • the current mirror circuit CM has a function of passing a current ICM corresponding to the potential of the node NPref to the wiring ILref and a function of passing the current ICM to the wiring IL [1] to IL [n].
  • FIG. 19 shows an example in which the current ICM is discharged from the wiring BLref to the wiring ILref , and the current ICM is discharged from the wiring BL [1] to BL [n] to the wiring IL [1] to IL [n]. ing.
  • the current flowing from the current mirror circuit CM to the cell array CA via the wiring BL [1] to BL [n] is referred to as IB [1] to IB [n].
  • the current flowing from the current mirror circuit CM to the cell array CA via the wiring BLref is referred to as IBref .
  • the circuit WDD has a function of supplying the potential corresponding to the first data stored in the memory cell MC to the wiring WD [1] to WD [n]. Further, the circuit WDD has a function of supplying the potential corresponding to the reference data stored in the memory cell MCref to the wiring WDref.
  • the circuit WLD has a function of supplying a signal for selecting a memory cell MC or a memory cell MCref for writing data to the wirings WL [1] to WL [m].
  • the circuit CLD has a function of supplying the potential corresponding to the second data to the wiring RW [1] to RW [m].
  • the offset circuit OFST has a function of detecting the amount of current flowing from the wirings BL [1] to BL [n] or the amount of change thereof. Further, the offset circuit OFST has a function of outputting the detection result to the wiring OL [1] to OL [n].
  • the offset circuit OFST may output the current corresponding to the detection result to the wiring OL [1] to OL [n], or convert the current corresponding to the detection result into a voltage to wire OL [1] to OL [n]. It may be output to OL [n].
  • the current flowing between the cell array CA and the offset circuit OFST is referred to as I ⁇ [1] to I ⁇ [n].
  • the activation function circuit ACTV has a function of performing an operation for converting a signal input from the offset circuit OFST according to a predefined activation function.
  • a sigmoid function for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function and the like can be used.
  • the signal converted by the activation function circuit ACTV is output to the wiring NIL [1] to NIL [n] as output data.
  • the product-sum calculation can be performed by the semiconductor device MAC.
  • the product-sum calculation circuit can be configured with a small number of transistors. Therefore, the circuit scale of the semiconductor device MAC can be reduced.
  • the number of rows m of the memory cell MC corresponds to the number of input data supplied to one neuron
  • the number of columns n of the memory cell MC corresponds to the number of neurons.
  • the number of rows m of the memory cell MC is set to the number of input data supplied from the input layer IL (the number of neurons of the input layer IL)
  • the number of columns n of the memory cell MC is the number of neurons of the intermediate layer HL.
  • the structure of the neural network to which the semiconductor device MAC is applied is not particularly limited.
  • the semiconductor device MAC can also be used for a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a Boltzmann machine (including a restricted Boltzmann machine), and the like.
  • CNN convolutional neural network
  • RNN recurrent neural network
  • autoencoder a Boltzmann machine (including a restricted Boltzmann machine), and the like.
  • the product-sum operation of the neural network can be performed by using the semiconductor device MAC. Further, by using the memory cell MC and the memory cell MCref shown in FIG. 20 for the cell array CA, it is possible to provide an integrated circuit capable of improving calculation accuracy, reducing power consumption, or reducing the circuit scale. ..
  • This embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.
  • the pixel 200 has a plurality of pixels 210. Each of the plurality of pixels 210 functions as a sub-pixel. By forming one pixel 200 by a plurality of pixels 210 each exhibiting a different color, the display unit can perform full-color display.
  • Each of the pixels 200 shown in FIGS. 21A and 21B has three sub-pixels.
  • the color combinations exhibited by the pixels 210 of the pixels 200 shown in FIG. 21A are red (R), green (G), and blue (B).
  • the color combinations exhibited by the pixels 210 of the pixels 200 shown in FIG. 21B are cyan (C), magenta (M), and yellow (Y).
  • Each of the pixels 200 shown in FIGS. 21C to 21E has four sub-pixels.
  • the color combinations exhibited by the pixels 210 of the pixels 200 shown in FIG. 21C are red (R), green (G), blue (B), and white (W).
  • the color combinations exhibited by the pixels 210 of the pixels 200 shown in FIG. 21D are red (R), green (G), blue (B), and yellow (Y).
  • the color combinations exhibited by the pixels 210 of the pixels 200 shown in FIG. 21E are cyan (C), magenta (M), yellow (Y), and white (W).
  • the display device of one aspect of the present invention can reproduce the color gamut of various standards.
  • the PAL Phase Alternate Line
  • NTSC National Television System Committee
  • sRGB standard RGB
  • ITU-R BT Standards, Adobe RGB standards, and HDTV (High Definition Television, also called high-definition television).
  • 709 International Telecommunication Union Radiocommunication Vector Broadcasting Service (Television) 709) standard
  • DCI-P3 Digital Cinema Projection
  • DCI-P3 Digital Cinema Indefiation TV
  • Super Initives HD R BT It is possible to reproduce a color gamut such as the 2020 (REC. 2020 (Recommendation 2020)) standard.
  • a display device capable of full-color display at a so-called full high-definition (also referred to as “2K resolution”, “2K1K”, “2K”, etc.) resolution. can.
  • a display device capable of full-color display at a so-called ultra-high definition also referred to as “4K resolution”, “4K2K”, “4K”, etc.
  • ultra-high definition also referred to as “4K resolution”, “4K2K”, “4K”, etc.
  • a display device capable of full-color display at a so-called super high-definition also referred to as “8K resolution”, “8K4K”, “8K”, etc.
  • 8K resolution also referred to as “8K resolution”, “8K4K”, “8K”, etc.
  • Display elements included in the display device of one aspect of the present invention include inorganic EL elements, organic EL elements, light emitting elements such as LEDs (including mini LEDs and micro LEDs), liquid crystal elements, electrophoresis elements, and MEMS (micro-LEDs). Examples include display elements using an electromechanical system).
  • FIG. 22 shows a cross-sectional view of a light emitting display device having a top emission structure to which a color filter method is applied.
  • the display device shown in FIG. 22 has a pixel unit 562 and a scanning line drive circuit 564.
  • a transistor 251a, a transistor 446a, a light emitting element 170, and the like are provided on the substrate 202.
  • a transistor 201a or the like is provided on the substrate 202.
  • the transistor 251a includes a conductive layer 221 that functions as a first gate electrode, an insulating layer 211 that functions as a first gate insulating layer, a semiconductor layer 231 and a conductive layer 222a and a conductive layer that function as source and drain electrodes. It has 222b, a conductive layer 223 that functions as a second gate electrode, and an insulating layer 225 that functions as a second gate insulating layer.
  • the semiconductor layer 231 has a channel forming region and a low resistance region. The channel forming region overlaps with the conductive layer 223 via the insulating layer 225.
  • the low resistance region has a portion connected to the conductive layer 222a and a portion connected to the conductive layer 222b.
  • the transistor 251a has gate electrodes above and below the channel.
  • the two gate electrodes are preferably electrically connected.
  • a transistor having a configuration in which two gate electrodes are electrically connected can increase the field effect mobility as compared with other transistors, and can increase the on-current. As a result, it is possible to manufacture a circuit capable of high-speed operation. Furthermore, it is possible to reduce the occupied area of the circuit unit. By applying a transistor with a large on-current, it is possible to reduce the signal delay in each wiring even if the display device is made larger or finer and the number of wirings is increased, and display unevenness can be suppressed. Is possible. Further, since the occupied area of the circuit unit can be reduced, the frame of the display device can be narrowed. Further, by applying such a configuration, a highly reliable transistor can be realized.
  • An insulating layer 212 and an insulating layer 213 are provided on the conductive layer 223, and a conductive layer 222a and a conductive layer 222b are provided on the insulating layer 212a and the insulating layer 213. Since the structure of the transistor 251a makes it easy to separate the conductive layer 221 from the conductive layer 222a or the conductive layer 222b, it is possible to reduce the parasitic capacitance between them.
  • the structure of the transistor of the display device is not particularly limited. For example, it may be a planar type transistor, a stagger type transistor, or an inverted stagger type transistor. Further, a transistor structure having either a top gate structure or a bottom gate structure may be used. Alternatively, gate electrodes may be provided above and below the channel.
  • the transistor 251a has a metal oxide in the semiconductor layer 231.
  • the metal oxide can function as an oxide semiconductor.
  • the transistor 446a and the transistor 201a have the same configuration as the transistor 251a. In one aspect of the present invention, the configurations of these transistors may be different.
  • the transistor included in the drive circuit unit and the transistor included in the pixel unit 562 may have the same structure or different structures.
  • the transistors included in the drive circuit unit may all have the same structure, or two or more types of structures may be used in combination.
  • the transistors included in the pixel unit 562 may all have the same structure, or two or more types of structures may be used in combination.
  • the transistor 446a overlaps with the light emitting element 170 via the insulating layer 215.
  • the transistor, the capacitive element, the wiring, and the like so as to overlap with the light emitting region of the light emitting element 170, the aperture ratio of the pixel portion 562 can be increased.
  • the light emitting element 170 has a pixel electrode 171 and an EL layer 172, and a common electrode 173. The light emitting element 170 emits light to the colored layer 205 side.
  • the pixel electrode 171 and the common electrode 173 one functions as an anode and the other functions as a cathode.
  • a voltage higher than the threshold voltage of the light emitting element 170 is applied between the pixel electrode 171 and the common electrode 173, holes are injected into the EL layer 172 from the anode side, and electrons are injected from the cathode side.
  • the injected electrons and holes are recombined in the EL layer 172, and the luminescent substance contained in the EL layer 172 emits light.
  • the pixel electrode 171 is electrically connected to the conductive layer 222b of the transistor 251a. These may be directly connected or may be connected via another conductive layer.
  • the pixel electrode 171 functions as a pixel electrode and is provided for each light emitting element 170.
  • the two adjacent pixel electrodes 171 are electrically insulated by the insulating layer 216.
  • the EL layer 172 is a layer containing a luminescent substance.
  • the common electrode 173 functions as a common electrode and is provided over a plurality of light emitting elements 170. A constant potential is supplied to the common electrode 173.
  • the light emitting element 170 overlaps with the colored layer 205 via the adhesive layer 174.
  • the insulating layer 216 overlaps with the light shielding layer 206 via the adhesive layer 174.
  • a microcavity structure may be adopted for the light emitting element 170.
  • the color filter colored layer 205
  • the microcavity structure By combining the color filter (colored layer 205) and the microcavity structure, light having high color purity can be extracted from the display device.
  • the colored layer 205 is a colored layer that transmits light in a specific wavelength range.
  • a color filter that transmits light in the wavelength range of red, green, blue, or yellow can be used.
  • the material that can be used for the colored layer 205 include a metal material, a resin material, a resin material containing a pigment or a dye, and the like.
  • the display device is not limited to the color filter method, and a separate painting method, a color conversion method, a quantum dot method, or the like may be applied. Further, the display device according to one aspect of the present invention is not limited to the top emission structure, and a bottom emission structure or the like may be applied.
  • the light-shielding layer 206 is provided between the adjacent colored layers 205.
  • the light-shielding layer 206 shields light from adjacent light-emitting elements 170 and suppresses color mixing between adjacent light-emitting elements 170.
  • a material that blocks light emission from the light-emitting element 170 can be used, and for example, a metal material, a resin material containing a pigment or a dye, or the like can be used to form a black matrix.
  • the light-shielding layer 206 is provided in a region other than the pixel portion 562 such as the scanning line drive circuit 564 because it can suppress unintended light leakage due to waveguide light or the like.
  • the substrate 202 and the substrate 203 are bonded to each other by the adhesive layer 174.
  • the conductive layer 565 is electrically connected to the FPC 162 via the conductive layer 255 and the connecting body 242.
  • the conductive layer 565 is preferably formed of the same material and the same process as the conductive layer of the transistor. In this embodiment, an example is shown in which the conductive layer 565 is formed of the same material and the same process as the conductive layer that functions as a source electrode and a drain electrode.
  • ACF Anisotropic Conducive Film
  • ACP Anisotropic Conducive Paste
  • FIG. 23 shows a cross-sectional view of a transmissive liquid crystal display device to which the vertical electric field method is applied.
  • the display device shown in FIG. 23 has a pixel unit 562 and a scanning line drive circuit 564.
  • a transistor 446d, a liquid crystal element 180, and the like are provided on the substrate 202.
  • a transistor 201d or the like is provided on the substrate 202.
  • the colored layer 205 is provided on the substrate 203 side.
  • the colored layer 205 may be provided on the substrate 202 side.
  • the transistor 446d has a conductive layer 221 that functions as a gate electrode, an insulating layer 211 that functions as a gate insulating layer, a semiconductor layer 231 and a conductive layer 222a and a conductive layer 222b that function as source electrodes and drain electrodes.
  • the transistor 446d is covered with an insulating layer 217 and an insulating layer 218.
  • the transistor 446d has a metal oxide in the semiconductor layer 231.
  • the liquid crystal element 180 has a pixel electrode 181 and a common electrode 182, and a liquid crystal layer 183.
  • the liquid crystal layer 183 is located between the pixel electrode 181 and the common electrode 182.
  • the alignment film 208a is provided in contact with the pixel electrode 181.
  • the alignment film 208b is provided in contact with the common electrode 182.
  • the pixel electrode 181 is electrically connected to the conductive layer 222b of the transistor 446d via the openings provided in the insulating layer 215, the insulating layer 218, and the insulating layer 217.
  • the alignment film can control the orientation of the liquid crystal layer 183.
  • the light from the backlight unit 552 is emitted to the outside of the display device via the substrate 202, the pixel electrode 181 and the liquid crystal layer 183, the common electrode 182, the colored layer 205, and the substrate 203.
  • a material that transmits visible light is used as the material of these layers through which the light of the backlight unit 552 is transmitted.
  • An overcoat 207 is provided between the light-shielding layer 206 and the common electrode 182, and between the colored layer 205 and the common electrode 182.
  • the overcoat 207 can prevent impurities contained in the colored layer 205, the light-shielding layer 206, and the like from diffusing into the liquid crystal layer 183.
  • the substrate 202 and the substrate 203 are bonded to each other by the adhesive layer 209.
  • the liquid crystal layer 183 is sealed in the region surrounded by the substrate 202, the substrate 203, and the adhesive layer 209.
  • the polarizing plate 204a and the polarizing plate 204b are arranged so as to sandwich the pixel portion 562 of the display device.
  • the light from the backlight unit 552 arranged outside the polarizing plate 204a is incident on the display device via the polarizing plate 204a.
  • the orientation of the liquid crystal layer 183 can be controlled by the voltage applied between the pixel electrode 181 and the common electrode 182, and the optical modulation of light can be controlled. That is, the intensity of the light emitted through the polarizing plate 204b can be controlled.
  • the incident light is absorbed by the colored layer 205 in a light other than the specific wavelength region, the emitted light is, for example, red, blue, or green.
  • the conductive layer 565 is electrically connected to the FPC 162 via the conductive layer 255 and the connecting body 242.
  • the liquid crystal display device is not limited to the vertical electric field method, but may be a horizontal electric field method.
  • a liquid crystal element to which the FFS (Fringe Field Switching) mode is applied may be used.
  • the crystallinity of the semiconductor material used for the transistor disclosed in one aspect of the present invention is not particularly limited, and is an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having a crystalline property other than a single crystal (microcrystalline semiconductor, polycrystalline semiconductor). , Or a semiconductor having a partially crystalline region) may be used. It is preferable to use a single crystal semiconductor or a semiconductor having crystallinity because deterioration of transistor characteristics can be suppressed.
  • a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used.
  • a typical example is a metal oxide containing indium, and for example, CAC-OS, which will be described later, can be used.
  • a transistor using a metal oxide having a wider bandgap and a smaller carrier density than silicon retains the charge accumulated in the capacitive element connected in series with the transistor for a long period of time due to its small off-current. Is possible.
  • silicon can be used as the semiconductor material used for the transistor. It is particularly preferable to use amorphous silicon as the silicon. By using amorphous silicon, a transistor can be formed on a large substrate with good yield, and mass productivity can be improved.
  • silicon having crystallinity such as microcrystalline silicon, polycrystalline silicon, and single crystal silicon can also be used.
  • polycrystalline silicon can be formed at a lower temperature than single crystal silicon, and has higher field effect mobility and higher reliability than amorphous silicon.
  • one display device may have two or more types of transistors having different semiconductor layer materials.
  • the metal oxide that can be used for the semiconductor layer of the transistor disclosed in one aspect of the present invention will be described.
  • the metal oxide may be read as an oxide semiconductor.
  • Oxide semiconductors are divided into single crystal oxide semiconductors and non-single crystal oxide semiconductors.
  • Examples of the non-single crystal oxide semiconductor include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystal oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudoamorphic oxide semiconductor (a-like). : Amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.
  • CAC-OS Cloud-Aligned Composite oxide semiconductor
  • CAC-OS Cloud-Aligned Composite oxide semiconductor
  • non-single crystal oxide semiconductor can be preferably used as the semiconductor layer of the transistor disclosed in one aspect of the present invention. Further, as the non-single crystal oxide semiconductor, nc-OS or CAAC-OS can be preferably used.
  • CAC-OS As the semiconductor layer of the transistor, it is preferable to use CAC-OS as the semiconductor layer of the transistor.
  • CAC-OS high electrical characteristics or high reliability can be imparted to the transistor.
  • CAC-OS The details of CAC-OS will be described below.
  • CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material.
  • the conductive function is the function of flowing electrons (or holes) to be carriers
  • the insulating function is the carrier. It is a function that does not allow electrons to flow.
  • CAC-OS or CAC-metal oxide has a conductive region and an insulating region.
  • the conductive region has the above-mentioned conductive function
  • the insulating region has the above-mentioned insulating function.
  • the conductive region and the insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.
  • CAC-OS or CAC-metal oxide when the conductive region and the insulating region are dispersed in the material in a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively. There is.
  • CAC-OS or CAC-metal oxide is composed of components having different band gaps.
  • CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region.
  • the carrier when the carrier is flown, the carrier mainly flows in the component having a narrow gap.
  • the component having a narrow gap acts complementarily to the component having a wide gap, and the carrier flows to the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel forming region of the transistor, a high current driving force, that is, a large on-current and a high field effect mobility can be obtained in the ON state of the transistor.
  • CAC-OS or CAC-metal oxide can also be referred to as a matrix composite material (matrix composite) or a metal matrix composite material (metal matrix composite).
  • CAC-OS is, for example, a composition of a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or a vicinity thereof.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or its vicinity.
  • the mixed state is also called a mosaic or patch.
  • the metal oxide preferably contains at least indium.
  • CAC-OS in In-Ga-Zn oxide is an indium oxide (hereinafter, InO).
  • InO indium oxide
  • X1 X1 is a real number larger than 0
  • In X2 Zn Y2 O Z2 X2, Y2, and Z2 are real numbers larger than 0
  • gallium With an oxide (hereinafter, GaO X3 (X3 is a real number larger than 0)) or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers larger than 0)).
  • Ga X4 Zn Y4 O Z4 X4, Y4, and Z4 are real numbers larger than 0
  • CAC-OS is a composite metal oxide having a structure in which a region containing GaO X3 as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component are mixed.
  • the atomic number ratio of In to the element M in the first region is larger than the atomic number ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the region 2.
  • IGZO is a common name and may refer to one compound consisting of In, Ga, Zn, and O. As a typical example, it is represented by InGaO 3 (ZnO) m1 (m1 is a natural number) or In (1 + x0) Ga (1-x0) O 3 (ZnO) m0 (-1 ⁇ x0 ⁇ 1, m0 is an arbitrary number). Crystalline compounds can be mentioned.
  • the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC (c-axis aligned crystalline) structure.
  • the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without orientation on the ab plane.
  • CAC-OS relates to the material composition of metal oxides.
  • CAC-OS is a region observed in the form of nanoparticles mainly composed of Ga in a material composition containing In, Ga, Zn, and O, and nanoparticles mainly composed of In. The regions observed in the shape are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.
  • CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component.
  • CAC-OS has a region observed in the form of nanoparticles mainly composed of the metal element and a nano portion containing In as a main component.
  • the regions observed in the form of particles refer to a configuration in which the regions are randomly dispersed in a mosaic pattern.
  • CAC-OS can be formed by a sputtering method, for example, under the condition that the substrate is not intentionally heated.
  • a sputtering method one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as the film forming gas. good.
  • the lower the flow rate ratio of the oxygen gas to the total flow rate of the film-forming gas at the time of film formation is preferable, and for example, the flow rate ratio of the oxygen gas is preferably 0% or more and less than 30%, preferably 0% or more and 10% or less. ..
  • CAC-OS is characterized by the fact that no clear peak is observed when measured using the ⁇ / 2 ⁇ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, from the X-ray diffraction measurement, it can be seen that the orientation of the measurement region in the ab plane direction and the c axis direction is not observed.
  • XRD X-ray diffraction
  • CAC-OS has an electron beam diffraction pattern obtained by irradiating an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam) in a ring-shaped region having high brightness and in the ring-shaped region. Multiple bright spots are observed. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
  • nc nano-crystal
  • CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IGZO compound. That is, the CAC-OS is phase-separated into a region containing GaO X3 or the like as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component, and a region containing each element as a main component. Has a mosaic-like structure.
  • the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component is a region having higher conductivity than the region in which GaO X3 or the like is the main component. That is, the conductivity as an oxide semiconductor is exhibited by the carrier flowing through the region where In X2 Zn Y2 O Z2 or InO X1 is the main component. Therefore, a high field effect mobility ( ⁇ ) can be realized by distributing the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component in the oxide semiconductor in a cloud shape.
  • the region in which GaO X3 or the like is the main component is a region having higher insulating properties than the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component. That is, since the region containing GaO X3 or the like as the main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be realized.
  • CAC-OS when CAC-OS is used for a semiconductor element, the insulation caused by GaO X3 and the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act in a complementary manner, resulting in a large effect. On current (Ion) and high field effect mobility ( ⁇ ) can be realized.
  • CAC-OS is most suitable for various semiconductor devices.
  • the electronic device of the present embodiment has a display system of one aspect of the present invention.
  • the display unit of the electronic device can display a high-quality image.
  • a large display device or a high-definition display device can realize good display quality.
  • the display unit of the electronic device of the present embodiment can display, for example, a full high-definition image having a resolution of 2K, 4K, 8K, 16K, or higher.
  • the screen size of the display unit can be 20 inches or more diagonally, 30 inches or more diagonally, 50 inches or more diagonally, 60 inches or more diagonally, or 70 inches or more diagonally.
  • Examples of electronic devices that can use the display system of one aspect of the present invention include television devices, desktop or notebook personal computers, monitors for computers, digital signage (electronic signage), and pachinko.
  • electronic devices with relatively large screens such as large game machines such as machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, mobile information terminals, sound reproduction devices, etc. can be mentioned. ..
  • the display system according to one aspect of the present invention can be suitably used for a portable electronic device, a wearable electronic device (wearable device), a VR (Virtual Reality) device, an AR (Augmented Reality) device, and the like. ..
  • the electronic device of one aspect of the present invention may have a secondary battery, and it is preferable that the secondary battery can be charged by using non-contact power transmission.
  • the secondary battery examples include a lithium ion secondary battery such as a lithium polymer battery (lithium ion polymer battery) using a gel-like electrolyte, a nickel hydrogen battery, a nicad battery, an organic radical battery, a lead storage battery, an air secondary battery, and nickel.
  • a lithium ion secondary battery such as a lithium polymer battery (lithium ion polymer battery) using a gel-like electrolyte, a nickel hydrogen battery, a nicad battery, an organic radical battery, a lead storage battery, an air secondary battery, and nickel.
  • Examples include zinc batteries and silver-zinc batteries.
  • the electronic device of one aspect of the present invention may have an antenna.
  • the display unit can display video or information.
  • the antenna may be used for non-contact power transmission.
  • the electronic device of one aspect of the present invention includes sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It may have the ability to detect, detect, or measure voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).
  • the electronic device of one aspect of the present invention can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function to display a date or time, a function to execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, and the like.
  • an electronic device having a plurality of display units a function of mainly displaying image information on one display unit and mainly displaying character information on another display unit, or parallax is considered on the plurality of display units.
  • a function of displaying a three-dimensional image or the like it is possible to have a function of displaying a three-dimensional image or the like.
  • a function of shooting a still image or a moving image, a function of automatically or manually correcting the shot image, and a function of saving the shot image in a recording medium (external or built in the electronic device). It is possible to have a function of displaying the captured image on the display unit and the like.
  • the functions of the electronic device of one aspect of the present invention are not limited to these, and can have various functions.
  • FIG. 24A shows the television device 1810.
  • the television device 1810 has a display unit 1811, a housing 1812, a speaker 1813, and the like. Further, it may have an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.
  • the television device 1810 can be operated by the remote controller 1814.
  • broadcast radio waves examples include terrestrial waves and radio waves transmitted from satellites. Further, as broadcast radio waves, there are analog broadcasting, digital broadcasting, etc., and there are also video and audio broadcasting, or audio-only broadcasting. For example, it is possible to receive broadcast radio waves transmitted in a specific frequency band within the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz). Further, for example, by using a plurality of data received in a plurality of frequency bands, the transfer rate can be increased and more information can be obtained. As a result, an image having a resolution exceeding full high-definition can be displayed on the display unit 1811. For example, it is possible to display an image having a resolution of 4K, 8K, 16K, or higher.
  • an image to be displayed on the display unit 1811 is generated using broadcast data transmitted by a data transmission technology via a computer network such as the Internet, LAN (Local Area Network), or Wi-Fi (registered trademark). It may be configured. At this time, the television device 1810 does not have to have a tuner.
  • a computer network such as the Internet, LAN (Local Area Network), or Wi-Fi (registered trademark). It may be configured.
  • the television device 1810 does not have to have a tuner.
  • FIG. 24B shows a digital signage 1820 attached to a columnar pillar 1822.
  • the digital signage 1820 has a display unit 1821.
  • the wider the display unit 1821 the more information can be provided at one time. Further, the wider the display unit 1821 is, the easier it is to be noticed by people, and for example, the advertising effect of the advertisement can be enhanced.
  • the touch panel By applying the touch panel to the display unit 1821, not only a still image or a moving image can be displayed on the display unit 1821, but also the user can intuitively operate the display unit 1821, which is preferable. In addition, when used for the purpose of providing information such as route information or traffic information, usability can be improved by intuitive operation.
  • FIG. 24C shows a notebook personal computer 1830.
  • the personal computer 1830 has a display unit 1831, a housing 1832, a touch pad 1833, a connection port 1834, and the like.
  • the touch pad 1833 functions as an input means for a pointing device, a pen tablet, or the like, and can be operated with a finger, a stylus, or the like.
  • the touch pad 1833 has a built-in display element. As shown in FIG. 24C, the touchpad 1833 can be used as a keyboard by displaying the input key 1835 on the surface of the touchpad 1833. At this time, a vibration module may be incorporated in the touch pad 1833 in order to realize a tactile sensation by vibration when the input key 1835 is touched.
  • FIG. 24D shows an example of a mobile information terminal.
  • the portable information terminal 1840 shown in FIG. 24D has a housing 1841, a display unit 1842, an operation button 1843, an external connection port 1844, a speaker 1845, a microphone 1846, a camera 1847, and the like.
  • the mobile information terminal 1840 is provided with a touch sensor on the display unit 1842. All operations such as making a phone call or entering characters can be performed by touching the display unit 1842 with a finger or a stylus.
  • the operation button 1843 by operating the operation button 1843, the power ON / OFF operation or the type of the image displayed on the display unit 1842 can be switched. For example, you can switch from the mail composition screen to the main menu screen.
  • the orientation (vertical or horizontal) of the mobile information terminal 1840 is determined, and the orientation of the screen display of the display unit 1842 is determined. It can be switched automatically. Further, the orientation of the screen display can be switched by touching the display unit 1842, operating the operation button 1843, voice input using the microphone 1846, or the like.
  • the mobile information terminal 1840 has one or more functions selected from, for example, a telephone, a notebook, an information browsing device, and the like. Specifically, it can be used as a smartphone.
  • the personal digital assistant 1840 can execute various applications such as mobile phone, e-mail, text viewing and creation, music playback, video playback, Internet communication, and games.
  • the mobile information terminal 1850 has a housing 1851, a housing 1852, a display unit 1853, a display unit 1854, a hinge unit 1855, and the like.
  • the housing 1851 and the housing 1852 are connected by a hinge portion 1855.
  • the mobile information terminal 1850 can open the housing 1851 and the housing 1852 as shown in FIG. 24F from the folded state as shown in FIG. 24E.
  • document information can be displayed on the display unit 1853 and the display unit 1854, and can also be used as an electronic book terminal. Further, a still image or a moving image can be displayed on the display unit 1853 and the display unit 1854.
  • the mobile information terminal 1850 is excellent in versatility because it can be folded when it is carried.
  • the housing 1851 and the housing 1852 may have a power button, an operation button, an external connection port, a speaker, a microphone, and the like.

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Abstract

Provided is a display system that has high display quality. Provided is a display system that has low power consumption. A display system that has a processing unit, a display unit, and a storage unit. The storage unit holds correction data. The correction data and a first image signal are supplied to the processing unit. The processing unit uses the first image signal to generate a second image signal. The processing unit also generates a correction signal on the basis of the correction data. The display unit has pixels that include a display element and a storage circuit. The second image signal and the correction signal are supplied to the pixels. The storage circuits hold the correction signal. The storage unit includes: a capacitive element that has a ferroelectric layer; and a transistor that is electrically connected to the capacitive element.

Description

表示システムDisplay system
　本発明の一態様は、表示システムに関する。 One aspect of the present invention relates to a display system.
　なお、本発明の一態様は、上記の技術分野に限定されない。本発明の一態様の技術分野としては、半導体装置、表示装置、発光装置、蓄電装置、記憶装置、電子機器、照明装置、入力装置（例えば、タッチセンサなど）、入出力装置（例えば、タッチパネルなど）、それらの駆動方法、またはそれらの製造方法を一例として挙げることができる。 Note that one aspect of the present invention is not limited to the above technical fields. The technical fields of one aspect of the present invention include semiconductor devices, display devices, light emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices (for example, touch sensors, etc.), input / output devices (for example, touch panels, etc.). ), Their driving method, or their manufacturing method can be given as an example.
　なお、本明細書等において、半導体装置とは、半導体特性を利用することで機能しうる装置全般を指す。表示装置（液晶表示装置、発光表示装置など）、投影装置、照明装置、電気光学装置、蓄電装置、記憶装置、半導体回路、撮像装置、及び電子機器などは、半導体装置といえる場合がある。もしくは、これらは半導体装置を有するといえる場合がある。 In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. Display devices (liquid crystal display devices, light emission display devices, etc.), projection devices, lighting devices, electro-optic devices, power storage devices, storage devices, semiconductor circuits, image pickup devices, electronic devices, and the like may be said to be semiconductor devices. Alternatively, they may be said to have semiconductor devices.
　近年、解像度の高い表示装置が求められている。例えば、フルハイビジョン（画素数１９２０×１０８０）、４Ｋ（画素数３８４０×２１６０もしくは４０９６×２１６０等）、さらには８Ｋ（画素数７６８０×４３２０もしくは８１９２×４３２０等）といった画素数の多い表示装置が盛んに開発されている。 In recent years, there has been a demand for high-resolution display devices. For example, display devices with a large number of pixels such as full high definition (number of pixels 1920 × 1080), 4K (number of pixels 3840 × 2160 or 4096 × 2160, etc.), and 8K (number of pixels 7680 × 4320 or 8192 × 4320, etc.) are popular. Has been developed in.
　また、表示装置の大型化が求められている。例えば、家庭用のテレビジョン装置では、画面サイズが対角５０インチを超えるものが主流となっている。画面のサイズが大きいほど、一度に表示可能な情報量を多くできるため、デジタルサイネージ等では更なる大画面化が求められている。 In addition, there is a demand for larger display devices. For example, most household television devices have a screen size of more than 50 inches diagonally. The larger the screen size, the larger the amount of information that can be displayed at one time. Therefore, digital signage and the like are required to have a larger screen.
　表示装置としては、液晶ディスプレイ及び有機ＥＬディスプレイに代表されるフラットパネルディスプレイが広く用いられている。これらの表示装置を構成するトランジスタの半導体材料には主にシリコンが用いられているが、近年、金属酸化物を用いたトランジスタを表示装置の画素に用いる技術も開発されている。 As a display device, a flat panel display represented by a liquid crystal display and an organic EL display is widely used. Silicon is mainly used as the semiconductor material of the transistors constituting these display devices, but in recent years, a technique of using a transistor using a metal oxide as a pixel of the display device has also been developed.
　特許文献１には、トランジスタの半導体材料に非晶質シリコンを用いる技術が開示されている。特許文献２及び特許文献３には、トランジスタの半導体材料に金属酸化物を用いる技術が開示されている。 Patent Document 1 discloses a technique of using amorphous silicon as a semiconductor material for a transistor. Patent Document 2 and Patent Document 3 disclose a technique of using a metal oxide as a semiconductor material of a transistor.
特開２００１−５３２８３号公報Japanese Unexamined Patent Publication No. 2001-53283 特開２００７−１２３８６１号公報Japanese Unexamined Patent Publication No. 2007-123861 特開２００７−９６０５５号公報Japanese Unexamined Patent Publication No. 2007-96055
　８Ｋなどに対応した高解像度の映像はデータ量が多いため、放送局から受信機へデータの送信を行う際の通信負荷が大きい。また、高解像度の映像を一般に普及させるためには、撮像装置、記憶装置、通信装置などの周辺技術を整える必要もある。例えば、放送局がデータ量の少ない低解像度の映像を放送し、当該放送を受信した受信機側で解像度を高める技術が必要とされている。 Since the amount of data in high-resolution video compatible with 8K etc. is large, the communication load when transmitting data from the broadcasting station to the receiver is large. Further, in order to popularize high-resolution images to the general public, it is necessary to prepare peripheral technologies such as an image pickup device, a storage device, and a communication device. For example, there is a need for a technique in which a broadcasting station broadcasts a low-resolution video with a small amount of data and the receiver that receives the broadcast increases the resolution.
　例えば、アップコンバートを行うことで、低解像度の映像を疑似的に高解像度の映像に変換することができる。しかし、アップコンバートを行う際に、膨大な量の画像データを解析して新たな画像データを生成するため、回路規模及び消費電力の一方又は双方が大きくなる問題がある。また、リアルタイムでの処理が追いつかず、表示の遅延が生じることもある。 For example, by performing up-conversion, it is possible to pseudo-convert a low-resolution video into a high-resolution video. However, when up-converting, a huge amount of image data is analyzed to generate new image data, so that there is a problem that one or both of the circuit scale and the power consumption become large. In addition, real-time processing may not be able to keep up, and display delays may occur.
　また、表示装置の画素数が多いほど、表示装置が有するトランジスタ及び表示素子の数が増えるため、トランジスタの特性のばらつき及び表示素子の特性のばらつきに起因する表示ムラが顕著になってしまう。 Further, as the number of pixels of the display device increases, the number of transistors and display elements of the display device increases, so that the variation in the characteristics of the transistor and the variation in the characteristics of the display element become remarkable.
　本発明の一態様は、表示品位の高い表示システムを提供することを課題の一つとする。本発明の一態様は、消費電力が低い表示システムを提供することを課題の一つとする。本発明の一態様は、解像度の高い表示システムを提供することを課題の一つとする。本発明の一態様は、表示ムラが低減された表示システムを提供することを課題の一つとする。本発明の一態様は、大型の表示領域を有する表示システムを提供することを課題の一つとする。本発明の一態様は、高いフレーム周波数で動作可能な表示システムを提供することを課題の一つとする。 One aspect of the present invention is to provide a display system with high display quality. One aspect of the present invention is to provide a display system having low power consumption. One aspect of the present invention is to provide a display system having a high resolution. One of the problems of one aspect of the present invention is to provide a display system in which display unevenness is reduced. One aspect of the present invention is to provide a display system having a large display area. One aspect of the present invention is to provide a display system that can operate at a high frame frequency.
　なお、これらの課題の記載は、他の課題の存在を妨げるものではない。本発明の一態様は、必ずしも、これらの課題の全てを解決する必要はないものとする。明細書、図面、請求項の記載から、これら以外の課題を抽出することが可能である。 The description of these issues does not prevent the existence of other issues. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract problems other than these from the description, drawings, and claims.
　本発明の一態様は、処理部、表示部、及び記憶部を有する表示システムである。記憶部は、補正データを有する。処理部には、第１の画像信号及び補正データが供給される。また処理部は、第１の画像信号を用いて、第２の画像信号を生成する機能を有する。また処理部は、補正データに基づいた補正信号を生成する機能を有する。表示部は、画素を有し、画素は、表示素子及び記憶回路を有する。また、画素には、第２の画像信号及び補正信号が供給される。記憶回路は、補正信号を保持する機能を有する。また、記憶部は、強誘電体層を有する容量素子と、容量素子と電気的に接続するトランジスタと、を有する。 One aspect of the present invention is a display system having a processing unit, a display unit, and a storage unit. The storage unit has correction data. The first image signal and correction data are supplied to the processing unit. Further, the processing unit has a function of generating a second image signal by using the first image signal. Further, the processing unit has a function of generating a correction signal based on the correction data. The display unit has pixels, and the pixels have a display element and a storage circuit. Further, a second image signal and a correction signal are supplied to the pixels. The storage circuit has a function of holding a correction signal. Further, the storage unit includes a capacitive element having a ferroelectric layer and a transistor electrically connected to the capacitive element.
　また、本発明の他の一態様は、処理部、表示部、及び記憶部を有する表示システムである。記憶部は、補正データを有する。処理部には、第１の画像信号及び補正データが供給される。処理部は、第１の画像信号を用いて、第２の画像信号を生成する機能を有する。また処理部は、第１の画像信号及び補正データを用いて、補正信号を生成する機能を有する。表示部は、画素を有し、画素は、表示素子及び記憶回路を有する。画素には、第２の画像信号及び補正信号が供給される。記憶回路は、補正信号を保持する機能を有する。また、記憶部は、強誘電体層を有する容量素子と、容量素子と電気的に接続するトランジスタと、を有する。 Further, another aspect of the present invention is a display system having a processing unit, a display unit, and a storage unit. The storage unit has correction data. The first image signal and correction data are supplied to the processing unit. The processing unit has a function of generating a second image signal by using the first image signal. Further, the processing unit has a function of generating a correction signal by using the first image signal and the correction data. The display unit has pixels, and the pixels have a display element and a storage circuit. A second image signal and a correction signal are supplied to the pixels. The storage circuit has a function of holding a correction signal. Further, the storage unit includes a capacitive element having a ferroelectric layer and a transistor electrically connected to the capacitive element.
　また、本発明の他の一態様は、処理部、表示部、及び記憶部を有する表示システムである。記憶部は、補正データを有する。表示部は、第１の回路及び画素を有する。第１の回路は、第１の信号を生成する機能を有する。処理部には、第１の画像信号、第１の信号及び補正データが供給される。処理部は、第１の画像信号を用いて、第２の画像信号を生成する機能を有する。さらに、処理部は、第１の信号及び補正データを用いて、補正信号を生成する機能を有する。画素は、表示素子及び記憶回路を有する。画素には、第２の画像信号及び補正信号が供給される。記憶回路は、補正信号を保持する機能を有する。記憶部は、強誘電体層を有する容量素子と、容量素子と電気的に接続するトランジスタと、を有する。 Further, another aspect of the present invention is a display system having a processing unit, a display unit, and a storage unit. The storage unit has correction data. The display unit has a first circuit and pixels. The first circuit has a function of generating a first signal. A first image signal, a first signal, and correction data are supplied to the processing unit. The processing unit has a function of generating a second image signal by using the first image signal. Further, the processing unit has a function of generating a correction signal by using the first signal and the correction data. The pixel has a display element and a storage circuit. A second image signal and a correction signal are supplied to the pixels. The storage circuit has a function of holding a correction signal. The storage unit includes a capacitive element having a ferroelectric layer and a transistor electrically connected to the capacitive element.
　また、上記いずれかにおいて、処理部は、ニューラルネットワークを用いて、第２の画像信号及び補正信号のうち一方または双方を生成することが好ましい。または、処理部は、ニューラルネットワーク回路を有することが好ましい。 Further, in any of the above, it is preferable that the processing unit generates one or both of the second image signal and the correction signal by using the neural network. Alternatively, the processing unit preferably has a neural network circuit.
　また、上記いずれかにおいて、強誘電体層は、ハフニウム及びジルコニウムの一方または双方を含む酸化物を有することが好ましい。 Further, in any of the above, the ferroelectric layer preferably has an oxide containing one or both of hafnium and zirconium.
　また、上記いずれかにおいて、強誘電体層に含まれる、水素、炭化水素、及び炭素の少なくとも一つの濃度は、ＳＩＭＳ分析において、５×１０２０ａｔｏｍｓ／ｃｍ３以下、または、１×１０２０ａｔｏｍｓ／ｃｍ３以下であることが好ましい。 Further, in any of the above, the concentration of at least one of hydrogen, hydrocarbon, and carbon contained in the ferroelectric layer is 5 × 10 20 atoms / cm 3 or less, or 1 × 10 20 atoms in SIMS analysis. It is preferably / cm 3 or less.
　また、上記いずれかにおいて、トランジスタは、チャネル形成領域にシリコンを有することが好ましい。または、トランジスタは、チャネル形成領域に酸化物半導体を有することが好ましい。 Further, in any of the above, it is preferable that the transistor has silicon in the channel forming region. Alternatively, the transistor preferably has an oxide semiconductor in the channel forming region.
　本発明の一態様により、解像度の高い表示システムを提供できる。本発明の一態様により、表示品位の高い表示システムを提供できる。本発明の一態様により、消費電力が低い表示システムを提供できる。本発明の一態様により、表示ムラが低減された表示システムを提供できる。本発明の一態様により、大型の表示領域を有する表示システムを提供できる。本発明の一態様により、高いフレーム周波数で動作可能な表示システムを提供できる。 According to one aspect of the present invention, a display system with high resolution can be provided. According to one aspect of the present invention, it is possible to provide a display system having high display quality. According to one aspect of the present invention, it is possible to provide a display system having low power consumption. According to one aspect of the present invention, it is possible to provide a display system in which display unevenness is reduced. According to one aspect of the present invention, it is possible to provide a display system having a large display area. According to one aspect of the present invention, it is possible to provide a display system capable of operating at a high frame frequency.
　なお、これらの効果の記載は、他の効果の存在を妨げるものではない。本発明の一態様は、必ずしも、これらの効果の全てを有する必要はない。明細書、図面、請求項の記載から、これら以外の効果を抽出することが可能である。 The description of these effects does not prevent the existence of other effects. One aspect of the invention does not necessarily have to have all of these effects. It is possible to extract effects other than these from the description, drawings, and claims.
図１Ａ、図１Ｂは表示システムの一例を示す図である。
図２Ａ、図２Ｂはアップコンバートを説明する図である。
図３はアップコンバートの比較例を説明する図である。
図４Ａ、図４Ｂ、図４Ｃは表示システムの一例を示す図である。
図５Ａ、図５Ｂ、図５Ｃ、図５Ｄ、図５Ｅ、図５Ｆは表示システムの一例を示す図である。
図６は表示部の一例を示すブロック図である。
図７Ａ、図７Ｃ、及び図７Ｄは、表示装置の回路図である。図７Ｂは、タイミングチャートである。
図８Ａ、図８Ｂは表示システムの一例を示す図である。
図９は表示部の一例を示すブロック図である。
図１０Ａは、記憶装置の一例を示すブロック図である。図１０Ｂは、記憶装置の一例を示す斜視図である。
図１１Ａは、メモリセルの一例を示す回路図である。図１１Ｂは、強誘電体層のヒステリシス特性の一例を示すグラフである。
図１２は、メモリセルの駆動方法の一例を示すタイミングチャートである。
図１３Ａ１、図１３Ｂ１、及び図１３Ｃ１は、強誘電体メモリの一例を示す回路図である。図１３Ａ２、図１３Ｂ２、及び図１３Ｃ２乃至図１３Ｃ４は、強誘電体メモリの一例を示す断面図である。
図１４Ａ乃至図１４Ｃは、容量素子の作製方法の一例を示す断面図である。
図１５は、酸化ハフニウムの結晶構造を説明するモデル図である。
図１６は、金属酸化物膜の成膜シーケンスの一例を示す図である。
図１７Ａは、金属酸化物膜の製造装置の一例を示す断面図である。図１７Ｂは、ＨｆＺｒＯＸの結晶構造のモデル図である。
図１８Ａ、図１８Ｂはニューラルネットワークの構成例を説明する図である。
図１９は半導体装置の構成例を説明する図である。
図２０はメモリセルの構成例を説明する図である。
図２１Ａ、図２１Ｂ、図２１Ｃ、図２１Ｄ、図２１Ｅは画素の一例を示す図である。
図２２は表示装置の一例を示す図である。
図２３は表示装置の一例を示す図である。
図２４Ａ、図２４Ｂ、図２４Ｃ、図２４Ｄ、図２４Ｅ、図２４Ｆは電子機器の一例を示す図である。 1A and 1B are diagrams showing an example of a display system.
2A and 2B are diagrams illustrating up-conversion.
FIG. 3 is a diagram illustrating a comparative example of up-conversion.
4A, 4B, and 4C are diagrams showing an example of a display system.
5A, 5B, 5C, 5D, 5E, and 5F are diagrams showing an example of a display system.
FIG. 6 is a block diagram showing an example of the display unit.
7A, 7C, and 7D are circuit diagrams of the display device. FIG. 7B is a timing chart.
8A and 8B are diagrams showing an example of a display system.
FIG. 9 is a block diagram showing an example of the display unit.
FIG. 10A is a block diagram showing an example of a storage device. FIG. 10B is a perspective view showing an example of a storage device.
FIG. 11A is a circuit diagram showing an example of a memory cell. FIG. 11B is a graph showing an example of the hysteresis characteristics of the ferroelectric layer.
FIG. 12 is a timing chart showing an example of a memory cell driving method.
13A1, 13B1 and 13C1 are circuit diagrams showing an example of a ferroelectric memory. 13A2, 13B2, and 13C2 to 13C4 are cross-sectional views showing an example of a ferroelectric memory.
14A to 14C are cross-sectional views showing an example of a method for manufacturing a capacitive element.
FIG. 15 is a model diagram illustrating the crystal structure of hafnium oxide.
FIG. 16 is a diagram showing an example of a film formation sequence of a metal oxide film.
FIG. 17A is a cross-sectional view showing an example of a metal oxide film manufacturing apparatus. FIG. 17B is a model diagram of the crystal structure of HfZrOX .
18A and 18B are diagrams illustrating a configuration example of a neural network.
FIG. 19 is a diagram illustrating a configuration example of a semiconductor device.
FIG. 20 is a diagram illustrating a configuration example of a memory cell.
21A, 21B, 21C, 21D, and 21E are diagrams showing an example of pixels.
FIG. 22 is a diagram showing an example of a display device.
FIG. 23 is a diagram showing an example of a display device.
24A, 24B, 24C, 24D, 24E, and 24F are diagrams showing an example of an electronic device.
　実施の形態について、図面を用いて詳細に説明する。但し、本発明は以下の説明に限定されず、本発明の趣旨及びその範囲から逸脱することなくその形態及び詳細を様々に変更し得ることは当業者であれば容易に理解される。従って、本発明は以下に示す実施の形態の記載内容に限定して解釈されるものではない。 The embodiment will be described in detail using drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below.
　なお、以下に説明する発明の構成において、同一部分または同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する。また、同様の機能を指す場合には、ハッチパターンを同じくし、特に符号を付さない場合がある。 In the configuration of the invention described below, the same reference numerals are commonly used between different drawings for the same parts or parts having similar functions, and the repeated description thereof will be omitted. Further, when referring to the same function, the hatch pattern may be the same and no particular reference numeral may be added.
　また、図面において示す各構成の、位置、大きさ、範囲などは、理解の簡単のため、実際の位置、大きさ、範囲などを表していない場合がある。このため、開示する発明は、必ずしも、図面に開示された位置、大きさ、範囲などに限定されない。 In addition, the position, size, range, etc. of each configuration shown in the drawing may not represent the actual position, size, range, etc. for the sake of easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range and the like disclosed in the drawings.
　なお、「膜」という言葉と、「層」という言葉とは、場合によっては、または、状況に応じて、互いに入れ替えることが可能である。例えば、「導電層」という用語を、「導電膜」という用語に変更することが可能である。または、例えば、「絶縁膜」という用語を、「絶縁層」という用語に変更することが可能である。 The word "membrane" and the word "layer" can be interchanged with each other in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". Alternatively, for example, the term "insulating film" can be changed to the term "insulating layer".
（実施の形態１）
　本実施の形態では、本発明の一態様の表示システムについて図１~図９を用いて説明する。 (Embodiment 1)
In the present embodiment, the display system of one aspect of the present invention will be described with reference to FIGS. 1 to 9.
　本実施の形態の表示システムは、補正信号を生成する機能と、外部から受信したデータを用いて画像信号を生成する機能と、当該補正信号及び当該画像信号を用いて、映像を表示する機能と、を有する。 The display system of the present embodiment has a function of generating a correction signal, a function of generating an image signal using data received from the outside, and a function of displaying an image using the correction signal and the image signal. , Have.
　本実施の形態の表示システムは、処理部及び表示部を有する。処理部は、補正信号を生成する機能と、外部から受信したデータを用いて画像信号を生成する機能と、を有する。表示部は、表示素子及び記憶回路を有する。記憶回路は、補正信号を保持する機能を有する。記憶回路は、画像信号に補正信号を付加する機能を有する。補正信号は容量結合によって画像信号に付加され、表示素子に供給される。したがって、表示部では、補正信号及び画像信号を用いて、映像を表示することができる。 The display system of the present embodiment has a processing unit and a display unit. The processing unit has a function of generating a correction signal and a function of generating an image signal using data received from the outside. The display unit includes a display element and a storage circuit. The storage circuit has a function of holding a correction signal. The storage circuit has a function of adding a correction signal to the image signal. The correction signal is added to the image signal by capacitive coupling and supplied to the display element. Therefore, the display unit can display an image using the correction signal and the image signal.
　表示システムでは、外部から受信したデータに対して様々な画像処理を行うことができる。しかしながら、特に解像度のアップコンバートを行う場合では、処理部で行う演算量は膨大となる。そこで、本発明の一態様の表示システムは、処理部において、補正信号と、画像信号と、を生成する。外部から受信したデータに画像処理を施して生成する画像信号は、外部から受信したデータと同等の解像度のデータを含む信号とする。そして、別途生成した補正信号を、当該画像信号に付加することで、画像のアップコンバートを行う。これにより、処理部における演算量の低減、消費電力の低減、回路規模の縮小、または表示の遅延の抑制などを実現することができる。 The display system can perform various image processing on the data received from the outside. However, especially in the case of up-converting the resolution, the amount of calculation performed by the processing unit becomes enormous. Therefore, the display system of one aspect of the present invention generates a correction signal and an image signal in the processing unit. The image signal generated by performing image processing on the data received from the outside is a signal including data having the same resolution as the data received from the outside. Then, the image is up-converted by adding the separately generated correction signal to the image signal. As a result, it is possible to reduce the amount of calculation in the processing unit, reduce the power consumption, reduce the circuit scale, suppress the display delay, and the like.
　処理部は、外部から受信したデータなどを用いて、リアルタイムで補正信号を生成してもよく、記録媒体に保存されている補正データを読み出し、当該補正データに基づいた補正信号を生成してもよい。外部から受信したデータによらず、補正データに基づいた補正信号を表示部に供給することで、処理部における演算量の低減を図ることができる。 The processing unit may generate a correction signal in real time using data received from the outside, or may read the correction data stored in the recording medium and generate a correction signal based on the correction data. good. By supplying the correction signal based on the correction data to the display unit regardless of the data received from the outside, it is possible to reduce the amount of calculation in the processing unit.
　なお、補正信号は、アップコンバート以外の目的でも使用することができる。例えば、補正信号を用いて、画素が有するトランジスタの特性のばらつきに起因する表示ムラを補正することができる。このように、補正信号を用いることで、画像信号の生成に係る処理部の負荷を低減することができる。 The correction signal can be used for purposes other than up-conversion. For example, the correction signal can be used to correct display unevenness caused by variations in the characteristics of the transistors of the pixels. In this way, by using the correction signal, it is possible to reduce the load on the processing unit related to the generation of the image signal.
　また、本発明の一態様の表示システムは、処理部のほかに、記憶部を有することが好ましい。記憶部は、表示システムが扱う様々なデータを保持する機能を有する。さらに記憶部は、誘電体層に強誘電体を用いた、強誘電体メモリを適用することが好ましい。特に、誘電体層にハフニウムまたはジルコニウムの一方または双方を含む強誘電体を用いることが好ましい。これにより、処理部が有する記憶部として、高速な読出し及び高速な書込みを実現することができる。さらには、高いデータ保持特性と、高い書き換え耐性とを兼ね備えた記憶部とすることができる。これにより、高速処理が可能で、信頼性の高い表示システムを実現することができる。 Further, it is preferable that the display system of one aspect of the present invention has a storage unit in addition to the processing unit. The storage unit has a function of holding various data handled by the display system. Further, as the storage unit, it is preferable to apply a ferroelectric memory in which a ferroelectric layer is used for the dielectric layer. In particular, it is preferable to use a ferroelectric layer containing one or both of hafnium and zirconium in the dielectric layer. As a result, high-speed reading and high-speed writing can be realized as a storage unit possessed by the processing unit. Further, the storage unit can have both high data retention characteristics and high rewrite resistance. As a result, high-speed processing is possible and a highly reliable display system can be realized.
＜表示システムの構成例１＞
　図１Ａに、表示システム１００Ａのブロック図を示す。 <Display system configuration example 1>
FIG. 1A shows a block diagram of the display system 100A.
　表示システム１００Ａは、制御部１５１、記憶部１５２、処理部１５３、入出力部１５４、通信部１５５、及び表示部１５６を有する。他に、タッチセンサ、タッチセンサ制御部、バッテリ、バッテリコントローラ、受電部、アンテナ、撮像部、振動部などを有してもよい。制御部１５１、記憶部１５２、処理部１５３、入出力部１５４、通信部１５５、及び表示部１５６等は、バスライン１５７を介して互いに電気的に接続される。 The display system 100A has a control unit 151, a storage unit 152, a processing unit 153, an input / output unit 154, a communication unit 155, and a display unit 156. In addition, it may have a touch sensor, a touch sensor control unit, a battery, a battery controller, a power receiving unit, an antenna, an image pickup unit, a vibration unit, and the like. The control unit 151, the storage unit 152, the processing unit 153, the input / output unit 154, the communication unit 155, the display unit 156, and the like are electrically connected to each other via the bus line 157.
　図１Ｂを用いて、表示システム１００Ａにおける画像信号Ｓ２と補正信号Ｗ２の生成について説明する。 The generation of the image signal S2 and the correction signal W2 in the display system 100A will be described with reference to FIG. 1B.
　通信部１５５は、外部から受信したデータに基づいた画像信号Ｓ１を処理部１５３に供給する。処理部１５３は、画像信号Ｓ１に含まれるデータに対して画像処理を行い、画像信号Ｓ２を生成する。画像信号Ｓ２は、処理部１５３から表示部１５６に供給される。 The communication unit 155 supplies the image signal S1 based on the data received from the outside to the processing unit 153. The processing unit 153 performs image processing on the data included in the image signal S1 to generate the image signal S2. The image signal S2 is supplied from the processing unit 153 to the display unit 156.
　処理部１５３は、人工知能（ＡＩ：Ａｒｔｉｆｉｃｉａｌ　Ｉｎｔｅｌｌｉｇｅｎｃｅ）を利用して画像信号Ｓ２を生成する機能を有することが好ましい。これにより、表示部１５６における表示品位を高めることができる。 It is preferable that the processing unit 153 has a function of generating an image signal S2 by using artificial intelligence (AI: Artificial Intelligence). Thereby, the display quality in the display unit 156 can be improved.
　なお、人工知能とは、人間の知能を模した計算機である。処理部１５３には、例えば、人工ニューラルネットワーク（ＡＮＮ：Ａｒｔｉｆｉｃｉａｌ　Ｎｅｕｒａｌ　Ｎｅｔｗｏｒｋ）を用いることができる。人工ニューラルネットワークとは、ニューロンとシナプスで構成される神経網を模した回路であり、人工ニューラルネットワークは人工知能の一種である。本明細書等において「ニューラルネットワーク」と記載する場合、特に人工ニューラルネットワークを指す。 Artificial intelligence is a computer that imitates human intelligence. For the processing unit 153, for example, an artificial neural network (ANN: Artificial Neural Network) can be used. An artificial neural network is a circuit that imitates a neural network composed of neurons and synapses, and an artificial neural network is a kind of artificial intelligence. When the term "neural network" is used in the present specification and the like, it particularly refers to an artificial neural network.
　図１Ａ、図１Ｂでは、処理部１５３は、ニューラルネットワーク１５９を有する例を示す。 1A and 1B show an example in which the processing unit 153 has a neural network 159.
　画像信号Ｓ１に含まれるデータに対して行う画像処理の例としては、ノイズ除去処理、階調変換処理、色調補正処理、または輝度補正処理などが挙げられる。色調補正処理、及び輝度補正処理は、ガンマ補正などを用いて行うことができる。また、処理部１５３は、フレーム周波数のアップコンバートに伴うフレーム間補間処理などを実行する機能を有していてもよい。 Examples of image processing performed on the data included in the image signal S1 include noise reduction processing, gradation conversion processing, color tone correction processing, and luminance correction processing. The color tone correction process and the luminance correction process can be performed by using gamma correction or the like. Further, the processing unit 153 may have a function of executing interpolation processing between frames accompanying the up-conversion of the frame frequency.
　ノイズ除去処理としては、文字などの輪郭の周辺に生じるモスキートノイズ、高速の動画で生じるブロックノイズ、ちらつきを生じさせるランダムノイズ、解像度のアップコンバートにより生じるドットノイズなどのさまざまなノイズの除去が挙げられる。 Noise reduction processing includes removal of various noises such as mosquito noise that occurs around contours such as characters, block noise that occurs in high-speed moving images, random noise that causes flicker, and dot noise that occurs due to resolution up-conversion. ..
　階調変換処理は、画像信号Ｓ１が有する画像データが示す階調を表示部１５６の出力特性に対応した階調へ変換する処理である。例えば階調数を大きくする場合、小さい階調数で入力された画像に対して、各画素に対応する階調値を補間して割り当てることで、ヒストグラムを平滑化する処理を行うことができる。また、ダイナミックレンジを広げる、ハイダイナミックレンジ（ＨＤＲ）処理も、階調変換処理に含まれる。 The gradation conversion process is a process of converting the gradation indicated by the image data of the image signal S1 into the gradation corresponding to the output characteristics of the display unit 156. For example, when increasing the number of gradations, it is possible to perform a process of smoothing the histogram by interpolating and assigning gradation values corresponding to each pixel to an image input with a small number of gradations. In addition, high dynamic range (HDR) processing that widens the dynamic range is also included in the gradation conversion processing.
　色調補正処理は、映像の色調を補正する処理である。また輝度補正処理は、映像の明るさ（輝度コントラスト）を補正する処理である。例えば、表示部１５６が設けられる空間の照明の種類、輝度、または色純度などに応じて、表示部１５６に表示される映像の輝度または色調が最適となるように補正される。 The color tone correction process is a process for correcting the color tone of an image. The luminance correction process is a process for correcting the brightness (luminance contrast) of an image. For example, the brightness or color tone of the image displayed on the display unit 156 is corrected so as to be optimum according to the type, brightness, color purity, and the like of the space in which the display unit 156 is provided.
　フレーム間補間処理は、表示する映像のフレーム周波数を増大させる場合に、本来存在しないフレーム（補間フレーム）の画像を生成する処理である。例えば、ある２枚の画像の差分から２枚の画像の間に挿入する補間フレームの画像を生成する。または２枚の画像の間に複数枚の補間フレームの画像を生成することもできる。例えば画像データのフレーム周波数が６０Ｈｚであったとき、複数枚の補間フレームを生成することで、表示部１５６に出力される画像信号のフレーム周波数を、２倍の１２０Ｈｚ、４倍の２４０Ｈｚ、または８倍の４８０Ｈｚなどに増大させることができる。 The interpolation process between frames is a process of generating an image of a frame (interpolation frame) that does not originally exist when the frame frequency of the image to be displayed is increased. For example, an image of an interpolated frame to be inserted between two images is generated from the difference between two images. Alternatively, it is possible to generate an image of a plurality of interpolation frames between two images. For example, when the frame frequency of the image data is 60 Hz, the frame frequency of the image signal output to the display unit 156 is doubled to 120 Hz, quadrupled to 240 Hz, or 8 by generating a plurality of interpolated frames. It can be doubled to 480 Hz or the like.
　また、処理部１５３には、記憶部１５２から補正データＷ１が供給される。処理部１５３は、補正データＷ１に基づいた補正信号Ｗ２を生成する。補正信号Ｗ２は、処理部１５３から表示部１５６に供給される。 Further, the correction data W1 is supplied to the processing unit 153 from the storage unit 152. The processing unit 153 generates a correction signal W2 based on the correction data W1. The correction signal W2 is supplied from the processing unit 153 to the display unit 156.
　補正データＷ１は、事前に、人工知能を利用して生成されたデータであることが好ましい。 The correction data W1 is preferably data generated in advance using artificial intelligence.
　当該補正データＷ１を用いて生成した補正信号Ｗ２を、画像信号Ｓ２に付加することで、例えば、画像のアップコンバートを行うことができる。または、画素が有するトランジスタの特性のばらつきに起因する表示ムラを補正することができる。 By adding the correction signal W2 generated by using the correction data W1 to the image signal S2, for example, an image can be up-converted. Alternatively, it is possible to correct display unevenness caused by variations in the characteristics of the transistors of the pixels.
　図２及び図３を用いて、本発明の一態様の表示システムにおけるアップコンバートと、比較例のアップコンバートと、について説明する。 The up-conversion in the display system of one aspect of the present invention and the up-conversion of the comparative example will be described with reference to FIGS. 2 and 3.
　画像信号Ｓ１をアップコンバートせずに画像信号Ｓ２を生成し、かつ、補正信号Ｗ２も用いない場合、低解像度の画像データを高解像度の表示部１５６で表示しようとすると、複数の画素に同じ画像信号が供給されることになる。例えば、８Ｋ４Ｋの表示装置の画素数は、４Ｋ２Ｋの表示装置の画素数（３８４０×２１６０）の４倍である。つまり、４Ｋ２Ｋの表示装置の画像データを単純に８Ｋ４Ｋの表示装置で表示しようとすると、４Ｋ２Ｋの表示装置の１画素に供給される画像信号が、８Ｋ４Ｋの表示装置の４画素に供給されることになる。 When the image signal S2 is generated without up-converting the image signal S1 and the correction signal W2 is not used, when the low resolution image data is to be displayed on the high resolution display unit 156, the same image is displayed on a plurality of pixels. The signal will be supplied. For example, the number of pixels of the 8K4K display device is four times the number of pixels of the 4K2K display device (3840 × 2160). That is, when the image data of the 4K2K display device is simply displayed on the 8K4K display device, the image signal supplied to one pixel of the 4K2K display device is supplied to the four pixels of the 8K4K display device. Become.
　図３は、比較例における、水平垂直方向の４画素に表示される画像を説明する図である。図３に示すように、アップコンバート前では４画素全てが画像信号Ｓ１を用いて画像を表示することになるが、アップコンバート後ではそれぞれの画素に画像信号Ｓ１ａ乃至Ｓ１ｃが供給され、解像度を向上することができる。さらに、アップコンバート後に画像処理を行うことで、より高品質な画像を表示することができる。画像処理後ではそれぞれの画素に画像信号Ｓ２ａ乃至Ｓ２ｃが供給される。 FIG. 3 is a diagram illustrating an image displayed in four pixels in the horizontal and vertical directions in the comparative example. As shown in FIG. 3, before the up-conversion, all four pixels display an image using the image signal S1, but after the up-conversion, the image signals S1a to S1c are supplied to each pixel to improve the resolution. can do. Further, by performing image processing after up-conversion, a higher quality image can be displayed. After the image processing, the image signals S2a to S2c are supplied to each pixel.
　しかし、アップコンバート後に画像処理を行うことで、演算量が増加し、処理部の消費電力の増加、または表示の遅延などが発生してしまう。 However, by performing image processing after up-conversion, the amount of calculation increases, the power consumption of the processing unit increases, or display delay occurs.
　一方、本発明の一態様の表示システムでは、画像信号に、補正信号を付加することができる。そのため、図２Ａに示すように、画像信号Ｓ１をアップコンバートせずに、画像信号Ｓ１に画像処理を行い、画像信号Ｓ２を生成する。これにより、画像処理の演算量を低減し、消費電力を低減させることができる。そして、４画素に同じ画像信号Ｓ２を供給する。 On the other hand, in the display system of one aspect of the present invention, a correction signal can be added to the image signal. Therefore, as shown in FIG. 2A, the image signal S1 is subjected to image processing without up-converting the image signal S1 to generate the image signal S2. As a result, the amount of calculation for image processing can be reduced and the power consumption can be reduced. Then, the same image signal S2 is supplied to the four pixels.
　また、各画素には、補正信号Ｗ２ａ乃至Ｗ２ｃを供給する。ここで、補正信号Ｗ２ａ乃至Ｗ２ｃを生成する方法は限定されない。図１Ｂに示すように、記憶部１５２に保存されている補正データＷ１を読み出して、当該補正データＷ１に基づいた補正信号Ｗ２を生成してもよい。補正信号Ｗ２の生成をリアルタイムで行わない場合、演算量の低減に伴い、消費電力が低減され、また表示の遅延を抑制でき、好ましい。または、後述するように、画像信号Ｓ１を用いてリアルタイムで補正信号Ｗ２を生成してもよい（図４Ｂなどを参照）。補正信号Ｗ２の生成をリアルタイムで行う場合、アップコンバートの質を高めることができ、好ましい。この場合においても、画像信号Ｓ２の生成における演算量を低減できる。特に、画像信号Ｓ２の生成と、補正信号Ｗ２の生成と、を同時に行うことで、表示の遅延を抑制でき、好ましい。 Further, the correction signals W2a to W2c are supplied to each pixel. Here, the method for generating the correction signals W2a to W2c is not limited. As shown in FIG. 1B, the correction data W1 stored in the storage unit 152 may be read out to generate a correction signal W2 based on the correction data W1. When the correction signal W2 is not generated in real time, the power consumption is reduced and the display delay can be suppressed as the amount of calculation is reduced, which is preferable. Alternatively, as will be described later, the correction signal W2 may be generated in real time using the image signal S1 (see FIG. 4B and the like). When the correction signal W2 is generated in real time, the quality of up-conversion can be improved, which is preferable. Even in this case, the amount of calculation in the generation of the image signal S2 can be reduced. In particular, it is preferable to simultaneously generate the image signal S2 and the correction signal W2 because the display delay can be suppressed.
　そして、図２Ｂに示すように、画像信号Ｓ２に各補正信号が付加され、新しい画像信号Ｓ２ａ乃至Ｓ２ｃが生成される。画像処理により生成された画像信号Ｓ２に、各補正信号が付加されることで、画素では、元の画像信号Ｓ１をアップコンバートした表示を行うことができる。 Then, as shown in FIG. 2B, each correction signal is added to the image signal S2, and new image signals S2a to S2c are generated. By adding each correction signal to the image signal S2 generated by the image processing, the pixels can display the original image signal S1 up-converted.
　図４Ａに、表示システム１００Ｂのブロック図を示す。 FIG. 4A shows a block diagram of the display system 100B.
　処理部１５３は、複数のニューラルネットワークを有していてもよい。表示システム１００Ｂでは、処理部１５３が、ニューラルネットワーク１５９ａ及びニューラルネットワーク１５９ｂを有する。 The processing unit 153 may have a plurality of neural networks. In the display system 100B, the processing unit 153 has a neural network 159a and a neural network 159b.
　図４Ｂ、図４Ｃを用いて、表示システム１００Ｂにおける画像信号Ｓ２と補正信号Ｗ２の生成について説明する。 The generation of the image signal S2 and the correction signal W2 in the display system 100B will be described with reference to FIGS. 4B and 4C.
　通信部１５５は、外部から受信したデータに基づいた画像信号Ｓ１を処理部１５３に供給することができる。処理部１５３は、ニューラルネットワーク１５９ａを用いて、画像信号Ｓ１に含まれるデータに対して画像処理を行い、画像信号Ｓ２を生成する。また、処理部１５３は、ニューラルネットワーク１５９ｂ及び画像信号Ｓ１に含まれるデータを用いて、補正信号Ｗ２を生成する。画像信号Ｓ２及び補正信号Ｗ２は、処理部１５３から表示部１５６に供給される。 The communication unit 155 can supply the image signal S1 based on the data received from the outside to the processing unit 153. The processing unit 153 performs image processing on the data included in the image signal S1 using the neural network 159a, and generates the image signal S2. Further, the processing unit 153 generates the correction signal W2 by using the data included in the neural network 159b and the image signal S1. The image signal S2 and the correction signal W2 are supplied from the processing unit 153 to the display unit 156.
　表示システム１００Ｂでは、画像信号Ｓ１を用いて補正信号Ｗ２を生成するため、表示システム１００Ａに比べて、高品質なアップコンバートを実現できる。例えば、膨大な数の画像を教師データとして学習したディープニューラルネットワークを用いることで、精度の高い補正信号Ｗ２を生成することができる。 Since the display system 100B uses the image signal S1 to generate the correction signal W2, higher quality up-conversion can be realized as compared with the display system 100A. For example, a highly accurate correction signal W2 can be generated by using a deep neural network in which a huge number of images are learned as teacher data.
　補正信号Ｗ２により、解像度のアップコンバートに伴う画素間補間処理を行うことができる。画素間補間処理は、解像度をアップコンバートした際に、本来存在しないデータを補間する処理である。例えば、新たに補間する画素の色のデータ（例えば赤色（Ｒ）、緑色（Ｇ）、青色（Ｂ）の各色に対応する階調値）として、当該画素の周囲の画素の色のデータを参照し、それらの中間色となる色のデータとなるように、データを補間する。 The correction signal W2 can be used for interpolation processing between pixels due to resolution up-conversion. The interpolation process between pixels is a process of interpolating data that does not originally exist when the resolution is up-converted. For example, refer to the color data of the pixels around the pixel as the color data of the pixel to be newly interpolated (for example, the gradation value corresponding to each color of red (R), green (G), and blue (B)). Then, the data is interpolated so that the data is a color that is an intermediate color between them.
　処理部１５３は、画像信号Ｓ１をアップコンバートせずに、画像信号Ｓ１に画像処理を行い、画像信号Ｓ２を生成する。これにより、リアルタイムで補正信号Ｗ２を生成する場合においても、画像処理の演算量を低減することができる。また、画像信号Ｓ２の生成と補正信号Ｗ２の生成を並行して行うことで、表示の遅延を抑制することができる。 The processing unit 153 performs image processing on the image signal S1 without up-converting the image signal S1 to generate the image signal S2. This makes it possible to reduce the amount of image processing calculation even when the correction signal W2 is generated in real time. Further, by generating the image signal S2 and the correction signal W2 in parallel, the display delay can be suppressed.
　図４Ｂには、ニューラルネットワーク１５９ｂに、画像信号Ｓ１のみが供給される例を示す。図４Ｃには、ニューラルネットワーク１５９ｂに、画像信号Ｓ１に加えて、補正データＷ１が供給される例を示す。画像信号Ｓ１及び補正データＷ１を用いて生成された補正信号Ｗ２を、画像信号Ｓ２に付加することで、例えば、画像のアップコンバートに加えて、画素が有するトランジスタの特性のばらつきに起因する表示ムラを補正することができる。 FIG. 4B shows an example in which only the image signal S1 is supplied to the neural network 159b. FIG. 4C shows an example in which the correction data W1 is supplied to the neural network 159b in addition to the image signal S1. By adding the correction signal W2 generated by using the image signal S1 and the correction data W1 to the image signal S2, for example, in addition to up-converting the image, display unevenness due to variations in the characteristics of the transistors of the pixels is caused. Can be corrected.
　図５Ａ~図５Ｆを用いて、本実施の形態の表示システムにおける画像信号Ｓ２と補正信号Ｗ２の生成の変形例について説明する。 A modified example of the generation of the image signal S2 and the correction signal W2 in the display system of the present embodiment will be described with reference to FIGS. 5A to 5F.
　画像信号Ｓ１を用いて、画像信号Ｓ２及び補正信号Ｗ２を生成する場合、図５Ａに示すように、画像信号Ｓ２の生成にのみ、ニューラルネットワーク１５９を用いてもよいし、図５Ｂに示すように、補正信号Ｗ２の生成にのみ、ニューラルネットワーク１５９を用いてもよい。ニューラルネットワーク１５９を用いない信号の生成は、人工知能を利用した他の方法で行ってもよいし、人工知能を利用しない方法で行ってもよい。図５Ｃ、図５Ｄに示すように、補正信号Ｗ２を、画像信号Ｓ１及び補正データＷ１を用いて生成する場合においても同様である。 When the image signal S1 is used to generate the image signal S2 and the correction signal W2, as shown in FIG. 5A, the neural network 159 may be used only for the generation of the image signal S2, or as shown in FIG. 5B. , The neural network 159 may be used only for the generation of the correction signal W2. The signal generation without using the neural network 159 may be performed by another method using artificial intelligence, or may be performed by a method not using artificial intelligence. As shown in FIGS. 5C and 5D, the same applies to the case where the correction signal W2 is generated by using the image signal S1 and the correction data W1.
　図５Ｅ、図５Ｆに示すように、１つのニューラルネットワーク１５９を用いて、同時に画像信号Ｓ２及び補正信号Ｗ２を生成してもよい。このとき、ニューラルネットワークの出力層からは、画像信号Ｓ２のデータと補正信号Ｗ２のデータの双方が出力される。図５Ｅにおけるニューラルネットワークの入力層には、画像信号Ｓ１のデータが入力される。図５Ｆにおけるニューラルネットワークの入力層には、画像信号Ｓ１のデータと補正データＷ１の双方が入力される。 As shown in FIGS. 5E and 5F, one neural network 159 may be used to simultaneously generate the image signal S2 and the correction signal W2. At this time, both the data of the image signal S2 and the data of the correction signal W2 are output from the output layer of the neural network. The data of the image signal S1 is input to the input layer of the neural network in FIG. 5E. Both the data of the image signal S1 and the correction data W1 are input to the input layer of the neural network in FIG. 5F.
　本発明の一態様では、画像処理によって画像信号が有するデータの解像度は変化させず、画像信号に加えて補正信号を供給した画素で新たな画像信号を生成することで、映像の解像度を高めるため、演算量の低減、消費電力の低減、回路規模の縮小、または表示の遅延の抑制などを実現することができる。そのため、高解像度または表示品位の高い表示システムを実現することができる。さらに、表示システムの大型化、低消費電力化を実現することができる。また、後述するように、本発明の一態様によれば、新たな画像信号を画素で生成するための動作を少ないステップで行うことができるため、画素数が多く水平期間の短い表示装置でも実現することができる。そのため、高いフレーム周波数で動作可能な表示システムを実現できる。 In one aspect of the present invention, the resolution of the data contained in the image signal is not changed by image processing, and a new image signal is generated by the pixel to which the correction signal is supplied in addition to the image signal, thereby increasing the resolution of the image. , Reduction of calculation amount, reduction of power consumption, reduction of circuit scale, suppression of display delay, and the like can be realized. Therefore, it is possible to realize a display system having high resolution or high display quality. Furthermore, it is possible to increase the size of the display system and reduce the power consumption. Further, as will be described later, according to one aspect of the present invention, since the operation for generating a new image signal with pixels can be performed in a small number of steps, it can be realized even in a display device having a large number of pixels and a short horizontal period. can do. Therefore, it is possible to realize a display system that can operate at a high frame frequency.
　次に、表示システムの構成要素について説明する。なお、以下では、表示システム１００Ａを例に挙げて説明するが、表示システム１００Ｂにも同様の構成を適用できる。 Next, the components of the display system will be described. In the following, the display system 100A will be described as an example, but the same configuration can be applied to the display system 100B.
［制御部１５１］
　制御部１５１は、表示システム１００Ａ全体の動作を制御する機能を有する。制御部１５１は、記憶部１５２、処理部１５３、入出力部１５４、通信部１５５、及び表示部１５６などの動作を制御する。 [Control unit 151]
The control unit 151 has a function of controlling the operation of the entire display system 100A. The control unit 151 controls the operations of the storage unit 152, the processing unit 153, the input / output unit 154, the communication unit 155, the display unit 156, and the like.
［記憶部１５２］
　記憶部１５２としては、記憶素子として強誘電体メモリを有する記憶装置を適用することが好ましい。強誘電体メモリは、少ない要素からなる素子構成を実現可能であるため、強誘電体メモリの微細化と高密度化により、記憶容量が大きな記憶装置を実現することができる。 [Memory unit 152]
As the storage unit 152, it is preferable to apply a storage device having a ferroelectric memory as a storage element. Since the ferroelectric memory can realize an element configuration consisting of a small number of elements, it is possible to realize a storage device having a large storage capacity by miniaturizing and increasing the density of the ferroelectric memory.
　また、強誘電体メモリは不揮発性であり、データを長期間保持することができる。これにより、リフレッシュ（メモリへのデータの再書き込み）の頻度を低減できるため、本発明の一態様の表示システムの消費電力を低減することができる。 In addition, the ferroelectric memory is non-volatile and can retain data for a long period of time. As a result, the frequency of refreshing (rewriting data to the memory) can be reduced, so that the power consumption of the display system according to one aspect of the present invention can be reduced.
　本発明の一態様の表示システムが有する強誘電体メモリは、例えば、強誘電体層を有する容量素子と、当該容量素子と電気的に接続するトランジスタと、を有する。 The ferroelectric memory included in the display system of one aspect of the present invention includes, for example, a capacitive element having a ferroelectric layer and a transistor electrically connected to the capacitive element.
　強誘電体層を有する容量素子（強誘電体キャパシタ）と、トランジスタと、を用いて、不揮発性の記憶素子（強誘電体メモリ）である、ＦｅＲＡＭ（Ｆｅｒｒｏｅｌｅｃｔｒｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）を作製することができる。ＦｅＲＡＭは、微細化が可能である、高速動作が可能である、書き換え耐性が高い、などの特徴を有する。また、ＦｅＲＡＭは、ＤＲＡＭ（Ｄｙｎａｍｉｃ　ＲＡＭ）と同様に、１トランジスタ１キャパシタ型の素子構成であり、高密度化が可能である。ＦｅＲＡＭの微細化と高密度化により、記憶容量が大きな記憶装置を実現することができる。 FeRAM (Feroelectric Random Access Memory), which is a non-volatile storage element (ferroelectric memory), can be manufactured by using a capacitive element (ferroelectric capacitor) having a ferroelectric layer and a transistor. .. FeRAM has features such as miniaturization, high-speed operation, and high rewrite resistance. Further, the FeRAM has a 1-transistor, 1-capacitor type element configuration similar to a DRAM (Dynamic RAM), and can be increased in density. By miniaturizing and increasing the density of FeRAM, it is possible to realize a storage device having a large storage capacity.
　強誘電体メモリが有する強誘電体層は、ハフニウム及びジルコニウムの一方又は双方を有する酸化物を有することが好ましい。特に、強誘電体層には、酸化ハフニウム及び酸化ジルコニウムを有する材料（ＨｆＺｒＯＸ（Ｘは０よりも大きい実数とする））を用いることが好ましい。 The ferroelectric layer of the ferroelectric memory preferably has an oxide having one or both of hafnium and zirconium. In particular, it is preferable to use a material having hafnium oxide and zirconium oxide (HfZrOX ( X is a real number larger than 0)) for the ferroelectric layer.
　強誘電体層に含まれる、水素、炭化水素、及び炭素の少なくとも一つの濃度は、ＳＩＭＳ分析において、５×１０２０ａｔｏｍｓ／ｃｍ３以下であることが好ましく、１×１０２０ａｔｏｍｓ／ｃｍ３以下であることがより好ましい。強誘電体層は、プリカーサとして、炭化水素を含まない、塩素系材料を用いることが好ましい。これにより、強誘電体層に含まれる水素、炭化水素、及び炭素の濃度をそれぞれ低減することができる。また、強誘電体層には、塩素が含まれていてもよい。 The concentration of at least one of hydrogen, hydrocarbon, and carbon contained in the ferroelectric layer is preferably 5 × 10 20 atoms / cm 3 or less in SIMS analysis, and is preferably 1 × 10 20 atoms / cm 3 or less. Is more preferable. As the ferroelectric layer, it is preferable to use a chlorine-based material that does not contain hydrocarbons as a precursor. This makes it possible to reduce the concentrations of hydrogen, hydrocarbons, and carbon contained in the ferroelectric layer, respectively. Further, the ferroelectric layer may contain chlorine.
　ＦｅＲＡＭ及びＦｅＦＥＴなどの強誘電体メモリには、チャネル形成領域に酸化物半導体を有するトランジスタ（ＯＳトランジスタ）を用いることができる。ＯＳトランジスタは高耐圧であるため、トランジスタを微細化しても高電圧を印加することができる。 For ferroelectric memories such as FeRAM and FeFET, a transistor (OS transistor) having an oxide semiconductor in the channel forming region can be used. Since the OS transistor has a high withstand voltage, a high voltage can be applied even if the transistor is miniaturized.
　また、ＦｅＲＡＭ及びＦｅＦＥＴなどの強誘電体メモリには、チャネル形成領域にシリコンを有するトランジスタ（Ｓｉトランジスタ）を用いることができる。Ｓｉトランジスタは、電気特性のばらつきが小さいため、信頼性が高くセル間の電気特性のばらつきの小さい記憶装置を実現できる。 Further, a transistor (Si transistor) having silicon in the channel forming region can be used for the ferroelectric memory such as FeRAM and FeFET. Since the Si transistor has a small variation in electrical characteristics, it is possible to realize a storage device having high reliability and a small variation in electrical characteristics between cells.
　本発明の一態様の半導体装置は、動作させる必要のない回路を、パワーゲーティングにより、停止させることができる。これにより、半導体装置の消費電力を低減することができる。パワーゲーティングでは、電源供給を停止するため、スタンバイ中の電力を無くす効果を奏する。具体的には、ＣＰＵ及びＧＰＵの一方または双方において、パワーゲーティングが可能である。 The semiconductor device of one aspect of the present invention can stop a circuit that does not need to be operated by power gating. This makes it possible to reduce the power consumption of the semiconductor device. In power gating, since the power supply is stopped, the effect of eliminating the power during standby is achieved. Specifically, power gating is possible on one or both of the CPU and the GPU.
　なお、本実施の形態では、主に強誘電体メモリとして、ＦｅＲＡＭを用いる例を示すが、他の強誘電体メモリを用いてもよい。例えば、本発明の一態様の表示システムは、ＦｅＲＡＭ、１つのトランジスタを有するＦｅＦＥＴ（Ｆｅｒｒｏｅｌｅｃｔｒｉｃ　ＦＥＴ）、及び、少なくとも１つの強誘電キャパシタまたはトンネル接合素子を有するＦＴＪ（Ｆｅｒｒｏｅｌｅｃｔｒｉｃ　Ｔｕｎｎｅｌ　Ｊｕｎｃｔｉｏｎ）メモリの少なくとも一つを有することができる。このような強誘電体メモリを用いることで、消費電力の低い半導体装置を実現することができる。 In this embodiment, an example in which FeRAM is mainly used as the ferroelectric memory is shown, but other ferroelectric memories may be used. For example, the display system of one aspect of the present invention is a FeRAM, a FeFET having one transistor, and at least one of an FTJ (Ferroelectric Tunnel Junction) memory having at least one ferroelectric capacitor or a tunnel junction element. Can have. By using such a ferroelectric memory, it is possible to realize a semiconductor device having low power consumption.
　強誘電電界効果トランジスタ（ＦｅＦＥＴ）は、トランジスタが有する絶縁層の少なくとも一部（例えば、ゲート絶縁層）に強誘電体層を用いることで作製される、不揮発性の記憶素子（強誘電体メモリ）である。ＦｅＦＥＴは、消費電力が低い、高速動作が可能である、非破壊読み出しが可能である、などの特長を有する。また、ＦｅＦＥＴは、１トランジスタ型の素子構成であり、高密度化が可能である。これにより、記憶容量が大きな記憶装置を実現することができる。 The ferroelectric field effect transistor (FeFET) is a non-volatile storage element (ferroelectric memory) manufactured by using a ferroelectric layer for at least a part (for example, a gate insulating layer) of the insulating layer of the transistor. Is. FeFET has features such as low power consumption, high-speed operation, and non-destructive readout. Further, the FeFET has a one-transistor type element configuration, and high density can be achieved. This makes it possible to realize a storage device having a large storage capacity.
　強誘電トンネル接合（ＦＴＪ）メモリは、強誘電体層を有する容量素子（強誘電キャパシタ）を用いることで作製される、トンネル接合を利用した不揮発性の記憶素子（強誘電体メモリ）である。ＦＴＪメモリは、占有面積が小さい、高速動作が可能である、非破壊読み出しが可能である、などの特長を有する。また、ＦＴＪメモリは、トンネル接合を利用しており、容量としての機能と、ダイオードとしての機能と、を有する素子構成であり、高密度化が可能である。これにより、記憶容量が大きな記憶装置を実現することができる。ＦＴＪメモリは、強誘電体層を有するトンネル接合素子を有する、ともいえる。 The ferroelectric tunnel junction (FTJ) memory is a non-volatile storage element (ferroelectric memory) using a tunnel junction, which is manufactured by using a capacitive element (ferroelectric capacitor) having a ferroelectric layer. The FTJ memory has features such as a small occupied area, high-speed operation, and non-destructive reading. Further, the FTJ memory utilizes a tunnel junction and has an element configuration having a function as a capacitance and a function as a diode, and can be increased in density. This makes it possible to realize a storage device having a large storage capacity. It can be said that the FTJ memory has a tunnel junction element having a ferroelectric layer.
　本実施の形態の表示システムは、記憶部１５２だけでなく、表示システムが有するあらゆる記憶装置に、不揮発性の記憶素子である強誘電体メモリを適用することが好ましい。表示システムが有する記憶素子の全てまたは半分以上を、強誘電体メモリとすることで、消費電力を劇的に削減することができる。なお、本実施の形態の表示システムは、他の揮発性の記憶素子、及び不揮発性の記憶素子のいずれか一方または双方を有していてもよい。また、本実施の形態の表示システムは、従来、ＤＲＡＭまたはキャッシュメモリなど、揮発性の記憶素子で構成されていたメモリについても、強誘電体メモリで置き換えられていることが好ましい。 In the display system of the present embodiment, it is preferable to apply the ferroelectric memory, which is a non-volatile storage element, not only to the storage unit 152 but also to all the storage devices of the display system. Power consumption can be dramatically reduced by using ferroelectric memory for all or more than half of the storage elements of the display system. The display system of the present embodiment may have one or both of other volatile storage elements and non-volatile storage elements. Further, in the display system of the present embodiment, it is preferable that the memory configured by the volatile storage element such as the DRAM or the cache memory is replaced with the ferroelectric memory.
　そのほか、記憶部１５２として、例えば、フラッシュメモリ、ＭＲＡＭ（Ｍａｇｎｅｔｏｒｅｓｉｓｔｉｖｅ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、ＰＲＡＭ（Ｐｈａｓｅ　ｃｈａｎｇｅ　ＲＡＭ）、ＲｅＲＡＭ（Ｒｅｓｉｓｔｉｖｅ　ＲＡＭ）などの不揮発性の記憶素子が適用された記憶装置、またはＤＲＡＭ、またはＳＲＡＭ（Ｓｔａｔｉｃ　ＲＡＭ）などの揮発性の記憶素子が適用された記憶装置等を用いてもよい。また例えばハードディスクドライブ（ＨＤＤ：Ｈａｒｄ　Ｄｉｓｋ　Ｄｒｉｖｅ）またはソリッドステートドライブ（ＳＳＤ：Ｓｏｌｉｄ　Ｓｔａｔｅ　Ｄｒｉｖｅ）などの記録メディアドライブを用いてもよい。 In addition, as the storage unit 152, for example, a storage device to which a non-volatile storage element such as a flash memory, an MRAM (Magnetoristive Random Access Memory), a PRAM (Phase change RAM), or a ReRAM (Resistive RAM) is applied, or a DRAM, or A storage device or the like to which a volatile storage element such as SRAM (Static RAM) is applied may be used. Further, for example, a recording media drive such as a hard disk drive (HDD: Hard Disk Drive) or a solid state drive (SSD: Solid State Drive) may be used.
　入出力部１５４を介してコネクタにより脱着可能なＨＤＤもしくはＳＳＤなどの記憶装置、または、フラッシュメモリ、ブルーレイディスク、もしくはＤＶＤなどの記録媒体のメディアドライブを記憶部１５２として用いることもできる。なお、記憶部１５２を表示システム１００Ａに内蔵せず、表示システム１００Ａの外部に置かれる記憶装置を記憶部１５２として用いてもよい。その場合、記憶部１５２は、入出力部１５４を介して表示システム１００Ａと接続される。または通信部１５５を介して、無線通信でデータのやりとりをする構成であってもよい。 A storage device such as an HDD or SSD that can be attached / detached by a connector via an input / output unit 154, or a media drive of a recording medium such as a flash memory, a Blu-ray disc, or a DVD can also be used as the storage unit 152. The storage unit 152 may not be built in the display system 100A, and a storage device placed outside the display system 100A may be used as the storage unit 152. In that case, the storage unit 152 is connected to the display system 100A via the input / output unit 154. Alternatively, the configuration may be such that data is exchanged by wireless communication via the communication unit 155.
　記憶部１５２には、処理部１５３で用いるプログラム、アルゴリズム、重み係数などが記憶されている。また、記憶部１５２には、表示部１５６に表示する映像情報などが記憶されている。また、記憶部１５２には、補正データＷ１が記憶されていてもよい。 The storage unit 152 stores the program, algorithm, weighting coefficient, etc. used in the processing unit 153. Further, the storage unit 152 stores video information and the like to be displayed on the display unit 156. Further, the correction data W1 may be stored in the storage unit 152.
［処理部１５３］
　処理部１５３は、表示システム１００Ａ全体の動作に関わる演算を行う機能を有し、例えば中央演算処理装置（ＣＰＵ：Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）などを用いることができる。 [Processing unit 153]
The processing unit 153 has a function of performing an operation related to the operation of the entire display system 100A, and for example, a central processing unit (CPU: Central Processing Unit) or the like can be used.
　処理部１５３としては、ＣＰＵのほか、ＤＳＰ（Ｄｉｇｉｔａｌ　Ｓｉｇｎａｌ　Ｐｒｏｃｅｓｓｏｒ）、ＧＰＵ（Ｇｒａｐｈｉｃｓ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）などの他のマイクロプロセッサを単独で、または組み合わせて用いることができる。またこれらマイクロプロセッサをＦＰＧＡ（Ｆｉｅｌｄ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）またはＦＰＡＡ（Ｆｉｅｌｄ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ａｎａｌｏｇ　Ａｒｒａｙ）といったＰＬＤ（Ｐｒｏｇｒａｍｍａｂｌｅ　Ｌｏｇｉｃ　Ｄｅｖｉｃｅ）によって実現してもよい。 As the processing unit 153, in addition to the CPU, other microprocessors such as a DSP (Digital Signal Processor) and a GPU (Graphics Processing Unit) can be used alone or in combination. Further, these microprocessors may be realized by a PLD (Programmable Logic Device) such as FPGA (Field Programmable Gate Array) or FPGA (Field Programmable Analog Array).
　処理部１５３は、ニューラルネットワーク１５９（図中ではＮＮ１５９とも記す）を有する。ニューラルネットワーク１５９はソフトウェアで構成してもよい。 The processing unit 153 has a neural network 159 (also referred to as NN159 in the figure). The neural network 159 may be configured by software.
　処理部１５３は、プロセッサにより種々のプログラムからの命令を解釈し実行することで、各種のデータ処理及びプログラム制御などを行う。プロセッサにより実行しうるプログラムは、プロセッサが有するメモリ領域に格納されていてもよいし、記憶部１５２に格納されていてもよい。 The processing unit 153 performs various data processing, program control, and the like by interpreting and executing instructions from various programs by the processor. The program that can be executed by the processor may be stored in the memory area of the processor or may be stored in the storage unit 152.
　プロセッサが有するメモリ領域としては、キャッシュメモリを用いることができる。ここで、キャッシュメモリとしてＳＲＡＭを用いてもよいが、上述の強誘電体が適用された記憶素子を用いることが特に好ましい。当該記憶素子は、不揮発性の記憶素子であるためデータ保持にかかる電力を、ＳＲＡＭを用いた時と比較して、大幅に削減することができる。そのため、表示システムの低消費電力化が可能であるだけではなく、表示システムの発熱を抑制することができる。例えば、システムのプロセッサ等を冷却するためのヒートシンンク及び冷却ファンなどのうち、一つ以上をなくすことも可能となる。 A cache memory can be used as the memory area of the processor. Here, SRAM may be used as the cache memory, but it is particularly preferable to use a storage element to which the above-mentioned ferroelectric substance is applied. Since the storage element is a non-volatile storage element, the power required for data retention can be significantly reduced as compared with the case where SRAM is used. Therefore, not only the power consumption of the display system can be reduced, but also the heat generation of the display system can be suppressed. For example, it is possible to eliminate one or more of the heat sink and the cooling fan for cooling the processor of the system and the like.
　処理部１５３はメインメモリを有していてもよい。メインメモリは、ＲＡＭ（Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）などの揮発性メモリ、または、ＲＯＭ（Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）などの不揮発性メモリを備える構成とすることができる。 The processing unit 153 may have a main memory. The main memory can be configured to include a volatile memory such as a RAM (Random Access Memory) or a non-volatile memory such as a ROM (Read Only Memory).
　特に、処理部１５３が有するメインメモリに、上述の強誘電体が適用された記憶素子を用いることが好ましい。 In particular, it is preferable to use a storage element to which the above-mentioned ferroelectric substance is applied for the main memory of the processing unit 153.
　メインメモリに設けられるＲＡＭとしては、例えばＦｅＲＡＭまたはＤＲＡＭなどが用いられ、処理部１５３の作業空間として仮想的にメモリ空間が割り当てられ利用される。記憶部１５２に格納されたオペレーティングシステム、アプリケーションプログラム、プログラムモジュール、プログラムデータ等は、実行のためにＲＡＭにロードされる。ＲＡＭにロードされたこれらのデータ、プログラム、またはプログラムモジュールは、処理部１５３に直接アクセスされ、操作される。 As the RAM provided in the main memory, for example, FeRAM or DRAM is used, and the memory space is virtually allocated and used as the work space of the processing unit 153. The operating system, application program, program module, program data, etc. stored in the storage unit 152 are loaded into the RAM for execution. These data, programs, or program modules loaded into the RAM are directly accessed and operated by the processing unit 153.
　一方、ＲＯＭには書き換えを必要としないＢＩＯＳ（Ｂａｓｉｃ　Ｉｎｐｕｔ／Ｏｕｔｐｕｔ　Ｓｙｓｔｅｍ）、またはファームウェア等を格納することができる。ＲＯＭとしては、マスクＲＯＭ、ＯＴＰＲＯＭ（Ｏｎｅ　Ｔｉｍｅ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）、またはＥＰＲＯＭ（Ｅｒａｓａｂｌｅ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）等を用いることができる。ＥＰＲＯＭとしては、紫外線照射により記憶データの消去を可能とするＵＶ−ＥＰＲＯＭ（Ｕｌｔｒａ−Ｖｉｏｌｅｔ　Ｅｒａｓａｂｌｅ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）、ＥＥＰＲＯＭ（Ｅｌｅｃｔｒｉｃａｌｌｙ　Ｅｒａｓａｂｌｅ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）、フラッシュメモリなどが挙げられる。また、ＲＯＭとして、不揮発性の記憶素子を用いてもよい。特に上述したＦｅＲＡＭは、データの保持特性が極めて高いため、ＲＯＭに適用することもできる。 On the other hand, the ROM can store BIOS (Basic Input / Output System) or firmware that does not require rewriting. As the ROM, a mask ROM, an OTPROM (One Time Program Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), or the like can be used. Examples of EPROM include UV-EPROM (Ultra-Violet Erasable Project Only Memory), EEPROM (Electrically Erasable Erasable Memory), etc., which enables erasure of stored data by irradiation with ultraviolet rays. Further, a non-volatile storage element may be used as the ROM. In particular, the above-mentioned FeRAM has extremely high data retention characteristics, and therefore can be applied to ROM.
　処理部１５３の演算をハードウェアによって行う場合、チャネル形成領域にシリコンまたは酸化物半導体を含むトランジスタによって構成された演算回路が好適である。例えば、チャネル形成領域にシリコン（アモルファスシリコン、低温ポリシリコン、または単結晶シリコン）または酸化物半導体を含むトランジスタによって構成された演算回路が好適である。また、実施の形態４で詳述するが、処理部１５３で積和演算を行う場合、積和演算回路を構成するトランジスタとして、酸化物半導体を含むトランジスタが好適である。 When the calculation of the processing unit 153 is performed by hardware, a calculation circuit composed of a transistor containing silicon or an oxide semiconductor in the channel forming region is suitable. For example, an arithmetic circuit composed of a transistor containing silicon (amorphous silicon, low temperature polysilicon, or single crystal silicon) or an oxide semiconductor in the channel forming region is suitable. Further, as will be described in detail in the fourth embodiment, when the product-sum calculation is performed by the processing unit 153, a transistor containing an oxide semiconductor is suitable as the transistor constituting the product-sum calculation circuit.
［入出力部１５４］
　入出力部１５４としては、例えば、入力コンポーネントが接続可能な外部ポートなどが挙げられる。入出力部１５４は、バスライン１５７を介して処理部１５３と電気的に接続される。 [I / O unit 154]
Examples of the input / output unit 154 include an external port to which an input component can be connected. The input / output unit 154 is electrically connected to the processing unit 153 via the bus line 157.
　外部ポートとしては、例えば、コンピュータまたはプリンタなどの外部装置にケーブルを介して接続できる構成とすることができる。代表的には、ＵＳＢ端子などがある。また、外部ポートとして、ＬＡＮ（Ｌｏｃａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）接続用端子、デジタル放送の受信用端子、ＡＣアダプタを接続する端子等を有していてもよい。また、有線だけでなく、赤外線、可視光、紫外線などを用いた光通信用の送受信機を設けてもよい。 The external port can be configured to be connected to an external device such as a computer or a printer via a cable, for example. Typically, there is a USB terminal or the like. Further, as the external port, it may have a LAN (Local Area Network) connection terminal, a digital broadcast reception terminal, a terminal for connecting an AC adapter, and the like. Further, a transceiver for optical communication using infrared rays, visible light, ultraviolet rays, or the like may be provided as well as wired.
［通信部１５５］
　通信部１５５は、例えば制御部１５１からの命令に応じて表示システム１００Ａをコンピュータネットワークに接続するための制御信号を制御し、当該信号をコンピュータネットワークに発信する。表示システム１００Ａにアンテナを設けて、当該アンテナを介して通信を行ってもよい。 [Communication unit 155]
The communication unit 155 controls a control signal for connecting the display system 100A to the computer network in response to a command from the control unit 151, and transmits the signal to the computer network. An antenna may be provided in the display system 100A, and communication may be performed via the antenna.
　通信部１５５によって、Ｗｏｒｌｄ　Ｗｉｄｅ　Ｗｅｂ（ＷＷＷ）の基盤であるインターネット、イントラネット、エクストラネット、ＰＡＮ（Ｐｅｒｓｏｎａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）、ＬＡＮ、ＣＡＮ（Ｃａｍｐｕｓ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）、ＭＡＮ（Ｍｅｔｒｏｐｏｌｉｔａｎ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）、ＷＡＮ（Ｗｉｄｅ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）、ＧＡＮ（Ｇｌｏｂａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）等のコンピュータネットワークに表示システム１００Ａを接続させ、通信を行うことができる。また複数の異なる通信方法を用いる場合には、通信方法に応じて複数のアンテナを設けてもよい。 By the communication unit 155, the Internet, the intranet, the extranet, the PAN (Personal Area Network), the LAN, the CAN (Campus Area Network), the MAN (Metropolitan Area Network), which are the foundations of the World Wide Web (WWW), and the MAN (Metropolitan Area Network) ), GAN (Global Area Network), etc., the display system 100A can be connected to a computer network for communication. Further, when a plurality of different communication methods are used, a plurality of antennas may be provided depending on the communication method.
　通信部１５５には、例えば高周波回路（ＲＦ回路）を設け、ＲＦ信号の送受信を行えばよい。高周波回路は、各国法制により定められた周波数帯域の電磁信号と電気信号とを相互に変換し、当該電磁信号を用いて無線で他の通信機器との間で通信を行うための回路である。実用的な周波数帯域として数１０ｋＨｚ~数１０ＧＨｚが一般に用いられている。高周波回路は、複数の周波数帯域に対応した回路部を有し、当該回路部は、増幅器（アンプ）、ミキサ、フィルタ、ＤＳＰ、ＲＦトランシーバ等を有する構成とすることができる。 For example, a high frequency circuit (RF circuit) may be provided in the communication unit 155 to transmit and receive RF signals. The high frequency circuit is a circuit for mutually converting an electromagnetic signal and an electric signal in the frequency band specified by the legislation of each country and wirelessly communicating with other communication devices using the electromagnetic signal. A few tens of kHz to a few tens of GHz are generally used as a practical frequency band. The high-frequency circuit has a circuit unit corresponding to a plurality of frequency bands, and the circuit unit can be configured to include an amplifier (amplifier), a mixer, a filter, a DSP, an RF transceiver, and the like.
　また、通信部１５５は、表示システム１００Ａを電話回線と接続する機能を有していてもよい。電話回線を通じた通話を行う場合には、通信部１５５は、制御部１５１からの命令に応じて、表示システム１００Ａを電話回線に接続するための接続信号を制御し、当該信号を電話回線に発信する。 Further, the communication unit 155 may have a function of connecting the display system 100A to the telephone line. When making a call through a telephone line, the communication unit 155 controls a connection signal for connecting the display system 100A to the telephone line in response to a command from the control unit 151, and transmits the signal to the telephone line. do.
　通信部１５５は、受信した放送電波から、表示部１５６に出力する画像信号を生成するチューナーを有していてもよい。例えばチューナーは、復調回路と、Ａ−Ｄ変換回路（アナログ−デジタル変換回路）と、デコーダ回路等を有する構成とすることができる。復調回路は入力された信号を復調する機能を有する。Ａ−Ｄ変換回路は、復調されたアナログ信号をデジタル信号に変換する機能を有する。デコーダ回路は、デジタル信号に含まれる映像データをデコードし、画像信号を生成する機能を有する。 The communication unit 155 may have a tuner that generates an image signal to be output to the display unit 156 from the received broadcast radio wave. For example, the tuner can be configured to include a demodulation circuit, an AD conversion circuit (analog-digital conversion circuit), a decoder circuit, and the like. The demodulation circuit has a function of demodulating the input signal. The AD conversion circuit has a function of converting a demodulated analog signal into a digital signal. The decoder circuit has a function of decoding video data included in a digital signal and generating an image signal.
　また、デコーダが分割回路と、複数のプロセッサを有する構成としてもよい。分割回路は、入力された映像のデータを空間的、時間的に分割し、各プロセッサに出力する機能を有する。複数のプロセッサは、入力された映像データをデコードし、画像信号を生成する。このように、デコーダとして、複数のプロセッサによりデータを並列処理する構成を適用することで、極めて情報量の多い映像データをデコードすることができる。特にフルハイビジョンを超える解像度を有する映像を表示する場合には、圧縮されたデータをデコードするデコーダ回路が極めて高速な処理能力を有するプロセッサを有していることが好ましい。また、例えばデコーダ回路は、４以上、好ましくは８以上、より好ましくは１６以上の並列処理が可能な複数のプロセッサを含む構成とすることが好ましい。またデコーダは、入力された信号に含まれる映像用の信号と、それ以外の信号（文字情報、番組情報、認証情報等）を分離する回路を有していてもよい。 Further, the decoder may be configured to have a dividing circuit and a plurality of processors. The division circuit has a function of spatially and temporally dividing the input video data and outputting it to each processor. The plurality of processors decode the input video data and generate an image signal. In this way, by applying a configuration in which data is processed in parallel by a plurality of processors as a decoder, it is possible to decode video data having an extremely large amount of information. In particular, when displaying an image having a resolution exceeding full high-definition, it is preferable that the decoder circuit for decoding the compressed data has a processor having extremely high-speed processing capability. Further, for example, the decoder circuit is preferably configured to include a plurality of processors capable of parallel processing of 4 or more, preferably 8 or more, and more preferably 16 or more. Further, the decoder may have a circuit for separating a video signal included in the input signal and other signals (character information, program information, authentication information, etc.).
　通信部１５５により受信できる放送電波としては、地上波、または衛星から送信される電波などが挙げられる。また通信部１５５により受信できる放送電波として、アナログ放送、及びデジタル放送などがあり、また映像及び音声、または音声のみの放送などがある。例えばＵＨＦ帯（約３００ＭＨｚ~３ＧＨｚ）またはＶＨＦ帯（３０ＭＨｚ~３００ＭＨｚ）のうちの特定の周波数帯域で送信される放送電波を受信することができる。また例えば、複数の周波数帯域で受信した複数のデータを用いることで、転送レートを高くすることができ、より多くの情報を得ることができる。これによりフルハイビジョンを超える解像度を有する映像を、表示部１５６に表示させることができる。例えば、４Ｋ、８Ｋ、１６Ｋ、またはそれ以上の解像度を有する映像を表示させることができる。 Examples of broadcast radio waves that can be received by the communication unit 155 include terrestrial waves and radio waves transmitted from satellites. Further, as broadcast radio waves that can be received by the communication unit 155, there are analog broadcasting, digital broadcasting, and the like, and there are video and audio, or audio-only broadcasting. For example, it is possible to receive broadcast radio waves transmitted in a specific frequency band within the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz). Further, for example, by using a plurality of data received in a plurality of frequency bands, the transfer rate can be increased and more information can be obtained. As a result, an image having a resolution exceeding full high-definition can be displayed on the display unit 156. For example, it is possible to display an image having a resolution of 4K, 8K, 16K, or higher.
　また、チューナーはコンピュータネットワークを介したデータ伝送技術により送信された放送のデータを用いて、画像信号を生成する構成としてもよい。このとき、受信する信号がデジタル信号の場合には、チューナーは復調回路及びＡ−Ｄ変換回路を有していなくてもよい。 Further, the tuner may be configured to generate an image signal by using the broadcast data transmitted by the data transmission technology via the computer network. At this time, if the received signal is a digital signal, the tuner does not have to have a demodulation circuit and an AD conversion circuit.
　通信部１５５で取得した画像信号は、記憶部１５２に記憶することができる。 The image signal acquired by the communication unit 155 can be stored in the storage unit 152.
　また、入出力部１５４または通信部１５５は、補正データを取得する機能を有していてもよい。外部機器によって生成された補正データを取得し、記憶部１５２に記憶することができる。これにより、表示システムが有する補正データを随時更新し、表示品位を向上させることができる。 Further, the input / output unit 154 or the communication unit 155 may have a function of acquiring correction data. The correction data generated by the external device can be acquired and stored in the storage unit 152. As a result, the correction data of the display system can be updated at any time to improve the display quality.
［表示部１５６］
　表示部１５６には、様々な表示装置及び表示素子を適用することができる。例えば、発光表示装置、液晶表示装置などを用いることができる。発光表示装置は、表示素子として、ＥＬ（Ｅｌｅｃｔｒｏ　Ｌｕｍｉｎｅｓｃｅｎｃｅ）素子（有機ＥＬ素子、無機ＥＬ素子、または、有機物及び無機物を含むＥＬ素子）、ＬＥＤ（Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）などを用いることができる。液晶表示装置は、表示素子として、液晶素子を用いることができる。 [Display unit 156]
Various display devices and display elements can be applied to the display unit 156. For example, a light emitting display device, a liquid crystal display device, or the like can be used. As the light emitting display device, an EL (Electroluminescence) element (organic EL element, an inorganic EL element, or an EL element containing an organic substance and an inorganic substance), an LED (Light Emitting Diode), or the like can be used as the display element. The liquid crystal display device can use a liquid crystal element as the display element.
　図６に、表示部１５６のブロック図の一例を示す。 FIG. 6 shows an example of a block diagram of the display unit 156.
　表示部１５６は、複数の画素１０、走査線駆動回路１２、及び信号線駆動回路１３を有する。複数の画素１０は、マトリクス状に設けられている。 The display unit 156 has a plurality of pixels 10, a scanning line driving circuit 12, and a signal line driving circuit 13. The plurality of pixels 10 are provided in a matrix.
　走査線駆動回路１２及び信号線駆動回路１３には、例えばシフトレジスタ回路を用いることができる。 For the scanning line drive circuit 12 and the signal line drive circuit 13, for example, a shift register circuit can be used.
　信号線駆動回路１３には、処理部１５３から画像信号Ｓ２及び補正信号Ｗ２が供給される。処理部１５３は、供給された画像信号Ｓ１（及び補正データＷ１）を用いて、画像信号Ｓ２及び補正信号Ｗ２を生成する。 The image signal S2 and the correction signal W2 are supplied from the processing unit 153 to the signal line drive circuit 13. The processing unit 153 uses the supplied image signal S1 (and correction data W1) to generate the image signal S2 and the correction signal W2.
＜画素の構成例＞
　以下では、画素に表示される階調を補正するためのメモリを備える画素回路の構成例について説明する。 <Pixel configuration example>
Hereinafter, a configuration example of a pixel circuit including a memory for correcting the gradation displayed on the pixel will be described.
　図７Ａに、画素１０の回路図を示す。画素１０は、トランジスタＭ１、トランジスタＭ２、容量Ｃ１、及び回路４１を有する。また画素１０には、配線ＳＬ１、配線ＳＬ２、配線ＧＬ１、及び配線ＧＬ２が接続される。 FIG. 7A shows a circuit diagram of the pixel 10. The pixel 10 has a transistor M1, a transistor M2, a capacitance C1, and a circuit 41. Further, wiring SL1, wiring SL2, wiring GL1, and wiring GL2 are connected to the pixel 10.
　トランジスタＭ１は、ゲートが配線ＧＬ１と、ソース及びドレインの一方が配線ＳＬ１と、他方が容量Ｃ１の一方の電極と、それぞれ接続する。トランジスタＭ２は、ゲートが配線ＧＬ２と、ソース及びドレインの一方が配線ＳＬ２と、他方が容量Ｃ１の他方の電極、及び回路４１と、それぞれ接続する。 In the transistor M1, the gate is connected to the wiring GL1, one of the source and drain is connected to the wiring SL1, and the other is connected to one electrode of the capacitance C1. The transistor M2 connects the gate to the wiring GL2, one of the source and the drain to the wiring SL2, the other to the other electrode of the capacitance C1, and the circuit 41, respectively.
　回路４１は、少なくとも一の表示素子を含む回路である。表示素子としては様々な素子を用いることができるが、代表的には有機ＥＬ素子、及びＬＥＤなどの発光素子、液晶素子、またはＭＥＭＳ（Ｍｉｃｒｏ　Ｅｌｅｃｔｒｏ　Ｍｅｃｈａｎｉｃａｌ　Ｓｙｓｔｅｍｓ）素子等を適用することができる。 The circuit 41 is a circuit including at least one display element. Various elements can be used as the display element, but typically an organic EL element, a light emitting element such as an LED, a liquid crystal element, a MEMS (Micro Electro Mechanical Systems) element, or the like can be applied.
　ＬＥＤとしては、サイズの大きいものからマクロＬＥＤ（巨大ＬＥＤともいう）、ミニＬＥＤ、マイクロＬＥＤなどがある。ここで、ＬＥＤチップの一辺の寸法が１ｍｍを超えるものをマクロＬＥＤ、１００μｍより大きく１ｍｍ以下のものをミニＬＥＤ、１００μｍ以下のものをマイクロＬＥＤと呼ぶ。画素に適用するＬＥＤ素子として、特にマイクロＬＥＤを用いることが好ましい。マイクロＬＥＤを用いることで、極めて高精細な表示装置を実現できる。 As LEDs, there are macro LEDs (also called giant LEDs), mini LEDs, micro LEDs, etc., from large ones. Here, an LED chip having a side size of more than 1 mm is called a macro LED, an LED chip larger than 100 μm and 1 mm or less is called a mini LED, and an LED chip having a side size of 100 μm or less is called a micro LED. It is particularly preferable to use a micro LED as the LED element applied to the pixel. By using a micro LED, an extremely high-definition display device can be realized.
　トランジスタＭ１と容量Ｃ１とを接続するノードをノードＮ１、トランジスタＭ２と回路４１とを接続するノードをノードＮ２とする。 The node connecting the transistor M1 and the capacitance C1 is referred to as a node N1, and the node connecting the transistor M2 and the circuit 41 is referred to as a node N2.
　画素１０は、トランジスタＭ１をオフ状態とすることで、ノードＮ１の電位を保持することができる。また、トランジスタＭ２をオフ状態とすることで、ノードＮ２の電位を保持することができる。また、トランジスタＭ２をオフ状態とした状態で、トランジスタＭ１を介してノードＮ１に所定の電位を書き込むことで、容量Ｃ１を介した容量結合により、ノードＮ１の電位の変位に応じてノードＮ２の電位を変化させることができる。 The pixel 10 can hold the potential of the node N1 by turning off the transistor M1. Further, by turning off the transistor M2, the potential of the node N2 can be maintained. Further, by writing a predetermined potential to the node N1 via the transistor M1 with the transistor M2 turned off, the potential of the node N2 is corresponding to the displacement of the potential of the node N1 by the capacitive coupling via the capacitance C1. Can be changed.
　ここで、トランジスタＭ１、トランジスタＭ２のうちの一方または両方に、酸化物半導体が適用され、オフ状態におけるリーク電流（オフ電流）が著しく低いトランジスタを適用することができる。そのため極めて低いオフ電流により、ノードＮ１またはノードＮ２の電位を長期間に亘って保持することができる。なお、各ノードの電位を保持する期間が短い場合（具体的には、フレーム周波数が３０Ｈｚ以上である場合等）には、シリコン等の半導体を適用したトランジスタを用いてもよい。 Here, an oxide semiconductor is applied to one or both of the transistor M1 and the transistor M2, and a transistor having a significantly low leakage current (off current) in the off state can be applied. Therefore, the potential of the node N1 or the node N2 can be maintained for a long period of time due to the extremely low off current. When the period for holding the potential of each node is short (specifically, when the frame frequency is 30 Hz or more), a transistor to which a semiconductor such as silicon is applied may be used.
　続いて、図７Ｂを用いて、画素１０の動作方法の一例を説明する。図７Ｂは、画素１０の動作に係るタイミングチャートである。なおここでは説明を容易にするため、配線抵抗などの各種抵抗、トランジスタまたは配線などの寄生容量、及びトランジスタのしきい値電圧などの影響は考慮しない。 Subsequently, an example of the operation method of the pixel 10 will be described with reference to FIG. 7B. FIG. 7B is a timing chart relating to the operation of the pixel 10. For the sake of simplicity, the effects of various resistances such as wiring resistance, parasitic capacitance such as transistors or wiring, and threshold voltage of transistors are not considered here.
　図７Ｂに示す動作では、１フレーム期間を期間Ｔ１と期間Ｔ２とに分ける。期間Ｔ１はノードＮ２に電位を書き込む期間であり、期間Ｔ２はノードＮ１に電位を書き込む期間である。 In the operation shown in FIG. 7B, one frame period is divided into a period T1 and a period T2. The period T1 is a period for writing the potential to the node N2, and the period T2 is a period for writing the potential to the node N1.
〔期間Ｔ１〕
　期間Ｔ１では、配線ＧＬ１と配線ＧＬ２の両方に、トランジスタをオン状態にする電位を与える。また、配線ＳＬ１には固定電位である電位Ｖｒｅｆを供給し、配線ＳＬ２には第１データ電位Ｖｗを供給する。 [Period T1]
In the period T1, both the wiring GL1 and the wiring GL2 are given a potential to turn on the transistor. Further, the potential V ref , which is a fixed potential, is supplied to the wiring SL1, and the first data potential V w is supplied to the wiring SL2.
　ノードＮ１には、トランジスタＭ１を介して配線ＳＬ１から電位Ｖｒｅｆが与えられる。また、ノードＮ２には、トランジスタＭ２を介して配線ＳＬ２から第１データ電位Ｖｗが与えられる。したがって、容量Ｃ１には電位差Ｖｗ−Ｖｒｅｆが保持された状態となる。 The potential V ref is given to the node N1 from the wiring SL1 via the transistor M1. Further, the node N2 is given a first data potential V w from the wiring SL2 via the transistor M2. Therefore, the potential difference V w −V ref is held in the capacitance C1.
〔期間Ｔ２〕
　続いて期間Ｔ２では、配線ＧＬ１にはトランジスタＭ１をオン状態とする電位を与え、配線ＧＬ２にはトランジスタＭ２をオフ状態とする電位を与える。また、配線ＳＬ１には第２データ電位Ｖｄａｔａを供給する。配線ＳＬ２には所定の定電位を与える、またはフローティング状態としてもよい。 [Period T2]
Subsequently, in the period T2, the wiring GL1 is given a potential for turning on the transistor M1, and the wiring GL2 is given a potential for turning off the transistor M2. Further, a second data potential V data is supplied to the wiring SL1. A predetermined constant potential may be applied to the wiring SL2, or the wiring SL2 may be in a floating state.
　ノードＮ１には、トランジスタＭ１を介して配線ＳＬ１から第２データ電位Ｖｄａｔａが与えられる。このとき、容量Ｃ１による容量結合により、第２データ電位Ｖｄａｔａに応じてノードＮ２の電位が電位ｄＶだけ変化する。すなわち、回路４１には、第１データ電位Ｖｗと電位ｄＶを足した電位が入力されることとなる。なお、図７Ｂでは電位ｄＶが正の値であるように示しているが、負の値であってもよい。すなわち、第２データ電位Ｖｄａｔａが電位Ｖｒｅｆより低くてもよい。 A second data potential V data is given to the node N1 from the wiring SL1 via the transistor M1. At this time, due to the capacitive coupling by the capacitance C1, the potential of the node N2 changes by the potential dV according to the second data potential V data . That is, the potential obtained by adding the first data potential V w and the potential dV is input to the circuit 41. Although FIG. 7B shows that the potential dV is a positive value, it may be a negative value. That is, the second data potential V data may be lower than the potential V ref .
　ここで、電位ｄＶは、容量Ｃ１の容量値と、回路４１の容量値によって概ね決定される。容量Ｃ１の容量値が回路４１の容量値よりも十分に大きい場合、電位ｄＶは第２データ電位Ｖｄａｔａに近い電位となる。 Here, the potential dV is generally determined by the capacitance value of the capacitance C1 and the capacitance value of the circuit 41. When the capacitance value of the capacitance C1 is sufficiently larger than the capacitance value of the circuit 41, the potential dV becomes a potential close to the second data potential V data .
　このように、画素１０は、２種類のデータ信号を組み合わせて表示素子を含む回路４１に供給する電位を生成することができるため、画素１０内で階調の補正を行うことが可能となる。 As described above, since the pixel 10 can generate a potential to be supplied to the circuit 41 including the display element by combining two types of data signals, it is possible to correct the gradation in the pixel 10.
　また画素１０は、配線ＳＬ１及び配線ＳＬ２に接続されるソースドライバが供給可能な最大電位を超える電位を生成することも可能となる。例えば発光素子を用いた場合では、ハイダイナミックレンジ（ＨＤＲ）表示等を行うことができる。また、液晶素子を用いた場合では、オーバードライブ駆動等を実現できる。 Further, the pixel 10 can also generate a potential exceeding the maximum potential that can be supplied by the source driver connected to the wiring SL1 and the wiring SL2. For example, when a light emitting element is used, high dynamic range (HDR) display and the like can be performed. Further, when a liquid crystal element is used, overdrive drive and the like can be realized.
〔液晶素子を用いた例〕
　図７Ｃに示す画素１０ＬＣは、回路４１ＬＣを有する。回路４１ＬＣは、液晶素子ＬＣと、容量Ｃ２とを有する。 [Example using a liquid crystal element]
The pixel 10LC shown in FIG. 7C has a circuit 41LC. The circuit 41LC has a liquid crystal element LC and a capacitance C2.
　液晶素子ＬＣは、一方の電極がノードＮ２及び容量Ｃ２の一方の電極と、他方の電極が電位Ｖｃｏｍ２が与えられる配線と接続する。容量Ｃ２は、他方の電極が電位Ｖｃｏｍ１が与えられる配線と接続する。 In the liquid crystal element LC, one electrode is connected to one electrode of the node N2 and the capacitance C2, and the other electrode is connected to the wiring to which the potential V com2 is given. The capacitance C2 is connected to a wiring in which the other electrode is given the potential V com1 .
　容量Ｃ２は保持容量として機能する。なお、容量Ｃ２は不要であれば省略することができる。 Capacity C2 functions as a holding capacity. The capacity C2 can be omitted if it is unnecessary.
　画素１０ＬＣは、液晶素子ＬＣに高い電圧を供給することができるため、例えばオーバードライブ駆動により高速な表示を実現すること、駆動電圧の高い液晶材料を適用することなどができる。また、配線ＳＬ１または配線ＳＬ２に補正信号を供給することで、使用温度、及び液晶素子ＬＣの劣化状態等に応じて階調を補正することもできる。 Since the pixel 10LC can supply a high voltage to the liquid crystal element LC, for example, it is possible to realize a high-speed display by overdrive driving, or to apply a liquid crystal material having a high driving voltage. Further, by supplying the correction signal to the wiring SL1 or the wiring SL2, the gradation can be corrected according to the operating temperature, the deterioration state of the liquid crystal element LC, and the like.
〔発光素子を用いた例〕
　図７Ｄに示す画素１０ＥＬは、回路４１ＥＬを有する。回路４１ＥＬは、発光素子ＥＬ、トランジスタＭ３、及び容量Ｃ２を有する。 [Example using a light emitting element]
The pixel 10EL shown in FIG. 7D has a circuit 41EL. The circuit 41EL has a light emitting element EL, a transistor M3, and a capacitance C2.
　トランジスタＭ３は、ゲートがノードＮ２及び容量Ｃ２の一方の電極と、ソース及びドレインの一方が電位ＶＨが与えられる配線と、他方が発光素子ＥＬの一方の電極と、それぞれ接続される。容量Ｃ２は、他方の電極が電位Ｖｃｏｍが与えられる配線と接続する。発光素子ＥＬは、他方の電極が電位ＶＬが与えられる配線と接続する。 In the transistor M3, the gate is connected to one electrode of the node N2 and the capacitance C2, one of the source and the drain is connected to the wiring to which the potential VH is given, and the other is connected to one electrode of the light emitting element EL. The capacitance C2 connects the other electrode to a wiring to which the potential V com is given. The light emitting element EL is connected to a wiring in which the other electrode is given the potential VL .
　トランジスタＭ３は、発光素子ＥＬに供給する電流を制御する機能を有する。容量Ｃ２は保持容量として機能する。容量Ｃ２は不要であれば省略することができる。 The transistor M3 has a function of controlling the current supplied to the light emitting element EL. The capacity C2 functions as a holding capacity. The capacity C2 can be omitted if it is unnecessary.
　なお、ここでは発光素子ＥＬのアノード側がトランジスタＭ３と接続する構成を示しているが、カソード側にトランジスタＭ３を接続してもよい。そのとき、電位ＶＨと電位ＶＬの値を適宜変更することができる。 Although the anode side of the light emitting element EL is connected to the transistor M3 here, the transistor M3 may be connected to the cathode side. At that time, the values of the potential V H and the potential VL can be changed as appropriate.
　画素１０ＥＬは、トランジスタＭ３のゲートに高い電位を与えることで、発光素子ＥＬに大きな電流を流すことができるため、例えばＨＤＲ表示などを実現することができる。また、配線ＳＬ１または配線ＳＬ２に補正信号を供給することで、トランジスタＭ３、及び発光素子ＥＬのうち一方または双方の電気特性のばらつきを補正することもできる。 By giving a high potential to the gate of the transistor M3, the pixel 10EL can pass a large current through the light emitting element EL, so that HDR display can be realized, for example. Further, by supplying the correction signal to the wiring SL1 or the wiring SL2, it is possible to correct the variation in the electrical characteristics of one or both of the transistor M3 and the light emitting element EL.
　なお、図７Ｃ及び図７Ｄで例示した回路に限られず、別途トランジスタまたは容量などを追加した構成としてもよい。 Note that the circuit is not limited to the circuit illustrated in FIGS. 7C and 7D, and a transistor or a capacitance may be added separately.
　以上が画素回路の説明である。 The above is the explanation of the pixel circuit.
　画素１０において、補正信号（第１データ電位Ｖｗ）の書き込み動作と、画像信号（第２データ電位Ｖｄａｔａ）の入力動作は連続して行ってもよいが、全ての画素に補正信号を書き込んだのちに画像信号の入力動作を行うことが好ましい。 In the pixel 10, the writing operation of the correction signal (first data potential V w ) and the input operation of the image signal (second data potential V data ) may be continuously performed, but the correction signal is written to all the pixels. It is preferable to perform the image signal input operation later.
　本発明の一態様の表示システムは、アップコンバートした画像を画素内で生成することができる。当該表示システムにおいて、画素に供給する画像信号は解像度の低い画像信号であり、複数の画素に同じ画像信号を供給することがある。例えば、水平垂直方向の４画素に同じ画像信号を供給する場合がある。この場合、各画素に接続される信号線のそれぞれに同じ画像信号を供給してもよいが、同じ画像信号を供給する信号線同士を電気的に接続することが好ましい。これにより、画像信号の書き込み動作を高速化することができる。 The display system of one aspect of the present invention can generate an up-converted image in pixels. In the display system, the image signal supplied to the pixels is an image signal having a low resolution, and the same image signal may be supplied to a plurality of pixels. For example, the same image signal may be supplied to four pixels in the horizontal and vertical directions. In this case, the same image signal may be supplied to each of the signal lines connected to each pixel, but it is preferable to electrically connect the signal lines that supply the same image signal. This makes it possible to speed up the operation of writing the image signal.
　例えば、２本の信号線同士を電気的に接続し、さらに隣り合う２本の走査線同士を電気的に接続することで、４画素の同時書き込みを行うことができる。これにより、書き込み時間を短縮することができ、フレーム周波数を高めることもできる。 For example, by electrically connecting two signal lines to each other and then electrically connecting two adjacent scanning lines, simultaneous writing of four pixels can be performed. As a result, the writing time can be shortened and the frame frequency can be increased.
＜表示システムの構成例２＞
　図８Ａ、図８Ｂを用いて、本実施の形態の表示システムにおける画像信号Ｓ２と補正信号Ｗ２の生成について説明する。 <Display system configuration example 2>
The generation of the image signal S2 and the correction signal W2 in the display system of the present embodiment will be described with reference to FIGS. 8A and 8B.
　処理部１５３は、表示部１５６から供給された信号Ｗ３を用いて、補正信号Ｗ２を生成してもよい。例えば、画素が有するトランジスタの電気特性を取得し、それに基づいた信号Ｗ３を処理部１５３に供給する。当該信号Ｗ３を用いて補正信号Ｗ２を生成することで、表示部１５６の表示ムラの抑制を実現できる。 The processing unit 153 may generate the correction signal W2 by using the signal W3 supplied from the display unit 156. For example, the electrical characteristics of the transistor possessed by the pixel are acquired, and the signal W3 based on the electrical characteristics is supplied to the processing unit 153. By generating the correction signal W2 using the signal W3, it is possible to suppress display unevenness of the display unit 156.
　図８Ａには、信号Ｗ３のみを用いて補正信号Ｗ２を生成する例を示す。図８Ｂには、信号Ｗ３に加えて、記憶部１５２から供給された補正データＷ１を用いて、補正信号Ｗ２を生成する例を示す。補正データＷ１を用いることで、例えば、表示ムラの補正に加えて、画像のアップコンバートなども可能となる。 FIG. 8A shows an example of generating a correction signal W2 using only the signal W3. FIG. 8B shows an example in which the correction signal W2 is generated by using the correction data W1 supplied from the storage unit 152 in addition to the signal W3. By using the correction data W1, for example, in addition to correcting display unevenness, up-conversion of an image can be performed.
　図９に、表示部１５６のブロック図の一例を示す。 FIG. 9 shows an example of a block diagram of the display unit 156.
　表示部１５６は、複数の画素１０ｄ、走査線駆動回路１２、信号線駆動回路１３、及び回路１５を有する。複数の画素１０ｄは、マトリクス状に設けられている。 The display unit 156 has a plurality of pixels 10d, a scanning line drive circuit 12, a signal line drive circuit 13, and a circuit 15. The plurality of pixels 10d are provided in a matrix.
　回路１５には、例えばシフトレジスタ回路を用いることができる。回路１５によって配線１６を順次選択し、その出力値（信号Ｗ３）を処理部１５３に入力することができる。 For the circuit 15, for example, a shift register circuit can be used. The wiring 16 can be sequentially selected by the circuit 15 and the output value (signal W3) thereof can be input to the processing unit 153.
　処理部１５３には、画像信号Ｓ１が供給される。さらに、処理部１５３には、補正データＷ１が供給されてもよい。また、上述の通り、処理部１５３には、回路１５から信号Ｗ３が供給される。 The image signal S1 is supplied to the processing unit 153. Further, the correction data W1 may be supplied to the processing unit 153. Further, as described above, the signal W3 is supplied to the processing unit 153 from the circuit 15.
　画素１０ｄと回路１５とは、配線１６を介して電気的に接続される。配線１６は、画素１０ｄ内のトランジスタまたは表示素子の、電気特性に関する情報を電位または電流として出力するための配線である。 The pixel 10d and the circuit 15 are electrically connected via the wiring 16. The wiring 16 is a wiring for outputting information on electrical characteristics of the transistor or display element in the pixel 10d as a potential or a current.
　処理部１５３は、画像信号Ｓ２及び補正信号Ｗ２を生成する機能を有する。 The processing unit 153 has a function of generating an image signal S2 and a correction signal W2.
　当該画素１０ｄでは、トランジスタの特性ばらつきを補正する動作を行うこともできる。ＥＬ素子を用いた画素では、ＥＬ素子に電流を供給する駆動トランジスタの閾値電圧のばらつきが表示品位に与える影響が大きいため、画素に駆動トランジスタの閾値電圧を補正する信号を保持させ、画像信号に付加することで表示品位を向上させることができる。 The pixel 10d can also perform an operation of correcting the variation in the characteristics of the transistor. In a pixel using an EL element, the variation in the threshold voltage of the drive transistor that supplies current to the EL element has a large effect on the display quality. Therefore, the pixel is made to hold a signal for correcting the threshold voltage of the drive transistor, and the image signal is used. By adding it, the display quality can be improved.
　例えば、信号Ｗ３としては、画素１０ｄに基準となる任意の電圧を書き込んだ際の、トランジスタに流れる電流値の情報を含む信号とすることができる。このとき、処理部１５３は、信号Ｗ３に含まれる電流値の情報を読み取って解析し、電流値が平均値または中央値であるトランジスタを基準として各画素に格納する補正信号Ｗ２を生成する。当該補正信号Ｗ２は、信号線駆動回路１３に入力され、各画素に書き込まれる。なお、電流値を読み取る機能を有する回路と、補正信号Ｗ２を生成する機能を有する回路は、それぞれ別であってもよい。 For example, the signal W3 can be a signal including information on the current value flowing through the transistor when an arbitrary voltage as a reference is written to the pixel 10d. At this time, the processing unit 153 reads and analyzes the information of the current value included in the signal W3, and generates a correction signal W2 to be stored in each pixel with the transistor whose current value is the average value or the median value as a reference. The correction signal W2 is input to the signal line drive circuit 13 and written to each pixel. The circuit having the function of reading the current value and the circuit having the function of generating the correction signal W2 may be different from each other.
　ここで、トランジスタの閾値電圧は、長期に亘って大きく変動することはあるが、短期間における変動は極めて少ない。したがって、補正信号の生成及び画素への書き込み動作は、フレームごとなどに行う必要はなく、電源投入時または動作終了時などに行えばよい。または、表示部１５６の動作時間を記録し、日、週、月、年などを単位とした一定期間ごとに動作を行ってもよい。 Here, the threshold voltage of the transistor may fluctuate greatly over a long period of time, but the fluctuation in a short period of time is extremely small. Therefore, the operation of generating the correction signal and writing to the pixel does not have to be performed for each frame, and may be performed at the time of turning on the power or at the end of the operation. Alternatively, the operation time of the display unit 156 may be recorded, and the operation may be performed at regular intervals in units of days, weeks, months, years, and the like.
　また、処理部１５３に供給される画像信号Ｓ１及び補正データＷ１のうち一方または双方と、信号Ｗ３と、を用いて補正信号Ｗ２を生成することで、閾値電圧補正とアップコンバートの両方の動作を行うこともできる。 Further, by generating the correction signal W2 using one or both of the image signal S1 and the correction data W1 supplied to the processing unit 153 and the signal W3, both the threshold voltage correction and the up-conversion operation can be performed. You can also do it.
　なお、上記では画素が有するトランジスタが出力する電流値を実測して補正信号Ｗ２を生成する方法を説明したが、その他の方法で補正信号Ｗ２を生成してもよい。例えば、グレースケールの表示を行い、当該表示の輝度を輝度計で読み取ったデータ、または当該表示の写真を読み取ったデータなどを元に、補正信号Ｗ２を生成してもよい。当該補正信号Ｗ２の生成には、ニューラルネットワークを用いた推論を用いることが好ましい。 Although the method of generating the correction signal W2 by actually measuring the current value output by the transistor of the pixel has been described above, the correction signal W2 may be generated by another method. For example, a grayscale display may be performed, and the correction signal W2 may be generated based on data obtained by reading the brightness of the display with a luminance meter, data obtained by reading a photograph of the display, and the like. It is preferable to use inference using a neural network to generate the correction signal W2.
　以上のように、本実施の形態の表示システムは、処理部及び表示部を有し、処理部は、画像信号及び補正信号を生成することができ、表示部は、画素に設けられた記憶回路で、当該補正信号を保持することができる。そして、表示部は、当該補正信号及び当該画像信号を用いて、映像を表示することができる。例えば、補正信号を画像信号に付加することで画像の解像度を変換することができる。画像処理で生成する画像信号に含まれるデータの解像度は、外部から入力されたデータの解像度から変更しなくてよいため、当該画像処理の演算量を低減し、消費電力を低減させることができる。 As described above, the display system of the present embodiment has a processing unit and a display unit, the processing unit can generate an image signal and a correction signal, and the display unit is a storage circuit provided in a pixel. Therefore, the correction signal can be held. Then, the display unit can display an image by using the correction signal and the image signal. For example, the resolution of an image can be converted by adding a correction signal to the image signal. Since the resolution of the data included in the image signal generated by the image processing does not have to be changed from the resolution of the data input from the outside, the calculation amount of the image processing can be reduced and the power consumption can be reduced.
　本実施の形態で例示した構成例、及びそれらに対応する図面等は、少なくともその一部を他の構成例、または図面等と適宜組み合わせることができる。 At least a part of the configuration example illustrated in the present embodiment and the drawings corresponding to them can be appropriately combined with other configuration examples, drawings, or the like.
　本実施の形態は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。 This embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.
（実施の形態２）
　本実施の形態では、本発明の一態様の記憶装置について、図１０及び図１１を用いて説明する。 (Embodiment 2)
In the present embodiment, the storage device of one aspect of the present invention will be described with reference to FIGS. 10 and 11.
＜記憶装置の構成例＞
　図１０Ａに記憶装置の構成の一例を示す。記憶装置１４００は、周辺回路１４１１及びメモリセルアレイ１４７０を有する。周辺回路１４１１は、行回路１４２０、列回路１４３０、出力回路１４４０、及び、コントロールロジック回路１４６０を有する。 <Configuration example of storage device>
FIG. 10A shows an example of the configuration of the storage device. The storage device 1400 has a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
　列回路１４３０は、例えば、列デコーダ、ビット線ドライバ回路、プリチャージ回路、センスアンプ、及び、書き込み回路等を有する。プリチャージ回路は、配線をプリチャージする機能を有する。センスアンプは、メモリセルから読み出されたデータ信号を増幅する機能を有する。なお、上記配線は、メモリセルアレイ１４７０が有するメモリセルに接続されている配線であり、詳しくは後述する。増幅されたデータ信号は、出力回路１４４０を介して、データ信号ＲＤＡＴＡとして記憶装置１４００の外部に出力される。また、行回路１４２０は、例えば、行デコーダ、及び、ワード線ドライバ回路等を有し、アクセスする行を選択することができる。 The column circuit 1430 includes, for example, a column decoder, a bit line driver circuit, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. The wiring is the wiring connected to the memory cell of the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440. Further, the row circuit 1420 has, for example, a row decoder, a word line driver circuit, and the like, and the row to be accessed can be selected.
　記憶装置１４００には、外部から電源電圧として、低電源電圧（ＶＳＳ）、周辺回路１４１１用の高電源電圧（ＶＤＤ）、及び、メモリセルアレイ１４７０用の高電源電圧（ＶＩＬ）が供給される。また、記憶装置１４００には、制御信号（ＣＥ、ＷＥ、ＲＥ）、アドレス信号ＡＤＤＲ、及び、データ信号ＷＤＡＴＡが外部から入力される。アドレス信号ＡＤＤＲは、行デコーダ及び列デコーダに入力され、データ信号ＷＤＡＴＡは書き込み回路に入力される。 The storage device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 as power supply voltages from the outside. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.
　コントロールロジック回路１４６０は、外部から入力される制御信号（ＣＥ、ＷＥ、ＲＥ）を処理して、行デコーダの制御信号及び列デコーダの制御信号を生成する。制御信号ＣＥは、チップイネーブル信号であり、制御信号ＷＥは、書き込みイネーブル信号であり、制御信号ＲＥは、読み出しイネーブル信号である。コントロールロジック回路１４６０が処理する信号は、これに限定されるものではなく、必要に応じて、他の制御信号を入力すればよい。 The control logic circuit 1460 processes the control signals (CE, WE, RE) input from the outside to generate the control signal of the row decoder and the control signal of the column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.
　メモリセルアレイ１４７０は、行列状に配置された、複数個のメモリセルＭＣと、複数の配線を有する。なお、メモリセルアレイ１４７０と行回路１４２０とを接続している配線の数は、メモリセルＭＣの構成、一列に有するメモリセルＭＣの数などによって決まる。また、メモリセルアレイ１４７０と列回路１４３０とを接続している配線の数は、メモリセルＭＣの構成、一行に有するメモリセルＭＣの数などによって決まる。 The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one column, and the like. Further, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one row, and the like.
　なお、図１０Ａにおいて、周辺回路１４１１とメモリセルアレイ１４７０を同一平面上に形成する例について示したが、本実施の形態はこれに限られるものではない。例えば、図１０Ｂに示すように、周辺回路１４１１の一部の上に、メモリセルアレイ１４７０が重なるように設けられてもよい。例えば、メモリセルアレイ１４７０の下に重なるように、センスアンプを設ける構成にしてもよい。 Although FIG. 10A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, the present embodiment is not limited to this. For example, as shown in FIG. 10B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap under the memory cell array 1470.
　なお、本実施の形態に示す、周辺回路１４１１、メモリセルアレイ１４７０等の構成は、上記に限定されるものではない。これらの回路、及び当該回路に接続される配線、回路素子等の、配置または機能は、必要に応じて、変更、削除、または追加してもよい。本発明の一態様の記憶装置は、動作速度が速く、長期間のデータ保持が可能である。また、本発明の一態様の記憶装置は、書き換え耐性が高い。 The configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in the present embodiment are not limited to the above. The arrangement or function of these circuits and the wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary. The storage device of one aspect of the present invention has a high operating speed and can retain data for a long period of time. Further, the storage device of one aspect of the present invention has high rewrite resistance.
＜メモリセルの構成例＞
　図１１Ａに示す回路図に、上述のメモリセルＭＣの構成例を示す。メモリセルＭＣは、トランジスタＴｒと、容量Ｆｅと、を有する。また、図１１Ａには、センスアンプ回路ＳＡも示す。 <Memory cell configuration example>
The circuit diagram shown in FIG. 11A shows a configuration example of the above-mentioned memory cell MC. The memory cell MC has a transistor Tr and a capacitance Fe. Further, FIG. 11A also shows a sense amplifier circuit SA.
　なお、トランジスタＴｒは、ゲートの他、バックゲートを有してもよいし、有していなくてもよい。また、図１１Ａでは、トランジスタＴｒをｎチャネル型トランジスタとしているが、ｐチャネル型トランジスタとしてもよい。以下では、トランジスタＴｒ等がｎチャネル型トランジスタであるとして説明を行うが、電位の大小関係を適宜逆転させること等により、トランジスタＴｒ等をｐチャネル型としても以下の説明を参照することができる。 The transistor Tr may or may not have a back gate in addition to the gate. Further, in FIG. 11A, the transistor Tr is an n-channel type transistor, but a p-channel type transistor may be used. Hereinafter, the description will be made assuming that the transistor Tr or the like is an n-channel type transistor, but the following description can be referred to even if the transistor Tr or the like is a p-channel type by appropriately reversing the magnitude relationship of the potentials.
　トランジスタＴｒのソースまたはドレインの一方は、容量Ｆｅの一方の電極と電気的に接続される。トランジスタＴｒのソースまたはドレインの他方は、配線ＢＬと電気的に接続される。トランジスタＴｒのゲートは、配線ＷＬと電気的に接続される。容量Ｆｅの他方の電極は、配線ＰＬと電気的に接続される。配線ＢＬは、センスアンプ回路ＳＡと電気的に接続される。 One of the source and drain of the transistor Tr is electrically connected to one electrode of the capacitance Fe. The other of the source or drain of the transistor Tr is electrically connected to the wiring BL. The gate of the transistor Tr is electrically connected to the wiring WL. The other electrode of the capacitance Fe is electrically connected to the wiring PL. The wiring BL is electrically connected to the sense amplifier circuit SA.
　配線ＷＬは、ワード線としての機能を有し、配線ＷＬの電位を制御することにより、トランジスタＴｒのオンオフを制御することができる。例えば、配線ＷＬの電位を高電位とすることにより、トランジスタＴｒをオン状態とし、配線ＷＬの電位を低電位とすることにより、トランジスタＴｒをオフ状態とすることができる。配線ＷＬは、行回路１４２０が有するワード線ドライバ回路と電気的に接続され、ワード線ドライバ回路により、配線ＷＬの電位を制御することができる。 The wiring WL has a function as a word line, and the on / off of the transistor Tr can be controlled by controlling the potential of the wiring WL. For example, by setting the potential of the wiring WL to a high potential, the transistor Tr can be turned on, and by setting the potential of the wiring WL to a low potential, the transistor Tr can be turned off. The wiring WL is electrically connected to the word line driver circuit included in the row circuit 1420, and the potential of the wiring WL can be controlled by the word line driver circuit.
　配線ＢＬは、ビット線としての機能を有し、配線ＢＬを介してメモリセルＭＣにデータが書き込まれ、またメモリセルＭＣに保持されたデータが配線ＢＬを介して読み出される。 The wiring BL has a function as a bit line, data is written to the memory cell MC via the wiring BL, and data held in the memory cell MC is read out via the wiring BL.
　センスアンプ回路ＳＡは、列回路１４３０のビット線ドライバ回路に設けられる。センスアンプ回路ＳＡには、電位Ｖｒｅｆを供給することができ、また信号ＥＮを供給することができる。 The sense amplifier circuit SA is provided in the bit line driver circuit of the column circuit 1430. The potential Vref can be supplied to the sense amplifier circuit SA, and the signal EN can be supplied.
　センスアンプ回路ＳＡは、例えばメモリセルＭＣから読み出されるデータを増幅する機能を有する。例えば、配線ＢＬの電位とＶｒｅｆの差に基づき、メモリセルＭＣから読み出されるデータを増幅する機能を有する。 The sense amplifier circuit SA has a function of amplifying data read from, for example, a memory cell MC. For example, it has a function of amplifying data read from the memory cell MC based on the difference between the potential of the wiring BL and Vref.
　信号ＥＮは、センスアンプ回路ＳＡを活性化するか否かを制御する、イネーブル信号とすることができる。信号ＥＮは、例えば２値のデジタル信号とすることができる。例えば、信号ＥＮの電位が高電位である場合は、センスアンプ回路ＳＡを活性化状態とすることができ、信号ＥＮの電位が低電位である場合は、センスアンプ回路ＳＡを非活性化状態とすることができる。センスアンプ回路ＳＡが活性化状態である場合は、例えばメモリセルＭＣから読み出されるデータの増幅が行われる。一方、センスアンプ回路ＳＡが非活性化状態である場合は、当該増幅は行われない。 The signal EN can be an enable signal that controls whether or not to activate the sense amplifier circuit SA. The signal EN can be, for example, a binary digital signal. For example, when the potential of the signal EN is high, the sense amplifier circuit SA can be in the activated state, and when the potential of the signal EN is low, the sense amplifier circuit SA can be in the deactivated state. can do. When the sense amplifier circuit SA is in the activated state, for example, the data read from the memory cell MC is amplified. On the other hand, when the sense amplifier circuit SA is in the deactivated state, the amplification is not performed.
　配線ＰＬは、プレート線としての機能を有し、配線ＰＬの電位を、容量Ｆｅの他方の電極の電位とすることができる。配線ＰＬは、プレート線ドライバ回路と電気的に接続され、プレート線ドライバ回路により、配線ＰＬの電位を制御することができる。プレート線ドライバ回路は行回路１４２０または列回路１４３０に設けられていてもよい。 The wiring PL has a function as a plate wire, and the potential of the wiring PL can be the potential of the other electrode of the capacitance Fe. The wiring PL is electrically connected to the plate wire driver circuit, and the potential of the wiring PL can be controlled by the plate wire driver circuit. The plate wire driver circuit may be provided in the row circuit 1420 or the column circuit 1430.
　トランジスタＴｒとして、チャネル形成領域に酸化物半導体を有するトランジスタ（ＯＳトランジスタ）を適用することが好ましい。ＯＳトランジスタは、高耐圧であるという特性を有する。よって、トランジスタＴｒをＯＳトランジスタとすることにより、トランジスタＴｒを微細化しても、トランジスタＴｒに高電圧を印加することができる。トランジスタＴｒを微細化することにより、メモリセルＭＣの占有面積を小さくすることができる。例えば、図１１Ａに示すメモリセルＭＣの１個あたりの占有面積は、ＳＲＡＭセルの１個あたりの占有面積の１／３乃至１／６とすることができる。よって、メモリセルＭＣを高密度に配置することができる。これにより、本発明の一態様に係る記憶装置を、記憶容量が大きな記憶装置とすることができる。 As the transistor Tr, it is preferable to apply a transistor (OS transistor) having an oxide semiconductor in the channel forming region. The OS transistor has a characteristic of having a high withstand voltage. Therefore, by using the transistor Tr as an OS transistor, a high voltage can be applied to the transistor Tr even if the transistor Tr is miniaturized. By miniaturizing the transistor Tr, the occupied area of the memory cell MC can be reduced. For example, the occupied area per memory cell MC shown in FIG. 11A can be 1/3 to 1/6 of the occupied area per SRAM cell. Therefore, the memory cells MC can be arranged at a high density. Thereby, the storage device according to one aspect of the present invention can be a storage device having a large storage capacity.
　また、トランジスタＴｒとして、チャネル形成領域にシリコンを有するトランジスタ（Ｓｉトランジスタ）を適用することが好ましい。特に、単結晶シリコンを用いたトランジスタを適用することが好ましい。Ｓｉトランジスタは、電気特性のばらつきが小さい、電気特性が安定している、電界効果移動度が高い、微細化が容易である、などの特性を有する。よって、トランジスタＴｒをＳｉトランジスタとすることにより、極めて微細で、信頼性が高く、かつ、セル間の電気特性のばらつきの小さいメモリセルＭＣを実現できる。また、Ｓｉトランジスタの微細化により、さらに電界効果移動度を高くできるため、１つのメモリセルＭＣあたりの読み出し速度を高めることができる。 Further, it is preferable to apply a transistor (Si transistor) having silicon in the channel forming region as the transistor Tr. In particular, it is preferable to apply a transistor using single crystal silicon. The Si transistor has characteristics such as small variation in electrical characteristics, stable electrical characteristics, high field effect mobility, and easy miniaturization. Therefore, by using the transistor Tr as a Si transistor, it is possible to realize a memory cell MC that is extremely fine, highly reliable, and has little variation in electrical characteristics between cells. Further, by miniaturizing the Si transistor, the field effect mobility can be further increased, so that the read speed per memory cell MC can be increased.
　容量Ｆｅは、一対の電極間に、誘電体層として強誘電体層を挟持した、ＭＦＭ（Ｍｅｔａｌ−Ｆｅｒｒｏｅｌｅｃｔｒｉｃ−Ｍｅｔａｌ）構造を有する強誘電キャパシタとすることができる。強誘電体層は、強誘電性を示す材料を有する。 The capacitive Fe can be a ferroelectric capacitor having an MFM (Metal-Ferroelectric-Metal) structure in which a ferroelectric layer is sandwiched between a pair of electrodes. The ferroelectric layer has a material that exhibits ferroelectricity.
　強誘電性を示す材料は、絶縁体であって、外部から電場を与えることによって内部に分極が生じ、かつ当該電場をゼロにしても分極が残る性質を有する。このため、当該材料を誘電体として用いた容量素子（強誘電キャパシタ）を用いて、不揮発性の記憶素子を形成することができる。強誘電キャパシタを用いた、不揮発性の記憶素子は、ＦｅＲＡＭ（Ｆｅｒｒｏｅｌｅｃｔｒｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、強誘電体メモリなどと呼ばれることがある。例えば、強誘電体メモリは、トランジスタと、強誘電キャパシタを有し、トランジスタのソース及びドレインの一方が、強誘電キャパシタの一方の端子に電気的に接続された構成にすることができる。 The material exhibiting ferroelectricity is an insulator, and has the property that polarization occurs inside by applying an electric field from the outside, and polarization remains even if the electric field is set to zero. Therefore, a non-volatile storage element can be formed by using a capacitive element (ferroelectric capacitor) using the material as a dielectric. A non-volatile storage element using a ferroelectric capacitor may be referred to as a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, or the like. For example, a ferroelectric memory may have a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor may be electrically connected to one terminal of the ferroelectric capacitor.
　強誘電性を示しうる材料として、例えば、酸化ハフニウム、あるいは、酸化ハフニウム及び酸化ジルコニウムを有する材料を用いることができる。酸化ハフニウム、あるいは、酸化ハフニウム及び酸化ジルコニウムを有する材料は、数ｎｍといった薄膜に加工しても強誘電性を示すことができるため、好ましい。強誘電体層を薄膜化することで、微細化されたトランジスタと組み合わされた記憶装置とすることができる。 As a material capable of exhibiting ferroelectricity, for example, hafnium oxide, or a material having hafnium oxide and zirconium oxide can be used. A material having hafnium oxide or hafnium oxide and zirconium oxide is preferable because it can exhibit ferroelectricity even when processed into a thin film of several nm. By thinning the ferroelectric layer, a storage device combined with a miniaturized transistor can be obtained.
　以上のように、図１１Ａに示すメモリセルＭＣには、強誘電キャパシタ及びトランジスタを有するＦｅＲＡＭが適用されている。図１１Ａに示すメモリセルＭＣは、少なくとも容量素子と、容量素子の充放電を制御するトランジスタと、を有する。 As described above, FeRAM having a ferroelectric capacitor and a transistor is applied to the memory cell MC shown in FIG. 11A. The memory cell MC shown in FIG. 11A has at least a capacitive element and a transistor for controlling charge / discharge of the capacitive element.
　なお、メモリセルＭＣには、他の強誘電体メモリを用いることもできる。本発明の一態様の記憶装置は、上記強誘電体メモリの一つまたは複数を用いて作製することができる。なお、本明細書等において、誘電体として強誘電性を有し得る材料を有する容量（例えば、容量Ｆｅ）の回路記号は、図１１Ａのとおり、容量の回路記号に斜線を加えたものとしている。 It should be noted that another ferroelectric memory can be used for the memory cell MC. The storage device of one aspect of the present invention can be manufactured by using one or more of the above-mentioned ferroelectric memories. In the present specification and the like, the circuit symbol of the capacitance (for example, the capacitance Fe) having a material capable of having ferroelectricity as a dielectric is assumed to be a diagonal line added to the circuit symbol of the capacitance as shown in FIG. 11A. ..
　容量Ｆｅが有する誘電体は、ヒステリシス特性を有する。図１１Ｂは、当該ヒステリシス特性の一例を示すグラフである。 The dielectric of the capacitance Fe has a hysteresis characteristic. FIG. 11B is a graph showing an example of the hysteresis characteristic.
　図１１Ｂにおいて、横軸は誘電体に印加する電圧を示す。当該電圧は、例えば容量Ｆｅの一方の電極の電位と、容量Ｆｅの他方の電極の電位と、の差とすることができる。 In FIG. 11B, the horizontal axis indicates the voltage applied to the dielectric. The voltage can be, for example, the difference between the potential of one electrode of the capacitance Fe and the potential of the other electrode of the capacitance Fe.
　また、図１１Ｂにおいて、縦軸は誘電体の分極量（分極ともいう）を示し、正の値の場合は負電荷が容量Ｆｅの一方の電極側に偏り、正電荷が容量Ｆｅの他方の電極側に偏っていることを示す。一方、分極量が負の値の場合は、負電荷が容量Ｆｅの他方の電極側に偏り、正電荷が容量Ｆｅの一方の電極側に偏っていることを示す。 Further, in FIG. 11B, the vertical axis indicates the amount of polarization (also referred to as polarization) of the dielectric. If the value is positive, the negative charge is biased toward one electrode of the capacitance Fe, and the positive charge is the other electrode of the capacitance Fe. Indicates that it is biased to the side. On the other hand, when the amount of polarization is a negative value, it indicates that the negative charge is biased toward the other electrode side of the capacitance Fe and the positive charge is biased toward one electrode side of the capacitance Fe.
　なお、図１１Ｂのグラフの横軸に示す電圧を、容量Ｆｅの他方の電極の電位と、容量Ｆｅの一方の電極の電位と、の差としてもよい。また、図１１Ｂのグラフの縦軸に示す分極量を、負電荷が容量Ｆｅの他方の電極側に偏り、正電荷が容量Ｆｅの一方の電極側に偏っている場合に正の値とし、負電荷が容量Ｆｅの一方の電極側に偏り、正電荷が容量Ｆｅの他方の電極側に偏っている場合に負の値としてもよい。 The voltage shown on the horizontal axis of the graph of FIG. 11B may be the difference between the potential of the other electrode of the capacitance Fe and the potential of one electrode of the capacitance Fe. Further, the amount of polarization shown on the vertical axis of the graph of FIG. 11B is set to a positive value when the negative charge is biased toward the other electrode side of the capacitance Fe and the positive charge is biased toward one electrode side of the capacitance Fe, and is negative. When the charge is biased to one electrode side of the capacitance Fe and the positive charge is biased to the other electrode side of the capacitance Fe, it may be a negative value.
　図１１Ｂに示すように、誘電体のヒステリシス特性は、曲線５１と、曲線５２と、により表すことができる。曲線５１と曲線５２の交点における電圧を、ＶＳＰ及び−ＶＳＰとする。 As shown in FIG. 11B, the hysteresis characteristic of the dielectric can be represented by the curve 51 and the curve 52. Let the voltage at the intersection of the curve 51 and the curve 52 be VSP and −VSP.
　誘電体に−ＶＳＰ以下の電圧を印加した後に、誘電体に印加する電圧を高くしていくと、誘電体の分極量は、曲線５１に沿って増加する。一方、誘電体にＶＳＰ以上の電圧を印加した後に、誘電体に印加する電圧を低くしていくと、誘電体の分極量は、曲線５２に沿って減少する。よって、ＶＳＰ及び−ＶＳＰは、飽和分極電圧ということができる。 When the voltage applied to the dielectric is increased after applying a voltage of −VSP or less to the dielectric, the amount of polarization of the dielectric increases along the curve 51. On the other hand, when the voltage applied to the dielectric is lowered after applying a voltage equal to or higher than VSP to the dielectric, the amount of polarization of the dielectric decreases along the curve 52. Therefore, VSP and −VSP can be said to be saturated polarization voltages.
　ここで、誘電体の分極量が曲線５１に沿って変化する際の、誘電体の分極量が０である場合における、誘電体に印加される電圧をＶｃとする。また、誘電体の分極量が曲線５２に沿って変化する際の、誘電体の分極量が０である場合における、誘電体に印加される電圧を−Ｖｃとする。Ｖｃ及び−Ｖｃは、抗電圧ということができる。Ｖｃの値及び−Ｖｃの値は、−ＶＳＰとＶＳＰの間の値であるということができる。 Here, the voltage applied to the dielectric when the polarization amount of the dielectric changes along the curve 51 and the polarization amount of the dielectric is 0 is defined as Vc. Further, when the polarization amount of the dielectric changes along the curve 52 and the polarization amount of the dielectric is 0, the voltage applied to the dielectric is −Vc. Vc and -Vc can be said to be withstand voltage. It can be said that the value of Vc and the value of -Vc are values between -VSP and VSS.
　前述のように、容量Ｆｅが有する誘電体に印加される電圧は、容量Ｆｅの一方の電極の電位と、容量Ｆｅの他方の電極の電位と、の差により表すことができる。また、前述のように、容量Ｆｅの他方の電極は、配線ＰＬと電気的に接続される。よって、配線ＰＬの電位を制御することにより、容量Ｆｅが有する誘電体に印加される電圧を制御することができる。 As described above, the voltage applied to the dielectric of the capacitance Fe can be expressed by the difference between the potential of one electrode of the capacitance Fe and the potential of the other electrode of the capacitance Fe. Further, as described above, the other electrode of the capacitance Fe is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, it is possible to control the voltage applied to the dielectric material of the capacitance Fe.
　メモリセルＭＣは、例えば値を“０”又は“１”で表すことができる２値データを保持することができる。この場合、メモリセルＭＣに保持されるデータは、例えば容量Ｆｅが有する誘電体の分極量により判断することができる。例えば、容量Ｆｅが有する誘電体の分極量が正の値である場合は、メモリセルＭＣには値が“１”のデータが保持されているとすることができる。一方、容量Ｆｅが有する誘電体の分極量が負の値である場合は、メモリセルＭＣには値が“０”のデータが保持されているとすることができる。なお、例えば容量Ｆｅが有する誘電体の分極量が正の値である場合に、メモリセルＭＣに値が“０”のデータが保持されているとし、負の値である場合に、メモリセルＭＣに値が“１”のデータが保持されているとしてもよい。 The memory cell MC can hold binary data whose value can be represented by, for example, "0" or "1". In this case, the data held in the memory cell MC can be determined, for example, by the amount of polarization of the dielectric contained in the capacitance Fe. For example, when the amount of polarization of the dielectric contained in the capacitance Fe is a positive value, it can be assumed that the memory cell MC holds data having a value of “1”. On the other hand, when the polarization amount of the dielectric contained in the capacitance Fe is a negative value, it can be assumed that the data having a value of "0" is held in the memory cell MC. For example, when the polarization amount of the dielectric contained in the capacitance Fe is a positive value, it is assumed that the data having a value of "0" is held in the memory cell MC, and when the value is negative, the memory cell MC is used. Data having a value of "1" may be held in the data.
＜メモリセルの駆動方法例＞
　以下では、図１１Ａに示すメモリセルＭＣの駆動方法の一例を説明する。以下の説明において、容量Ｆｅの誘電体に印加される電圧とは、容量Ｆｅの一方の電極の電位と、容量Ｆｅの他方の電極（配線ＰＬ）の電位と、の差を示すものとする。また、メモリセルＭＣに書き込まれ、メモリセルＭＣから読み出されるデータは、値を“０”又は“１”で表すことができる２値データとする。また、容量Ｆｅが有する誘電体の分極量が負の値である場合は、メモリセルＭＣに値が“０”のデータが保持されているとし、正の値である場合は、メモリセルＭＣに値が“１”のデータが保持されているとする。さらに、トランジスタＴｒは、ｎチャネル型トランジスタとする。 <Example of driving method of memory cell>
Hereinafter, an example of the driving method of the memory cell MC shown in FIG. 11A will be described. In the following description, the voltage applied to the dielectric of the capacitance Fe indicates the difference between the potential of one electrode of the capacitance Fe and the potential of the other electrode (wiring PL) of the capacitance Fe. Further, the data written in the memory cell MC and read out from the memory cell MC is binary data whose value can be represented by "0" or "1". Further, when the polarization amount of the dielectric contained in the capacitance Fe is a negative value, it is assumed that the data having a value of "0" is held in the memory cell MC, and when the value is positive, the memory cell MC has. It is assumed that the data having a value of "1" is held. Further, the transistor Tr is an n-channel type transistor.
　図１２は、図１１Ａに示すメモリセルＭＣの駆動方法の一例を示すタイミングチャートである。図１２において、“Ｈ”は高電位を示し、“Ｌ”は低電位を示す。図１２では、メモリセルＭＣが駆動する期間として、時刻Ｔ０１乃至時刻Ｔ３６を示している。 FIG. 12 is a timing chart showing an example of the driving method of the memory cell MC shown in FIG. 11A. In FIG. 12, “H” indicates a high potential and “L” indicates a low potential. In FIG. 12, the time T01 to the time T36 are shown as the period during which the memory cell MC is driven.
　時刻Ｔ０１以前において、メモリセルＭＣに値が“０”のデータが保持されているものとする。つまり、容量Ｆｅの誘電体の分極量が、負であるとする。 It is assumed that the data whose value is "0" is held in the memory cell MC before the time T01. That is, it is assumed that the amount of polarization of the dielectric of the capacitance Fe is negative.
　時刻Ｔ０１乃至時刻Ｔ０６において、値が“０”のデータをメモリセルＭＣから読み出す。時刻Ｔ１１乃至時刻Ｔ１６において、値が“０”のデータをメモリセルＭＣから読み出した後に、値が“１”のデータのメモリセルＭＣへの書き込みを行う。時刻Ｔ２１乃至時刻Ｔ２６において、値が“１”のデータをメモリセルＭＣから読み出した後に、当該データのメモリセルＭＣへの書き戻しを行う。時刻Ｔ３１乃至時刻Ｔ３６において、値が“１”のデータをメモリセルＭＣから読み出した後に、値が“０”のデータのメモリセルＭＣへの書き込みを行う。 At time T01 to time T06, the data whose value is "0" is read from the memory cell MC. At time T11 to time T16, after reading the data having a value of "0" from the memory cell MC, the data having a value "1" is written to the memory cell MC. At time T21 to time T26, after reading the data having a value of "1" from the memory cell MC, the data is written back to the memory cell MC. At time T31 to time T36, after reading the data having a value of "1" from the memory cell MC, the data having a value "0" is written to the memory cell MC.
　時刻Ｔ０１以前において、配線ＷＬの電位及び信号ＥＮの電位が、低電位であるとする。また、時刻Ｔ０１以前において、配線ＰＬの電位及び配線ＢＬの電位がＧＮＤであるとする。ＧＮＤは、例えば接地電位とすることができる。なお、ＧＮＤは、メモリセルＭＣ等を本発明の一態様の趣旨を充足するように駆動させることができるのであれば、必ずしも接地電位としなくてもよい。 Before time T01, it is assumed that the potential of the wiring WL and the potential of the signal EN are low potentials. Further, it is assumed that the potential of the wiring PL and the potential of the wiring BL are GND before the time T01. GND can be, for example, a ground potential. The GND does not necessarily have to be the ground potential as long as the memory cell MC or the like can be driven so as to satisfy the gist of one aspect of the present invention.
　時刻Ｔ０１乃至時刻Ｔ０２において、配線ＷＬの電位を高電位とする。これにより、トランジスタＴｒがオン状態となるため、容量Ｆｅの一方の電極と配線ＢＬが導通する。 At time T01 to time T02, the potential of the wiring WL is set to a high potential. As a result, the transistor Tr is turned on, so that one electrode of the capacitance Fe and the wiring BL are conducted.
　時刻Ｔ０２乃至時刻Ｔ０３において、配線ＰＬの電位をＶｗとする。ＧＮＤが接地電位である場合は、ＶｗはＶＳＰ以上とする。配線ＰＬの電位をＧＮＤからＶｗに上昇させることで、配線ＢＬの電位が、容量Ｆｅを介した容量結合により、時刻Ｔ０２の開始時点における容量Ｆｅの誘電体の分極量、つまりメモリセルＭＣに保持されているデータに応じて上昇する。 At time T02 to time T03, the potential of the wiring PL is Vw. When GND is the ground potential, Vw is VSP or higher. By raising the potential of the wiring PL from GND to Vw, the potential of the wiring BL is held in the polarization amount of the dielectric of the capacitance Fe at the start time of time T02, that is, in the memory cell MC due to the capacitive coupling via the capacitance Fe. It rises according to the data being made.
　以下では、ＶｗはＶＳＰ以上の高さの電位であり、ＧＮＤは接地電位であるとして説明を行う。また、配線ＰＬ及び配線ＢＬに供給される電位について、Ｖｗを高電位、ＧＮＤを低電位として説明を行う。さらに、Ｖｒｅｆは、ＶｗとＧＮＤの間の電位として説明を行う。 In the following, it will be described that Vw is a potential higher than VSS and GND is a ground potential. Further, the potentials supplied to the wiring PL and the wiring BL will be described with Vw as a high potential and GND as a low potential. Further, Vref is described as a potential between Vw and GND.
　時刻Ｔ０２乃至時刻Ｔ０３では、メモリセルＭＣに値が“０”のデータが保持されている。この場合は、配線ＢＬの電位がＶｒｅｆまでは上昇しないものとする。 At time T02 to time T03, data having a value of "0" is held in the memory cell MC. In this case, it is assumed that the potential of the wiring BL does not rise to Vref.
　以上により、メモリセルＭＣに保持されているデータが読み出され、配線ＢＬを介してセンスアンプ回路ＳＡに入力することができる。 From the above, the data held in the memory cell MC can be read out and input to the sense amplifier circuit SA via the wiring BL.
　時刻Ｔ０３乃至時刻Ｔ０４において、信号ＥＮの電位を高電位とする。これにより、センスアンプ回路ＳＡが活性化状態となり、メモリセルＭＣから読み出されるデータが、配線ＢＬの電位とＶｒｅｆの差に基づいて増幅される。時刻Ｔ０３の開始時点では、配線ＢＬの電位はＶｒｅｆより低い。よって、配線ＢＬの電位が、低電位であるＧＮＤとなり、メモリセルＭＣから読み出された、値が“０”のデータが増幅される。 At time T03 to time T04, the potential of the signal EN is set to a high potential. As a result, the sense amplifier circuit SA is activated, and the data read from the memory cell MC is amplified based on the difference between the potential of the wiring BL and Vref. At the start of time T03, the potential of the wiring BL is lower than Vref. Therefore, the potential of the wiring BL becomes GND, which is a low potential, and the data whose value is “0” read from the memory cell MC is amplified.
　また、時刻Ｔ０３乃至時刻Ｔ０４において、トランジスタＴｒがオン状態であるため、容量Ｆｅの誘電体に印加される電圧は、−Ｖｗとなる。よって、図１１Ｂに示すように、容量Ｆｅの誘電体の分極量は負のままであり、メモリセルＭＣには値が“０”のデータが引き続き保持される。 Further, since the transistor Tr is in the ON state at time T03 to time T04, the voltage applied to the dielectric of the capacitance Fe is −Vw. Therefore, as shown in FIG. 11B, the amount of polarization of the dielectric of the capacitance Fe remains negative, and the data having a value of “0” is continuously held in the memory cell MC.
　時刻Ｔ０４乃至時刻Ｔ０５において、配線ＰＬの電位をＧＮＤとする。時刻Ｔ０４乃至時刻Ｔ０５において、トランジスタＴｒはオン状態であり、配線ＢＬの電位はＧＮＤであるため、容量Ｆｅの誘電体に印加される電位は０Ｖとなる。容量Ｆｅの誘電体の分極量は、図１１Ｂに示す曲線５１に沿って変化するため、容量Ｆｅの誘電体に印加される電位を０Ｖとしても、容量Ｆｅの誘電体の分極量は負のままである。よって、メモリセルＭＣには値が“０”のデータが引き続き保持される。 At time T04 to time T05, the potential of the wiring PL is set to GND. At time T04 to time T05, the transistor Tr is in the ON state and the potential of the wiring BL is GND, so that the potential applied to the dielectric of the capacitance Fe is 0V. Since the amount of polarization of the dielectric of the capacitance Fe changes along the curve 51 shown in FIG. 11B, the amount of polarization of the dielectric of the capacitance Fe remains negative even if the potential applied to the dielectric of the capacitance Fe is 0V. Is. Therefore, the data having a value of "0" is continuously held in the memory cell MC.
　時刻Ｔ０５乃至時刻Ｔ０６において、信号ＥＮの電位を低電位とする。これにより、センスアンプ回路ＳＡが非活性状態となる。 At time T05 to time T06, the potential of the signal EN is set to a low potential. As a result, the sense amplifier circuit SA becomes inactive.
　時刻Ｔ０６乃至時刻Ｔ１１において、配線ＷＬの電位を低電位とする。これにより、トランジスタＴｒがオフ状態となる。 At time T06 to time T11, the potential of the wiring WL is set to a low potential. As a result, the transistor Tr is turned off.
　時刻Ｔ１１乃至時刻Ｔ２１における配線ＷＬの電位、配線ＰＬの電位、及び信号ＥＮの電位は、時刻Ｔ０１乃至時刻Ｔ１１における配線ＷＬの電位、配線ＰＬの電位、及び信号ＥＮの電位と同様とすることができる。 The potential of the wiring WL, the potential of the wiring PL, and the potential of the signal EN at time T11 to time T21 may be the same as the potential of the wiring WL, the potential of the wiring PL, and the potential of the signal EN at time T01 to time T11. can.
　時刻Ｔ１２乃至時刻Ｔ１３では、メモリセルＭＣに値が“０”のデータが保持されている。よって、時刻Ｔ０２乃至時刻Ｔ０３と同様に、配線ＢＬの電位はＶｒｅｆまでは上昇しない。 At time T12 to time T13, data having a value of "0" is held in the memory cell MC. Therefore, similarly to the time T02 to the time T03, the potential of the wiring BL does not rise up to Vref.
　時刻Ｔ１３乃至時刻Ｔ１４において、配線ＢＬの電位が、低電位であるＧＮＤとなり、メモリセルＭＣから読み出された、値が“０”のデータが増幅される。 At time T13 to time T14, the potential of the wiring BL becomes GND, which is a low potential, and the data read from the memory cell MC and having a value of "0" is amplified.
　ここで、上記増幅を行った後、配線ＢＬの電位をＶｗとする。トランジスタＴｒはオン状態であるため、容量Ｆｅの一方の電極の電位はＶｗとなる。 Here, after performing the above amplification, the potential of the wiring BL is set to Vw. Since the transistor Tr is in the ON state, the potential of one electrode of the capacitance Fe is Vw.
　時刻Ｔ１４乃至時刻Ｔ１５において、配線ＰＬの電位をＧＮＤとすることにより、容量Ｆｅの誘電体に印加される電圧が、Ｖｗとなる。これにより、図１１Ｂに示すように、容量Ｆｅの誘電体の分極量が正となる。よって、メモリセルＭＣには、値が“１”のデータが書き込まれる。 By setting the potential of the wiring PL to GND at time T14 to time T15, the voltage applied to the dielectric of the capacitance Fe becomes Vw. As a result, as shown in FIG. 11B, the amount of polarization of the dielectric of the capacitive Fe becomes positive. Therefore, data having a value of "1" is written in the memory cell MC.
　時刻Ｔ１５乃至時刻Ｔ１６において、信号ＥＮの電位を低電位とすることにより、配線ＢＬの電位が低電位であるＧＮＤとなる。時刻Ｔ１５乃至時刻Ｔ１６において、トランジスタＴｒはオン状態であり、配線ＰＬの電位はＧＮＤであるため、容量Ｆｅの誘電体に印加される電位は０Ｖとなる。容量Ｆｅの誘電体の分極量は、図１１Ｂに示す曲線５２に沿って変化するため、容量Ｆｅの誘電体に印加される電位を０Ｖとしても、容量Ｆｅの誘電体の分極量は正のままである。よって、メモリセルＭＣには値が“１”のデータが保持される。 By setting the potential of the signal EN to a low potential at time T15 to time T16, the potential of the wiring BL becomes GND, which is a low potential. At time T15 to time T16, the transistor Tr is in the ON state and the potential of the wiring PL is GND, so that the potential applied to the dielectric of the capacitance Fe is 0V. Since the amount of polarization of the dielectric of the capacitance Fe changes along the curve 52 shown in FIG. 11B, the amount of polarization of the dielectric of the capacitance Fe remains positive even if the potential applied to the dielectric of the capacitance Fe is 0V. Is. Therefore, the data whose value is "1" is held in the memory cell MC.
　時刻Ｔ２１乃至時刻Ｔ３１における配線ＷＬの電位、配線ＰＬの電位、及び信号ＥＮの電位は、時刻Ｔ１１乃至時刻Ｔ２１等における配線ＷＬの電位、配線ＰＬの電位、及び信号ＥＮの電位と同様とすることができる。 The potential of the wiring WL, the potential of the wiring PL, and the potential of the signal EN at the time T21 to the time T31 shall be the same as the potential of the wiring WL, the potential of the wiring PL, and the potential of the signal EN at the time T11 to the time T21 and the like. Can be done.
　時刻Ｔ２２の開始時点では、メモリセルＭＣに値が“１”のデータが保持されている。この状態で、配線ＰＬの電位を高電位とすることにより、配線ＢＬの電位がＶｒｅｆより高くなるものとする。ここで、配線ＰＬの電位を高電位とすることにより、容量Ｆｅの誘電体において分極反転が発生し、メモリセルＭＣに保持される値が“１”のデータが破壊される場合がある。 At the start of time T22, data having a value of "1" is held in the memory cell MC. In this state, by setting the potential of the wiring PL to a high potential, the potential of the wiring BL is assumed to be higher than that of Vref. Here, by setting the potential of the wiring PL to a high potential, polarization inversion may occur in the dielectric of the capacitance Fe, and the data whose value held in the memory cell MC is “1” may be destroyed.
　時刻Ｔ２３乃至時刻Ｔ２４において、センスアンプ回路ＳＡが活性化状態となり、メモリセルＭＣから読み出されるデータが、配線ＢＬの電位とＶｒｅｆの差に基づいて増幅される。時刻Ｔ２３の開始時点では、配線ＢＬの電位はＶｒｅｆより高い。よって、配線ＢＬの電位が、高電位であるＶｗとなり、メモリセルＭＣから読み出された、値が“１”のデータが増幅される。 At time T23 to time T24, the sense amplifier circuit SA is activated, and the data read from the memory cell MC is amplified based on the difference between the potential of the wiring BL and Vref. At the start of time T23, the potential of the wiring BL is higher than Vref. Therefore, the potential of the wiring BL becomes Vw, which is a high potential, and the data with the value “1” read from the memory cell MC is amplified.
　時刻Ｔ２４乃至時刻Ｔ２５において、配線ＰＬの電位をＧＮＤとすることにより、容量Ｆｅの誘電体に印加される電圧が、Ｖｗとなる。これにより、メモリセルＭＣに、値が“１”のデータを書き戻すことができる。よって、メモリセルＭＣに保持されたデータが破壊された場合であっても、値が“１”のデータをメモリセルＭＣに再度保持させることができる。 By setting the potential of the wiring PL to GND at time T24 to time T25, the voltage applied to the dielectric of the capacitance Fe becomes Vw. As a result, the data having a value of "1" can be written back to the memory cell MC. Therefore, even if the data held in the memory cell MC is destroyed, the data having a value of "1" can be held again in the memory cell MC.
　時刻Ｔ２５乃至時刻Ｔ２６において、信号ＥＮの電位を低電位とすることにより、配線ＢＬの電位が低電位であるＧＮＤとなる。これにより、容量Ｆｅの誘電体に印加される電位は０Ｖとなるが、分極反転は発生せず、メモリセルＭＣには値が“１”のデータが引き続き保持される。 By setting the potential of the signal EN to a low potential at time T25 to time T26, the potential of the wiring BL becomes GND, which is a low potential. As a result, the potential applied to the dielectric of the capacitance Fe becomes 0 V, but the polarization inversion does not occur, and the data having a value of “1” is continuously held in the memory cell MC.
　時刻Ｔ３１乃至時刻Ｔ３６以降における配線ＷＬの電位、配線ＰＬの電位、及び信号ＥＮの電位は、時刻Ｔ２１乃至時刻Ｔ３１等における配線ＷＬの電位、配線ＰＬの電位、及び信号ＥＮの電位と同様とすることができる。 The potential of the wiring WL, the potential of the wiring PL, and the potential of the signal EN after the time T31 to the time T36 are the same as the potential of the wiring WL, the potential of the wiring PL, and the potential of the signal EN at the time T21 to the time T31 and the like. be able to.
　時刻Ｔ３２の開始時点では、メモリセルＭＣに値が“１”のデータが保持されている。よって、時刻Ｔ３２乃至時刻Ｔ３３において、時刻Ｔ２２乃至時刻Ｔ２３と同様に、配線ＢＬの電位がＶｒｅｆより高くなる。 At the start of time T32, data having a value of "1" is held in the memory cell MC. Therefore, at the time T32 to the time T33, the potential of the wiring BL becomes higher than the Vref as in the time T22 to the time T23.
　時刻Ｔ３３乃至時刻Ｔ３４において、配線ＢＬの電位が、高電位であるＶｗとなり、メモリセルＭＣから読み出された、値が“１”のデータが増幅される。 At time T33 to time T34, the potential of the wiring BL becomes Vw, which is a high potential, and the data with a value of "1" read from the memory cell MC is amplified.
　ここで、上記増幅を行った後、配線ＢＬの電位をＧＮＤとする。トランジスタＴｒはオン状態であるため、容量Ｆｅの一方の電極の電位はＧＮＤとなる。また、配線ＰＬの電位は、Ｖｗである。以上より、容量Ｆｅの誘電体に印加される電圧が、−Ｖｗとなる。これにより、図１１Ｂに示すように、容量Ｆｅの誘電体の分極量が負となる。よって、メモリセルＭＣには、値が“０”のデータが書き込まれる。 Here, after performing the above amplification, the potential of the wiring BL is set to GND. Since the transistor Tr is in the ON state, the potential of one electrode of the capacitance Fe is GND. The potential of the wiring PL is Vw. From the above, the voltage applied to the dielectric of the capacitance Fe becomes −Vw. As a result, as shown in FIG. 11B, the amount of polarization of the dielectric of the capacitive Fe becomes negative. Therefore, data having a value of "0" is written in the memory cell MC.
　以上がメモリセルＭＣの駆動方法の一例である。 The above is an example of how to drive the memory cell MC.
　本実施の形態は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。 This embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.
（実施の形態３）
　本実施の形態では、本発明の一態様の半導体装置に用いることができる、強誘電体メモリについて説明する。 (Embodiment 3)
In this embodiment, a ferroelectric memory that can be used in the semiconductor device of one aspect of the present invention will be described.
　図１３Ａ１、図１３Ｂ１、及び図１３Ｃ１に、強誘電体メモリの回路図を示す。なお、図１３Ａ１、図１３Ｂ１、及び図１３Ｃ１に示す回路図において、白丸は端子を表す。 13A1, 13B1 and 13C1 show circuit diagrams of the ferroelectric memory. In the circuit diagram shown in FIGS. 13A1, 13B1, and 13C1, white circles represent terminals.
　図１３Ａ１に、ＦｅＲＡＭの回路図を示す。図１３Ａ１に示す回路図は、１つのトランジスタ（電界効果トランジスタ、ＦＥＴともいう）と、１つの容量素子と、を有し、当該容量素子は、強誘電性を示しうる材料を含む。強誘電性を示しうる材料については、実施の形態２及び実施の形態４を参照することができる。 FIG. 13A1 shows a circuit diagram of FeRAM. The circuit diagram shown in FIG. 13A1 has one transistor (also referred to as a field effect transistor or FET) and one capacitive element, and the capacitive element includes a material capable of exhibiting ferroelectricity. For the material capable of exhibiting ferroelectricity, the second embodiment and the fourth embodiment can be referred to.
　図１３Ｂ１に、ＦｅＦＥＴの回路図を示す。図１３Ｂ１に示す回路図は、１つのトランジスタを有し、当該トランジスタのゲート絶縁膜に強誘電性を示しうる材料を含む。 FIG. 13B1 shows a circuit diagram of FeFET. The circuit diagram shown in FIG. 13B1 has one transistor and includes a material capable of exhibiting ferroelectricity in the gate insulating film of the transistor.
　図１３Ｃ１に、ＦＴＪメモリの回路図を示す。図１３Ｃ１に示す回路図は、１つの容量素子と、１つのダイオードと、を有し、当該容量素子は強誘電性を示しうる材料を含む。 FIG. 13C1 shows a circuit diagram of the FTJ memory. The circuit diagram shown in FIG. 13C1 has one capacitive element and one diode, and the capacitive element contains a material capable of exhibiting ferroelectricity.
　なお、図１３Ｃ１において、１つの容量素子と、１つのダイオードと、を分けて記載しているが、これに限定されない。例えば、１つの素子にて、１つの容量素子と、１つのダイオードと、の双方の機能を有する場合には、それぞれの機能を分離する必要はない。例えば、図１３Ｃ１に示す回路図に相当する構成としては、一対の電極間に絶縁体を有し、当該絶縁体と、電極との間で、トンネル接合を利用する素子構成などを用いることができる。また、図１３Ｃ１に示す回路図は、トンネル接合を利用した１つのキャパシタの素子構成として捉えることができる。 Note that, in FIG. 13C1, one capacitive element and one diode are described separately, but the present invention is not limited to this. For example, when one element has both the functions of one capacitive element and one diode, it is not necessary to separate the respective functions. For example, as a configuration corresponding to the circuit diagram shown in FIG. 13C1, an element configuration in which an insulator is provided between a pair of electrodes and a tunnel junction is used between the insulator and the electrodes can be used. .. Further, the circuit diagram shown in FIG. 13C1 can be regarded as an element configuration of one capacitor using a tunnel junction.
　図１３Ａ２は、図１３Ａ１に示すＦｅＲＡＭが有する容量素子に対応する断面図である。 FIG. 13A2 is a cross-sectional view corresponding to the capacitive element of the FeRAM shown in FIG. 13A1.
　図１３Ａ２は、導電体１１０と、導電体１１０上の絶縁体１３０と、絶縁体１３０上の導電体１２０と、を有する。導電体１１０は、下部電極として機能する。導電体１２０は、上部電極として機能する。なお、絶縁体１３０は、強誘電性を示しうる材料を用いることが好ましい。なお、絶縁体１３０を、誘電体または強誘電体と、読み替えてもよい。なお、図１３Ａ２において、図示していないが、図１３Ａ１に示すように、導電体１２０は、トランジスタのソースまたはドレインと接続する構成とすればよい。 FIG. 13A2 has a conductor 110, an insulator 130 on the conductor 110, and a conductor 120 on the insulator 130. The conductor 110 functions as a lower electrode. The conductor 120 functions as an upper electrode. The insulator 130 preferably uses a material capable of exhibiting ferroelectricity. The insulator 130 may be read as a dielectric or a ferroelectric substance. Although not shown in FIG. 13A2, as shown in FIG. 13A1, the conductor 120 may be configured to be connected to the source or drain of the transistor.
　図１３Ｂ２は、図１３Ｂ１に示すＦｅＦＥＴに対応する断面図である。 FIG. 13B2 is a cross-sectional view corresponding to the FeFET shown in FIG. 13B1.
　図１３Ｂ２は、酸化物２３０と、酸化物２３０上の絶縁体１３０と、絶縁体１３０上の導電体１２０と、を有する。酸化物２３０は、チャネル形成領域を含む。なお、酸化物２３０を、シリコン等の半導体に置き換えてもよい。つまり、ＦｅＦＥＴは、チャネル形成領域に、酸化物半導体を有していてもよく、シリコンを有していてもよい。なお、絶縁体１３０は、強誘電性を示しうる材料を用いることが好ましい。また、図１３Ｂ２に示す積層構造は、酸化物２３０と、絶縁体１３０、すなわち強誘電性を示しうる材料とが、接する構成と別言することができる。 FIG. 13B2 has an oxide 230, an insulator 130 on the oxide 230, and a conductor 120 on the insulator 130. Oxide 230 contains a channel forming region. The oxide 230 may be replaced with a semiconductor such as silicon. That is, the FeFET may have an oxide semiconductor or silicon in the channel forming region. The insulator 130 preferably uses a material capable of exhibiting ferroelectricity. Further, the laminated structure shown in FIG. 13B2 can be said to be different from the configuration in which the oxide 230 and the insulator 130, that is, a material capable of exhibiting ferroelectricity, are in contact with each other.
　図１３Ｃ２、図１３Ｃ３、及び図１３Ｃ４は、それぞれ、図１３Ｃ１に示すＦＴＪメモリに対応する断面図である。 13C2, 13C3, and 13C4 are cross-sectional views corresponding to the FTJ memory shown in FIG. 13C1, respectively.
　図１３Ｃ２は、導電体１１０と、導電体１１０上の絶縁体１１５ａと、絶縁体１１５ａ上の絶縁体１３０と、絶縁体１３０上の導電体１２０と、を有する。なお、図１３Ｃ２は、図１３Ａ２の導電体１１０と、絶縁体１３０との間に絶縁体１１５ａを有する構造ともいえる。 FIG. 13C2 has a conductor 110, an insulator 115a on the conductor 110, an insulator 130 on the insulator 115a, and a conductor 120 on the insulator 130. It can be said that FIG. 13C2 has a structure having an insulator 115a between the conductor 110 of FIG. 13A2 and the insulator 130.
　また、図１３Ｃ３は、導電体１１０と、導電体１１０上の絶縁体１３０と、絶縁体１３０上の絶縁体１１５ｂと、絶縁体１１５ｂ上の導電体１２０と、を有する。 Further, FIG. 13C3 has a conductor 110, an insulator 130 on the conductor 110, an insulator 115b on the insulator 130, and a conductor 120 on the insulator 115b.
　また、図１３Ｃ４は、導電体１１０と、導電体１１０上の絶縁体１１５ａと、絶縁体１１５ａ上の絶縁体１３０と、絶縁体１３０上の絶縁体１１５ｂと、絶縁体１１５ｂ上の導電体１２０と、を有する。 Further, FIG. 13C4 shows the conductor 110, the insulator 115a on the conductor 110, the insulator 130 on the insulator 115a, the insulator 115b on the insulator 130, and the conductor 120 on the insulator 115b. , Have.
　なお、図１３Ｃ１の回路図の構成においては、Ｐ−Ｅ（Ｐｏｌａｒｉｚａｔｉｏｎ　ｄｅｎｓｉｔｙ−Ｅｌｅｃｔｒｉｃ　ｆｉｅｌｄ）特性に一定の分極が得られていることが好ましい。例えば、抗電界（Ｅｃ）以下の電圧範囲における電流−電圧特性が、電圧の走査方向に対して非対称であることが好ましい。本特性を満たすためには、例えば、絶縁体１１５ａと、絶縁体１１５ｂとは、膜種、膜質、または膜厚の少なくともいずれか一を異なる構成とすればよい。 In the configuration of the circuit diagram of FIG. 13C1, it is preferable that a certain degree of polarization is obtained in the PE (Polarization density-Electric field) characteristics. For example, it is preferable that the current-voltage characteristic in the voltage range below the coercive electric field (Ec) is asymmetric with respect to the scanning direction of the voltage. In order to satisfy this characteristic, for example, the insulator 115a and the insulator 115b may have different configurations in at least one of the film type, the film quality, and the film thickness.
　絶縁体１１５ａ及び絶縁体１１５ｂは、それぞれ、常誘電体材料であればよく、例えば、酸化シリコン、窒化シリコン、酸化窒化シリコン、窒化シリコン、酸化アルミニウム、窒化アルミニウム、及び酸化窒化アルミニウムなどを用いることができる。特に、絶縁体１１５ａ、１１５ｂとしては、窒化シリコン膜が好ましい。また、絶縁体１１５ａ、及び絶縁体１１５ｂは、それぞれ、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法、ＡＬＤ法などを用いて成膜することができる。特に絶縁体１１５ａ、及び絶縁体１１５ｂとしては、ＰＥＡＬＤ法を用いて成膜することが好ましい。例えば、ＰＥＡＬＤ法を用いて、窒化シリコン膜を成膜する場合、フッ素、塩素、臭素、ヨウ素などのハロゲンを含むプリカーサを用いると好適である。また、上記プリカーサを導入後、Ｎ２、Ｎ２Ｏ、ＮＨ３、ＮＯ、ＮＯ２、及びＮ２Ｏ２などの窒化剤を導入した雰囲気中でプラズマ処理を行うことで、良質な窒化シリコン膜を成膜することができる。 The insulator 115a and the insulator 115b may be of normal dielectric materials, respectively, and for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, and the like may be used. can. In particular, as the insulators 115a and 115b, silicon nitride films are preferable. Further, the insulator 115a and the insulator 115b can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, respectively. In particular, as the insulator 115a and the insulator 115b, it is preferable to form a film by using the PEALD method. For example, when a silicon nitride film is formed by using the PEALD method, it is preferable to use a precursor containing halogens such as fluorine, chlorine, bromine and iodine. Further, after introducing the above-mentioned precursor, plasma treatment is performed in an atmosphere in which a nitride such as N 2 , N 2 O, NH 3 , NO, NO 2 , and N 2 O 2 is introduced to obtain a high-quality silicon nitride film. Can be formed.
　本発明の一態様により、強誘電性を示しうる材料を利用した強誘電体デバイスを提供することができる。または、本発明の一態様により、強誘電性を示しうる材料を利用した容量素子を提供することができる。または、本発明の一態様により、強誘電性を示しうる材料を利用したトランジスタを提供することができる。または、本発明の一態様により、強誘電性を示しうる材料を利用した容量素子、及びダイオードを提供することができる。 According to one aspect of the present invention, it is possible to provide a ferroelectric device using a material capable of exhibiting ferroelectricity. Alternatively, according to one aspect of the present invention, it is possible to provide a capacitive element using a material capable of exhibiting ferroelectricity. Alternatively, according to one aspect of the present invention, it is possible to provide a transistor using a material capable of exhibiting ferroelectricity. Alternatively, according to one aspect of the present invention, it is possible to provide a capacitive element and a diode using a material capable of exhibiting ferroelectricity.
　本実施の形態は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。 This embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.
（実施の形態４）
　本実施の形態では、本発明の一態様の容量素子について、図１４乃至図１７を用いて説明する。 (Embodiment 4)
In the present embodiment, the capacitive element of one aspect of the present invention will be described with reference to FIGS. 14 to 17.
　本実施の形態の容量素子は、誘電体層として、強誘電性を示しうる材料を有する。本実施の形態の容量素子は、実施の形態２で例示した記憶装置に用いることができる。具体的には、本実施の形態の容量素子は、図１１Ａに示す容量Ｆｅとして用いることができる。 The capacitive element of the present embodiment has a material capable of exhibiting ferroelectricity as a dielectric layer. The capacitive element of the present embodiment can be used for the storage device exemplified in the second embodiment. Specifically, the capacitive element of this embodiment can be used as the capacitive Fe shown in FIG. 11A.
＜容量素子の作製方法例＞
　図１４Ａ乃至図１４Ｃを用いて、本発明の一態様に係る、容量素子の作製方法について説明する。 <Example of manufacturing method of capacitive element>
A method for manufacturing a capacitive element according to one aspect of the present invention will be described with reference to FIGS. 14A to 14C.
　図１４Ａに示すように、基板（図示せず。）の上に導電体１１０を成膜する。導電体１１０の成膜は、スパッタリング法、化学気相成長（ＣＶＤ：Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、分子線エピタキシー（ＭＢＥ：Ｍｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅｐｉｔａｘｙ）法、パルスレーザ堆積（ＰＬＤ：Ｐｕｌｓｅｄ　Ｌａｓｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、原子層堆積（ＡＬＤ：Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法などを用いて行うことができる。ＡＬＤ法を用いて導電体１１０を成膜することで、平坦性の良好な導電膜を比較的容易に成膜することができる場合がある。例えば、熱ＡＬＤ法を用いて窒化チタンを成膜すればよい。また、導電体１１０は、リソグラフィー法などを用いて、適宜パターン形成すればよい。 As shown in FIG. 14A, the conductor 110 is formed on a substrate (not shown). The film formation of the conductor 110 is performed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, and an atomic layer deposition (PLD) method. It can be carried out by using a deposition (ALD: Atomic Layer Deposition) method or the like. By forming the conductor 110 by using the ALD method, it may be possible to relatively easily form a conductive film having good flatness. For example, titanium nitride may be formed by using the thermal ALD method. Further, the conductor 110 may be appropriately patterned by using a lithography method or the like.
　次に、図１４Ｂに示すように、導電体１１０上に絶縁体１３０を成膜する。絶縁体１３０の成膜は、スパッタリング法、ＣＶＤ法、ＡＬＤ法などを用いて行うことができる。例えば、ＡＬＤ法を用いて成膜することで、導電体１１０上に被覆性よく絶縁体１３０を成膜することができる。これにより、容量素子１００の上部電極と下部電極の間でリーク電流が発生するのを抑制することができる。 Next, as shown in FIG. 14B, the insulator 130 is formed on the conductor 110. The film formation of the insulator 130 can be performed by using a sputtering method, a CVD method, an ALD method, or the like. For example, by forming a film using the ALD method, the insulator 130 can be formed on the conductor 110 with good coverage. As a result, it is possible to suppress the generation of a leak current between the upper electrode and the lower electrode of the capacitive element 100.
　絶縁体１３０は、強誘電性を示しうる材料を用いることが好ましい。強誘電性を示しうる材料としては、酸化ハフニウム、酸化ジルコニウム、酸化ハフニウム及び酸化ジルコニウムを有する材料（ＨｆＺｒＯＸ（Ｘは０よりも大きい実数とする））、酸化ハフニウムに元素Ｊ１（ここでの元素Ｊ１は、ジルコニウム（Ｚｒ）、シリコン（Ｓｉ）、アルミニウム（Ａｌ）、ガドリニウム（Ｇｄ）、イットリウム（Ｙ）、ランタン（Ｌａ）、ストロンチウム（Ｓｒ）などから選ばれた一つまたは複数）を添加した材料、及び、酸化ジルコニウムに元素Ｊ２（ここでの元素Ｊ２は、ハフニウム（Ｈｆ）、シリコン（Ｓｉ）、アルミニウム（Ａｌ）、ガドリニウム（Ｇｄ）、イットリウム（Ｙ）、ランタン（Ｌａ）、ストロンチウム（Ｓｒ）などから選ばれた一つまたは複数）を添加した材料、などが挙げられる。また、強誘電性を示す材料として、ＰｂＴｉＯＸ、チタン酸バリウムストロンチウム（ＢＳＴ）、チタン酸ストロンチウム、チタン酸ジルコン酸鉛（ＰＺＴ）、タンタル酸ビスマス酸ストロンチウム（ＳＢＴ）、ビスマスフェライト（ＢＦＯ）、チタン酸バリウム、などのペロブスカイト構造を有する圧電性セラミックを用いてもよい。また、強誘電性を示しうる材料としては、例えば、上記に列挙した材料から選ばれた複数の材料を含む混合物または化合物を用いることができる。または、絶縁体１３０を、上記に列挙した材料から選ばれた複数の材料からなる積層構造とすることができる。ところで、酸化ハフニウム、酸化ジルコニウム、ＨｆＺｒＯＸ、酸化ハフニウムに元素Ｊ１を添加した材料、酸化ジルコニウムに元素Ｊ２を添加した材料などは、成膜条件だけでなく、各種プロセスなどによっても結晶構造及び特性が変わる可能性があるため、上記材料は、強誘電性を示しうる材料と呼ぶことができる。 As the insulator 130, it is preferable to use a material capable of exhibiting ferroelectricity. Materials that can exhibit strong dielectric property include hafnium oxide, zirconium oxide, hafnium oxide, and a material having zirconium oxide (HfZrOX ( X is a real number larger than 0)), hafnium oxide and element J1 (element here). J1 is added with one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadrinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr) and the like. Element J2 in the material and zirconium oxide (element J2 here is hafnium (Hf), silicon (Si), aluminum (Al), gadrinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr). ), Etc., and the material to which one or more) is added. Further, as a material exhibiting strong dielectric property, PbTiO X , barium titanate strontium (BST), barium titanate, lead zirconate titanate (PZT), strontium bismuthate tantanate (SBT), bismuth ferrite (BFO), titanium A piezoelectric ceramic having a perovskite structure such as barium acid acid may be used. Further, as the material capable of exhibiting ferroelectricity, for example, a mixture or compound containing a plurality of materials selected from the materials listed above can be used. Alternatively, the insulator 130 may have a laminated structure composed of a plurality of materials selected from the materials listed above. By the way, hafnium oxide, zirconium oxide, HfZrOX , a material in which element J1 is added to hafnium oxide, a material in which element J2 is added to zirconium oxide, and the like have crystal structures and characteristics depending not only on film forming conditions but also on various processes. The above materials can be referred to as materials capable of exhibiting strong dielectric properties because they are subject to change.
　特に、酸化ハフニウム、あるいは酸化ハフニウム及び酸化ジルコニウムを有する材料は、数ｎｍといった薄膜に加工しても強誘電性を示すことができるため、好ましい。ここで、絶縁体１３０の膜厚は、１００ｎｍ以下、好ましくは５０ｎｍ以下、より好ましくは２０ｎｍ以下、さらに好ましくは、１０ｎｍ以下（代表的には、２ｎｍ以上９ｎｍ以下）にすることができる。絶縁体１３０を薄膜化することで、容量素子１００を、微細化されたトランジスタに組み合わせて半導体装置を形成することができる。なお、本明細書等において、強誘電性を示しうる材料を層状にしたものを指して、強誘電体層または金属酸化物膜と呼ぶ場合がある。 Particularly, a material having hafnium oxide, or hafnium oxide and zirconium oxide is preferable because it can exhibit ferroelectricity even when processed into a thin film of several nm. Here, the film thickness of the insulator 130 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, still more preferably 10 nm or less (typically 2 nm or more and 9 nm or less). By thinning the insulator 130, the capacitive element 100 can be combined with a miniaturized transistor to form a semiconductor device. In the present specification and the like, a layered material capable of exhibiting ferroelectricity may be referred to as a ferroelectric layer or a metal oxide film.
　ここで、絶縁体１３０に用いることのできる材料の一つである、酸化ハフニウムの結晶構造について、図１５を用いて説明を行う。図１５は、酸化ハフニウム（本実施の形態においてはＨｆＯ２）の結晶構造を説明するモデル図である。酸化ハフニウムは、多様な結晶構造をとることが知られており、例えば、図１５に示す立方晶系（ｃｕｂｉｃ、空間群：Ｆｍ−３ｍ）、正方晶系（ｔｅｔｒａｇｏｎａｌ、空間群：Ｐ４２／ｎｍｃ）、直方晶系（ｏｒｔｈｏｒｈｏｍｂｉｃ、空間群：Ｐｂｃ２２）、及び単斜晶系（ｍｏｎｏｃｌｉｎｉｃ、空間群：Ｐ２１／ｃ）などの結晶構造を取りうる。また、図１５に示すように、上述のそれぞれの結晶構造は、相変化しうる。例えば、酸化ハフニウムに、ジルコニウムのドーピングを行った複合材料とすることで、単斜晶系の酸化ハフニウムの結晶構造を直方晶系の結晶構造とすることができる。 Here, the crystal structure of hafnium oxide, which is one of the materials that can be used for the insulator 130, will be described with reference to FIG. FIG. 15 is a model diagram illustrating the crystal structure of hafnium oxide (HfO 2 in this embodiment). Hafnium oxide is known to have various crystal structures, for example, the cubic system (cubic, space group: Fm-3m) and the tetragonal system (tetragonal, space group: P42 2 / nmc) shown in FIG. ), Orthorhombic, space group: Pbc2 2 ), and monoclinic, space group: P2 1 / c. Further, as shown in FIG. 15, each of the above-mentioned crystal structures can undergo a phase change. For example, by using a composite material in which hafnium oxide is doped with zirconium, the crystal structure of monoclinic hafnium oxide can be changed to an orthorhombic crystal structure.
　上述の複合材料として、ＡＬＤ法を用いて酸化ハフニウムと酸化ジルコニウムとを１：１の組成になるように交互に成膜する場合、当該複合材料は、直方晶系の結晶構造を有する。または、当該複合材料は、アモルファス構造を有する。その後、上記複合材料に熱処理などを加えることで、アモルファス構造を、直方晶系の結晶構造とすることができる。なお、当該直方晶系の結晶構造は、単斜晶系の結晶構造に変化する場合がある。上述の複合材料に強誘電性を付与する場合、単斜晶系の結晶構造よりも、直方晶系の結晶構造が好ましい。 When the above-mentioned composite material is formed by alternately forming hafnium oxide and zirconium oxide in a 1: 1 composition using the ALD method, the composite material has an orthorhombic crystal structure. Alternatively, the composite material has an amorphous structure. Then, by applying heat treatment or the like to the composite material, the amorphous structure can be made into an orthorhombic crystal structure. The crystal structure of the orthorhombic system may change to the crystal structure of the monoclinic system. When imparting strong dielectric property to the above-mentioned composite material, an orthorhombic crystal structure is preferable to a monoclinic crystal structure.
　なお、絶縁体１３０の結晶構造は、特に限定されない。絶縁体１３０の結晶構造としては、立方晶系、正方晶系、直方晶系、及び単斜晶系の中から選ばれるいずれか一つまたは複数とすればよい。特に絶縁体１３０としては、直方晶系の結晶構造を有すると、強誘電性が発現するため好ましい。または、絶縁体１３０としては、アモルファス構造としてもよい。あるいは、絶縁体１３０として、アモルファス構造と、結晶構造とを有する複合構造としてもよい。また、絶縁体１３０は、複数の結晶構造が混在した状態であってもよい。このとき、少なくとも絶縁体１３０中に直方晶系の結晶構造が含まれることで、絶縁体１３０は強誘電性を示すことができる。 The crystal structure of the insulator 130 is not particularly limited. The crystal structure of the insulator 130 may be one or more selected from a cubic system, a tetragonal system, an orthorhombic system, and a monoclinic system. In particular, it is preferable that the insulator 130 has an orthorhombic crystal structure because it exhibits ferroelectricity. Alternatively, the insulator 130 may have an amorphous structure. Alternatively, the insulator 130 may be a composite structure having an amorphous structure and a crystal structure. Further, the insulator 130 may be in a state in which a plurality of crystal structures are mixed. At this time, the insulator 130 can exhibit ferroelectricity by including at least the orthorhombic crystal structure in the insulator 130.
　絶縁体１３０として、酸化ハフニウム及び酸化ジルコニウムを有する材料（ＨｆＺｒＯＸ）を用いる場合、熱ＡＬＤ法を用いて成膜することが好ましい。 When a material having hafnium oxide and zirconium oxide ( HfZrOX ) is used as the insulator 130, it is preferable to form a film by using the thermal ALD method.
　また、熱ＡＬＤ法を用いて、絶縁体１３０を成膜する場合、プリカーサとして炭化水素（Ｈｙｄｒｏ　Ｃａｒｂｏｎ、ＨＣともいう）を含まない材料を用いると好適である。絶縁体１３０中に、水素及び炭素のいずれか一方または双方が含まれる場合、絶縁体１３０の結晶化を阻害する場合がある。このため、上記のように、炭化水素を含まないプリカーサを用いることで、絶縁体１３０中の、水素及び炭素のいずれか一方または双方の濃度を低減することが好ましい。例えば、炭化水素を含まないプリカーサとしては、塩素系材料が挙げられる。なお、絶縁体１３０として、酸化ハフニウム及び酸化ジルコニウムを有する材料（ＨｆＺｒＯＸ）を用いる場合、プリカーサとしては、ＨｆＣｌ４、及び／またはＺｒＣｌ４を用いることができる。 Further, when the insulator 130 is formed into a film by using the thermal ALD method, it is preferable to use a material containing no hydrocarbon (hydrocarbon, also referred to as HC) as a precursor. If the insulator 130 contains one or both of hydrogen and carbon, it may inhibit the crystallization of the insulator 130. Therefore, as described above, it is preferable to reduce the concentration of either one or both of hydrogen and carbon in the insulator 130 by using a precursor containing no hydrocarbon. For example, examples of the precursor containing no hydrocarbon include chlorine-based materials. When a material having hafnium oxide and zirconium oxide ( HfZrOX ) is used as the insulator 130, HfCl 4 and / or ZrCl 4 can be used as the precursor.
　また、熱ＡＬＤ法を用いて、絶縁体１３０を成膜する場合、酸化剤としてはＨ２ＯまたはＯ３を用いることができる。なお、熱ＡＬＤ法の酸化剤としては、Ｈ２Ｏを用いるよりも、Ｏ３を用いる方が、膜中の水素濃度を低減できるため好適である。ただし、熱ＡＬＤ法の酸化剤は、これに限定されない。例えば、熱ＡＬＤ法の酸化剤としては、Ｏ２、Ｏ３、Ｎ２Ｏ、ＮＯ２、Ｈ２Ｏ、及びＨ２Ｏ２の中から選ばれるいずれか一つまたは複数を用いることができる。 Further, when the insulator 130 is formed into a film by using the thermal ALD method , H2O or O3 can be used as the oxidizing agent. As the oxidizing agent of the thermal ALD method , it is preferable to use O3 rather than H2O because the hydrogen concentration in the membrane can be reduced. However, the oxidizing agent of the thermal ALD method is not limited to this. For example, as the oxidizing agent of the thermal ALD method, any one or a plurality selected from O 2 , O 3 , N 2 O, NO 2 , H 2 O, and H 2 O 2 can be used.
　次に、図１４Ｃに示すように、絶縁体１３０上に導電体１２０を成膜する。ここで、導電体１２０は、絶縁体１３０を介して、導電体１１０と離隔して配置される。導電体１２０は、絶縁体１３０上に接して設けられる導電体１２０ａと、導電体１２０ａ上に接して設けられる導電体１２０ｂの積層構造にしてもよい。この場合、導電体１２０ａは、被覆性の良好な、膜厚の薄い導電膜を絶縁体１３０上に設けることが好ましい。また、導電体１２０ｂは、導電体１２０ａ上の開口を埋め込むように配置すればよい。 Next, as shown in FIG. 14C, the conductor 120 is formed on the insulator 130. Here, the conductor 120 is arranged apart from the conductor 110 via the insulator 130. The conductor 120 may have a laminated structure of a conductor 120a provided in contact with the insulator 130 and a conductor 120b provided in contact with the conductor 120a. In this case, it is preferable that the conductor 120a is provided with a thin conductive film having a good covering property on the insulator 130. Further, the conductor 120b may be arranged so as to embed an opening on the conductor 120a.
　導電体１２０ａは、ＡＬＤ法またはＣＶＤ法などを用いて成膜することができる。例えば、熱ＡＬＤ法を用いて窒化チタンを成膜すればよい。ここで、導電体１２０ａの成膜方法は、熱ＡＬＤ法のように、基板を加熱しながら成膜する方法が好ましい。例えば、基板温度を、室温以上、好ましくは３００℃以上、より好ましくは３２５℃以上、さらに好ましくは３５０℃以上にして成膜すればよい。また、例えば、基板温度を、５００℃以下、好ましくは４５０℃以下にして成膜すればよい。例えば、基板温度を４００℃程度にして成膜すればよい。 The conductor 120a can be formed into a film by using an ALD method, a CVD method, or the like. For example, titanium nitride may be formed by using the thermal ALD method. Here, the film forming method of the conductor 120a is preferably a method of forming a film while heating the substrate, as in the thermal ALD method. For example, the film may be formed by setting the substrate temperature to room temperature or higher, preferably 300 ° C. or higher, more preferably 325 ° C. or higher, and further preferably 350 ° C. or higher. Further, for example, the film may be formed by setting the substrate temperature to 500 ° C. or lower, preferably 450 ° C. or lower. For example, the film may be formed by setting the substrate temperature to about 400 ° C.
　上記のような温度範囲で導電体１２０ａを成膜することで、導電体１２０ａの形成後に高温のベーク処理（例えば、熱処理温度４００℃以上または５００℃以上のベーク処理）を行わなくても、絶縁体１３０に強誘電性を付与させること、または、絶縁体１３０の強誘電性を高めることができる。これにより、容易に強誘電キャパシタを作製し、半導体装置の生産性を向上させることができる。また、上記のように下地に与えるダメージが比較的少ないＡＬＤ法を用いて導電体１２０ａを成膜することで、絶縁体１３０の結晶構造が過剰に破壊されるのを抑制でき、絶縁体１３０の強誘電性を高めることができる。 By forming the conductor 120a in the temperature range as described above, insulation is performed without performing a high-temperature baking treatment (for example, a baking treatment having a heat treatment temperature of 400 ° C. or higher or 500 ° C. or higher) after the conductor 120a is formed. The ferroelectricity can be imparted to the body 130, or the ferroelectricity of the insulator 130 can be enhanced. This makes it possible to easily manufacture a ferroelectric capacitor and improve the productivity of the semiconductor device. Further, by forming the conductor 120a by using the ALD method, which causes relatively little damage to the substrate as described above, it is possible to prevent the crystal structure of the insulator 130 from being excessively destroyed, and the insulator 130 can be prevented from being excessively destroyed. Ferroelectricity can be increased.
　例えば、導電体１２０ａをスパッタリング法などにより形成する場合、下地膜、ここでは絶縁体１３０、にダメージが入り込む可能性がある。例えば、絶縁体１３０として酸化ハフニウム及び酸化ジルコニウムを有する材料（ＨｆＺｒＯＸ）を用い、導電体１２０ａをスパッタリング法により形成する場合、下地膜であるＨｆＺｒＯＸにダメージが入り、ＨｆＺｒＯＸの結晶構造（代表的には直方晶系などの結晶構造）が崩れる可能性がある。なお、この場合、その後に熱処理を行うことにより、ＨｆＺｒＯＸの結晶構造の損傷を回復させるといった方法もあるが、スパッタリング法により形成されたＨｆＺｒＯＸ中のダメージ、例えばＨｆＺｒＯＸ中のダングリングボンド（例えば、Ｏ＊）と、ＨｆＺｒＯＸ中に含まれる水素とが結合し、ＨｆＺｒＯＸの結晶構造中の損傷を回復できない場合がある。 For example, when the conductor 120a is formed by a sputtering method or the like, damage may enter the base film, here, the insulator 130. For example, when a material having hafnium oxide and zirconium oxide (HfZrO X ) is used as the insulator 130 and the conductor 120a is formed by a sputtering method, the underlying film HfZrOX is damaged and the crystal structure of HfZrOX (representative). There is a possibility that the crystal structure such as the orthorhombic system) will collapse. In this case, there is also a method of recovering the damage of the crystal structure of HfZrOX by performing a heat treatment after that, but the damage in HfZrOX formed by the sputtering method, for example, the dangling bond in HfZrOX ( For example, O * ) and hydrogen contained in HfZrOX may be bonded to each other, and damage in the crystal structure of HfZrOX may not be recovered.
　そのため、絶縁体１３０（ここではＨｆＺｒＯＸ）は、水素を含まない材料、または水素の含有量が極めて少ない材料を用いることが好適である。例えば、絶縁体１３０に含まれる水素の濃度は、５×１０２０ａｔｏｍｓ／ｃｍ３以下が好ましく、１×１０２０ａｔｏｍｓ／ｃｍ３以下がより好ましい。 Therefore, as the insulator 130 (here, HfZrOX ), it is preferable to use a material that does not contain hydrogen or a material that has an extremely low hydrogen content. For example, the concentration of hydrogen contained in the insulator 130 is preferably 5 × 10 20 atoms / cm 3 or less, and more preferably 1 × 10 20 atoms / cm 3 or less.
　また、上記のように、絶縁体１３０中の水素濃度を低減するためには、プリカーサとして炭化水素を含まない材料を用いることが好適である。これにより、絶縁体１３０は、主成分として炭化水素を含まない、または炭化水素の含有量が極めて少ない膜になる場合がある。例えば、絶縁体１３０に含まれる炭化水素の濃度は、好ましくは５×１０２０ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０２０ａｔｏｍｓ／ｃｍ３以下になる。 Further, as described above, in order to reduce the hydrogen concentration in the insulator 130, it is preferable to use a hydrocarbon-free material as the precursor. As a result, the insulator 130 may become a film that does not contain hydrocarbons as a main component or has an extremely low content of hydrocarbons. For example, the concentration of the hydrocarbon contained in the insulator 130 is preferably 5 × 10 20 atoms / cm 3 or less, and more preferably 1 × 10 20 atoms / cm 3 or less.
　また、絶縁体１３０の成膜に、プリカーサとして炭化水素を含まない材料を用いる場合、絶縁体１３０は、主成分として炭素を含まない、または炭素の含有量が極めて少ない膜になる場合がある。例えば、絶縁体１３０に含まれる炭素の濃度は、好ましくは５×１０２０ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０２０ａｔｏｍｓ／ｃｍ３以下になる。 Further, when a hydrocarbon-free material is used as the precursor for forming the insulator 130, the insulator 130 may be a film containing no carbon as a main component or having an extremely low carbon content. For example, the concentration of carbon contained in the insulator 130 is preferably 5 × 10 20 atoms / cm 3 or less, more preferably 1 × 10 20 atoms / cm 3 or less.
　なお、絶縁体１３０としては、水素、炭化水素、及び炭素の少なくとも一つの含有量が極めて少ない材料を用いることが好適であるが、中でも炭化水素及び炭素の含有量を極めて低減することが重要である。炭化水素及び炭素は、水素よりも重い分子または重い原子であるため、後の工程で取り除くことが困難である。そのため、絶縁体１３０の成膜時に、炭化水素及び炭素を徹底的に排除することが好適である。 As the insulator 130, it is preferable to use a material having an extremely low content of at least one of hydrogen, hydrocarbon, and carbon, but it is particularly important to extremely reduce the content of hydrogen and carbon. be. Hydrocarbons and carbon are heavier molecules or atoms than hydrogen and are difficult to remove in later steps. Therefore, it is preferable to thoroughly eliminate hydrocarbons and carbon when forming the insulator 130.
　以上のように、絶縁体１３０に、水素、炭化水素、及び炭素の少なくとも一つを含まない、または水素、炭化水素、及び炭素の少なくとも一つの含有量が極めて少ない材料を用いることで、絶縁体１３０の結晶性を向上させることが可能となり、高い強誘電性を有する構造とすることができる。 As described above, the insulator 130 is made of a material that does not contain at least one of hydrogen, hydrocarbon, and carbon, or has an extremely low content of at least one of hydrogen, hydrocarbon, and carbon. It is possible to improve the crystallinity of 130, and it is possible to form a structure having high strong dielectric property.
　なお、上述のように絶縁体１３０の膜中の不純物、ここでは水素、炭化水素、及び炭素の少なくとも一つを徹底的に排除することで、高純度真性な強誘電性を有する膜、ここでは高純度真性な容量素子を形成することができる。なお、高純度真性な強誘電性を有する容量素子と、後述する実施の形態に示す高純度真性な酸化物半導体との、製造プロセスの整合性は非常に高い。よって、生産性が高い半導体装置の作製方法を提供することができる。 As described above, a film having high purity and intrinsic ferroelectricity by thoroughly removing at least one of impurities, here hydrogen, hydrocarbon, and carbon in the film of the insulator 130, here. It is possible to form a high-purity intrinsic capacitive element. It should be noted that the consistency of the manufacturing process between the capacitive element having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later is very high. Therefore, it is possible to provide a method for manufacturing a semiconductor device having high productivity.
　以上のように、本発明の一態様においては、例えば、絶縁体１３０として、熱ＡＬＤ法を用いて、炭化水素を用いないプリカーサ（代表的には塩素系プリカーサ）と、酸化剤（代表的にはＯ３）と、を用いて強誘電性材料を形成する。その後、熱ＡＬＤ法による成膜（代表的には４００℃以上の成膜）により、導電体１２０ａを形成することによって、成膜後のアニールを行わずに、別言すると導電体１２０ａ成膜時の温度を利用することで、絶縁体１３０の結晶性または強誘電性を向上させることができる。なお、導電体１２０ａの成膜後のアニールを行わず、導電体１２０ａの成膜時の温度を利用して絶縁体１３０の結晶性または強誘電性を向上させることを、セルフアニールと呼称する場合がある。 As described above, in one aspect of the present invention, for example, as the insulator 130, a hydrocarbon-free precursor (typically a chlorine-based precursor) and an oxidizing agent (typically, using the thermal ALD method) and an oxidizing agent (typically) are used. Uses O 3 ) and to form a ferroelectric material. After that, by forming the conductor 120a by film formation by the thermal ALD method (typically, film formation at 400 ° C. or higher), the conductor 120a is not annealed after the film formation, in other words, at the time of film formation of the conductor 120a. By utilizing the temperature of the above, the crystallinity or the strong dielectric property of the insulator 130 can be improved. In the case of self-annealing, improving the crystallinity or ferroelectricity of the insulator 130 by utilizing the temperature at the time of film formation of the conductor 120a without performing annealing after the film formation of the conductor 120a is performed. There is.
　なお、導電体１２０ｂは、スパッタリング法、ＡＬＤ法、またはＣＶＤ法などを用いて成膜することができる。例えば、メタルＣＶＤ法を用いてタングステンを成膜すればよい。 The conductor 120b can be formed into a film by using a sputtering method, an ALD method, a CVD method, or the like. For example, tungsten may be formed by using a metal CVD method.
　以上のようにして、図１４Ｃに示す、導電体１１０と導電体１２０の間に絶縁体１３０を有する、容量素子１００を作製することができる。上記のように、本実施の形態に係る容量素子１００は、導電体１２０ａの形成後に高温のベーク処理を行わなくても、絶縁体１３０の強誘電性を高めることができる。これにより、強誘電キャパシタを製造する工程を削減することができるため、強誘電キャパシタ及びそれを含む半導体装置の生産性を向上させることができる。 As described above, the capacitive element 100 having the insulator 130 between the conductor 110 and the conductor 120 shown in FIG. 14C can be manufactured. As described above, the capacitive element 100 according to the present embodiment can enhance the ferroelectricity of the insulator 130 without performing a high-temperature baking treatment after the conductor 120a is formed. As a result, the process of manufacturing the ferroelectric capacitor can be reduced, so that the productivity of the ferroelectric capacitor and the semiconductor device including the ferroelectric capacitor can be improved.
＜ＡＬＤ法による成膜＞
　以下では、図１６及び図１７を用いて、ＡＬＤ法による絶縁体１３０の成膜方法、及び当該成膜に用いる製造装置について、説明する。 <Deposition by ALD method>
Hereinafter, the film forming method of the insulator 130 by the ALD method and the manufacturing apparatus used for the film forming will be described with reference to FIGS. 16 and 17.
　ＡＬＤ法は、原子の性質である自己制御性を利用し、一層ずつ原子を堆積することができるため、極薄の成膜が可能、アスペクト比の高い構造への成膜が可能、ピンホールなどの欠陥の少ない成膜が可能、被覆性に優れた成膜が可能、低温での成膜が可能、などの効果がある。 The ALD method utilizes the self-regulating properties of atoms and allows atoms to be deposited layer by layer, so ultra-thin film formation is possible, film formation into structures with a high aspect ratio is possible, pinholes, etc. It has the effects of being able to form a film with few defects, being able to form a film with excellent coverage, and being able to form a film at a low temperature.
　ＡＬＤ法は、反応のための第１の原料ガス（プリカーサとも呼ぶ）と第２の原料ガス（酸化性ガスとも呼ぶ）を交互にチャンバーに導入し、これらの原料ガスの導入を繰り返すことで成膜を行う。また、プリカーサまたは酸化性ガス導入の際、Ｎ２、Ａｒなどをキャリア・パージガスとして、プリカーサまたは酸化性ガスと一緒に反応室に導入してもよい。キャリア・パージガスを用いることで、プリカーサまたは酸化性ガスが、配管内部及びバルブ内部に吸着することを抑制し、プリカーサまたは酸化性ガスを反応室に導入することが可能になる（キャリアガスとも呼ぶ）。さらに反応室に残留するプリカーサまたは酸化性ガスを、速やかに排気することが可能となる（パージガスとも呼ぶ）。このように導入（キャリア）と排気（パージ）の２つの役割を有するため、キャリア・パージガスと呼ぶことがある。また、キャリア・パージガスを用いることで、形成される膜の均一性が向上し、好ましい。 The ALD method is carried out by alternately introducing a first raw material gas (also called a precursor) and a second raw material gas (also called an oxidizing gas) for the reaction into the chamber and repeating the introduction of these raw material gases. Make a membrane. Further, when introducing the precursor or the oxidizing gas, N2 , Ar or the like may be introduced into the reaction chamber together with the precursor or the oxidizing gas as a carrier purge gas. By using the carrier purge gas, it is possible to suppress the adsorption of the precursor or oxidizing gas to the inside of the pipe and the inside of the valve, and to introduce the precursor or oxidizing gas into the reaction chamber (also called carrier gas). .. Further, the precursor or oxidizing gas remaining in the reaction chamber can be quickly exhausted (also referred to as purge gas). Since it has two roles of introduction (carrier) and exhaust (purge) in this way, it is sometimes called a carrier purge gas. Further, it is preferable to use the carrier purge gas because the uniformity of the formed film is improved.
　図１６にＡＬＤ法を用いた、強誘電性を示す材料の膜（以下、強誘電体層と呼ぶ。）の成膜シーケンスを示す。以下では、絶縁体１３０として、酸化ハフニウム及び酸化ジルコニウムを有する強誘電体層の成膜を例として示す。 FIG. 16 shows a film formation sequence of a film of a material exhibiting ferroelectricity (hereinafter referred to as a ferroelectric layer) using the ALD method. In the following, as the insulator 130, a film formation of a ferroelectric layer having hafnium oxide and zirconium oxide will be shown as an example.
　プリカーサ４０１としては、ハフニウムを含み、さらに塩素、フッ素、臭素、ヨウ素、及び水素の中から選ばれるいずれか一つまたは複数を含むプリカーサを用いることができる。また、プリカーサ４０２としては、ジルコニウムを含み、さらに塩素、フッ素、臭素、ヨウ素、及び水素の中から選ばれるいずれか一つまたは複数を含むプリカーサを用いることができる。本項目では、ハフニウムを含むプリカーサ４０１として、ＨｆＣｌ４を用い、ジルコニウムを含むプリカーサ４０２として、ＺｒＣｌ４を用いる。 As the precursor 401, a precursor containing hafnium and further containing one or more selected from chlorine, fluorine, bromine, iodine, and hydrogen can be used. Further, as the precursor 402, a precursor containing zirconium and further containing one or more selected from chlorine, fluorine, bromine, iodine, and hydrogen can be used. In this item, HfCl 4 is used as the precursor 401 containing hafnium, and ZrCl 4 is used as the precursor 402 containing zirconium.
　なお、プリカーサ４０１及びプリカーサ４０２は、液体原料または固体原料を加熱してガス化することによって、形成される。プリカーサ４０１は、ＨｆＣｌ４の固体原料から形成され、プリカーサ４０２は、ＺｒＣｌ４の固体原料から形成される。プリカーサ４０１及びプリカーサ４０２は、不純物が低減されていることが好ましく、これらの固体原料も不純物が低減されていることが好ましい。例えば、当該不純物としては、Ｂａ、Ｃｄ、Ｃｏ、Ｃｒ、Ｃｕ、Ｆｅ、Ｇａ、Ｌｉ、Ｍｇ、Ｍｎ、Ｎａ、Ｎｉ、Ｓｒ、Ｖ、Ｚｎなどが挙げられる。ＨｆＣｌ４の固体原料、及び、ＺｒＣｌ４の固体原料において、上記の不純物は、１０００ｗｐｐｂ未満であることが好ましい。ここで、ｗｐｐｂとは、質量で換算した不純物の濃度を十億分率で表した単位である。 The precursor 401 and the precursor 402 are formed by heating and gasifying a liquid raw material or a solid raw material. The precursor 401 is formed from a solid raw material of HfCl 4 , and the precursor 402 is formed from a solid raw material of ZrCl 4 . Impurities are preferably reduced in the precursor 401 and the precursor 402, and it is preferable that these solid raw materials also have reduced impurities. For example, examples of the impurities include Ba, Cd, Co, Cr, Cu, Fe, Ga, Li, Mg, Mn, Na, Ni, Sr, V, Zn and the like. In the solid raw material of HfCl 4 and the solid raw material of ZrCl 4 , the above impurities are preferably less than 1000 wppb. Here, wppb is a unit in which the concentration of impurities converted by mass is expressed in parts per billion.
　また、酸化性ガス４０３として、Ｏ２、Ｏ３、Ｎ２Ｏ、ＮＯ２、Ｈ２Ｏ、及びＨ２Ｏ２中から選ばれるいずれか一つまたは複数を用いることができる。本項目では、酸化性ガス４０３としてＨ２Ｏを含むガスを用いる。また、キャリア・パージガス４０４として、Ｎ２、Ｈｅ、Ａｒ、Ｋｒ、及びＸｅの中から選ばれるいずれか一つまたは複数を用いることができる。本項目では、キャリア・パージガス４０４としてＮ２を用いる。 Further, as the oxidizing gas 403, any one or a plurality selected from O 2 , O 3 , N 2 O, NO 2 , H 2 O, and H 2 O 2 can be used. In this item, a gas containing H2O is used as the oxidizing gas 403. Further, as the carrier purge gas 404, any one or a plurality selected from N2 , He, Ar, Kr, and Xe can be used. In this item, N 2 is used as the carrier purge gas 404.
　まず、反応室に、キャリア・パージガス４０４を導入する。キャリア・パージガス４０４は、ステップＳ０１乃至ステップＳ０８の間、常に導入される。次に、反応室に酸化性ガス４０３を導入する（ステップＳ０１）。次に、酸化性ガス４０３の導入を止めて、キャリア・パージガス４０４のみとし、反応室内に残留する酸化性ガス４０３のパージを行う（ステップＳ０２）。次に、反応室内にプリカーサ４０１を導入し、反応室内の圧力を一定に保つ（ステップＳ０３）。このようにして、被形成面にプリカーサ４０１を吸着させる。次に、プリカーサ４０１の導入を止めて、キャリア・パージガス４０４のみとし、反応室内に残留するプリカーサ４０１のパージを行う（ステップＳ０４）。次に、反応室に酸化性ガス４０３を導入する。酸化性ガス４０３を導入することで、プリカーサ４０１を酸化させて酸化ハフニウムを形成する（ステップＳ０５）。次に、酸化性ガス４０３の導入を止めて、キャリア・パージガス４０４のみとし、反応室内に残留する酸化性ガス４０３のパージを行う（ステップＳ０６）。 First, the carrier purge gas 404 is introduced into the reaction chamber. The carrier purge gas 404 is always introduced during steps S01 to S08. Next, the oxidizing gas 403 is introduced into the reaction chamber (step S01). Next, the introduction of the oxidizing gas 403 is stopped, only the carrier purge gas 404 is used, and the oxidizing gas 403 remaining in the reaction chamber is purged (step S02). Next, the precursor 401 is introduced into the reaction chamber to keep the pressure in the reaction chamber constant (step S03). In this way, the precursor 401 is adsorbed on the surface to be formed. Next, the introduction of the precursor 401 is stopped, only the carrier purge gas 404 is used, and the precursor 401 remaining in the reaction chamber is purged (step S04). Next, the oxidizing gas 403 is introduced into the reaction chamber. By introducing the oxidizing gas 403, the precursor 401 is oxidized to form hafnium oxide (step S05). Next, the introduction of the oxidizing gas 403 is stopped, only the carrier purge gas 404 is used, and the oxidizing gas 403 remaining in the reaction chamber is purged (step S06).
　次に、反応室内にプリカーサ４０２を導入し、反応室内の圧力を一定に保つ（ステップＳ０７）。このようにして、上記酸化ハフニウムの酸素の層上にプリカーサ４０２を吸着させる。次に、プリカーサ４０２の導入を止めて、キャリア・パージガス４０４のみとし、反応室内に残留するプリカーサ４０２のパージを行う（ステップＳ０８）。次に、ステップＳ０１に戻って、反応室に酸化性ガス４０３を導入する。酸化性ガス４０３を導入することで、プリカーサ４０２を酸化させ、酸化ハフニウム上に酸化ジルコニウムを形成する。 Next, the precursor 402 is introduced into the reaction chamber to keep the pressure in the reaction chamber constant (step S07). In this way, the precursor 402 is adsorbed on the oxygen layer of hafnium oxide. Next, the introduction of the precursor 402 is stopped, only the carrier purge gas 404 is used, and the precursor 402 remaining in the reaction chamber is purged (step S08). Next, returning to step S01, the oxidizing gas 403 is introduced into the reaction chamber. By introducing the oxidizing gas 403, the precursor 402 is oxidized and zirconium oxide is formed on hafnium oxide.
　上述のステップＳ０１乃至ステップＳ０８を１サイクルとして、所望の膜厚に達するまで当該サイクルを繰り返し行う。なお、ステップＳ０１乃至ステップＳ０８は、それぞれ２５０℃以上４５０℃以下の温度範囲で行うことが好ましく、３５０℃以上４００℃以下の温度範囲で行うことがより好ましい。 The above steps S01 to S08 are set as one cycle, and the cycle is repeated until a desired film thickness is reached. It is preferable that steps S01 to S08 are performed in a temperature range of 250 ° C. or higher and 450 ° C. or lower, and more preferably in a temperature range of 350 ° C. or higher and 400 ° C. or lower.
　以上のように、ＡＬＤ法を用いて成膜することで、ハフニウムの層、酸素の層、ジルコニウムの層、酸素の層を繰り返す層状の結晶構造を形成することができる。さらに、上記のように、不純物の低減されたプリカーサを用いて成膜することで、成膜中に不純物が混入して、当該層状の結晶構造の形成を妨げることを抑制できる。このように、絶縁体１３０を、結晶性の高い、層状の結晶構造にすることで、絶縁体１３０に高い強誘電性を有せしめることができる。 As described above, by forming a film using the ALD method, it is possible to form a layered crystal structure in which a hafnium layer, an oxygen layer, a zirconium layer, and an oxygen layer are repeated. Further, as described above, by forming a film using a precursor having reduced impurities, it is possible to prevent impurities from being mixed in during the film formation and hindering the formation of the layered crystal structure. As described above, by forming the insulator 130 into a layered crystal structure having high crystallinity, the insulator 130 can be given high ferroelectricity.
　ただし、絶縁体１３０は、必ずしも成膜直後に強誘電性を示すものではない。上述の通り、絶縁体１３０は成膜直後ではなく、絶縁体１３０の上に導電体１２０を形成した後で、強誘電性を示す場合がある。 However, the insulator 130 does not necessarily exhibit ferroelectricity immediately after film formation. As described above, the insulator 130 may exhibit ferroelectricity not immediately after film formation but after forming the conductor 120 on the insulator 130.
　次に、上記ＡＬＤ法による成膜に用いられる製造装置について図１７Ａを用いて説明する。図１７Ａは、ＡＬＤ法による製造装置９００の模式図である。 Next, the manufacturing apparatus used for the film formation by the ALD method will be described with reference to FIG. 17A. FIG. 17A is a schematic view of the manufacturing apparatus 900 by the ALD method.
　図１７Ａに示すように製造装置９００は、反応室９０１と、ガス導入口９０３と、反応室入り口９０４と、排気口９０５と、ウエハステージ９０７と、軸９０８と、を有する。図１７Ａでは、ウエハステージ９０７上にウエハ９５０が配置されている。 As shown in FIG. 17A, the manufacturing apparatus 900 has a reaction chamber 901, a gas introduction port 903, a reaction chamber inlet 904, an exhaust port 905, a wafer stage 907, and a shaft 908. In FIG. 17A, the wafer 950 is arranged on the wafer stage 907.
　反応室９０１は、反応室９０１の内部、プリカーサ４０１、プリカーサ４０２、酸化性ガス４０３、及びキャリア・パージガス４０４を加熱するためのヒーターシステムが配置されていてもよい。また、ウエハステージ９０７は、ウエハ９５０を加熱するためのヒーターシステムが配置されていてもよい。また、ウエハステージ９０７は、軸９０８を回転軸として水平に回転する回転機構を備えていてもよい。また、図示しないが、ガス導入口の手前には、プリカーサ４０１、プリカーサ４０２、酸化性ガス４０３、及びキャリア・パージガス４０４を適切なタイミングで、適切な流量を適切な時間、ガス導入口９０３へ導入するガス供給システムが設置されている。また、図示しないが、排気口９０５の先には、真空ポンプを有する排気システムが設置されている。 The reaction chamber 901 may be provided with a heater system for heating the inside of the reaction chamber 901, the precursor 401, the precursor 402, the oxidizing gas 403, and the carrier purge gas 404. Further, the wafer stage 907 may be provided with a heater system for heating the wafer 950. Further, the wafer stage 907 may be provided with a rotation mechanism that rotates horizontally with the shaft 908 as a rotation axis. Although not shown, the precursor 401, the precursor 402, the oxidizing gas 403, and the carrier purge gas 404 are introduced into the gas inlet 903 at an appropriate timing and at an appropriate flow rate in front of the gas inlet. Gas supply system is installed. Further, although not shown, an exhaust system having a vacuum pump is installed at the end of the exhaust port 905.
　図１７Ａに示す、製造装置９００は、クロスフロー方式と呼ばれるＡＬＤ装置である。クロスフロー方式におけるプリカーサ４０１、プリカーサ４０２、酸化性ガス４０３、及びキャリア・パージガス４０４の流れを以下に説明する。プリカーサ４０１、プリカーサ４０２、酸化性ガス４０３、及びキャリア・パージガス４０４は、ガス導入口９０３から反応室入り口９０４を介して反応室９０１へ流れ、ウエハ９５０に到達し、排気口９０５を通り排気される。図１７Ａに示す矢印は、ガスの流れる方向を模式的に示している。 The manufacturing device 900 shown in FIG. 17A is an ALD device called a cross-flow method. The flow of the precursor 401, the precursor 402, the oxidizing gas 403, and the carrier purge gas 404 in the cross-flow method will be described below. The precursor 401, the precursor 402, the oxidizing gas 403, and the carrier purge gas 404 flow from the gas inlet 903 to the reaction chamber 901 via the reaction chamber inlet 904, reach the wafer 950, and are exhausted through the exhaust port 905. .. The arrow shown in FIG. 17A schematically indicates the direction in which the gas flows.
　上述のように、図１６に示す、酸化性ガス４０３を反応室９０１に導入するステップＳ０５では、ウエハ９５０上に吸着しているプリカーサ４０１を酸化性ガス４０３によって酸化し、酸化ハフニウムを形成する。クロスフロー方式である製造装置９００の構造上、酸化性ガス４０３が加熱された反応室部材に長く触れてからウエハ９５０に到達する。このため、例えば、酸化性ガス４０３としてＯ３を用いる場合、到達するまでに高温の固体表面と酸化性ガス４０３が反応することで、酸化性ガス４０３が分解し、酸化力が低下する。従って、酸化ハフニウムの成膜速度は、酸化性ガスの、反応室入り口９０４からウエハ９５０への到達距離に依存する。ウエハステージ９０７が軸９０８を中心に水平に回転している場合、ウエハ９５０の周辺部が先に酸化性ガス４０３に到達するため、酸化ハフニウムの膜厚はウエハ９５０の周辺部ほど厚くなり中央部が周辺部より薄くなる。 As described above, in step S05 for introducing the oxidizing gas 403 into the reaction chamber 901 shown in FIG. 16, the precursor 401 adsorbed on the wafer 950 is oxidized by the oxidizing gas 403 to form hafnium oxide. Due to the structure of the manufacturing apparatus 900 of the cross-flow method, the oxidizing gas 403 reaches the wafer 950 after being in contact with the heated reaction chamber member for a long time. Therefore, for example , when O3 is used as the oxidizing gas 403, the oxidizing gas 403 is decomposed by the reaction between the high temperature solid surface and the oxidizing gas 403 by the time it reaches the state, and the oxidizing power is lowered. Therefore, the film formation rate of hafnium oxide depends on the reach of the oxidizing gas from the reaction chamber inlet 904 to the wafer 950. When the wafer stage 907 is rotated horizontally about the shaft 908, the peripheral portion of the wafer 950 reaches the oxidizing gas 403 first, so that the film thickness of hafnium oxide becomes thicker toward the peripheral portion of the wafer 950 and the central portion. Is thinner than the peripheral part.
　そこで、酸化性ガス４０３が分解し、酸化力が低下することを抑制させるため、反応室の加熱温度を適切な温度に設定する必要がある。なお、上記においては、プリカーサ４０１の酸化を例に挙げて説明したが、プリカーサ４０２の酸化についても同様である。 Therefore, in order to suppress the decomposition of the oxidizing gas 403 and the decrease in oxidizing power, it is necessary to set the heating temperature of the reaction chamber to an appropriate temperature. In the above description, the oxidation of the precursor 401 has been described as an example, but the same applies to the oxidation of the precursor 402.
　以上により、基板面内の膜厚均一性に優れた酸化ハフニウムを形成することができる。基板面内の均一性としては、好ましくは、±１．５％以下、より好ましくは、±１．０％以下である。ここで、基板面内とは、基板の大きさの１辺の長さが５インチの正方形の範囲内をいう。また、基板面内の最大膜厚−基板面内の最小膜厚をＲＡＮＧＥと定義し、基板面内の膜厚均一性を±ＰＮＵ（Ｐｅｒｃｅｎｔ　Ｎｏｎ　Ｕｎｉｆｏｒｍｉｔｙ）（％）と定義すると、±ＰＮＵ（％）＝（ＲＡＮＧＥ×１００）／（２×基板面内の膜厚の平均値）で求めることができる。 From the above, hafnium oxide having excellent film thickness uniformity in the substrate surface can be formed. The uniformity in the substrate surface is preferably ± 1.5% or less, more preferably ± 1.0% or less. Here, the inside of the substrate surface means the range of a square in which the length of one side of the size of the substrate is 5 inches. Further, if the maximum film thickness in the substrate surface-the minimum film thickness in the substrate surface is defined as RANGE, and the film thickness uniformity in the substrate surface is defined as ± PNU (Percent Non Uniformity) (%), ± PNU (%). ) = (RANGE × 100) / (2 × average value of film thickness in the substrate surface).
　また、上記のように、酸化性ガス４０３により均一性に優れた酸素の層が形成されることで、より規則性の高い、層状の結晶構造を形成することができる。このように、絶縁体１３０を、規則性の高い、層状の結晶構造にすることで、絶縁体１３０に高い強誘電性を有せしめることができる。 Further, as described above, the oxidizing gas 403 forms a layer of oxygen having excellent uniformity, so that a more regular layered crystal structure can be formed. As described above, by forming the insulator 130 into a highly regular, layered crystal structure, the insulator 130 can be given high ferroelectricity.
　以上の方法を用いることにより、強誘電性を示す材料からなる絶縁体１３０を形成することができる。このような絶縁体１３０を用いて容量素子１００を形成することで、容量素子１００を強誘電キャパシタにすることができる。 By using the above method, an insulator 130 made of a material exhibiting ferroelectricity can be formed. By forming the capacitive element 100 using such an insulator 130, the capacitive element 100 can be made into a ferroelectric capacitor.
　次に、本発明の一態様の金属酸化物、ここではＨｆＺｒＯＸの結晶構造のモデルについて、図１７Ｂを用いて説明を行う。 Next, a model of the crystal structure of the metal oxide of one aspect of the present invention, here HfZrOX , will be described with reference to FIG. 17B.
　図１７Ｂは、ＨｆＺｒＯＸ、ここでは、Ｈｆ０．５Ｚｒ０．５Ｏ２の結晶構造のモデル図である。また、図１７Ｂ中において、ａ軸、ｂ軸、ｃ軸の方向も図示してある。図１７Ｂは、ＨｆＯ２のｏｒｔｈｏｒｈｏｍｂｉｃ構造（Ｐｃａ２１）に関する第一原理計算によるセルを含めた最適化後の構造に対して、Ｚｒを層状に配置した構造である。 FIG. 17B is a model diagram of the crystal structure of HfZrO X , here Hf 0.5 Zr 0.5 O 2 . Further, in FIG. 17B, the directions of the a-axis, the b-axis, and the c-axis are also shown. FIG. 17B is a structure in which Zr is arranged in layers with respect to the optimized structure including the cell by the first-principles calculation regarding the orthorhombic structure (Pca2 1 ) of HfO 2 .
　なお、図１７Ｂでは、ハフニウムと、ジルコニウムと、が酸素を介して互いに結合している状態であることが分かる。これは、図１６に示す成膜シーケンスのように、ハフニウムと、ジルコニウムとを、ＡＬＤ法により交互に成膜することで、形成することができる。 In addition, in FIG. 17B, it can be seen that hafnium and zirconium are in a state of being bonded to each other via oxygen. This can be formed by alternately depositing hafnium and zirconium by the ALD method as in the film formation sequence shown in FIG.
　別言すると、本発明の一態様の金属酸化物は、図１６に示す成膜シーケンス、及び、図１７Ａに示す製造装置を用いることで、図１７Ｂに示すような結晶構造を作製できる。 In other words, the metal oxide of one aspect of the present invention can produce a crystal structure as shown in FIG. 17B by using the film forming sequence shown in FIG. 16 and the manufacturing apparatus shown in FIG. 17A.
　本発明の一態様により、強誘電性を示しうる材料を含む容量素子を提供することができる。または、本発明の一態様により、上記容量素子を良好な生産性で提供することができる。または、本発明の一態様により、微細化または高集積化が可能な、容量素子を提供することができる。 According to one aspect of the present invention, it is possible to provide a capacitive element containing a material capable of exhibiting ferroelectricity. Alternatively, according to one aspect of the present invention, the capacitive element can be provided with good productivity. Alternatively, according to one aspect of the present invention, it is possible to provide a capacitive element capable of miniaturization or high integration.
　本実施の形態は、他の実施の形態と適宜組み合わせることができる。 This embodiment can be appropriately combined with other embodiments.
（実施の形態５）
　本実施の形態では、実施の形態１で説明したニューラルネットワークに用いることが可能な半導体装置の構成例について説明する。 (Embodiment 5)
In this embodiment, a configuration example of a semiconductor device that can be used for the neural network described in the first embodiment will be described.
　図１８Ａに示すように、ニューラルネットワークＮＮは入力層ＩＬ、出力層ＯＬ、中間層（隠れ層）ＨＬによって構成することができる。入力層ＩＬ、出力層ＯＬ、中間層ＨＬはそれぞれ、１または複数のニューロン（ユニット）を有する。なお、中間層ＨＬは１層であってもよいし２層以上であってもよい。２層以上の中間層ＨＬを有するニューラルネットワークはＤＮＮ（ディープニューラルネットワーク）と呼ぶこともでき、ディープニューラルネットワークを用いた学習は深層学習と呼ぶこともできる。 As shown in FIG. 18A, the neural network NN can be composed of an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. The input layer IL, the output layer OL, and the intermediate layer HL each have one or more neurons (units). The intermediate layer HL may be one layer or two or more layers. A neural network having two or more layers of intermediate layers HL can also be called a DNN (deep neural network), and learning using a deep neural network can also be called deep learning.
　入力層ＩＬの各ニューロンには入力データが入力され、中間層ＨＬの各ニューロンには前層または後層のニューロンの出力信号が入力され、出力層ＯＬの各ニューロンには前層のニューロンの出力信号が入力される。なお、各ニューロンは、前後の層の全てのニューロンと結合されていてもよいし（全結合）、一部のニューロンと結合されていてもよい。 Input data is input to each neuron in the input layer IL, the output signal of the anterior layer or posterior layer neuron is input to each neuron in the intermediate layer HL, and the output of the anterior layer neuron is input to each neuron in the output layer OL. A signal is input. In addition, each neuron may be connected to all neurons in the anterior and posterior layers (fully connected), or may be connected to some neurons.
　図１８Ｂに、ニューロンによる演算の例を示す。ここでは、ニューロンＮと、ニューロンＮに信号を出力する前層の２つのニューロンを示している。ニューロンＮには、前層のニューロンの出力ｘ１と、前層のニューロンの出力ｘ２が入力される。そして、ニューロンＮにおいて、出力ｘ１と重みｗ１の乗算結果（ｘ１ｗ１）と出力ｘ２と重みｗ２の乗算結果（ｘ２ｗ２）の総和ｘ１ｗ１＋ｘ２ｗ２が計算された後、必要に応じてバイアスｂが加算され、値ａ＝ｘ１ｗ１＋ｘ２ｗ２＋ｂが得られる。そして、値ａは活性化関数ｈによって変換され、ニューロンＮから出力信号ｙ＝ｈ（ａ）が出力される。 FIG. 18B shows an example of an operation by a neuron. Here, two neurons in the presheaf layer that output a signal to the neuron N are shown. The output x 1 of the presheaf neuron and the output x 2 of the presheaf neuron are input to the neuron N. Then, in the neuron N, the sum of the multiplication result of the output x 1 and the weight w 1 (x 1 w 1 ) and the multiplication result of the output x 2 and the weight w 2 (x 2 w 2 ) is x 1 w 1 + x 2 w 2 . After the calculation, the bias b is added as needed to give the value a = x 1 w 1 + x 2 w 2 + b. Then, the value a is converted by the activation function h, and the output signal y = h (a) is output from the neuron N.
　このように、ニューロンによる演算には、前層のニューロンの出力と重みの積を足し合わせる演算、すなわち積和演算が含まれる（上記のｘ１ｗ１＋ｘ２ｗ２）。この積和演算は、プログラムを用いてソフトウェア上で行ってもよいし、ハードウェアによって行われてもよい。積和演算をハードウェアによって行う場合は、積和演算回路を用いることができる。この積和演算回路としては、デジタル回路を用いてもよいし、アナログ回路を用いてもよい。積和演算回路にアナログ回路を用いる場合、積和演算回路の回路規模の縮小、または、メモリへのアクセス回数の減少による処理速度の向上及び消費電力の低減を図ることができる。 As described above, the operation by the neuron includes the operation of adding the product of the output of the neuron in the previous layer and the weight, that is, the product-sum operation (x 1 w 1 + x 2 w 2 above). This product-sum operation may be performed by software using a program or by hardware. When the product-sum calculation is performed by hardware, a product-sum calculation circuit can be used. As the product-sum calculation circuit, a digital circuit or an analog circuit may be used. When an analog circuit is used for the product-sum calculation circuit, it is possible to improve the processing speed and reduce the power consumption by reducing the circuit scale of the product-sum calculation circuit or reducing the number of times the memory is accessed.
　積和演算回路は、チャネル形成領域にシリコン（単結晶シリコンなど）を含むトランジスタ（「Ｓｉトランジスタ」ともいう）によって構成してもよいし、チャネル形成領域に金属酸化物の一種である酸化物半導体を含むトランジスタ（「ＯＳトランジスタ」ともいう）によって構成してもよい。特に、ＯＳトランジスタはオフ電流が極めて小さいため、積和演算回路のメモリを構成するトランジスタとして好適である。なお、ＳｉトランジスタとＯＳトランジスタの両方を用いて積和演算回路を構成してもよい。以下、積和演算回路の機能を備えた半導体装置の構成例について説明する。 The product-sum calculation circuit may be composed of a transistor (also referred to as a “Si transistor”) containing silicon (single crystal silicon or the like) in the channel forming region, or an oxide semiconductor which is a kind of metal oxide in the channel forming region. It may be configured by a transistor (also referred to as “OS transistor”) containing. In particular, since the OS transistor has an extremely small off current, it is suitable as a transistor constituting the memory of the product-sum calculation circuit. A product-sum calculation circuit may be configured by using both a Si transistor and an OS transistor. Hereinafter, a configuration example of a semiconductor device having a function of a product-sum calculation circuit will be described.
＜半導体装置の構成例＞
　図１９に、ニューラルネットワークの演算を行う機能を有する半導体装置ＭＡＣの構成例を示す。半導体装置ＭＡＣは、ニューロン間の結合強度（重み）に対応する第１のデータと、入力データに対応する第２のデータの積和演算を行う機能を有する。なお、第１のデータ及び第２のデータはそれぞれ、アナログデータまたは多値のデジタルデータ（離散的なデータ）とすることができる。また、半導体装置ＭＡＣは、積和演算によって得られたデータを活性化関数によって変換する機能を有する。 <Semiconductor device configuration example>
FIG. 19 shows a configuration example of a semiconductor device MAC having a function of performing a neural network calculation. The semiconductor device MAC has a function of performing a product-sum operation of the first data corresponding to the bond strength (weight) between neurons and the second data corresponding to the input data. The first data and the second data can be analog data or multi-valued digital data (discrete data), respectively. Further, the semiconductor device MAC has a function of converting the data obtained by the product-sum operation by the activation function.
　半導体装置ＭＡＣは、セルアレイＣＡ、電流源回路ＣＳ、カレントミラー回路ＣＭ、回路ＷＤＤ、回路ＷＬＤ、回路ＣＬＤ、オフセット回路ＯＦＳＴ、及び活性化関数回路ＡＣＴＶを有する。 The semiconductor device MAC has a cell array CA, a current source circuit CS, a current mirror circuit CM, a circuit WDD, a circuit WLD, a circuit CLD, an offset circuit OFST, and an activation function circuit ACTV.
　セルアレイＣＡは、複数のメモリセルＭＣ及び複数のメモリセルＭＣｒｅｆを有する。図１９には、セルアレイＣＡがｍ行ｎ列（ｍ，ｎは１以上の整数）のメモリセルＭＣ（ＭＣ［１，１］乃至ＭＣ［ｍ，ｎ］）と、ｍ個のメモリセルＭＣｒｅｆ（ＭＣｒｅｆ［１］乃至ＭＣｒｅｆ［ｍ］）を有する構成例を示している。メモリセルＭＣは、第１のデータを格納する機能を有する。また、メモリセルＭＣｒｅｆは、積和演算に用いられる参照データを格納する機能を有する。なお、参照データはアナログデータまたは多値のデジタルデータとすることができる。 The cell array CA has a plurality of memory cells MC and a plurality of memory cells MCref. In FIG. 19, memory cells MC (MC [1,1] to MC [m, n]) in which the cell array CA is m rows and n columns (m, n are integers of 1 or more) and m memory cells MCref (m, n). An example of the configuration having MCref [1] to MCref [m]) is shown. The memory cell MC has a function of storing the first data. Further, the memory cell MCref has a function of storing reference data used for the product-sum operation. The reference data can be analog data or multi-valued digital data.
　メモリセルＭＣ［ｉ，ｊ］（ｉは１以上ｍ以下の整数、ｊは１以上ｎ以下の整数）は、配線ＷＬ［ｉ］、配線ＲＷ［ｉ］、配線ＷＤ［ｊ］、及び配線ＢＬ［ｊ］と接続されている。また、メモリセルＭＣｒｅｆ［ｉ］は、配線ＷＬ［ｉ］、配線ＲＷ［ｉ］、配線ＷＤｒｅｆ、配線ＢＬｒｅｆと接続されている。ここで、メモリセルＭＣ［ｉ，ｊ］と配線ＢＬ［ｊ］間を流れる電流をＩＭＣ［ｉ，ｊ］と表記し、メモリセルＭＣｒｅｆ［ｉ］と配線ＢＬｒｅｆ間を流れる電流をＩＭＣｒｅｆ［ｉ］と表記する。 The memory cells MC [i, j] (i is an integer of 1 or more and m or less, j is an integer of 1 or more and n or less) are wiring WL [i], wiring RW [i], wiring WD [j], and wiring BL. It is connected to [j]. Further, the memory cell MCref [i] is connected to the wiring WL [i], the wiring RW [i], the wiring WDref, and the wiring BLref. Here, the current flowing between the memory cell MC [i, j] and the wiring BL [j] is referred to as I MC [i, j] , and the current flowing between the memory cell MCref [i] and the wiring BLref [i] is referred to as I MCref [ i, j]. i] is written.
　メモリセルＭＣ及びメモリセルＭＣｒｅｆの具体的な構成例を、図２０に示す。図２０には代表例としてメモリセルＭＣ［１，１］、ＭＣ［２，１］及びメモリセルＭＣｒｅｆ［１］、ＭＣｒｅｆ［２］を示しているが、他のメモリセルＭＣ及びメモリセルＭＣｒｅｆにも同様の構成を用いることができる。メモリセルＭＣ及びメモリセルＭＣｒｅｆはそれぞれ、トランジスタＴｒ１１、トランジスタＴｒ１２、容量素子Ｃ１１を有する。ここでは、トランジスタＴｒ１１及びトランジスタＴｒ１２がｎチャネル型のトランジスタである場合について説明する。 FIG. 20 shows a specific configuration example of the memory cell MC and the memory cell MCref. FIG. 20 shows memory cells MC [1,1], MC [2,1] and memory cells MCref [1], MCref [2] as typical examples, but other memory cells MC and memory cells MCref are shown. Can also use a similar configuration. The memory cell MC and the memory cell MCref each have a transistor Tr11, a transistor Tr12, and a capacitive element C11. Here, a case where the transistor Tr11 and the transistor Tr12 are n-channel type transistors will be described.
　メモリセルＭＣにおいて、トランジスタＴｒ１１のゲートは配線ＷＬと接続され、ソースまたはドレインの一方はトランジスタＴｒ１２のゲート、及び容量素子Ｃ１１の第１の電極と接続され、ソースまたはドレインの他方は配線ＷＤと接続されている。トランジスタＴｒ１２のソースまたはドレインの一方は配線ＢＬと接続され、ソースまたはドレインの他方は配線ＶＲと接続されている。容量素子Ｃ１１の第２の電極は、配線ＲＷと接続されている。配線ＶＲは、所定の電位を供給する機能を有する配線である。ここでは一例として、配線ＶＲから低電源電位（接地電位など）が供給される場合について説明する。 In the memory cell MC, the gate of the transistor Tr11 is connected to the wiring WL, one of the source or drain is connected to the gate of the transistor Tr12 and the first electrode of the capacitive element C11, and the other of the source or drain is connected to the wiring WD. Has been done. One of the source or drain of the transistor Tr12 is connected to the wiring BL, and the other of the source or drain is connected to the wiring VR. The second electrode of the capacitive element C11 is connected to the wiring RW. The wiring VR is a wiring having a function of supplying a predetermined potential. Here, as an example, a case where a low power supply potential (ground potential or the like) is supplied from the wiring VR will be described.
　トランジスタＴｒ１１のソースまたはドレインの一方、トランジスタＴｒ１２のゲート、及び容量素子Ｃ１１の第１の電極と接続されたノードを、ノードＮＭとする。また、メモリセルＭＣ［１，１］、ＭＣ［２，１］のノードＮＭを、それぞれノードＮＭ［１，１］、ＮＭ［２，１］と表記する。 A node connected to one of the source and drain of the transistor Tr11, the gate of the transistor Tr12, and the first electrode of the capacitive element C11 is referred to as a node NM. Further, the node NMs of the memory cells MC [1,1] and MC [2,1] are referred to as nodes NM [1,1] and NM [2,1], respectively.
　メモリセルＭＣｒｅｆも、メモリセルＭＣと同様の構成を有する。 The memory cell MCref also has the same configuration as the memory cell MC.
　ノードＮＭとノードＮＭｒｅｆはそれぞれ、保持ノードとして機能する。ノードＮＭには第１のデータが保持され、ノードＮＭｒｅｆには参照データが保持される。また、配線ＢＬ［１］からメモリセルＭＣ［１，１］及びＭＣ［２，１］のトランジスタＴｒ１２には、それぞれ電流ＩＭＣ［１，１］、ＩＭＣ［２，１］が流れる。また、配線ＢＬｒｅｆからメモリセルＭＣｒｅｆ［１］、ＭＣｒｅｆ［２］のトランジスタＴｒ１２には、それぞれ電流ＩＭＣｒｅｆ［１］、ＩＭＣｒｅｆ［２］が流れる。 The node NM and the node NMref each function as a holding node. The first data is held in the node NM, and the reference data is held in the node NMref. Further, currents I MC [1, 1] and I MC [2, 1] flow from the wiring BL [1] to the transistors Tr12 of the memory cells MC [1, 1] and MC [2, 1], respectively. Further, currents I MCref [1] and I MCref [2] flow from the wiring BLref to the transistors Tr12 of the memory cells MCref [1] and MCref [2], respectively.
　トランジスタＴｒ１１は、ノードＮＭまたはノードＮＭｒｅｆの電位を保持するため、オフ電流が極めて小さいＯＳトランジスタを用いることが好ましい。これにより、ノードＮＭまたはノードＮＭｒｅｆの電位の変動を抑えることができ、演算精度の向上を図ることができる。また、ノードＮＭまたはノードＮＭｒｅｆの電位をリフレッシュする動作の頻度を低く抑えることが可能となり、消費電力を削減することができる。 Since the transistor Tr11 holds the potential of the node NM or the node NMref, it is preferable to use an OS transistor having an extremely small off current. As a result, the fluctuation of the potential of the node NM or the node NMref can be suppressed, and the calculation accuracy can be improved. Further, the frequency of the operation of refreshing the potential of the node NM or the node NMref can be suppressed low, and the power consumption can be reduced.
　トランジスタＴｒ１２は特に限定されず、例えばＳｉトランジスタまたはＯＳトランジスタなどを用いることができる。トランジスタＴｒ１２にＯＳトランジスタを用いる場合、トランジスタＴｒ１１と同じ製造装置を用いて、トランジスタＴｒ１２を作製することが可能となり、製造コストを抑制することができる。なお、トランジスタＴｒ１２はｎチャネル型であってもｐチャネル型であってもよい。 The transistor Tr12 is not particularly limited, and for example, a Si transistor or an OS transistor can be used. When an OS transistor is used for the transistor Tr12, the transistor Tr12 can be manufactured by using the same manufacturing apparatus as the transistor Tr11, and the manufacturing cost can be suppressed. The transistor Tr12 may be an n-channel type or a p-channel type.
　電流源回路ＣＳは、配線ＢＬ［１］乃至ＢＬ［ｎ］及び配線ＢＬｒｅｆと接続されている。電流源回路ＣＳは、配線ＢＬ［１］乃至ＢＬ［ｎ］及び配線ＢＬｒｅｆに電流を供給する機能を有する。なお、配線ＢＬ［１］乃至ＢＬ［ｎ］に供給される電流値と配線ＢＬｒｅｆに供給される電流値は異なっていてもよい。ここでは、電流源回路ＣＳから配線ＢＬ［１］乃至ＢＬ［ｎ］に供給される電流をＩＣ、電流源回路ＣＳから配線ＢＬｒｅｆに供給される電流をＩＣｒｅｆと表記する。 The current source circuit CS is connected to the wiring BL [1] to BL [n] and the wiring BLref. The current source circuit CS has a function of supplying a current to the wiring BL [1] to BL [n] and the wiring BLref. The current value supplied to the wiring BL [1] to BL [n] and the current value supplied to the wiring BLref may be different. Here, the current supplied from the current source circuit CS to the wiring BL [1] to BL [n] is referred to as IC, and the current supplied from the current source circuit CS to the wiring BLref is referred to as ICRef .
　カレントミラー回路ＣＭは、配線ＩＬ［１］乃至ＩＬ［ｎ］及び配線ＩＬｒｅｆを有する。配線ＩＬ［１］乃至ＩＬ［ｎ］はそれぞれ配線ＢＬ［１］乃至ＢＬ［ｎ］と接続され、配線ＩＬｒｅｆは、配線ＢＬｒｅｆと接続されている。ここでは、配線ＩＬ［１］乃至ＩＬ［ｎ］と配線ＢＬ［１］乃至ＢＬ［ｎ］の接続箇所をノードＮＰ［１］乃至ＮＰ［ｎ］と表記する。また、配線ＩＬｒｅｆと配線ＢＬｒｅｆの接続箇所をノードＮＰｒｅｆと表記する。 The current mirror circuit CM has wiring IL [1] to IL [n] and wiring ILref. The wiring IL [1] to IL [n] are connected to the wiring BL [1] to BL [n], respectively, and the wiring ILref is connected to the wiring BLref. Here, the connection points between the wiring IL [1] to IL [n] and the wiring BL [1] to BL [n] are referred to as nodes NP [1] to NP [n]. Further, the connection point between the wiring ILref and the wiring BLref is referred to as a node NPref.
　カレントミラー回路ＣＭは、ノードＮＰｒｅｆの電位に応じた電流ＩＣＭを配線ＩＬｒｅｆに流す機能と、この電流ＩＣＭを配線ＩＬ［１］乃至ＩＬ［ｎ］にも流す機能を有する。図１９には、配線ＢＬｒｅｆから配線ＩＬｒｅｆに電流ＩＣＭが排出され、配線ＢＬ［１］乃至ＢＬ［ｎ］から配線ＩＬ［１］乃至ＩＬ［ｎ］に電流ＩＣＭが排出される例を示している。また、カレントミラー回路ＣＭから配線ＢＬ［１］乃至ＢＬ［ｎ］を介してセルアレイＣＡに流れる電流を、ＩＢ［１］乃至ＩＢ［ｎ］と表記する。また、カレントミラー回路ＣＭから配線ＢＬｒｅｆを介してセルアレイＣＡに流れる電流を、ＩＢｒｅｆと表記する。 The current mirror circuit CM has a function of passing a current ICM corresponding to the potential of the node NPref to the wiring ILref and a function of passing the current ICM to the wiring IL [1] to IL [n]. FIG. 19 shows an example in which the current ICM is discharged from the wiring BLref to the wiring ILref , and the current ICM is discharged from the wiring BL [1] to BL [n] to the wiring IL [1] to IL [n]. ing. Further, the current flowing from the current mirror circuit CM to the cell array CA via the wiring BL [1] to BL [n] is referred to as IB [1] to IB [n]. Further, the current flowing from the current mirror circuit CM to the cell array CA via the wiring BLref is referred to as IBref .
　回路ＷＤＤは、メモリセルＭＣに格納される第１のデータに対応する電位を、配線ＷＤ［１］乃至ＷＤ［ｎ］に供給する機能を有する。また、回路ＷＤＤは、メモリセルＭＣｒｅｆに格納される参照データに対応する電位を、配線ＷＤｒｅｆに供給する機能を有する。回路ＷＬＤは、データの書き込みを行うメモリセルＭＣまたはメモリセルＭＣｒｅｆを選択するための信号を、配線ＷＬ［１］乃至ＷＬ［ｍ］に供給する機能を有する。回路ＣＬＤは、第２のデータに対応する電位を、配線ＲＷ［１］乃至ＲＷ［ｍ］に供給する機能を有する。 The circuit WDD has a function of supplying the potential corresponding to the first data stored in the memory cell MC to the wiring WD [1] to WD [n]. Further, the circuit WDD has a function of supplying the potential corresponding to the reference data stored in the memory cell MCref to the wiring WDref. The circuit WLD has a function of supplying a signal for selecting a memory cell MC or a memory cell MCref for writing data to the wirings WL [1] to WL [m]. The circuit CLD has a function of supplying the potential corresponding to the second data to the wiring RW [1] to RW [m].
　オフセット回路ＯＦＳＴは、配線ＢＬ［１］乃至ＢＬ［ｎ］から流れる電流の量またはその変化量を検出する機能を有する。また、オフセット回路ＯＦＳＴは、検出結果を配線ＯＬ［１］乃至ＯＬ［ｎ］に出力する機能を有する。なお、オフセット回路ＯＦＳＴは、検出結果に対応する電流を配線ＯＬ［１］乃至ＯＬ［ｎ］に出力してもよいし、検出結果に対応する電流を電圧に変換して配線ＯＬ［１］乃至ＯＬ［ｎ］に出力してもよい。セルアレイＣＡとオフセット回路ＯＦＳＴの間を流れる電流を、Ｉα［１］乃至Ｉα［ｎ］と表記する。 The offset circuit OFST has a function of detecting the amount of current flowing from the wirings BL [1] to BL [n] or the amount of change thereof. Further, the offset circuit OFST has a function of outputting the detection result to the wiring OL [1] to OL [n]. The offset circuit OFST may output the current corresponding to the detection result to the wiring OL [1] to OL [n], or convert the current corresponding to the detection result into a voltage to wire OL [1] to OL [n]. It may be output to OL [n]. The current flowing between the cell array CA and the offset circuit OFST is referred to as I α [1] to I α [n].
　活性化関数回路ＡＣＴＶは、オフセット回路ＯＦＳＴから入力された信号を、あらかじめ定義された活性化関数に従って変換するための演算を行う機能を有する。活性化関数としては、例えば、シグモイド関数、ｔａｎｈ関数、ｓｏｆｔｍａｘ関数、ＲｅＬＵ関数、閾値関数などを用いることができる。活性化関数回路ＡＣＴＶによって変換された信号は、出力データとして配線ＮＩＬ［１］乃至ＮＩＬ［ｎ］に出力される。 The activation function circuit ACTV has a function of performing an operation for converting a signal input from the offset circuit OFST according to a predefined activation function. As the activation function, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function and the like can be used. The signal converted by the activation function circuit ACTV is output to the wiring NIL [1] to NIL [n] as output data.
　半導体装置ＭＡＣにより、積和演算を行うことができる。なお、メモリセルＭＣ及びメモリセルＭＣｒｅｆとして図２０に示す構成を用いることにより、少ないトランジスタ数で積和演算回路を構成することができる。そのため、半導体装置ＭＡＣの回路規模の縮小を図ることができる。 The product-sum calculation can be performed by the semiconductor device MAC. By using the configurations shown in FIG. 20 as the memory cell MC and the memory cell MCref, the product-sum calculation circuit can be configured with a small number of transistors. Therefore, the circuit scale of the semiconductor device MAC can be reduced.
　半導体装置ＭＡＣをニューラルネットワークにおける演算に用いる場合、メモリセルＭＣの行数ｍは一のニューロンに供給される入力データの数に対応させ、メモリセルＭＣの列数ｎはニューロンの数に対応させることができる。例えば、図１８Ａに示す中間層ＨＬにおいて半導体装置ＭＡＣを用いた積和演算を行う場合を考える。このとき、メモリセルＭＣの行数ｍは、入力層ＩＬから供給される入力データの数（入力層ＩＬのニューロンの数）に設定し、メモリセルＭＣの列数ｎは、中間層ＨＬのニューロンの数に設定することができる。 When the semiconductor device MAC is used for an operation in a neural network, the number of rows m of the memory cell MC corresponds to the number of input data supplied to one neuron, and the number of columns n of the memory cell MC corresponds to the number of neurons. Can be done. For example, consider a case where a product-sum operation using a semiconductor device MAC is performed in the intermediate layer HL shown in FIG. 18A. At this time, the number of rows m of the memory cell MC is set to the number of input data supplied from the input layer IL (the number of neurons of the input layer IL), and the number of columns n of the memory cell MC is the number of neurons of the intermediate layer HL. Can be set to the number of.
　なお、半導体装置ＭＡＣを適用するニューラルネットワークの構造は特に限定されない。例えば半導体装置ＭＡＣは、畳み込みニューラルネットワーク（ＣＮＮ）、再帰型ニューラルネットワーク（ＲＮＮ）、オートエンコーダ、ボルツマンマシン（制限ボルツマンマシンを含む）などに用いることもできる。 The structure of the neural network to which the semiconductor device MAC is applied is not particularly limited. For example, the semiconductor device MAC can also be used for a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a Boltzmann machine (including a restricted Boltzmann machine), and the like.
　以上のように、半導体装置ＭＡＣを用いることにより、ニューラルネットワークの積和演算を行うことができる。さらに、セルアレイＣＡに図２０に示すメモリセルＭＣ及びメモリセルＭＣｒｅｆを用いることにより、演算精度の向上、消費電力の削減、または回路規模の縮小を図ることが可能な集積回路を提供することができる。 As described above, the product-sum operation of the neural network can be performed by using the semiconductor device MAC. Further, by using the memory cell MC and the memory cell MCref shown in FIG. 20 for the cell array CA, it is possible to provide an integrated circuit capable of improving calculation accuracy, reducing power consumption, or reducing the circuit scale. ..
　本実施の形態は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。 This embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.
（実施の形態６）
　本実施の形態では、本発明の一態様の表示システムに用いることができる表示装置について図２１~図２３を用いて説明する。 (Embodiment 6)
In the present embodiment, a display device that can be used in the display system of one aspect of the present invention will be described with reference to FIGS. 21 to 23.
＜画素の構成例＞
　図２１Ａ~図２１Ｅを用いて、画素２００の構成例を説明する。 <Pixel configuration example>
A configuration example of the pixel 200 will be described with reference to FIGS. 21A to 21E.
　画素２００は、複数の画素２１０を有する。複数の画素２１０は、それぞれ、副画素として機能する。それぞれ異なる色を呈する複数の画素２１０によって１つの画素２００が構成されることで、表示部では、フルカラーの表示を行うことができる。 The pixel 200 has a plurality of pixels 210. Each of the plurality of pixels 210 functions as a sub-pixel. By forming one pixel 200 by a plurality of pixels 210 each exhibiting a different color, the display unit can perform full-color display.
　図２１Ａ、図２１Ｂに示す画素２００は、それぞれ、３つの副画素を有する。図２１Ａに示す画素２００が有する画素２１０が呈する色の組み合わせは、赤（Ｒ）、緑（Ｇ）、及び青（Ｂ）である。図２１Ｂに示す画素２００が有する画素２１０が呈する色の組み合わせは、シアン（Ｃ）、マゼンタ（Ｍ）、黄色（Ｙ）である。 Each of the pixels 200 shown in FIGS. 21A and 21B has three sub-pixels. The color combinations exhibited by the pixels 210 of the pixels 200 shown in FIG. 21A are red (R), green (G), and blue (B). The color combinations exhibited by the pixels 210 of the pixels 200 shown in FIG. 21B are cyan (C), magenta (M), and yellow (Y).
　図２１Ｃ~図２１Ｅに示す画素２００は、それぞれ、４つの副画素を有する。図２１Ｃに示す画素２００が有する画素２１０が呈する色の組み合わせは、赤（Ｒ）、緑（Ｇ）、青（Ｂ）、白（Ｗ）である。白色を呈する副画素を用いることで、表示部の輝度を高めることができる。図２１Ｄに示す画素２００が有する画素２１０が呈する色の組み合わせは、赤（Ｒ）、緑（Ｇ）、青（Ｂ）、黄（Ｙ）である。図２１Ｅに示す画素２００が有する画素２１０が呈する色の組み合わせは、シアン（Ｃ）、マゼンタ（Ｍ）、黄色（Ｙ）、白（Ｗ）である。 Each of the pixels 200 shown in FIGS. 21C to 21E has four sub-pixels. The color combinations exhibited by the pixels 210 of the pixels 200 shown in FIG. 21C are red (R), green (G), blue (B), and white (W). By using the sub-pixels exhibiting white color, the brightness of the display unit can be increased. The color combinations exhibited by the pixels 210 of the pixels 200 shown in FIG. 21D are red (R), green (G), blue (B), and yellow (Y). The color combinations exhibited by the pixels 210 of the pixels 200 shown in FIG. 21E are cyan (C), magenta (M), yellow (Y), and white (W).
　１つの画素として機能させる副画素の数を増やし、赤、緑、青、シアン、マゼンタ、及び黄などの色を呈する副画素を適宜組み合わせることにより、中間調の再現性を高めることができる。よって、表示品位を高めることができる。 By increasing the number of sub-pixels that function as one pixel and appropriately combining sub-pixels that exhibit colors such as red, green, blue, cyan, magenta, and yellow, the reproducibility of halftones can be improved. Therefore, the display quality can be improved.
　また、本発明の一態様の表示装置は、さまざまな規格の色域を再現することができる。例えば、テレビ放送で使われるＰＡＬ（Ｐｈａｓｅ　Ａｌｔｅｒｎａｔｉｎｇ　Ｌｉｎｅ）規格及びＮＴＳＣ（Ｎａｔｉｏｎａｌ　Ｔｅｌｅｖｉｓｉｏｎ　Ｓｙｓｔｅｍ　Ｃｏｍｍｉｔｔｅｅ）規格、パーソナルコンピュータ、デジタルカメラ、プリンタなどの電子機器に用いる表示装置で広く使われているｓＲＧＢ（ｓｔａｎｄａｒｄ　ＲＧＢ）規格及びＡｄｏｂｅ　ＲＧＢ規格、ＨＤＴＶ（Ｈｉｇｈ　Ｄｅｆｉｎｉｔｉｏｎ　Ｔｅｌｅｖｉｓｉｏｎ、ハイビジョンともいう）で使われるＩＴＵ−Ｒ　ＢＴ．７０９（Ｉｎｔｅｒｎａｔｉｏｎａｌ　Ｔｅｌｅｃｏｍｍｕｎｉｃａｔｉｏｎ　Ｕｎｉｏｎ　Ｒａｄｉｏｃｏｍｍｕｎｉｃａｔｉｏｎ　Ｓｅｃｔｏｒ　Ｂｒｏａｄｃａｓｔｉｎｇ　Ｓｅｒｖｉｃｅ（Ｔｅｌｅｖｉｓｉｏｎ）　７０９）規格、デジタルシネマ映写で使われるＤＣＩ−Ｐ３（Ｄｉｇｉｔａｌ　Ｃｉｎｅｍａ　Ｉｎｉｔｉａｔｉｖｅｓ　Ｐ３）規格、ＵＨＤＴＶ（Ｕｌｔｒａ　Ｈｉｇｈ　Ｄｅｆｉｎｉｔｉｏｎ　Ｔｅｌｅｖｉｓｉｏｎ、スーパーハイビジョンともいう）で使われるＩＴＵ−Ｒ　ＢＴ．２０２０（ＲＥＣ．２０２０（Ｒｅｃｏｍｍｅｎｄａｔｉｏｎ　２０２０））規格などの色域を再現することができる。 Further, the display device of one aspect of the present invention can reproduce the color gamut of various standards. For example, the PAL (Phase Alternate Line) standard used in television broadcasting, the NTSC (National Television System Committee) standard, and sRGB (standard RGB) widely used in display devices used in electronic devices such as personal computers, digital cameras, and printers. ITU-R BT. Standards, Adobe RGB standards, and HDTV (High Definition Television, also called high-definition television). 709 (International Telecommunication Union Radiocommunication Vector Broadcasting Service (Television) 709) standard, DCI-P3 (Digital Cinema Projection) used in digital cinema projection, DCI-P3 (Digital Cinema Indefiation TV) Super Initives HD R BT. It is possible to reproduce a color gamut such as the 2020 (REC. 2020 (Recommendation 2020)) standard.
　また、画素２００を１９２０×１０８０のマトリクス状に配置すると、いわゆるフルハイビジョン（「２Ｋ解像度」、「２Ｋ１Ｋ」、または「２Ｋ」などともいう）の解像度でフルカラー表示可能な表示装置を実現することができる。また、例えば、画素２００を３８４０×２１６０のマトリクス状に配置すると、いわゆるウルトラハイビジョン（「４Ｋ解像度」、「４Ｋ２Ｋ」、または「４Ｋ」などともいう）の解像度でフルカラー表示可能な表示装置を実現することができる。また、例えば、画素２００を７６８０×４３２０のマトリクス状に配置すると、いわゆるスーパーハイビジョン（「８Ｋ解像度」、「８Ｋ４Ｋ」、または「８Ｋ」などともいう）の解像度でフルカラー表示可能な表示装置を実現することができる。画素２００を増やすことで、１６Ｋまたは３２Ｋの解像度でフルカラー表示可能な表示装置を実現することも可能である。 Further, by arranging the pixels 200 in a matrix of 1920 × 1080, it is possible to realize a display device capable of full-color display at a so-called full high-definition (also referred to as “2K resolution”, “2K1K”, “2K”, etc.) resolution. can. Further, for example, by arranging the pixels 200 in a matrix of 3840 × 2160, a display device capable of full-color display at a so-called ultra-high definition (also referred to as “4K resolution”, “4K2K”, “4K”, etc.) resolution is realized. be able to. Further, for example, by arranging the pixels 200 in a matrix of 7680 × 4320, a display device capable of full-color display at a so-called super high-definition (also referred to as “8K resolution”, “8K4K”, “8K”, etc.) resolution is realized. be able to. By increasing the number of pixels 200, it is possible to realize a display device capable of full-color display at a resolution of 16K or 32K.
　本発明の一態様の表示装置が有する表示素子としては、無機ＥＬ素子、有機ＥＬ素子、ＬＥＤ（ミニＬＥＤ、及びマイクロＬＥＤを含む）等の発光素子、液晶素子、電気泳動素子、ＭＥＭＳ（マイクロ・エレクトロ・メカニカル・システム）を用いた表示素子等が挙げられる。 Display elements included in the display device of one aspect of the present invention include inorganic EL elements, organic EL elements, light emitting elements such as LEDs (including mini LEDs and micro LEDs), liquid crystal elements, electrophoresis elements, and MEMS (micro-LEDs). Examples include display elements using an electromechanical system).
＜表示装置の構成例＞
　次に、図２２及び図２３を用いて、表示装置の構成例について説明する。 <Display device configuration example>
Next, a configuration example of the display device will be described with reference to FIGS. 22 and 23.
　図２２に、カラーフィルタ方式が適用されたトップエミッション構造の発光表示装置の断面図を示す。 FIG. 22 shows a cross-sectional view of a light emitting display device having a top emission structure to which a color filter method is applied.
　図２２に示す表示装置は、画素部５６２及び走査線駆動回路５６４を有する。 The display device shown in FIG. 22 has a pixel unit 562 and a scanning line drive circuit 564.
　画素部５６２において、基板２０２上には、トランジスタ２５１ａ、トランジスタ４４６ａ、及び発光素子１７０等が設けられている。走査線駆動回路５６４において、基板２０２上には、トランジスタ２０１ａ等が設けられている。 In the pixel unit 562, a transistor 251a, a transistor 446a, a light emitting element 170, and the like are provided on the substrate 202. In the scanning line drive circuit 564, a transistor 201a or the like is provided on the substrate 202.
　トランジスタ２５１ａは、第１のゲート電極として機能する導電層２２１と、第１のゲート絶縁層として機能する絶縁層２１１と、半導体層２３１と、ソース電極及びドレイン電極として機能する導電層２２２ａ及び導電層２２２ｂと、第２のゲート電極として機能する導電層２２３と、第２のゲート絶縁層として機能する絶縁層２２５と、を有する。半導体層２３１は、チャネル形成領域と低抵抗領域とを有する。チャネル形成領域は、絶縁層２２５を介して導電層２２３と重なる。低抵抗領域は、導電層２２２ａと接続される部分、及び、導電層２２２ｂと接続される部分を有する。 The transistor 251a includes a conductive layer 221 that functions as a first gate electrode, an insulating layer 211 that functions as a first gate insulating layer, a semiconductor layer 231 and a conductive layer 222a and a conductive layer that function as source and drain electrodes. It has 222b, a conductive layer 223 that functions as a second gate electrode, and an insulating layer 225 that functions as a second gate insulating layer. The semiconductor layer 231 has a channel forming region and a low resistance region. The channel forming region overlaps with the conductive layer 223 via the insulating layer 225. The low resistance region has a portion connected to the conductive layer 222a and a portion connected to the conductive layer 222b.
　トランジスタ２５１ａは、チャネルの上下にゲート電極を有する。２つのゲート電極は、電気的に接続されていることが好ましい。２つのゲート電極が電気的に接続されている構成のトランジスタは、他のトランジスタと比較して電界効果移動度を高めることが可能であり、オン電流を増大させることができる。その結果、高速動作が可能な回路を作製することができる。さらには回路部の占有面積を縮小することが可能となる。オン電流の大きなトランジスタを適用することで、表示装置を大型化、または高精細化して配線数が増大したとしても、各配線における信号遅延を低減することが可能であり、表示ムラを抑制することが可能である。また、回路部の占有面積を縮小できるため、表示装置の狭額縁化が可能である。また、このような構成を適用することで、信頼性の高いトランジスタを実現することができる。 The transistor 251a has gate electrodes above and below the channel. The two gate electrodes are preferably electrically connected. A transistor having a configuration in which two gate electrodes are electrically connected can increase the field effect mobility as compared with other transistors, and can increase the on-current. As a result, it is possible to manufacture a circuit capable of high-speed operation. Furthermore, it is possible to reduce the occupied area of the circuit unit. By applying a transistor with a large on-current, it is possible to reduce the signal delay in each wiring even if the display device is made larger or finer and the number of wirings is increased, and display unevenness can be suppressed. Is possible. Further, since the occupied area of the circuit unit can be reduced, the frame of the display device can be narrowed. Further, by applying such a configuration, a highly reliable transistor can be realized.
　導電層２２３上には絶縁層２１２及び絶縁層２１３が設けられており、その上に、導電層２２２ａ及び導電層２２２ｂが設けられている。トランジスタ２５１ａの構造は、導電層２２１と導電層２２２ａまたは導電層２２２ｂとの物理的な距離を離すことが容易なため、これらの間の寄生容量を低減することが可能である。 An insulating layer 212 and an insulating layer 213 are provided on the conductive layer 223, and a conductive layer 222a and a conductive layer 222b are provided on the insulating layer 212a and the insulating layer 213. Since the structure of the transistor 251a makes it easy to separate the conductive layer 221 from the conductive layer 222a or the conductive layer 222b, it is possible to reduce the parasitic capacitance between them.
　表示装置が有するトランジスタの構造は特に限定されない。例えば、プレーナ型のトランジスタとしてもよいし、スタガ型のトランジスタとしてもよいし、逆スタガ型のトランジスタとしてもよい。また、トップゲート構造またはボトムゲート構造のいずれのトランジスタ構造としてもよい。または、チャネルの上下にゲート電極が設けられていてもよい。 The structure of the transistor of the display device is not particularly limited. For example, it may be a planar type transistor, a stagger type transistor, or an inverted stagger type transistor. Further, a transistor structure having either a top gate structure or a bottom gate structure may be used. Alternatively, gate electrodes may be provided above and below the channel.
　トランジスタ２５１ａは、半導体層２３１に、金属酸化物を有する。金属酸化物は、酸化物半導体として機能することができる。 The transistor 251a has a metal oxide in the semiconductor layer 231. The metal oxide can function as an oxide semiconductor.
　トランジスタ４４６ａ及びトランジスタ２０１ａは、トランジスタ２５１ａと同様の構成を有する。本発明の一態様において、これらのトランジスタの構成が異なっていてもよい。駆動回路部が有するトランジスタと画素部５６２が有するトランジスタは、同じ構造であってもよく、異なる構造であってもよい。駆動回路部が有するトランジスタは、全て同じ構造であってもよく、２種類以上の構造が組み合わせて用いられていてもよい。同様に、画素部５６２が有するトランジスタは、全て同じ構造であってもよく、２種類以上の構造が組み合わせて用いられていてもよい。 The transistor 446a and the transistor 201a have the same configuration as the transistor 251a. In one aspect of the present invention, the configurations of these transistors may be different. The transistor included in the drive circuit unit and the transistor included in the pixel unit 562 may have the same structure or different structures. The transistors included in the drive circuit unit may all have the same structure, or two or more types of structures may be used in combination. Similarly, the transistors included in the pixel unit 562 may all have the same structure, or two or more types of structures may be used in combination.
　トランジスタ４４６ａは、絶縁層２１５を介して、発光素子１７０と重なる。トランジスタ、容量素子、及び配線等を、発光素子１７０の発光領域と重ねて配置することで、画素部５６２の開口率を高めることができる。 The transistor 446a overlaps with the light emitting element 170 via the insulating layer 215. By arranging the transistor, the capacitive element, the wiring, and the like so as to overlap with the light emitting region of the light emitting element 170, the aperture ratio of the pixel portion 562 can be increased.
　発光素子１７０は、画素電極１７１、ＥＬ層１７２、及び共通電極１７３を有する。発光素子１７０は、着色層２０５側に光を射出する。 The light emitting element 170 has a pixel electrode 171 and an EL layer 172, and a common electrode 173. The light emitting element 170 emits light to the colored layer 205 side.
　画素電極１７１及び共通電極１７３のうち、一方は、陽極として機能し、他方は、陰極として機能する。画素電極１７１及び共通電極１７３の間に、発光素子１７０の閾値電圧より高い電圧を印加すると、ＥＬ層１７２に陽極側から正孔が注入され、陰極側から電子が注入される。注入された電子と正孔はＥＬ層１７２において再結合し、ＥＬ層１７２に含まれる発光物質が発光する。 Of the pixel electrode 171 and the common electrode 173, one functions as an anode and the other functions as a cathode. When a voltage higher than the threshold voltage of the light emitting element 170 is applied between the pixel electrode 171 and the common electrode 173, holes are injected into the EL layer 172 from the anode side, and electrons are injected from the cathode side. The injected electrons and holes are recombined in the EL layer 172, and the luminescent substance contained in the EL layer 172 emits light.
　画素電極１７１は、トランジスタ２５１ａが有する導電層２２２ｂと電気的に接続される。これらは、直接接続されてもよいし、他の導電層を介して接続されてもよい。画素電極１７１は、画素電極として機能し、発光素子１７０ごとに設けられている。隣り合う２つの画素電極１７１は、絶縁層２１６によって電気的に絶縁されている。 The pixel electrode 171 is electrically connected to the conductive layer 222b of the transistor 251a. These may be directly connected or may be connected via another conductive layer. The pixel electrode 171 functions as a pixel electrode and is provided for each light emitting element 170. The two adjacent pixel electrodes 171 are electrically insulated by the insulating layer 216.
　ＥＬ層１７２は、発光性の物質を含む層である。 The EL layer 172 is a layer containing a luminescent substance.
　共通電極１７３は、共通電極として機能し、複数の発光素子１７０にわたって設けられている。共通電極１７３には、定電位が供給される。 The common electrode 173 functions as a common electrode and is provided over a plurality of light emitting elements 170. A constant potential is supplied to the common electrode 173.
　発光素子１７０は、接着層１７４を介して着色層２０５と重なる。絶縁層２１６は、接着層１７４を介して遮光層２０６と重なる。 The light emitting element 170 overlaps with the colored layer 205 via the adhesive layer 174. The insulating layer 216 overlaps with the light shielding layer 206 via the adhesive layer 174.
　発光素子１７０には、マイクロキャビティ構造を採用してもよい。カラーフィルタ（着色層２０５）とマイクロキャビティ構造との組み合わせにより、表示装置からは、色純度の高い光を取り出すことができる。 A microcavity structure may be adopted for the light emitting element 170. By combining the color filter (colored layer 205) and the microcavity structure, light having high color purity can be extracted from the display device.
　着色層２０５は特定の波長域の光を透過する有色層である。例えば、赤色、緑色、青色、または黄色の波長域の光を透過するカラーフィルタなどを用いることができる。着色層２０５に用いることのできる材料としては、金属材料、樹脂材料、顔料または染料が含まれた樹脂材料などが挙げられる。 The colored layer 205 is a colored layer that transmits light in a specific wavelength range. For example, a color filter that transmits light in the wavelength range of red, green, blue, or yellow can be used. Examples of the material that can be used for the colored layer 205 include a metal material, a resin material, a resin material containing a pigment or a dye, and the like.
　なお、本発明の一態様の表示装置は、カラーフィルタ方式に限られず、塗り分け方式、色変換方式、または量子ドット方式等を適用してもよい。また、本発明の一態様の表示装置は、トップエミッション構造に限られず、ボトムエミッション構造等を適用してもよい。 The display device according to one aspect of the present invention is not limited to the color filter method, and a separate painting method, a color conversion method, a quantum dot method, or the like may be applied. Further, the display device according to one aspect of the present invention is not limited to the top emission structure, and a bottom emission structure or the like may be applied.
　遮光層２０６は、隣接する着色層２０５の間に設けられている。遮光層２０６は隣接する発光素子１７０からの光を遮光し、隣接する発光素子１７０間における混色を抑制する。ここで、着色層２０５の端部を、遮光層２０６と重なるように設けることにより、光漏れを抑制することができる。遮光層２０６としては、発光素子１７０からの発光を遮る材料を用いることができ、例えば、金属材料、または、顔料もしくは染料を含む樹脂材料等を用いてブラックマトリクスを形成することができる。なお、遮光層２０６は、走査線駆動回路５６４などの画素部５６２以外の領域に設けると、導波光などによる意図しない光漏れを抑制できるため好ましい。 The light-shielding layer 206 is provided between the adjacent colored layers 205. The light-shielding layer 206 shields light from adjacent light-emitting elements 170 and suppresses color mixing between adjacent light-emitting elements 170. Here, by providing the end portion of the colored layer 205 so as to overlap the light-shielding layer 206, light leakage can be suppressed. As the light-shielding layer 206, a material that blocks light emission from the light-emitting element 170 can be used, and for example, a metal material, a resin material containing a pigment or a dye, or the like can be used to form a black matrix. It is preferable that the light-shielding layer 206 is provided in a region other than the pixel portion 562 such as the scanning line drive circuit 564 because it can suppress unintended light leakage due to waveguide light or the like.
　基板２０２と基板２０３は、接着層１７４によって貼り合わされている。 The substrate 202 and the substrate 203 are bonded to each other by the adhesive layer 174.
　導電層５６５は、導電層２５５及び接続体２４２を介して、ＦＰＣ１６２と電気的に接続される。導電層５６５は、トランジスタが有する導電層と同一の材料及び同一の工程で形成されることが好ましい。本実施の形態では、導電層５６５が、ソース電極及びドレイン電極として機能する導電層と同一の材料及び同一の工程で形成される例を示す。 The conductive layer 565 is electrically connected to the FPC 162 via the conductive layer 255 and the connecting body 242. The conductive layer 565 is preferably formed of the same material and the same process as the conductive layer of the transistor. In this embodiment, an example is shown in which the conductive layer 565 is formed of the same material and the same process as the conductive layer that functions as a source electrode and a drain electrode.
　接続体２４２としては、様々な異方性導電フィルム（ＡＣＦ：Ａｎｉｓｏｔｒｏｐｉｃ　Ｃｏｎｄｕｃｔｉｖｅ　Ｆｉｌｍ）及び異方性導電ペースト（ＡＣＰ：Ａｎｉｓｏｔｒｏｐｉｃ　Ｃｏｎｄｕｃｔｉｖｅ　Ｐａｓｔｅ）などを用いることができる。 As the connector 242, various anisotropic conductive films (ACF: Anisotropic Conducive Film), anisotropic conductive paste (ACP: Anisotropic Conducive Paste), and the like can be used.
　図２３に、縦電界方式が適用された透過型液晶表示装置の断面図を示す。 FIG. 23 shows a cross-sectional view of a transmissive liquid crystal display device to which the vertical electric field method is applied.
　図２３に示す表示装置は、画素部５６２及び走査線駆動回路５６４を有する。 The display device shown in FIG. 23 has a pixel unit 562 and a scanning line drive circuit 564.
　画素部５６２において、基板２０２上には、トランジスタ４４６ｄ、及び液晶素子１８０等が設けられている。走査線駆動回路５６４において、基板２０２上には、トランジスタ２０１ｄ等が設けられている。図２３に示す表示装置では、着色層２０５が基板２０３側に設けられている。なお、着色層２０５を基板２０２側に設けてもよい。着色層２０５を基板２０２側に設けることで、基板２０３側の構成を簡素化することができる。 In the pixel unit 562, a transistor 446d, a liquid crystal element 180, and the like are provided on the substrate 202. In the scanning line drive circuit 564, a transistor 201d or the like is provided on the substrate 202. In the display device shown in FIG. 23, the colored layer 205 is provided on the substrate 203 side. The colored layer 205 may be provided on the substrate 202 side. By providing the colored layer 205 on the substrate 202 side, the configuration on the substrate 203 side can be simplified.
　トランジスタ４４６ｄは、ゲート電極として機能する導電層２２１と、ゲート絶縁層として機能する絶縁層２１１と、半導体層２３１と、ソース電極及びドレイン電極として機能する導電層２２２ａ及び導電層２２２ｂと、を有する。トランジスタ４４６ｄは、絶縁層２１７及び絶縁層２１８に覆われている。 The transistor 446d has a conductive layer 221 that functions as a gate electrode, an insulating layer 211 that functions as a gate insulating layer, a semiconductor layer 231 and a conductive layer 222a and a conductive layer 222b that function as source electrodes and drain electrodes. The transistor 446d is covered with an insulating layer 217 and an insulating layer 218.
　トランジスタ４４６ｄは、半導体層２３１に、金属酸化物を有する。 The transistor 446d has a metal oxide in the semiconductor layer 231.
　液晶素子１８０は、画素電極１８１、共通電極１８２、及び液晶層１８３を有する。液晶層１８３は、画素電極１８１と共通電極１８２との間に位置する。配向膜２０８ａは画素電極１８１に接して設けられている。配向膜２０８ｂは共通電極１８２に接して設けられている。画素電極１８１は、絶縁層２１５、絶縁層２１８、及び絶縁層２１７に設けられた開口を介して、トランジスタ４４６ｄが有する導電層２２２ｂと電気的に接続される。 The liquid crystal element 180 has a pixel electrode 181 and a common electrode 182, and a liquid crystal layer 183. The liquid crystal layer 183 is located between the pixel electrode 181 and the common electrode 182. The alignment film 208a is provided in contact with the pixel electrode 181. The alignment film 208b is provided in contact with the common electrode 182. The pixel electrode 181 is electrically connected to the conductive layer 222b of the transistor 446d via the openings provided in the insulating layer 215, the insulating layer 218, and the insulating layer 217.
　液晶層１８３と接する配向膜を設けることが好ましい。配向膜は、液晶層１８３の配向を制御することができる。 It is preferable to provide an alignment film in contact with the liquid crystal layer 183. The alignment film can control the orientation of the liquid crystal layer 183.
　バックライトユニット５５２からの光は、基板２０２、画素電極１８１、液晶層１８３、共通電極１８２、着色層２０５、及び基板２０３を介して、表示装置の外部に射出される。バックライトユニット５５２の光が透過するこれらの層の材料には、可視光を透過する材料を用いる。 The light from the backlight unit 552 is emitted to the outside of the display device via the substrate 202, the pixel electrode 181 and the liquid crystal layer 183, the common electrode 182, the colored layer 205, and the substrate 203. As the material of these layers through which the light of the backlight unit 552 is transmitted, a material that transmits visible light is used.
　遮光層２０６と、共通電極１８２と、の間、及び着色層２０５と、共通電極１８２と、の間には、オーバーコート２０７が設けられている。オーバーコート２０７は、着色層２０５、遮光層２０６等に含まれる不純物が液晶層１８３に拡散することを抑制できる。 An overcoat 207 is provided between the light-shielding layer 206 and the common electrode 182, and between the colored layer 205 and the common electrode 182. The overcoat 207 can prevent impurities contained in the colored layer 205, the light-shielding layer 206, and the like from diffusing into the liquid crystal layer 183.
　基板２０２と基板２０３は、接着層２０９によって貼り合わされている。基板２０２、基板２０３、接着層２０９に囲まれた領域に、液晶層１８３が封止されている。 The substrate 202 and the substrate 203 are bonded to each other by the adhesive layer 209. The liquid crystal layer 183 is sealed in the region surrounded by the substrate 202, the substrate 203, and the adhesive layer 209.
　表示装置の画素部５６２を挟むように、偏光板２０４ａ及び偏光板２０４ｂが配置されている。偏光板２０４ａよりも外側に配置されたバックライトユニット５５２からの光は偏光板２０４ａを介して表示装置に入射する。このとき、画素電極１８１と共通電極１８２の間に与える電圧によって液晶層１８３の配向を制御し、光の光学変調を制御することができる。すなわち、偏光板２０４ｂを介して射出される光の強度を制御することができる。また、入射光は着色層２０５によって特定の波長領域以外の光が吸収されるため、射出される光は例えば赤色、青色、または緑色を呈する光となる。 The polarizing plate 204a and the polarizing plate 204b are arranged so as to sandwich the pixel portion 562 of the display device. The light from the backlight unit 552 arranged outside the polarizing plate 204a is incident on the display device via the polarizing plate 204a. At this time, the orientation of the liquid crystal layer 183 can be controlled by the voltage applied between the pixel electrode 181 and the common electrode 182, and the optical modulation of light can be controlled. That is, the intensity of the light emitted through the polarizing plate 204b can be controlled. Further, since the incident light is absorbed by the colored layer 205 in a light other than the specific wavelength region, the emitted light is, for example, red, blue, or green.
　導電層５６５は、導電層２５５及び接続体２４２を介して、ＦＰＣ１６２と電気的に接続される。 The conductive layer 565 is electrically connected to the FPC 162 via the conductive layer 255 and the connecting body 242.
　本発明の一態様の液晶表示装置は、縦電界方式に限られず、横電界方式であってもよい。横電界方式の液晶表示装置には、例えば、ＦＦＳ（Ｆｒｉｎｇｅ　Ｆｉｅｌｄ　Ｓｗｉｔｃｈｉｎｇ）モードが適用された液晶素子を用いてもよい。 The liquid crystal display device according to one aspect of the present invention is not limited to the vertical electric field method, but may be a horizontal electric field method. For the horizontal electric field type liquid crystal display device, for example, a liquid crystal element to which the FFS (Fringe Field Switching) mode is applied may be used.
＜半導体層について＞
　本発明の一態様で開示されるトランジスタに用いる半導体材料の結晶性は特に限定されず、非晶質半導体、単結晶半導体、または単結晶以外の結晶性を有する半導体（微結晶半導体、多結晶半導体、または一部に結晶領域を有する半導体）のいずれを用いてもよい。単結晶半導体または結晶性を有する半導体を用いると、トランジスタ特性の劣化を抑制できるため好ましい。 <About the semiconductor layer>
The crystallinity of the semiconductor material used for the transistor disclosed in one aspect of the present invention is not particularly limited, and is an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having a crystalline property other than a single crystal (microcrystalline semiconductor, polycrystalline semiconductor). , Or a semiconductor having a partially crystalline region) may be used. It is preferable to use a single crystal semiconductor or a semiconductor having crystallinity because deterioration of transistor characteristics can be suppressed.
　トランジスタに用いる半導体材料としては、エネルギーギャップが２ｅＶ以上、好ましくは２．５ｅＶ以上、より好ましくは３ｅＶ以上である金属酸化物を用いることができる。代表的には、インジウムを含む金属酸化物などであり、例えば、後述するＣＡＣ−ＯＳなどを用いることができる。 As the semiconductor material used for the transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is a metal oxide containing indium, and for example, CAC-OS, which will be described later, can be used.
　シリコンよりもバンドギャップが広く、且つキャリア密度の小さい金属酸化物を用いたトランジスタは、その小さいオフ電流により、トランジスタと直列に接続された容量素子に蓄積した電荷を長期間に亘って保持することが可能である。 A transistor using a metal oxide having a wider bandgap and a smaller carrier density than silicon retains the charge accumulated in the capacitive element connected in series with the transistor for a long period of time due to its small off-current. Is possible.
　半導体層に好適な金属酸化物の詳細については、実施の形態６等を参照できる。 For details of the metal oxide suitable for the semiconductor layer, refer to the sixth embodiment and the like.
　また、トランジスタに用いる半導体材料としては、例えばシリコンを用いることができる。シリコンとして、特にアモルファスシリコンを用いることが好ましい。アモルファスシリコンを用いることで、大型の基板上に歩留り良くトランジスタを形成でき、量産性を高めることができる。 Further, as the semiconductor material used for the transistor, for example, silicon can be used. It is particularly preferable to use amorphous silicon as the silicon. By using amorphous silicon, a transistor can be formed on a large substrate with good yield, and mass productivity can be improved.
　また、微結晶シリコン、多結晶シリコン、単結晶シリコンなどの結晶性を有するシリコンを用いることもできる。特に、多結晶シリコンは、単結晶シリコンに比べて低温で形成でき、且つアモルファスシリコンに比べて高い電界効果移動度と高い信頼性を備える。 Further, silicon having crystallinity such as microcrystalline silicon, polycrystalline silicon, and single crystal silicon can also be used. In particular, polycrystalline silicon can be formed at a lower temperature than single crystal silicon, and has higher field effect mobility and higher reliability than amorphous silicon.
　また、１つの表示装置が、それぞれ半導体層の材料が異なる２種類以上のトランジスタを有していてもよい。 Further, one display device may have two or more types of transistors having different semiconductor layer materials.
　本実施の形態は、他の実施の形態と適宜組み合わせることができる。 This embodiment can be appropriately combined with other embodiments.
（実施の形態７）
　本実施の形態では、本発明の一態様で開示されるトランジスタの半導体層に用いることができる金属酸化物について説明する。なお、トランジスタの半導体層に金属酸化物を用いる場合、当該金属酸化物を酸化物半導体と読み替えてもよい。 (Embodiment 7)
In this embodiment, the metal oxide that can be used for the semiconductor layer of the transistor disclosed in one aspect of the present invention will be described. When a metal oxide is used for the semiconductor layer of the transistor, the metal oxide may be read as an oxide semiconductor.
　酸化物半導体は、単結晶酸化物半導体と、非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、ＣＡＡＣ−ＯＳ（ｃ−ａｘｉｓ−ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、多結晶酸化物半導体、ｎｃ−ＯＳ（ｎａｎｏｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、擬似非晶質酸化物半導体（ａ−ｌｉｋｅ　ＯＳ：ａｍｏｒｐｈｏｕｓ−ｌｉｋｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、及び非晶質酸化物半導体などがある。 Oxide semiconductors are divided into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystal oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudoamorphic oxide semiconductor (a-like). : Amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.
　また、本発明の一態様で開示されるトランジスタの半導体層には、ＣＡＣ−ＯＳ（Ｃｌｏｕｄ−Ａｌｉｇｎｅｄ　Ｃｏｍｐｏｓｉｔｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）を用いてもよい。 Further, CAC-OS (Cloud-Aligned Composite oxide semiconductor) may be used for the semiconductor layer of the transistor disclosed in one aspect of the present invention.
　なお、本発明の一態様で開示されるトランジスタの半導体層は、上述した非単結晶酸化物半導体を好適に用いることができる。また、非単結晶酸化物半導体としては、ｎｃ−ＯＳまたはＣＡＡＣ−ＯＳを好適に用いることができる。 The above-mentioned non-single crystal oxide semiconductor can be preferably used as the semiconductor layer of the transistor disclosed in one aspect of the present invention. Further, as the non-single crystal oxide semiconductor, nc-OS or CAAC-OS can be preferably used.
　なお、本発明の一態様では、トランジスタの半導体層として、ＣＡＣ−ＯＳを用いると好ましい。ＣＡＣ−ＯＳを用いることで、トランジスタに高い電気特性または高い信頼性を付与することができる。 In one aspect of the present invention, it is preferable to use CAC-OS as the semiconductor layer of the transistor. By using CAC-OS, high electrical characteristics or high reliability can be imparted to the transistor.
　以下では、ＣＡＣ−ＯＳの詳細について説明する。 The details of CAC-OS will be described below.
　ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、材料の一部では導電性の機能と、材料の一部では絶縁性の機能とを有し、材料の全体では半導体としての機能を有する。なお、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅを、トランジスタのチャネル形成領域に用いる場合、導電性の機能は、キャリアとなる電子（またはホール）を流す機能であり、絶縁性の機能は、キャリアとなる電子を流さない機能である。導電性の機能と、絶縁性の機能とを、それぞれ相補的に作用させることで、スイッチングさせる機能（Ｏｎ／Ｏｆｆさせる機能）をＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅに付与することができる。ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅにおいて、それぞれの機能を分離させることで、双方の機能を最大限に高めることができる。 CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. When CAC-OS or CAC-metal oxide is used in the channel formation region of the transistor, the conductive function is the function of flowing electrons (or holes) to be carriers, and the insulating function is the carrier. It is a function that does not allow electrons to flow. By making the conductive function and the insulating function act in a complementary manner, a switching function (on / off function) can be imparted to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.
　また、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、導電性領域、及び絶縁性領域を有する。導電性領域は、上述の導電性の機能を有し、絶縁性領域は、上述の絶縁性の機能を有する。また、材料中において、導電性領域と、絶縁性領域とは、ナノ粒子レベルで分離している場合がある。また、導電性領域と、絶縁性領域とは、それぞれ材料中に偏在する場合がある。また、導電性領域は、周辺がぼけてクラウド状に連結して観察される場合がある。 Further, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Further, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.
　また、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅにおいて、導電性領域と、絶縁性領域とは、それぞれ０．５ｎｍ以上１０ｎｍ以下、好ましくは０．５ｎｍ以上３ｎｍ以下のサイズで材料中に分散している場合がある。 Further, in CAC-OS or CAC-metal oxide, when the conductive region and the insulating region are dispersed in the material in a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively. There is.
　また、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、異なるバンドギャップを有する成分により構成される。例えば、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、絶縁性領域に起因するワイドギャップを有する成分と、導電性領域に起因するナローギャップを有する成分と、により構成される。当該構成の場合、キャリアを流す際に、ナローギャップを有する成分において、主にキャリアが流れる。また、ナローギャップを有する成分が、ワイドギャップを有する成分に相補的に作用し、ナローギャップを有する成分に連動してワイドギャップを有する成分にもキャリアが流れる。このため、上記ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅをトランジスタのチャネル形成領域に用いる場合、トランジスタのオン状態において高い電流駆動力、つまり大きなオン電流、及び高い電界効果移動度を得ることができる。 Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In the case of this configuration, when the carrier is flown, the carrier mainly flows in the component having a narrow gap. Further, the component having a narrow gap acts complementarily to the component having a wide gap, and the carrier flows to the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel forming region of the transistor, a high current driving force, that is, a large on-current and a high field effect mobility can be obtained in the ON state of the transistor.
　すなわち、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、マトリックス複合材（ｍａｔｒｉｘ　ｃｏｍｐｏｓｉｔｅ）または金属マトリックス複合材（ｍｅｔａｌ　ｍａｔｒｉｘ　ｃｏｍｐｏｓｉｔｅ）と呼称することもできる。 That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite material (matrix composite) or a metal matrix composite material (metal matrix composite).
　ＣＡＣ−ＯＳは、例えば、金属酸化物を構成する元素が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上２ｎｍ以下またはその近傍のサイズで偏在した材料の一構成である。なお、以下では、金属酸化物において、一つあるいはそれ以上の金属元素が偏在し、該金属元素を有する領域が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上２ｎｍ以下またはその近傍のサイズで混合した状態をモザイク状またはパッチ状ともいう。 CAC-OS is, for example, a composition of a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or a vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or its vicinity. The mixed state is also called a mosaic or patch.
　なお、金属酸化物は、少なくともインジウムを含むことが好ましい。特にインジウム及び亜鉛を含むことが好ましい。また、それらに加えて、アルミニウム、ガリウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、またはマグネシウムなどから選ばれた一種または複数種が含まれていてもよい。 The metal oxide preferably contains at least indium. In particular, it is preferable to contain indium and zinc. Also, in addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. It may contain one or more species selected from.
　例えば、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳ（ＣＡＣ−ＯＳの中でもＩｎ−Ｇａ−Ｚｎ酸化物を、特にＣＡＣ−ＩＧＺＯと呼称してもよい。）とは、インジウム酸化物（以下、ＩｎＯＸ１（Ｘ１は０よりも大きい実数）とする。）、またはインジウム亜鉛酸化物（以下、ＩｎＸ２ＺｎＹ２ＯＺ２（Ｘ２、Ｙ２、及びＺ２は０よりも大きい実数）とする。）と、ガリウム酸化物（以下、ＧａＯＸ３（Ｘ３は０よりも大きい実数）とする。）、またはガリウム亜鉛酸化物（以下、ＧａＸ４ＺｎＹ４ＯＺ４（Ｘ４、Ｙ４、及びＺ４は０よりも大きい実数）とする。）などと、に材料が分離することでモザイク状となり、モザイク状のＩｎＯＸ１、またはＩｎＸ２ＺｎＹ２ＯＺ２が、膜中に均一に分布した構成（以下、クラウド状ともいう。）である。 For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide may be particularly referred to as CAC-IGZO in CAC-OS) is an indium oxide (hereinafter, InO). X1 (X1 is a real number larger than 0), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers larger than 0)) and gallium. With an oxide (hereinafter, GaO X3 (X3 is a real number larger than 0)) or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers larger than 0)). In _ _ _ be.
　つまり、ＣＡＣ−ＯＳは、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域とが、混合している構成を有する複合金属酸化物である。なお、本明細書において、例えば、第１の領域の元素Ｍに対するＩｎの原子数比が、第２の領域の元素Ｍに対するＩｎの原子数比よりも大きいことを、第１の領域は、第２の領域と比較して、Ｉｎの濃度が高いとする。 That is, CAC-OS is a composite metal oxide having a structure in which a region containing GaO X3 as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component are mixed. In the present specification, for example, the atomic number ratio of In to the element M in the first region is larger than the atomic number ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the region 2.
　なお、ＩＧＺＯは通称であり、Ｉｎ、Ｇａ、Ｚｎ、及びＯによる１つの化合物をいう場合がある。代表例として、ＩｎＧａＯ３（ＺｎＯ）ｍ１（ｍ１は自然数）、またはＩｎ（１＋ｘ０）Ｇａ（１−ｘ０）Ｏ３（ＺｎＯ）ｍ０（−１≦ｘ０≦１、ｍ０は任意数）で表される結晶性の化合物が挙げられる。 In addition, IGZO is a common name and may refer to one compound consisting of In, Ga, Zn, and O. As a typical example, it is represented by InGaO 3 (ZnO) m1 (m1 is a natural number) or In (1 + x0) Ga (1-x0) O 3 (ZnO) m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number). Crystalline compounds can be mentioned.
　上記結晶性の化合物は、単結晶構造、多結晶構造、またはＣＡＡＣ（ｃ−ａｘｉｓ　ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌ）構造を有する。なお、ＣＡＡＣ構造とは、複数のＩＧＺＯのナノ結晶がｃ軸配向を有し、かつａ−ｂ面においては配向せずに連結した結晶構造である。 The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC (c-axis aligned crystalline) structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without orientation on the ab plane.
　一方、ＣＡＣ−ＯＳは、金属酸化物の材料構成に関する。ＣＡＣ−ＯＳとは、Ｉｎ、Ｇａ、Ｚｎ、及びＯを含む材料構成において、一部にＧａを主成分とするナノ粒子状に観察される領域と、一部にＩｎを主成分とするナノ粒子状に観察される領域とが、それぞれモザイク状にランダムに分散している構成をいう。従って、ＣＡＣ−ＯＳにおいて、結晶構造は副次的な要素である。 On the other hand, CAC-OS relates to the material composition of metal oxides. CAC-OS is a region observed in the form of nanoparticles mainly composed of Ga in a material composition containing In, Ga, Zn, and O, and nanoparticles mainly composed of In. The regions observed in the shape are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.
　なお、ＣＡＣ−ＯＳは、組成の異なる二種類以上の膜の積層構造は含まないものとする。例えば、Ｉｎを主成分とする膜と、Ｇａを主成分とする膜との２層からなる構造は、含まない。 It should be noted that CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component.
　なお、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域とは、明確な境界が観察できない場合がある。 In some cases, a clear boundary cannot be observed between the region containing GaO X3 as the main component and the region containing In X2 Zn Y2 O Z2 or InO X1 as the main component.
　なお、ガリウムの代わりに、アルミニウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、またはマグネシウムなどから選ばれた一種、または複数種が含まれている場合、ＣＡＣ−ＯＳは、一部に該金属元素を主成分とするナノ粒子状に観察される領域と、一部にＩｎを主成分とするナノ粒子状に観察される領域とが、それぞれモザイク状にランダムに分散している構成をいう。 Instead of gallium, choose from aluminum, ittrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium. When one or more of these species are contained, CAC-OS has a region observed in the form of nanoparticles mainly composed of the metal element and a nano portion containing In as a main component. The regions observed in the form of particles refer to a configuration in which the regions are randomly dispersed in a mosaic pattern.
　ＣＡＣ−ＯＳは、例えば基板を意図的に加熱しない条件で、スパッタリング法により形成することができる。また、ＣＡＣ−ＯＳをスパッタリング法で形成する場合、成膜ガスとして、不活性ガス（代表的にはアルゴン）、酸素ガス、及び窒素ガスの中から選ばれたいずれか一つまたは複数を用いればよい。また、成膜時の成膜ガスの総流量に対する酸素ガスの流量比は低いほど好ましく、例えば酸素ガスの流量比を０％以上３０％未満、好ましくは０％以上１０％以下とすることが好ましい。 CAC-OS can be formed by a sputtering method, for example, under the condition that the substrate is not intentionally heated. When the CAC-OS is formed by the sputtering method, one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as the film forming gas. good. Further, the lower the flow rate ratio of the oxygen gas to the total flow rate of the film-forming gas at the time of film formation is preferable, and for example, the flow rate ratio of the oxygen gas is preferably 0% or more and less than 30%, preferably 0% or more and 10% or less. ..
　ＣＡＣ−ＯＳは、Ｘ線回折（ＸＲＤ：Ｘ−ｒａｙ　ｄｉｆｆｒａｃｔｉｏｎ）測定法のひとつであるＯｕｔ−ｏｆ−ｐｌａｎｅ法によるθ／２θスキャンを用いて測定したときに、明確なピークが観察されないという特徴を有する。すなわち、Ｘ線回折測定から、測定領域のａ−ｂ面方向、及びｃ軸方向の配向は見られないことが分かる。 CAC-OS is characterized by the fact that no clear peak is observed when measured using the θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, from the X-ray diffraction measurement, it can be seen that the orientation of the measurement region in the ab plane direction and the c axis direction is not observed.
　またＣＡＣ−ＯＳは、プローブ径が１ｎｍの電子線（ナノビーム電子線ともいう。）を照射することで得られる電子線回折パターンにおいて、輝度の高いリング状の領域と、該リング状の領域内に複数の輝点が観測される。従って、電子線回折パターンから、ＣＡＣ−ＯＳの結晶構造が、平面方向、及び断面方向において、配向性を有さないｎｃ（ｎａｎｏ−ｃｒｙｓｔａｌ）構造を有することがわかる。 Further, CAC-OS has an electron beam diffraction pattern obtained by irradiating an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam) in a ring-shaped region having high brightness and in the ring-shaped region. Multiple bright spots are observed. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
　また例えば、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳでは、エネルギー分散型Ｘ線分光法（ＥＤＸ：Ｅｎｅｒｇｙ　Ｄｉｓｐｅｒｓｉｖｅ　Ｘ−ｒａｙ　ｓｐｅｃｔｒｏｓｃｏｐｙ）を用いて取得したＥＤＸマッピングにより、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域とが、偏在し、混合している構造を有することが確認できる。 Further, for example, in CAC-OS in In-Ga-Zn oxide, a region containing GaO X3 as a main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). And, it can be confirmed that In X2 Zn Y2 O Z2 or a region containing InO X1 as a main component is unevenly distributed and has a mixed structure.
　ＣＡＣ−ＯＳは、金属元素が均一に分布したＩＧＺＯ化合物とは異なる構造であり、ＩＧＺＯ化合物と異なる性質を有する。つまり、ＣＡＣ−ＯＳは、ＧａＯＸ３などが主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域と、に互いに相分離し、各元素を主成分とする領域がモザイク状である構造を有する。 CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IGZO compound. That is, the CAC-OS is phase-separated into a region containing GaO X3 or the like as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component, and a region containing each element as a main component. Has a mosaic-like structure.
　ここで、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域は、ＧａＯＸ３などが主成分である領域と比較して、導電性が高い領域である。つまり、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域を、キャリアが流れることにより、酸化物半導体としての導電性が発現する。従って、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域が、酸化物半導体中にクラウド状に分布することで、高い電界効果移動度（μ）が実現できる。 Here, the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component is a region having higher conductivity than the region in which GaO X3 or the like is the main component. That is, the conductivity as an oxide semiconductor is exhibited by the carrier flowing through the region where In X2 Zn Y2 O Z2 or InO X1 is the main component. Therefore, a high field effect mobility (μ) can be realized by distributing the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component in the oxide semiconductor in a cloud shape.
　一方、ＧａＯＸ３などが主成分である領域は、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域と比較して、絶縁性が高い領域である。つまり、ＧａＯＸ３などが主成分である領域が、酸化物半導体中に分布することで、リーク電流を抑制し、良好なスイッチング動作を実現できる。 On the other hand, the region in which GaO X3 or the like is the main component is a region having higher insulating properties than the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component. That is, since the region containing GaO X3 or the like as the main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be realized.
　従って、ＣＡＣ−ＯＳを半導体素子に用いた場合、ＧａＯＸ３などに起因する絶縁性と、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１に起因する導電性とが、相補的に作用することにより、大きなオン電流（Ｉｏｎ）、及び高い電界効果移動度（μ）を実現することができる。 Therefore, when CAC-OS is used for a semiconductor element, the insulation caused by GaO X3 and the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act in a complementary manner, resulting in a large effect. On current (Ion) and high field effect mobility (μ) can be realized.
　また、ＣＡＣ−ＯＳを用いた半導体素子は、信頼性が高い。従って、ＣＡＣ−ＯＳは、さまざまな半導体装置に最適である。 Moreover, the semiconductor element using CAC-OS has high reliability. Therefore, CAC-OS is most suitable for various semiconductor devices.
　本実施の形態は、他の実施の形態と適宜組み合わせることができる。 This embodiment can be appropriately combined with other embodiments.
（実施の形態８）
　本実施の形態では、本発明の一態様の電子機器について、図２４を用いて説明する。 (Embodiment 8)
In the present embodiment, the electronic device of one aspect of the present invention will be described with reference to FIG. 24.
　本実施の形態の電子機器は、本発明の一態様の表示システムを有する。これにより、電子機器の表示部は、高品質な映像を表示することができる。具体的には、大型の表示装置または高精細化された表示装置で、良好な表示品位を実現できる。 The electronic device of the present embodiment has a display system of one aspect of the present invention. As a result, the display unit of the electronic device can display a high-quality image. Specifically, a large display device or a high-definition display device can realize good display quality.
　本実施の形態の電子機器の表示部には、例えばフルハイビジョン、２Ｋ、４Ｋ、８Ｋ、１６Ｋ、またはそれ以上の解像度を有する映像を表示させることができる。また、表示部の画面サイズは、対角２０インチ以上、対角３０インチ以上、対角５０インチ以上、対角６０インチ以上、または対角７０インチ以上とすることができる。 The display unit of the electronic device of the present embodiment can display, for example, a full high-definition image having a resolution of 2K, 4K, 8K, 16K, or higher. The screen size of the display unit can be 20 inches or more diagonally, 30 inches or more diagonally, 50 inches or more diagonally, 60 inches or more diagonally, or 70 inches or more diagonally.
　本発明の一態様の表示システムを用いることができる電子機器としては、例えば、テレビジョン装置、デスクトップ型もしくはノート型のパーソナルコンピュータ、コンピュータ用などのモニタ、デジタルサイネージ（Ｄｉｇｉｔａｌ　Ｓｉｇｎａｇｅ：電子看板）、パチンコ機などの大型ゲーム機などの比較的大きな画面を備える電子機器の他、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、などが挙げられる。また、本発明の一態様の表示システムは、携帯型の電子機器、装着型の電子機器（ウェアラブル機器）、ＶＲ（Ｖｉｒｔｕａｌ　Ｒｅａｌｉｔｙ）機器、ＡＲ（Ａｕｇｍｅｎｔｅｄ　Ｒｅａｌｉｔｙ）機器などにも好適に用いることができる。 Examples of electronic devices that can use the display system of one aspect of the present invention include television devices, desktop or notebook personal computers, monitors for computers, digital signage (electronic signage), and pachinko. In addition to electronic devices with relatively large screens such as large game machines such as machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, mobile information terminals, sound reproduction devices, etc. can be mentioned. .. Further, the display system according to one aspect of the present invention can be suitably used for a portable electronic device, a wearable electronic device (wearable device), a VR (Virtual Reality) device, an AR (Augmented Reality) device, and the like. ..
　本発明の一態様の電子機器は、二次電池を有していてもよく、非接触電力伝送を用いて、二次電池を充電することができると好ましい。 The electronic device of one aspect of the present invention may have a secondary battery, and it is preferable that the secondary battery can be charged by using non-contact power transmission.
　二次電池としては、例えば、ゲル状電解質を用いるリチウムポリマー電池（リチウムイオンポリマー電池）等のリチウムイオン二次電池、ニッケル水素電池、ニカド電池、有機ラジカル電池、鉛蓄電池、空気二次電池、ニッケル亜鉛電池、銀亜鉛電池などが挙げられる。 Examples of the secondary battery include a lithium ion secondary battery such as a lithium polymer battery (lithium ion polymer battery) using a gel-like electrolyte, a nickel hydrogen battery, a nicad battery, an organic radical battery, a lead storage battery, an air secondary battery, and nickel. Examples include zinc batteries and silver-zinc batteries.
　本発明の一態様の電子機器は、アンテナを有していてもよい。アンテナで信号を受信することで、表示部で映像または情報等の表示を行うことができる。また、電子機器がアンテナ及び二次電池を有する場合、アンテナを、非接触電力伝送に用いてもよい。 The electronic device of one aspect of the present invention may have an antenna. By receiving the signal with the antenna, the display unit can display video or information. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.
　本発明の一態様の電子機器は、センサ（力、変位、位置、速度、加速度、角速度、回転数、距離、光、液、磁気、温度、化学物質、音声、時間、硬度、電場、電流、電圧、電力、放射線、流量、湿度、傾度、振動、においまたは赤外線を検知、検出、または測定する機能を含むもの）を有していてもよい。 The electronic device of one aspect of the present invention includes sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It may have the ability to detect, detect, or measure voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).
　本発明の一態様の電子機器は、様々な機能を有することができる。例えば、様々な情報（静止画、動画、テキスト画像など）を表示部に表示する機能、タッチパネル機能、カレンダー、日付または時刻などを表示する機能、様々なソフトウェア（プログラム）を実行する機能、無線通信機能、記録媒体に記録されているプログラムまたはデータを読み出す機能等を有することができる。 The electronic device of one aspect of the present invention can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function to display a date or time, a function to execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, and the like.
　さらに、複数の表示部を有する電子機器においては、一つの表示部を主として画像情報を表示し、別の一つの表示部を主として文字情報を表示する機能、または複数の表示部に視差を考慮した画像を表示することで立体的な画像を表示する機能等を有することができる。さらに、受像部を有する電子機器においては、静止画または動画を撮影する機能、撮影した画像を自動または手動で補正する機能、撮影した画像を記録媒体（外部または電子機器に内蔵）に保存する機能、撮影した画像を表示部に表示する機能等を有することができる。なお、本発明の一態様の電子機器が有する機能はこれらに限定されず、様々な機能を有することができる。 Further, in an electronic device having a plurality of display units, a function of mainly displaying image information on one display unit and mainly displaying character information on another display unit, or parallax is considered on the plurality of display units. By displaying an image, it is possible to have a function of displaying a three-dimensional image or the like. Further, in an electronic device having an image receiving unit, a function of shooting a still image or a moving image, a function of automatically or manually correcting the shot image, and a function of saving the shot image in a recording medium (external or built in the electronic device). , It is possible to have a function of displaying the captured image on the display unit and the like. The functions of the electronic device of one aspect of the present invention are not limited to these, and can have various functions.
　図２４Ａに、テレビジョン装置１８１０を示す。テレビジョン装置１８１０は、表示部１８１１、筐体１８１２、スピーカ１８１３等を有する。さらに、ＬＥＤランプ、操作キー（電源スイッチ、または操作スイッチを含む）、接続端子、各種センサ、マイクロフォン等を有することができる。 FIG. 24A shows the television device 1810. The television device 1810 has a display unit 1811, a housing 1812, a speaker 1813, and the like. Further, it may have an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.
　テレビジョン装置１８１０は、リモコン操作機１８１４により、操作することができる。 The television device 1810 can be operated by the remote controller 1814.
　テレビジョン装置１８１０が受信できる放送電波としては、地上波、または衛星から送信される電波などが挙げられる。また放送電波として、アナログ放送、デジタル放送などがあり、また映像及び音声、または音声のみの放送などがある。例えばＵＨＦ帯（約３００ＭＨｚ~３ＧＨｚ）またはＶＨＦ帯（３０ＭＨｚ~３００ＭＨｚ）のうちの特定の周波数帯域で送信される放送電波を受信することができる。また例えば、複数の周波数帯域で受信した複数のデータを用いることで、転送レートを高くすることができ、より多くの情報を得ることができる。これによりフルハイビジョンを超える解像度を有する映像を、表示部１８１１に表示させることができる。例えば、４Ｋ、８Ｋ、１６Ｋ、またはそれ以上の解像度を有する映像を表示させることができる。 Examples of broadcast radio waves that can be received by the television device 1810 include terrestrial waves and radio waves transmitted from satellites. Further, as broadcast radio waves, there are analog broadcasting, digital broadcasting, etc., and there are also video and audio broadcasting, or audio-only broadcasting. For example, it is possible to receive broadcast radio waves transmitted in a specific frequency band within the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz). Further, for example, by using a plurality of data received in a plurality of frequency bands, the transfer rate can be increased and more information can be obtained. As a result, an image having a resolution exceeding full high-definition can be displayed on the display unit 1811. For example, it is possible to display an image having a resolution of 4K, 8K, 16K, or higher.
　また、インターネット、ＬＡＮ（Ｌｏｃａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）、またはＷｉ−Ｆｉ（登録商標）などのコンピュータネットワークを介したデータ伝送技術により送信された放送のデータを用いて、表示部１８１１に表示する画像を生成する構成としてもよい。このとき、テレビジョン装置１８１０にチューナーを有さなくてもよい。 In addition, an image to be displayed on the display unit 1811 is generated using broadcast data transmitted by a data transmission technology via a computer network such as the Internet, LAN (Local Area Network), or Wi-Fi (registered trademark). It may be configured. At this time, the television device 1810 does not have to have a tuner.
　図２４Ｂは円柱状の柱１８２２に取り付けられたデジタルサイネージ１８２０を示している。デジタルサイネージ１８２０は、表示部１８２１を有する。 FIG. 24B shows a digital signage 1820 attached to a columnar pillar 1822. The digital signage 1820 has a display unit 1821.
　表示部１８２１が広いほど、一度に提供できる情報量を増やすことができる。また、表示部１８２１が広いほど、人の目につきやすく、例えば、広告の宣伝効果を高めることができる。 The wider the display unit 1821, the more information can be provided at one time. Further, the wider the display unit 1821 is, the easier it is to be noticed by people, and for example, the advertising effect of the advertisement can be enhanced.
　表示部１８２１にタッチパネルを適用することで、表示部１８２１に静止画または動画を表示するだけでなく、使用者が直感的に操作することができ、好ましい。また、路線情報もしくは交通情報などの情報を提供するための用途に用いる場合には、直感的な操作によりユーザビリティを高めることができる。 By applying the touch panel to the display unit 1821, not only a still image or a moving image can be displayed on the display unit 1821, but also the user can intuitively operate the display unit 1821, which is preferable. In addition, when used for the purpose of providing information such as route information or traffic information, usability can be improved by intuitive operation.
　図２４Ｃはノート型のパーソナルコンピュータ１８３０を示している。パーソナルコンピュータ１８３０は、表示部１８３１、筐体１８３２、タッチパッド１８３３、接続ポート１８３４等を有する。 FIG. 24C shows a notebook personal computer 1830. The personal computer 1830 has a display unit 1831, a housing 1832, a touch pad 1833, a connection port 1834, and the like.
　タッチパッド１８３３は、ポインティングデバイス、またはペンタブレット等の入力手段として機能し、指またはスタイラス等で操作することができる。 The touch pad 1833 functions as an input means for a pointing device, a pen tablet, or the like, and can be operated with a finger, a stylus, or the like.
　また、タッチパッド１８３３には表示素子が組み込まれている。図２４Ｃに示すように、タッチパッド１８３３の表面に入力キー１８３５を表示することで、タッチパッド１８３３をキーボードとして使用することができる。このとき、入力キー１８３５に触れた際に、振動により触感を実現するため、振動モジュールがタッチパッド１８３３に組み込まれていてもよい。 In addition, the touch pad 1833 has a built-in display element. As shown in FIG. 24C, the touchpad 1833 can be used as a keyboard by displaying the input key 1835 on the surface of the touchpad 1833. At this time, a vibration module may be incorporated in the touch pad 1833 in order to realize a tactile sensation by vibration when the input key 1835 is touched.
　図２４Ｄに携帯情報端末の一例を示す。図２４Ｄに示す携帯情報端末１８４０は、筐体１８４１、表示部１８４２、操作ボタン１８４３、外部接続ポート１８４４、スピーカ１８４５、マイク１８４６、カメラ１８４７等を有する。 FIG. 24D shows an example of a mobile information terminal. The portable information terminal 1840 shown in FIG. 24D has a housing 1841, a display unit 1842, an operation button 1843, an external connection port 1844, a speaker 1845, a microphone 1846, a camera 1847, and the like.
　携帯情報端末１８４０は、表示部１８４２にタッチセンサを備える。電話を掛ける、或いは文字を入力するなどのあらゆる操作は、指またはスタイラスなどで表示部１８４２に触れることで行うことができる。 The mobile information terminal 1840 is provided with a touch sensor on the display unit 1842. All operations such as making a phone call or entering characters can be performed by touching the display unit 1842 with a finger or a stylus.
　また、操作ボタン１８４３の操作により、電源のＯＮ、ＯＦＦ動作、または、表示部１８４２に表示される画像の種類を切り替えることができる。例えば、メール作成画面から、メインメニュー画面に切り替えることができる。 Further, by operating the operation button 1843, the power ON / OFF operation or the type of the image displayed on the display unit 1842 can be switched. For example, you can switch from the mail composition screen to the main menu screen.
　また、携帯情報端末１８４０の内部に、ジャイロセンサまたは加速度センサ等の検出装置を設けることで、携帯情報端末１８４０の向き（縦か横か）を判断して、表示部１８４２の画面表示の向きを自動的に切り替えるようにすることができる。また、画面表示の向きの切り替えは、表示部１８４２を触れること、操作ボタン１８４３の操作、またはマイク１８４６を用いた音声入力等により行うこともできる。 Further, by providing a detection device such as a gyro sensor or an acceleration sensor inside the mobile information terminal 1840, the orientation (vertical or horizontal) of the mobile information terminal 1840 is determined, and the orientation of the screen display of the display unit 1842 is determined. It can be switched automatically. Further, the orientation of the screen display can be switched by touching the display unit 1842, operating the operation button 1843, voice input using the microphone 1846, or the like.
　携帯情報端末１８４０は、例えば、電話機、手帳または情報閲覧装置等から選ばれた一つまたは複数の機能を有する。具体的には、スマートフォンとして用いることができる。携帯情報端末１８４０は、例えば、移動電話、電子メール、文章閲覧及び作成、音楽再生、動画再生、インターネット通信、ゲームなどの種々のアプリケーションを実行することができる。 The mobile information terminal 1840 has one or more functions selected from, for example, a telephone, a notebook, an information browsing device, and the like. Specifically, it can be used as a smartphone. The personal digital assistant 1840 can execute various applications such as mobile phone, e-mail, text viewing and creation, music playback, video playback, Internet communication, and games.
　図２４Ｅ、図２４Ｆに、携帯情報端末１８５０を示す。携帯情報端末１８５０は、筐体１８５１、筐体１８５２、表示部１８５３、表示部１８５４、及びヒンジ部１８５５等を有する。 24E and 24F show the mobile information terminal 1850. The mobile information terminal 1850 has a housing 1851, a housing 1852, a display unit 1853, a display unit 1854, a hinge unit 1855, and the like.
　筐体１８５１と筐体１８５２は、ヒンジ部１８５５で連結されている。携帯情報端末１８５０は、図２４Ｅに示すように折り畳んだ状態から、図２４Ｆに示すように筐体１８５１と筐体１８５２を開くことができる。 The housing 1851 and the housing 1852 are connected by a hinge portion 1855. The mobile information terminal 1850 can open the housing 1851 and the housing 1852 as shown in FIG. 24F from the folded state as shown in FIG. 24E.
　例えば表示部１８５３及び表示部１８５４に、文書情報を表示することが可能であり、電子書籍端末としても用いることができる。また、表示部１８５３及び表示部１８５４に静止画像または動画像を表示することもできる。 For example, document information can be displayed on the display unit 1853 and the display unit 1854, and can also be used as an electronic book terminal. Further, a still image or a moving image can be displayed on the display unit 1853 and the display unit 1854.
　このように、携帯情報端末１８５０は、持ち運ぶ際には折り畳んだ状態にできるため、汎用性に優れる。 In this way, the mobile information terminal 1850 is excellent in versatility because it can be folded when it is carried.
　なお、筐体１８５１及び筐体１８５２には、電源ボタン、操作ボタン、外部接続ポート、スピーカ、マイク等を有していてもよい。 The housing 1851 and the housing 1852 may have a power button, an operation button, an external connection port, a speaker, a microphone, and the like.
　本実施の形態は、他の実施の形態と適宜組み合わせることができる。 This embodiment can be appropriately combined with other embodiments.
１０：画素、１０ｄ：画素、１０ＥＬ：画素、１０ＬＣ：画素、１２：走査線駆動回路、１３：信号線駆動回路、１５：回路、１６：配線、４１：回路、４１ＥＬ：回路、４１ＬＣ：回路、５１：曲線、５２：曲線、１００：容量素子、１００Ａ：表示システム、１００Ｂ：表示システム、１１０：導電体、１１５ａ：絶縁体、１１５ｂ：絶縁体、１２０：導電体、１２０ａ：導電体、１２０ｂ：導電体、１３０：絶縁体、１５１：制御部、１５２：記憶部、１５３：処理部、１５４：入出力部、１５５：通信部、１５６：表示部、１５７：バスライン、１５９：ニューラルネットワーク、１５９ａ：ニューラルネットワーク、１５９ｂ：ニューラルネットワーク、１６２：ＦＰＣ、１７０：発光素子、１７１：画素電極、１７２：ＥＬ層、１７３：共通電極、１７４：接着層、１８０：液晶素子、１８１：画素電極、１８２：共通電極、１８３：液晶層 10: pixel, 10d: pixel, 10EL: pixel, 10LC: pixel, 12: scanning line drive circuit, 13: signal line drive circuit, 15: circuit, 16: wiring, 41: circuit, 41EL: circuit, 41LC: circuit, 51: Curve, 52: Curve, 100: Capacitive element, 100A: Display system, 100B: Display system, 110: Conductor, 115a: Insulator, 115b: Insulator, 120: Conductor, 120a: Conductor, 120b: Conductor, 130: Insulator, 151: Control unit, 152: Storage unit, 153: Processing unit, 154: Input / output unit, 155: Communication unit, 156: Display unit, 157: Bus line, 159: Neural network, 159a : Neural network, 159b: Neural network, 162: FPC, 170: Light emitting element, 171: pixel electrode, 172: EL layer, 173: Common electrode, 174: Adhesive layer, 180: Liquid crystal element, 181: Pixel electrode, 182: Common electrode, 183: Liquid crystal layer

Claims (10)

  1. 　処理部、表示部、及び記憶部を有し、
    　前記記憶部は、補正データを有し、
    　前記処理部には、第１の画像信号及び前記補正データが供給され、
    　前記処理部は、前記第１の画像信号を用いて、第２の画像信号を生成する機能を有し、
    　前記処理部は、前記補正データに基づいた補正信号を生成する機能を有し、
    　前記表示部は、画素を有し、
    　前記画素は、表示素子及び記憶回路を有し、
    　前記画素には、前記第２の画像信号及び前記補正信号が供給され、
    　前記記憶回路は、前記補正信号を保持する機能を有し、
    　前記記憶部は、強誘電体層を有する容量素子と、前記容量素子と電気的に接続するトランジスタと、を有する、
    　表示システム。     It has a processing unit, a display unit, and a storage unit.
    The storage unit has correction data and has correction data.
    The first image signal and the correction data are supplied to the processing unit.
    The processing unit has a function of generating a second image signal by using the first image signal.
    The processing unit has a function of generating a correction signal based on the correction data.
    The display unit has pixels and
    The pixel has a display element and a storage circuit.
    The second image signal and the correction signal are supplied to the pixels.
    The storage circuit has a function of holding the correction signal and has a function of holding the correction signal.
    The storage unit includes a capacitive element having a ferroelectric layer and a transistor electrically connected to the capacitive element.
    Display system.
  2. 　処理部、表示部、及び記憶部を有し、
    　前記記憶部は、補正データを有し、
    　前記処理部には、第１の画像信号及び前記補正データが供給され、
    　前記処理部は、前記第１の画像信号を用いて、第２の画像信号を生成する機能を有し、
    　前記処理部は、前記第１の画像信号及び前記補正データを用いて、補正信号を生成する機能を有し、
    　前記表示部は、画素を有し、
    　前記画素は、表示素子及び記憶回路を有し、
    　前記画素には、前記第２の画像信号及び前記補正信号が供給され、
    　前記記憶回路は、前記補正信号を保持する機能を有し、
    　前記記憶部は、強誘電体層を有する容量素子と、前記容量素子と電気的に接続するトランジスタと、を有する、
    　表示システム。     It has a processing unit, a display unit, and a storage unit.
    The storage unit has correction data and has correction data.
    The first image signal and the correction data are supplied to the processing unit.
    The processing unit has a function of generating a second image signal by using the first image signal.
    The processing unit has a function of generating a correction signal by using the first image signal and the correction data.
    The display unit has pixels and
    The pixel has a display element and a storage circuit.
    The second image signal and the correction signal are supplied to the pixels.
    The storage circuit has a function of holding the correction signal and has a function of holding the correction signal.
    The storage unit includes a capacitive element having a ferroelectric layer and a transistor electrically connected to the capacitive element.
    Display system.
  3. 　処理部、表示部、及び記憶部を有し、
    　前記記憶部は、補正データを有し、
    　前記表示部は、第１の回路及び画素を有し、
    　前記第１の回路は、第１の信号を生成する機能を有し、
    　前記処理部には、第１の画像信号、前記第１の信号及び前記補正データが供給され、
    　前記処理部は、前記第１の画像信号を用いて、第２の画像信号を生成する機能を有し、
    　前記処理部は、前記第１の信号及び前記補正データを用いて、補正信号を生成する機能を有し、
    　前記画素は、表示素子及び記憶回路を有し、
    　前記画素には、前記第２の画像信号及び前記補正信号が供給され、
    　前記記憶回路は、前記補正信号を保持する機能を有し、
    　前記記憶部は、強誘電体層を有する容量素子と、前記容量素子と電気的に接続するトランジスタと、を有する、
    　表示システム。     It has a processing unit, a display unit, and a storage unit.
    The storage unit has correction data and has correction data.
    The display unit has a first circuit and pixels.
    The first circuit has a function of generating a first signal, and has a function of generating the first signal.
    The first image signal, the first signal, and the correction data are supplied to the processing unit.
    The processing unit has a function of generating a second image signal by using the first image signal.
    The processing unit has a function of generating a correction signal by using the first signal and the correction data.
    The pixel has a display element and a storage circuit.
    The second image signal and the correction signal are supplied to the pixels.
    The storage circuit has a function of holding the correction signal and has a function of holding the correction signal.
    The storage unit includes a capacitive element having a ferroelectric layer and a transistor electrically connected to the capacitive element.
    Display system.
  4. 　請求項１乃至請求項３のいずれか一において、
    　前記処理部は、ニューラルネットワークを用いて、前記第２の画像信号及び前記補正信号のうち一方または双方を生成する、
    　表示システム。     In any one of claims 1 to 3,
    The processing unit uses a neural network to generate one or both of the second image signal and the correction signal.
    Display system.
  5. 　請求項１乃至請求項４のいずれか一において、
    　前記処理部は、ニューラルネットワーク回路を有する、
    　表示システム。     In any one of claims 1 to 4,
    The processing unit has a neural network circuit.
    Display system.
  6. 　請求項１乃至請求項５のいずれか一において、
    　前記強誘電体層は、ハフニウム及びジルコニウムの一方または双方を含む酸化物を有する、
    　表示システム。     In any one of claims 1 to 5,
    The ferroelectric layer has an oxide containing one or both of hafnium and zirconium.
    Display system.
  7. 　請求項１乃至請求項６のいずれか一において、
    　前記強誘電体層に含まれる、水素、炭化水素、及び炭素の少なくとも一つの濃度は、ＳＩＭＳ分析において、５×１０２０ａｔｏｍｓ／ｃｍ３以下である、
    　表示システム。     In any one of claims 1 to 6,
    The concentration of at least one of hydrogen, hydrocarbon, and carbon contained in the ferroelectric layer is 5 × 10 20 atoms / cm 3 or less in SIMS analysis.
    Display system.
  8. 　請求項１乃至請求項６のいずれか一において、
    　前記強誘電体層に含まれる、水素、炭化水素、及び炭素の少なくとも一つの濃度は、ＳＩＭＳ分析において、１×１０２０ａｔｏｍｓ／ｃｍ３以下である、
    　表示システム。     In any one of claims 1 to 6,
    The concentration of at least one of hydrogen, hydrocarbon, and carbon contained in the ferroelectric layer is 1 × 10 20 atoms / cm 3 or less in SIMS analysis.
    Display system.
  9. 　請求項１乃至８のいずれか一において、
    　前記トランジスタは、チャネル形成領域にシリコンを有する、
    　表示システム。     In any one of claims 1 to 8,
    The transistor has silicon in the channel forming region.
    Display system.
  10. 　請求項１乃至８のいずれか一において、
    　前記トランジスタは、チャネル形成領域に酸化物半導体を有する、
    　表示システム。     In any one of claims 1 to 8,
    The transistor has an oxide semiconductor in the channel forming region.
    Display system.
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