WO2022052479A1 - 一种功耗调控方法、装置、设备及可读存储介质 - Google Patents

一种功耗调控方法、装置、设备及可读存储介质 Download PDF

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WO2022052479A1
WO2022052479A1 PCT/CN2021/089912 CN2021089912W WO2022052479A1 WO 2022052479 A1 WO2022052479 A1 WO 2022052479A1 CN 2021089912 W CN2021089912 W CN 2021089912W WO 2022052479 A1 WO2022052479 A1 WO 2022052479A1
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power consumption
computing
chip
value
node
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PCT/CN2021/089912
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English (en)
French (fr)
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林楷智
杨洋
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苏州浪潮智能科技有限公司
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Priority to US18/016,587 priority Critical patent/US11822412B2/en
Publication of WO2022052479A1 publication Critical patent/WO2022052479A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • G06F11/3062—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations where the monitored property is the power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of computer technologies, and in particular, to a power consumption regulation method, apparatus, device, and readable storage medium.
  • power consumption regulation of traditional rack servers can be performed in an in-band manner of an OS (Operating System, operating system).
  • OS Operating System, operating system
  • the power consumption control of traditional rack servers is mainly to control the memory, CPU (Central Processing Unit, central processing unit), fans, etc. in the server, because the total power consumption of these components accounts for a large proportion of the power consumption of the entire server. Most of the time, therefore regulating the power consumption of these components can regulate the power consumption of the server.
  • the power consumption of the computing chip accounts for a larger part of the power consumption of the entire AI computing node, and the power consumption of memory, CPU, fans, etc. accounts for a smaller part of the power consumption of the entire AI computing node.
  • the power consumption of the memory, CPU, and fans in the AI computing node can be adjusted, and the power consumption of the AI computing node cannot be effectively controlled. It can be seen that the existing method of regulating server power consumption is not suitable for regulating AI computing nodes.
  • the purpose of the present application is to provide a power consumption control method, apparatus, device and readable storage medium to control the power consumption of an AI computing node. Its specific plan is as follows:
  • the present application provides a power consumption control method, including:
  • the node power consumption value of the AI computing node is greater than the warning power consumption value, use the BMC to obtain the chip power consumption value of each computing chip in the AI computing node;
  • the power consumption control strategy corresponding to the grouping result, and adjust the power consumption limit value of each computing chip according to the power consumption control strategy, so that all power consumption limits are The sum of the values is in the target range; the warning power consumption value is less than the cap power consumption value; the power consumption regulation strategy is preset based on the target range, and the target range is used to regulate the power consumption in the AI computing node.
  • the energy efficiency value of each computing chip is used to regulate the power consumption in the AI computing node.
  • the method before obtaining the chip power consumption value of each computing chip in the AI computing node by using the BMC, the method further includes:
  • the BMC is used to monitor the power consumption value of the node in real time, and if the power consumption value of the node is greater than the warning power consumption value, the power consumption regulation function is enabled.
  • using the BMC to monitor the power consumption value of the node in real time includes:
  • the BMC is controlled to monitor the power consumption value of the node through the PMBUS bus.
  • the obtaining the chip power consumption value of each computing chip in the AI computing node by using the BMC includes:
  • the grouping of each computing chip according to the chip power consumption value of each computing chip to obtain a grouping result includes:
  • the optimal power consumption value in the target range determine the buffer space with the optimal power consumption value as the median value, and divide the computing chips that do not belong to the buffer space and are greater than the optimal power consumption value to the first One group, dividing the computing chips that do not belong to the buffer space and are not greater than the optimal power consumption value to the second group;
  • the process of determining the target range includes:
  • the energy efficiency value corresponding to the ratio greater than the preset threshold value is added to the energy efficiency regulation interval, and the power consumption value of each chip corresponding to the energy efficiency regulation interval is determined as the target range.
  • the computing chip is GPU, NPU, FPGA or ASIC.
  • the present application provides a power consumption control device, including:
  • an obtaining module configured to obtain the chip power consumption value of each computing chip in the AI computing node by using the BMC if the node power consumption value of the AI computing node is greater than the warning power consumption value;
  • the grouping module is used to group each computing chip according to the chip power consumption value of each computing chip, and obtain the grouping result;
  • a control module configured to query the power consumption control strategy corresponding to the grouping result if the node power consumption value is greater than the capped power consumption value, and adjust the power consumption limit value of each computing chip according to the power consumption control strategy, so as to The sum of all power consumption limit values is within a target range; the warning power consumption value is less than the capped power consumption value; the power consumption regulation strategy is preset based on the target range, and the target range is used to regulate the The energy efficiency value of each computing chip in the AI computing node.
  • the present application provides a power consumption control device, including:
  • the processor is configured to execute the computer program to implement the power consumption control method disclosed above.
  • the present application provides a readable storage medium for storing a computer program, wherein when the computer program is executed by a processor, the power consumption control method disclosed above is implemented.
  • the present application provides a power consumption control method, including: if the node power consumption value of the AI computing node is greater than the warning power consumption value, using the BMC to obtain the chip power of each computing chip in the AI computing node.
  • each computing chip is grouped to obtain a grouping result; if the node power consumption value is greater than the capped power consumption value, the power consumption control strategy corresponding to the grouping result is queried, and The power consumption limit value of each computing chip is adjusted according to the power consumption control strategy, so that the sum of all power consumption limit values is within the target range; the warning power consumption value is less than the capped power consumption value; the power consumption control strategy
  • the target range is preset based on the target range, and the target range is used to regulate the energy efficiency value of each computing chip in the AI computing node.
  • the BMC when the node power consumption value of the AI computing node is greater than the warning power consumption value, the BMC is used to obtain the chip power consumption value of each computing chip in the AI computing node; and then when the node power consumption value is greater than the capped power consumption value, Group each computing chip according to the chip power consumption value of each computing chip, and obtain the grouping result; finally query the power consumption control strategy corresponding to the grouping result, and adjust the power consumption limit value of each computing chip according to the power consumption control strategy, so that all The sum of the power consumption limit values is within the target range; the power consumption regulation strategy is preset based on the target range, and the target range is used to regulate the energy efficiency value of each computing chip in the AI computing node, so each calculation is adjusted according to the power consumption regulation strategy
  • the power consumption limit value of the chip not only regulates the power consumption of each computing chip, but also effectively regulates the energy efficiency value of each computing chip, thereby ensuring the energy efficiency of AI computing nodes.
  • a power consumption control device, device and readable storage medium provided by the present application also have the above technical effects.
  • FIG. 1 is a flowchart of a power consumption control method disclosed in the present application
  • FIG. 2 is a schematic structural diagram of an AI computing node disclosed in the application.
  • FIG. 3 is a schematic diagram of the relationship between a warning power consumption value, a capped power consumption value and a node maximum power consumption disclosed in the present application;
  • FIG. 5 is a schematic diagram of the relationship between energy efficiency and power consumption disclosed in the present application.
  • FIG. 6 is a flowchart of another power consumption control method disclosed in the present application.
  • FIG. 7 is a schematic diagram of a power consumption control device disclosed in the present application.
  • FIG. 8 is a schematic diagram of a power consumption control device disclosed in the present application.
  • the present application provides a power consumption control scheme, which can control the power consumption of an AI computing node and ensure the energy efficiency of the AI computing node.
  • an embodiment of the present application discloses a first power consumption control method, including:
  • an AI computing node is a device that runs a certain machine learning algorithm, which may be a device such as a server.
  • An AI computing node generally includes multiple computing chips, and these computing chips are the main components of the power consumption of the AI computing node.
  • other power-consuming components of AI computing nodes are memory, CPU, fans, etc.
  • the structure of the AI computing node can be seen in Figure 2.
  • DMI Direct Media Interface
  • UPI User Plantra Path Interconnect
  • the I2C routing chip is used to select the link where any GPU (Graphics Processing Unit, graphics processor) is located.
  • the method before using the BMC (Baseboard Management Controller, baseboard management controller) to obtain the chip power consumption value of each computing chip in the AI computing node, the method further includes: using the BMC to monitor the power consumption value of the node in real time. If the power consumption value is greater than the warning power consumption value, the power consumption control function is enabled. At this time, the power consumption of each computing chip is monitored and collected; the warning power consumption value is less than the capped power consumption value.
  • using the BMC to monitor the power consumption value of the node in real time includes: controlling the BMC to monitor the power consumption value of the node through the PMBUS bus.
  • PMBUS Power Management BUS
  • the BMC obtains the power consumption value out of band, which can improve the efficiency.
  • the node power consumption value is the actual total power consumption value of the AI computing node.
  • the warning power consumption value and the capped power consumption value are both preset values. The relationship between these values can be seen in Figure 3.
  • the maximum power consumption of the node is the total power consumption value when all components in the AI computing node are running at full capacity, so it is the maximum value.
  • using the BMC to obtain the chip power consumption value of each computing chip in the AI computing node includes: using the BMC to read the current value of each computing chip in the AI computing node to obtain the corresponding chip power consumption value.
  • the current value of each computing chip is the current value flowing through the current sensor corresponding to each computing chip, and the current value can be converted into a corresponding chip power consumption value.
  • Using this method to obtain the power consumption value of the chip can avoid frequent use of the I2C bus, and will not affect the energy efficiency of the computing chip.
  • the I2C (Inter-Integrated Circuit) bus is a two-wire serial bus.
  • S102 Group each computing chip according to the chip power consumption value of each computing chip, and obtain a grouping result.
  • the grouping method and the number of groups obtained by grouping can be flexibly determined according to the actual situation.
  • the following describes three grouping methods, the first one: the user submits grouping instructions based on the human-computer interaction interface or inputs grouping instructions (such as IPMI instructions) based on the command line window, and AI computing nodes can be grouped according to the grouping instructions.
  • IPMI Intelligent Platform Management Interface
  • the third type (see Figure 4): set up a buffer room, divide the computing chips on the left side of the buffer room into the first group (high priority group), and divide the computing chips on the right side of the buffer room into the second group (low priority group) Priority group), and then judge whether the computing chips located in the buffer room are more similar to the first group or the second group, and divide the computing chips located in the buffer room according to the judgment result to avoid simple cutting and misunderstanding.
  • GPUs of the same workload are grouped into different groups.
  • the computing chip in Figure 4 is a GPU (Graphics Processing Unit), the circle represents that the GPU is divided into G0 (the first group), and the five-pointed star represents that the GPU is divided into G1 (the second group).
  • a corresponding regulation strategy can be determined according to the grouping result, so that the power consumption of each computing chip is regulated and the energy efficiency of each computing chip is guaranteed.
  • grouping each computing chip according to the chip power consumption value of each computing chip to obtain a grouping result includes: grouping each computing chip according to the obtained grouping instruction to obtain a grouping result; or obtaining a target
  • the optimal power consumption value in the range the computing chips greater than the optimal power consumption value are divided into the first group, the computing chips not greater than the optimal power consumption value are divided into the second group, the first group and the second group are divided As the grouping result; or obtain the optimal power consumption value in the target range, determine the buffer space with the optimal power consumption value as the median value, and divide the computing chips that do not belong to the buffer space and are larger than the optimal power consumption value to the first group, Divide the computing chips that do not belong to the buffer room and are not greater than the optimal power consumption value into the second group; calculate the first power consumption gradient corresponding to the first group, the second power consumption gradient corresponding to the second group, and those belonging to the buffer room.
  • the first power consumption gradient corresponding to the first group may be a sequence formed by the difference between the power consumption values of adjacent chips within a preset time period (such as 5 seconds) of any computing chip in the first group. Of course, Others are also possible.
  • the second power consumption gradient corresponding to the second group may be a sequence formed by the difference between the power consumption values of adjacent chips within a preset time period of any computing chip in the second group, and of course, may also be other.
  • the chip power consumption gradient is a sequence formed by the difference between the power consumption values of adjacent chips within a preset time period of the computing chips located in the buffer space.
  • the BMC polls the current sensor multiple times within a preset time period to obtain corresponding multiple chip power consumption values.
  • the corresponding chip power consumption gradient calculate the first similarity between any chip power consumption gradient and the first power consumption gradient, and the second similarity with the second power consumption gradient, if the first similarity is greater than the second similarity, then The computing chips corresponding to the chip power consumption gradient are added to the first group. If the first similarity is less than the second similarity, the computing chips corresponding to the chip power consumption gradient are added to the second group, and the first group and the second group are added. Steps as a result of grouping.
  • the first power consumption gradient corresponding to the first group, the second power consumption gradient corresponding to the second group, and the corresponding calculation chips of each computing chip in the buffer room can be directly calculated.
  • the power consumption regulation strategy is preset based on the target range, and the target range is used to regulate the energy efficiency value of each computing chip in the AI computing node. If the power consumption value of the node is greater than the capped power consumption value, enter the control part of the power consumption control function to adjust the power consumption limit value of each computing chip.
  • the process of determining the target range includes: using a performance benchmarking tool (such as SGEMM) to obtain each energy efficiency value of any computing chip in the AI computing node under different chip power consumption values; Calculate the ratio of each energy efficiency value to the TDP energy efficiency value; add the energy efficiency value corresponding to the ratio greater than the preset threshold value to the energy efficiency regulation interval, and determine the power consumption value of each chip corresponding to the energy efficiency regulation interval as the target range .
  • a performance benchmarking tool such as SGEMM
  • TDP Thermal Design Power
  • Thermal Design Power is the thermal design power consumption, which refers to the power consumption value when the chip is running at full capacity.
  • the energy efficiency value W of any computing chip under the chip power consumption value U the performance data measured under the chip power consumption value U/the chip power consumption value U.
  • the ratios A/X, B can be obtained.
  • /X, C/X, D/X these ratios can form a graph as shown in Figure 5.
  • the target range is: 0.6TDP to 1TDP. It can be seen from Figure 5 that the curve reaches the highest point at 0.8TDP, indicating that the chip has the highest energy efficiency value at 0.8TDP, so 0.8TDP is the optimal power consumption value in the target range.
  • the target range corresponding to the computing chip in the AI computing node can be pre-calculated.
  • the target range is the controllable range of power consumption corresponding to the computing chip. Within this range, its energy efficiency will also remain in a better state.
  • each computing chip in an AI computing node is exactly the same, so based on any one of the computing chips, the target range can be determined.
  • the target range is: 0.6TDP ⁇ 1TDP. Adjusting the power consumption of the computing chip within this range can keep the energy efficiency of the AI computing node in a better state.
  • the power consumption regulation goal is to reduce n ⁇ (TDP-Ppeak) based on the maximum power consumption of the AI computing node, where n is the number of computing chips in the AI computing node, and Ppeak (ie 0.8TDP) is The power consumption of the corresponding single computing chip when Alpha is the highest value.
  • the computing chip is GPU, NPU (Neural-network Processing Unit, embedded neural network processor), FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) ).
  • the BMC when the node power consumption value of the AI computing node is greater than the capped power consumption value, the BMC is used to obtain the chip power consumption value of each computing chip in the AI computing node; Each computing chip is grouped to obtain a grouping result; finally, the power consumption regulation strategy corresponding to the grouping result is queried, and the power consumption limit value of each computing chip is adjusted according to the power consumption regulation strategy, so that the sum of all power consumption limit values is within the target range;
  • the power consumption regulation strategy is preset based on the target range, and the target range is used to regulate the energy efficiency value of each computing chip in the AI computing node. Therefore, adjusting the power consumption limit value of each computing chip according to the power consumption regulation strategy not only regulates each computing chip
  • the power consumption of computing chips can also effectively regulate the energy efficiency value of each computing chip, thereby ensuring the energy efficiency of AI computing nodes.
  • the embodiment of the present application uses BMC to monitor the power consumption value of the node. If the power consumption value of the node is greater than the warning power consumption value, the power consumption control function is enabled, and then the grouping strategy is determined to perform grouping, and then the power consumption of the node is calculated. When the value is greater than the capped power consumption value, control is performed according to the high-priority group and low-priority group obtained after grouping, and the corresponding power consumption control strategy.
  • FIG. 6 illustrates three grouping strategies, for details, please refer to the related introduction of the above embodiment.
  • the power consumption control strategy is shown in Table 1.
  • the AI computing node includes a total of 8 computing chips from GPU0 to GPU7. Among them, ⁇ represents belonging to G0 or G1.
  • Table 2 The grouping results shown in Table 2 are: the number of GPUs located in G0 is 4, and the number of GPUs located in G1 is 4, and the corresponding control strategy can be found in Table 1: the power consumption of GPUs located in G0 is not limited, and the number of GPUs located in The GPU power consumption of G1 is limited to 60%*TDP.
  • the power consumption limit of the GPU located in G0 is 90%*TDP
  • the power consumption limit of the GPU located in G1 is 60% *TDP.
  • the power consumption limit of GPUs located in G0 and G2 is 80%*TDP.
  • the power supply capacity of existing cabinets is generally low, and the power consumption of AI computing nodes is relatively large. Therefore, it is necessary to reduce the power consumption of AI computing nodes to meet the requirements of the PDU (Power Distribution Unit) of the cabinet. socket) required.
  • Multiple AI computing nodes are placed on a cabinet.
  • the PDU of the cabinet is generally C13-C14 interface.
  • domestic safety regulations require that the maximum continuous current of the C13-C14 interface cannot exceed 10A, and the AI computing node consumes a lot of power and needs to use a high-power PSU (Power Supply Unit, 2200W or above). power supply), this specification requires a C19-C20 interface (16A). It is difficult to upgrade PDUs in large quantities.
  • This embodiment can reduce the power consumption of the AI computing node, and at the same time keep the AI computing node in a better running state, thereby improving its energy efficiency.
  • GPU power consumption is regulated within a certain range, which ensures the efficient operation of AI computing nodes.
  • a power consumption control device provided by an embodiment of the present application will be introduced below.
  • a power consumption control device described below and a power consumption control method described above can be referred to each other.
  • an embodiment of the present application discloses a power consumption control device, including:
  • the obtaining module 701 is configured to obtain the chip power consumption value of each computing chip in the AI computing node by using the BMC if the node power consumption value of the AI computing node is greater than the warning power consumption value;
  • a grouping module 702 configured to group each computing chip according to the chip power consumption value of each computing chip, and obtain a grouping result
  • the control module 703 is configured to query the power consumption control strategy corresponding to the grouping result if the power consumption value of the node is greater than the capped power consumption value, and adjust the power consumption limit value of each computing chip according to the power consumption control strategy, so that all power The sum of the power consumption limit values is in the target range; the warning power consumption value is less than the capped power consumption value; the power consumption regulation strategy is preset based on the target range, and the target range is used to regulate the energy efficiency value of each computing chip in the AI computing node .
  • it also includes:
  • the monitoring module is used to use the BMC to monitor the power consumption value of the node in real time. If the power consumption value of the node is greater than the warning power consumption value, the power consumption regulation function is enabled.
  • the monitoring module is specifically used for:
  • the acquisition module is specifically used for:
  • the grouping module includes:
  • a first grouping unit configured to group each computing chip according to the obtained grouping instruction to obtain a grouping result
  • the second grouping unit is used to obtain the optimal power consumption value in the target range, divide the computing chips larger than the optimal power consumption value into the first group, and divide the computing chips not larger than the optimal power consumption value into the second group , take the first group and the second group as the grouping result;
  • the third grouping unit is used to obtain the optimal power consumption value in the target range, determine the buffer space with the optimal power consumption value as the median value, and divide the computing chips that do not belong to the buffer space and are larger than the optimal power consumption value to the first group, divide the computing chips that do not belong to the buffer space and are not greater than the optimal power consumption value into the second group; calculate the first power consumption gradient corresponding to the first group, the second power consumption gradient corresponding to the second group, and those belonging to the buffer Calculate the chip power consumption gradient corresponding to each calculation chip in the interval; calculate the first similarity between any chip power consumption gradient and the first power consumption gradient, and the second similarity with the second power consumption gradient, if the first similarity If the first similarity is less than the second similarity, the computing chip corresponding to the chip power consumption gradient is added to the second group, and the The first group and the second group are grouped results.
  • the process of determining the target range includes:
  • the energy efficiency value corresponding to the ratio greater than the preset threshold value is added to the energy efficiency regulation interval, and the power consumption value of each chip corresponding to the energy efficiency regulation interval is determined as the target range.
  • the computing chip is a GPU, NPU, FPGA or ASIC.
  • this embodiment provides a power consumption control device, which can reduce the power consumption of the AI computing node, and at the same time, keep the AI computing node in a better running state and improve its energy efficiency.
  • the following describes a power consumption control device provided by an embodiment of the present application.
  • the power consumption control device described below and the power consumption control method and apparatus described above can be referred to each other.
  • an embodiment of the present application discloses a power consumption control device, including:
  • the processor 802 is configured to execute the computer program to implement the method disclosed in any of the foregoing embodiments.
  • a readable storage medium provided by an embodiment of the present application is introduced below.
  • a readable storage medium described below and a power consumption control method, apparatus, and device described above can be referred to each other.
  • a readable storage medium for storing a computer program wherein when the computer program is executed by a processor, the power consumption control method disclosed in the foregoing embodiments is implemented.
  • the power consumption control method disclosed in the foregoing embodiments is implemented.
  • references in this application to "first”, “second”, “third”, “fourth”, etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It is to be understood that data so used may be interchanged under appropriate circumstances so that the embodiments described herein can be practiced in sequences other than those illustrated or described herein.
  • the terms “comprising” and “having”, and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method or apparatus comprising a series of steps or elements is not necessarily limited to those steps or elements expressly listed , but may include other steps or elements not expressly listed or inherent to these processes, methods or apparatus.
  • a software module can be placed in random access memory (RAM), internal memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other in the technical field. in any other form of readable storage medium that is well known.
  • RAM random access memory
  • ROM read only memory
  • EEPROM electrically programmable ROM
  • erasable programmable ROM electrically erasable programmable ROM
  • registers hard disk, removable disk, CD-ROM, or any other in the technical field. in any other form of readable storage medium that is well known.

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Abstract

一种功耗调控方法、装置、设备及可读存储介质。本申请公开的方法包括：若AI计算节点的节点功耗值大于警戒功耗值，则利用BMC获取AI计算节点中的各个计算芯片的芯片功耗值；根据芯片功耗值对各个计算芯片进行分组；若节点功耗值大于封顶功耗值，则查询分组结果对应的功耗调控策略，按照功耗调控策略调整各个计算芯片的功耗限制值，以使所有功耗限制值之和处于目标范围；功耗调控策略基于目标范围设定，目标范围用于调控AI计算节点中的各个计算芯片的能效值，因此按照功耗调控策略调整功耗限制值能调控计算芯片的能效值，保障AI计算节点的能效。

Description

一种功耗调控方法、装置、设备及可读存储介质
本申请要求于2020年09月11日提交至中国专利局、申请号为202010956191.4、发明名称为“一种功耗调控方法、装置、设备及可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，特别涉及一种功耗调控方法、装置、设备及可读存储介质。
背景技术
目前，可以通过OS(Operating System，操作系统)带内的方式对传统机架式服务器进行功耗调控。其中，对传统机架式服务器进行功耗调控主要是对服务器中的内存、CPU(Central Processing Unit，中央处理器)、风扇等进行调控，因为这些部件的总功耗占整个服务器功耗的较大部分，因此调控这些部件的功耗就可以调控服务器的功耗。
在AI(Artificial Intelligence)计算节点中，计算芯片的功耗占整个AI计算节点功耗的较大部分，内存、CPU、风扇等的功耗占整个AI计算节点功耗的较小部分，因此对AI计算节点中的内存、CPU、风扇的功耗进行调整，无法有效调控AI计算节点的功耗。可见，现有的调控服务器功耗的方式不适用于调控AI计算节点。
因此，如何调控AI计算节点的功耗，是本领域技术人员需要解决的问题。
发明内容
有鉴于此，本申请的目的在于提供一种功耗调控方法、装置、设备及可读存储介质，以调控AI计算节点的功耗。其具体方案如下：
第一方面，本申请提供了一种功耗调控方法，包括：
若AI计算节点的节点功耗值大于警戒功耗值，则利用BMC获取所述AI计算节点中的各个计算芯片的芯片功耗值；
根据各个计算芯片的芯片功耗值对各个计算芯片进行分组，获得分组 结果；
若所述节点功耗值大于封顶功耗值，则查询所述分组结果对应的功耗调控策略，并按照所述功耗调控策略调整各个计算芯片的功耗限制值，以使所有功耗限制值之和处于目标范围；所述警戒功耗值小于所述封顶功耗值；所述功耗调控策略基于所述目标范围预先设定，所述目标范围用于调控所述AI计算节点中的各个计算芯片的能效值。
优选地，所述利用BMC获取所述AI计算节点中的各个计算芯片的芯片功耗值之前，还包括：
利用所述BMC实时监控所述节点功耗值，若所述节点功耗值大于所述警戒功耗值，则开启功耗调控功能。
优选地，所述利用所述BMC实时监控所述节点功耗值，包括：
控制所述BMC通过PMBUS总线监控所述节点功耗值。
优选地，所述利用BMC获取所述AI计算节点中的各个计算芯片的芯片功耗值，包括：
利用所述BMC读所述AI计算节点中的各个计算芯片的电流值，以获得相应芯片功耗值。
优选地，所述根据各个计算芯片的芯片功耗值对各个计算芯片进行分组，获得分组结果，包括：
按照获取到的分组指令对各个计算芯片进行分组，获得所述分组结果；
或
获取所述目标范围中的最优功耗值，将大于所述最优功耗值的计算芯片划分至第一组，将不大于所述最优功耗值的计算芯片划分至第二组，将所述第一组和所述第二组作为所述分组结果；
或
获取所述目标范围中的最优功耗值，以所述最优功耗值为中值确定缓冲区间，将不属于所述缓冲区间且大于所述最优功耗值的计算芯片划分至第一组，将不属于所述缓冲区间且不大于所述最优功耗值的计算芯片划分至第二组；
计算所述第一组对应的第一功耗梯度，所述第二组对应的第二功耗梯度，以及属于所述缓冲区间中的每个计算芯片对应的芯片功耗梯度；
计算任一个芯片功耗梯度与所述第一功耗梯度的第一相似度，与所述第二功耗梯度的第二相似度，若所述第一相似度大于所述第二相似度，则将所述芯片功耗梯度对应的计算芯片添加至所述第一组，若所述第一相似度小于所述第二相似度，则将所述芯片功耗梯度对应的计算芯片添加至所述第二组，将所述第一组和所述第二组作为所述分组结果。
优选地，所述目标范围的确定过程包括：
利用性能基准测试工具获取所述AI计算节点中的任一个计算芯片在不同芯片功耗值下的各个能效值；所述AI计算节点中的各个计算芯片完全相同；
计算各个能效值与TDP能效值的比值；
将大于预设阈值的比值对应的能效值添加至能效调控区间，将所述能效调控区间对应的各个芯片功耗值确定为所述目标范围。
优选地，所述计算芯片为GPU、NPU、FPGA或ASIC。
第二方面，本申请提供了一种功耗调控装置，包括：
获取模块，用于若AI计算节点的节点功耗值大于警戒功耗值，则利用BMC获取所述AI计算节点中的各个计算芯片的芯片功耗值；
分组模块，用于根据各个计算芯片的芯片功耗值对各个计算芯片进行分组，获得分组结果；
调控模块，用于若所述节点功耗值大于封顶功耗值，则查询所述分组结果对应的功耗调控策略，并按照所述功耗调控策略调整各个计算芯片的功耗限制值，以使所有功耗限制值之和处于目标范围；所述警戒功耗值小于所述封顶功耗值；所述功耗调控策略基于所述目标范围预先设定，所述目标范围用于调控所述AI计算节点中的各个计算芯片的能效值。
第三方面，本申请提供了一种功耗调控设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行所述计算机程序，以实现前述公开的功耗调控方法。
第四方面，本申请提供了一种可读存储介质，用于保存计算机程序，其中，所述计算机程序被处理器执行时实现前述公开的功耗调控方法。
通过以上方案可知，本申请提供了一种功耗调控方法，包括：若AI计算节点的节点功耗值大于警戒功耗值，则利用BMC获取所述AI计算节点中 的各个计算芯片的芯片功耗值；根据各个计算芯片的芯片功耗值对各个计算芯片进行分组，获得分组结果；若所述节点功耗值大于封顶功耗值，则查询所述分组结果对应的功耗调控策略，并按照所述功耗调控策略调整各个计算芯片的功耗限制值，以使所有功耗限制值之和处于目标范围；所述警戒功耗值小于所述封顶功耗值；所述功耗调控策略基于所述目标范围预先设定，所述目标范围用于调控所述AI计算节点中的各个计算芯片的能效值。
可见，本申请在AI计算节点的节点功耗值大于警戒功耗值时，利用BMC获取AI计算节点中的各个计算芯片的芯片功耗值；然后在节点功耗值大于封顶功耗值时，根据各个计算芯片的芯片功耗值对各个计算芯片进行分组，获得分组结果；最后查询分组结果对应的功耗调控策略，并按照功耗调控策略调整各个计算芯片的功耗限制值，以使所有功耗限制值之和处于目标范围；其中，功耗调控策略基于目标范围预先设定，且目标范围用于调控AI计算节点中的各个计算芯片的能效值，因此按照功耗调控策略调整各个计算芯片的功耗限制值不仅调控了各个计算芯片的功耗，还可以有效调控各个计算芯片的能效值，从而保障AI计算节点的能效。
相应地，本申请提供的一种功耗调控装置、设备及可读存储介质，也同样具有上述技术效果。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本申请公开的一种功耗调控方法流程图；
图2为本申请公开的一种AI计算节点的结构示意图；
图3为本申请公开的一种警戒功耗值、封顶功耗值以及节点最大功耗的关系示意图；
图4为本申请公开的一种分组示意图；
图5为本申请公开的一种能效与功耗的关系示意图；
图6为本申请公开的另一种功耗调控方法流程图；
图7为本申请公开的一种功耗调控装置示意图；
图8为本申请公开的一种功耗调控设备示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
目前，现有的调控服务器功耗的方式不适用于调控AI计算节点。为此，本申请提供了一种功耗调控方案，能够调控AI计算节点的功耗，并保障AI计算节点的能效。
参见图1所示，本申请实施例公开了第一种功耗调控方法，包括：
S101、若AI计算节点的节点功耗值大于警戒功耗值，则利用BMC获取AI计算节点中的各个计算芯片的芯片功耗值。
需要说明的是，AI计算节点为运行某种机器学习算法的设备，其可以为服务器等设备。AI计算节点中一般包括多个计算芯片，这些计算芯片是AI计算节点功耗的主要部件。此外，AI计算节点的其他功耗部件为内存、CPU、风扇等。AI计算节点的结构可参见图2。在图2中，DMI(Direct Media Interface)为用于连接主板南北桥的总线，UPI(Ultra Path Interconnect)是处理器之间的通信方式。I2C选路芯片用于选择任一个GPU(Graphics Processing Unit，图形处理器)所在的链路。
在一种具体实施方式中，利用BMC(Baseboard Management Controller，基板管理控制器)获取AI计算节点中的各个计算芯片的芯片功耗值之前，还包括：利用BMC实时监控节点功耗值，若节点功耗值大于警戒功耗值，则开启功耗调控功能.此时先对各个计算芯片的功耗进行监控和收集；警戒功耗值小于封顶功耗值。其中，利用BMC实时监控节点功耗值，包括：控制BMC通过PMBUS总线监控节点功耗值。PMBUS(Power Management  BUS)总线即电源管理总线。BMC带外方式获取功耗值，可以提高效率。
节点功耗值为AI计算节点的实际总功耗值，警戒功耗值和封顶功耗值均为预设值，这几个值的关系可参见图3。在图3中，节点最大功耗为AI计算节点中的所有部件全力运行时的总功耗值，因此其为最大值。
在一种具体实施方式中，利用BMC获取AI计算节点中的各个计算芯片的芯片功耗值，包括：利用BMC读AI计算节点中的各个计算芯片的电流值，以获得相应芯片功耗值。各个计算芯片的电流值即各个计算芯片对应的电流传感器上流过的电流值，该电流值可转换为相应的芯片功耗值。利用此方式获取芯片功耗值，可以避免频繁利用I2C总线，也不会影响计算芯片工作的能效。I2C(Inter－Integrated Circuit)总线即两线式串行总线。需要说明的是，并非所有的计算芯片都可以支持通过I2C的方式直接读取计算芯片的芯片功耗值，所以通过读电流值的方式获得芯片功耗值，是一种低成本且通用的功耗获取方式。能效是一个设备在单位时间内所耗能量与所处理数据量的比值，单位为MB/s/watt。
S102、根据各个计算芯片的芯片功耗值对各个计算芯片进行分组，获得分组结果。
需要说明的是，分组方式以及分组得到的组个数可以根据实际情况灵活确定。下述介绍了三种分组方式，第一种：用户基于人机交互界面提交分组指令或基于命令行窗口输入分组指令(如IPMI指令)，AI计算节点按照该分组指令分组即可。IPMI(Intelligent Platform Management Interface)即智能平台管理接口。第二种：设置一个分界线(即最优功耗值)，以该分界线将所有计算芯片划分为两组。第三种(请参见图4)：设置一个缓冲区间，将位于缓冲区间左边的计算芯片划分至第一组(高优先级组)，将位于缓冲区间右边的计算芯片划分至第二组(低优先级组)，然后判断位于缓冲区间中的计算芯片与第一组相似度大，还是与第二组相似度大，按照判断结果划分位于缓冲区间中的计算芯片，避免简单的切割，误将相同工作负载的GPU分到不同的分组里。图4中的计算芯片为GPU(Graphics Processing Unit)，圆代表GPU被划分至G0(第一组)，五角星代表GPU被划分至G1(第二组)。
对各个计算芯片进行分组后，即可根据分组结果确定相应的调控策略， 从而在调控各个计算芯片的功耗的同时，保障各个计算芯片的能效。
在一种具体实施方式中，根据各个计算芯片的芯片功耗值对各个计算芯片进行分组，获得分组结果，包括：按照获取到的分组指令对各个计算芯片进行分组，获得分组结果；或获取目标范围中的最优功耗值，将大于最优功耗值的计算芯片划分至第一组，将不大于最优功耗值的计算芯片划分至第二组，将第一组和第二组作为分组结果；或获取目标范围中的最优功耗值，以最优功耗值为中值确定缓冲区间，将不属于缓冲区间且大于最优功耗值的计算芯片划分至第一组，将不属于缓冲区间且不大于最优功耗值的计算芯片划分至第二组；计算第一组对应的第一功耗梯度，第二组对应的第二功耗梯度，以及属于缓冲区间中的每个计算芯片对应的芯片功耗梯度；计算任一个芯片功耗梯度与第一功耗梯度的第一相似度，与第二功耗梯度的第二相似度，若第一相似度大于第二相似度，则将芯片功耗梯度对应的计算芯片添加至第一组，若第一相似度小于第二相似度，则将芯片功耗梯度对应的计算芯片添加至第二组，将第一组和第二组作为分组结果。
其中，第一组对应的第一功耗梯度可以为第一组中的任一个计算芯片在预设时间段(如5秒)内的相邻芯片功耗值的差值形成的序列，当然，也可以是其他。第二组对应的第二功耗梯度可以为第二组中的任一个计算芯片在预设时间段内的相邻芯片功耗值的差值形成的序列，当然，也可以是其他。芯片功耗梯度为位于缓冲区间中的计算芯片在预设时间段内的相邻芯片功耗值的差值形成的序列。BMC在预设时间段内多次轮询电流传感器，可获得相应的多个芯片功耗值。
例如：GPU0在T0，T1，T2，T3，T4时刻的芯片功耗值分别为P00，P01，P02，P03，P04，那么芯片功耗梯度可以为：P 0＝[(P01-P00),(P02-P01),(P03-P02),(P04-P03)]。若缓冲区间中的GPU和缓冲区间右侧的GPU存在很大的功耗差，可以认为他们有不同的工作负载，因此，将缓冲区中的GPU划入G1。
请参见图4，若落入缓冲区间中的所有GPU都位于分界线左侧，则可以直接将缓冲区间中的所有GPU加入G1。若落入缓冲区间中的所有GPU都位于分界线右侧，则可以直接将缓冲区间中的所有GPU加入G0。若落入缓冲区间中的所有GPU位于分界线两侧，则执行计算第一组对应的第一 功耗梯度，第二组对应的第二功耗梯度，以及属于缓冲区间中的每个计算芯片对应的芯片功耗梯度；计算任一个芯片功耗梯度与第一功耗梯度的第一相似度，与第二功耗梯度的第二相似度，若第一相似度大于第二相似度，则将芯片功耗梯度对应的计算芯片添加至第一组，若第一相似度小于第二相似度，则将芯片功耗梯度对应的计算芯片添加至第二组，将第一组和第二组作为分组结果的步骤。
当然，对于落入缓冲区间中的所有GPU，都可以直接执行计算第一组对应的第一功耗梯度，第二组对应的第二功耗梯度，以及属于缓冲区间中的每个计算芯片对应的芯片功耗梯度；计算任一个芯片功耗梯度与第一功耗梯度的第一相似度，与第二功耗梯度的第二相似度，若第一相似度大于第二相似度，则将芯片功耗梯度对应的计算芯片添加至第一组，若第一相似度小于第二相似度，则将芯片功耗梯度对应的计算芯片添加至第二组，将第一组和第二组作为分组结果的步骤。
S103、若节点功耗值大于封顶功耗值，则查询分组结果对应的功耗调控策略，并按照功耗调控策略调整各个计算芯片的功耗限制值，以使所有功耗限制值之和处于目标范围。
其中。功耗调控策略基于目标范围预先设定，目标范围用于调控AI计算节点中的各个计算芯片的能效值。若节点功耗值大于封顶功耗值，则进入功耗调控功能的调控部分，以调节各个计算芯片的功耗限制值。
在一种具体实施方式中，目标范围的确定过程包括：利用性能基准测试工具(如SGEMM)获取AI计算节点中的任一个计算芯片在不同芯片功耗值下的各个能效值；AI计算节点中的各个计算芯片完全相同；计算各个能效值与TDP能效值的比值；将大于预设阈值的比值对应的能效值添加至能效调控区间，将能效调控区间对应的各个芯片功耗值确定为目标范围。
TDP(Thermal Design Power)即散热设计功耗，指芯片全力运行时的功耗值，在该功耗值下用性能基准测试工具测得的性能数据与该功耗值的比值为TDP能效值。即：TDP能效值＝TDP下测得的性能数据/TDP。任一个计算芯片在芯片功耗值U下的能效值W＝芯片功耗值U下测得的性能数据/芯片功耗值U。
例如：AI计算节点中的某一个计算芯片在不同芯片功耗值下的各个能 效值为A、B、C、D，该计算芯片的TDP能效值为X，那么可获得比值A/X、B/X、C/X、D/X，这些比值可形成如图5所示的曲线图。在图5中，目标范围即为：0.6TDP～1TDP。由图5可看出，0.8TDP时曲线可达最高点，说明0.8TDP下的芯片能效值最大，因此0.8TDP即为目标范围中的最优功耗值。
为使功耗调控后，AI计算节点获得较高的能效，可以预先计算AI计算节点中计算芯片对应的目标范围，目标范围即计算芯片对应的功耗可调控范围，计算芯片的功耗保持在此范围内，其能效也会保持在较佳状态。一般地，一个AI计算节点中的各个计算芯片完全相同，因此以其中的任一个计算芯片为基础，就可以确定出目标范围。
如图5所示，Alpha＞1时，目标范围为：0.6TDP～1TDP，在此范围内调控计算芯片的功耗，可使AI计算节点的能效保持在较佳状态。需要说明的是，功耗调控目标为在AI计算节点最大功耗的基础上，降低n×(TDP-Ppeak)，其中n为AI计算节点中的计算芯片的数量，Ppeak(即0.8TDP)为Alpha为最高值时对应的单个计算芯片的功耗。以8张250W NVIDIA V100 GPU卡的AI计算节点为例，即TDP＝250W，其最大可降低的功耗为8×(250-0.8X250)W＝400W，假设该AI计算节点最大功耗为3100W，则功耗最低值可调为2700W。
在一种具体实施方式中，计算芯片为GPU、NPU(Neural-network Processing Unit，嵌入式神经网络处理器)、FPGA(Field－Programmable Gate Array，现场可编程门阵列)或ASIC(Application Specific Integrated Circuit)。
可见，本申请实施例在AI计算节点的节点功耗值大于封顶功耗值时，利用BMC获取AI计算节点中的各个计算芯片的芯片功耗值；然后根据各个计算芯片的芯片功耗值对各个计算芯片进行分组，获得分组结果；最后查询分组结果对应的功耗调控策略，并按照功耗调控策略调整各个计算芯片的功耗限制值，以使所有功耗限制值之和处于目标范围；其中，功耗调控策略基于目标范围预先设定，且目标范围用于调控AI计算节点中的各个计算芯片的能效值，因此按照功耗调控策略调整各个计算芯片的功耗限制值不仅调控了各个计算芯片的功耗，还可以有效调控各个计算芯片的能效值，从而保障AI计算节点的能效。
参见图6所示，本申请实施例利用BMC监控节点功耗值，若节点功耗值大于警戒功耗值，则开启功耗调控功能，之后确定分组策略，以进行分组，而后在节点功耗值大于封顶功耗值时，按照分组后得到的高优先级组和低优先级组，以及相应功耗调控策略进行调控。图6示意了3种分组策略，具体可参见上述实施例的相关介绍。
在本实施例中，功耗调控策略如表1所示。
表1
Figure PCTCN2021089912-appb-000001
在表1中，当G0中GPU数量为8，G1中GPU数量为0时，将G0中的8个GPU的功耗限制为0.8*TDP；当G0中GPU数量为6，G1中GPU数量为2时，将G0中的6个GPU的功耗限制为0.9*TDP，G1中的2个GPU功耗限制为0.6*TDP；当G0中GPU数量为4，G1中GPU数量为4时，将G0中的4个GPU的功耗限制为TDP，G1中的4个GPU功耗限制为0.6*TDP；其中0.9*TDP、0.8*TDP、0.6*TDP只是示例。
具体的，手动分组的结果可参见表2，假设AI计算节点中包括GPU0～GPU7共8个计算芯片。其中，√代表属于G0或G1。
表2
  高优先级组G0 低优先级组G1
GPU0 √  
GPU1   √
GPU2 √  
GPU3 √  
GPU4   √
GPU5 √  
GPU6   √
GPU7   √
表2所示的分组结果为：位于G0的GPU数量为4，位于G1的GPU数量为4，在表1中可查到与此对应的调控策略：位于G0的GPU功耗不做限制，位于G1的GPU功耗限制为60％*TDP。
相应的，假设位于G0的GPU数量为6，位于G1的GPU数量为2，那么按照表1所示，位于G0的GPU功耗限制为90％*TDP，位于G1的GPU功耗限制为60％*TDP。假设位于G0的GPU数量为7，位于G1的GPU数量为1，那么按照表1所示，位于G0和G2的GPU功耗限制为80％*TDP。
需要说明的是，现有机柜的供电能力普遍偏低，而AI计算节点的功耗又比较大，因此需要降低AI计算节点的功耗，以满足机柜的PDU(Power Distribution Unit，机柜用电源分配插座)要求。一个机柜上会放置多个AI计算节点。具体的，机柜的PDU一般为C13-C14接口，国内安规要求C13-C14接口最高持续通流不能超过10A，而AI计算节点功耗高，需使用2200W及以上高功率PSU(Power Supply Unit，电源供应器)，该规格需要C19-C20接口(16A)。PDU大批量升级困难，若使用C19-C14电源线缆，由于持续通流会超过10A，不符合国内安全规定的要求。可见，为了符合机柜的供电能力，需要降低AI计算节点的功耗。降低AI计算节点的功耗后，还可以增加一个机柜上放置的AI计算节点的个数，以增加机柜密度。
本实施例能够降低AI计算节点的功耗，同时使AI计算节点保持在较佳运行状态，提高其能效。通过带外的方式，在一定范围内调控GPU功耗，保障了AI计算节点高能效运行。
下面对本申请实施例提供的一种功耗调控装置进行介绍，下文描述的 一种功耗调控装置与上文描述的一种功耗调控方法可以相互参照。
参见图7所示，本申请实施例公开了一种功耗调控装置，包括：
获取模块701，用于若AI计算节点的节点功耗值大于警戒功耗值，则利用BMC获取AI计算节点中的各个计算芯片的芯片功耗值；
分组模块702，用于根据各个计算芯片的芯片功耗值对各个计算芯片进行分组，获得分组结果；
调控模块703，用于若所述节点功耗值大于封顶功耗值，则查询分组结果对应的功耗调控策略，并按照功耗调控策略调整各个计算芯片的功耗限制值，以使所有功耗限制值之和处于目标范围；所述警戒功耗值小于所述封顶功耗值；功耗调控策略基于目标范围预先设定，目标范围用于调控AI计算节点中的各个计算芯片的能效值。
在一种具体实施方式中，还包括：
监控模块，用于利用BMC实时监控节点功耗值，若节点功耗值大于警戒功耗值，则开启功耗调控功能。
在一种具体实施方式中，监控模块具体用于：
控制BMC通过PMBUS总线监控节点功耗值。
在一种具体实施方式中，获取模块具体用于：
利用BMC读AI计算节点中的各个计算芯片的电流值，以获得相应芯片功耗值。
在一种具体实施方式中，分组模块包括：
第一分组单元，用于按照获取到的分组指令对各个计算芯片进行分组，获得分组结果；
或
第二分组单元，用于获取目标范围中的最优功耗值，将大于最优功耗值的计算芯片划分至第一组，将不大于最优功耗值的计算芯片划分至第二组，将第一组和第二组作为分组结果；
或
第三分组单元，用于获取目标范围中的最优功耗值，以最优功耗值为中值确定缓冲区间，将不属于缓冲区间且大于最优功耗值的计算芯片划分至第一组，将不属于缓冲区间且不大于最优功耗值的计算芯片划分至第二 组；计算第一组对应的第一功耗梯度，第二组对应的第二功耗梯度，以及属于缓冲区间中的每个计算芯片对应的芯片功耗梯度；计算任一个芯片功耗梯度与第一功耗梯度的第一相似度，与第二功耗梯度的第二相似度，若第一相似度大于第二相似度，则将芯片功耗梯度对应的计算芯片添加至第一组，若第一相似度小于第二相似度，则将芯片功耗梯度对应的计算芯片添加至第二组，将第一组和第二组作为分组结果。
在一种具体实施方式中，目标范围的确定过程包括：
利用性能基准测试工具获取AI计算节点中的任一个计算芯片在不同芯片功耗值下的各个能效值；AI计算节点中的各个计算芯片完全相同；
计算各个能效值与TDP能效值的比值；
将大于预设阈值的比值对应的能效值添加至能效调控区间，将能效调控区间对应的各个芯片功耗值确定为目标范围。
在一种具体实施方式中，计算芯片为GPU、NPU、FPGA或ASIC。
其中，关于本实施例中各个模块、单元更加具体的工作过程可以参考前述实施例中公开的相应内容，在此不再进行赘述。
可见，本实施例提供了一种功耗调控装置，该装置能够降低AI计算节点的功耗，同时使AI计算节点保持在较佳运行状态，提高其能效。
下面对本申请实施例提供的一种功耗调控设备进行介绍，下文描述的一种功耗调控设备与上文描述的一种功耗调控方法及装置可以相互参照。
参见图8所示，本申请实施例公开了一种功耗调控设备，包括：
存储器801，用于保存计算机程序；
处理器802，用于执行所述计算机程序，以实现上述任意实施例公开的方法。
下面对本申请实施例提供的一种可读存储介质进行介绍，下文描述的一种可读存储介质与上文描述的一种功耗调控方法、装置及设备可以相互参照。
一种可读存储介质，用于保存计算机程序，其中，所述计算机程序被处理器执行时实现前述实施例公开的功耗调控方法。关于该方法的具体步 骤可以参考前述实施例中公开的相应内容，在此不再进行赘述。
本申请涉及的“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法或设备固有的其它步骤或单元。
需要说明的是，在本申请中涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似部分互相参见即可。
结合本文中所公开的实施例描述的方法或算法的步骤可以直接用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、或技术领域内所公知的任意其它形式的可读存储介质中。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (10)

  1. 一种功耗调控方法，其特征在于，包括：
    若AI计算节点的节点功耗值大于警戒功耗值，则利用BMC获取所述AI计算节点中的各个计算芯片的芯片功耗值；
    根据各个计算芯片的芯片功耗值对各个计算芯片进行分组，获得分组结果；
    若所述节点功耗值大于封顶功耗值，则查询所述分组结果对应的功耗调控策略，并按照所述功耗调控策略调整各个计算芯片的功耗限制值，以使所有功耗限制值之和处于目标范围；所述警戒功耗值小于所述封顶功耗值；所述功耗调控策略基于所述目标范围预先设定，所述目标范围用于调控所述AI计算节点中的各个计算芯片的能效值。
  2. 根据权利要求1所述的功耗调控方法，其特征在于，所述利用BMC获取所述AI计算节点中的各个计算芯片的芯片功耗值之前，还包括：
    利用所述BMC实时监控所述节点功耗值，若所述节点功耗值大于所述警戒功耗值，则开启功耗调控功能。
  3. 根据权利要求2所述的功耗调控方法，其特征在于，所述利用所述BMC实时监控所述节点功耗值，包括：
    控制所述BMC通过PMBUS总线监控所述节点功耗值。
  4. 根据权利要求1所述的功耗调控方法，其特征在于，所述利用BMC获取所述AI计算节点中的各个计算芯片的芯片功耗值，包括：
    利用所述BMC读所述AI计算节点中的各个计算芯片的电流值，以获得相应芯片功耗值。
  5. 根据权利要求1所述的功耗调控方法，其特征在于，所述根据各个计算芯片的芯片功耗值对各个计算芯片进行分组，获得分组结果，包括：
    按照获取到的分组指令对各个计算芯片进行分组，获得所述分组结果；
    或
    获取所述目标范围中的最优功耗值，将大于所述最优功耗值的计算芯片划分至第一组，将不大于所述最优功耗值的计算芯片划分至第二组，将所述第一组和所述第二组作为所述分组结果；
    或
    获取所述目标范围中的最优功耗值，以所述最优功耗值为中值确定缓冲区间，将不属于所述缓冲区间且大于所述最优功耗值的计算芯片划分至第一组，将不属于所述缓冲区间且不大于所述最优功耗值的计算芯片划分至第二组；
    计算所述第一组对应的第一功耗梯度，所述第二组对应的第二功耗梯度，以及属于所述缓冲区间中的每个计算芯片对应的芯片功耗梯度；
    计算任一个芯片功耗梯度与所述第一功耗梯度的第一相似度，与所述第二功耗梯度的第二相似度，若所述第一相似度大于所述第二相似度，则将所述芯片功耗梯度对应的计算芯片添加至所述第一组，若所述第一相似度小于所述第二相似度，则将所述芯片功耗梯度对应的计算芯片添加至所述第二组，将所述第一组和所述第二组作为所述分组结果。
  6. 根据权利要求1至5任一项所述的功耗调控方法，其特征在于，所述目标范围的确定过程包括：
    利用性能基准测试工具获取所述AI计算节点中的任一个计算芯片在不同芯片功耗值下的各个能效值；所述AI计算节点中的各个计算芯片完全相同；
    计算各个能效值与TDP能效值的比值；
    将大于预设阈值的比值对应的能效值添加至能效调控区间，将所述能效调控区间对应的各个芯片功耗值确定为所述目标范围。
  7. 根据权利要求6所述的功耗调控方法，其特征在于，所述计算芯片为GPU、NPU、FPGA或ASIC。
  8. 一种功耗调控装置，其特征在于，包括：
    获取模块，用于若AI计算节点的节点功耗值大于警戒功耗值，则利用BMC获取所述AI计算节点中的各个计算芯片的芯片功耗值；
    分组模块，用于根据各个计算芯片的芯片功耗值对各个计算芯片进行分组，获得分组结果；
    调控模块，用于若所述节点功耗值大于封顶功耗值，则查询所述分组结果对应的功耗调控策略，并按照所述功耗调控策略调整各个计算芯片的功耗限制值，以使所有功耗限制值之和处于目标范围；所述警戒功耗值小于所述封顶功耗值；所述功耗调控策略基于所述目标范围预先设定，所述 目标范围用于调控所述AI计算节点中的各个计算芯片的能效值。
  9. 一种功耗调控设备，其特征在于，包括：
    存储器，用于存储计算机程序；
    处理器，用于执行所述计算机程序，以实现如权利要求1至7任一项所述的功耗调控方法。
  10. 一种可读存储介质，其特征在于，用于保存计算机程序，其中，所述计算机程序被处理器执行时实现如权利要求1至7任一项所述的功耗调控方法。
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