WO2022048282A1 - 一种多路电源供电均流电路和控制方法 - Google Patents

一种多路电源供电均流电路和控制方法 Download PDF

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WO2022048282A1
WO2022048282A1 PCT/CN2021/103370 CN2021103370W WO2022048282A1 WO 2022048282 A1 WO2022048282 A1 WO 2022048282A1 CN 2021103370 W CN2021103370 W CN 2021103370W WO 2022048282 A1 WO2022048282 A1 WO 2022048282A1
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current sharing
power supply
gate
terminal
nmos transistor
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French (fr)
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刘云利
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Suzhou Wave Intelligent Technology Co Ltd
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Suzhou Wave Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

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  • the invention relates to the technical field of server power supplies, in particular to a multi-channel power supply current sharing circuit and a control method.
  • Power supply stability is generally manifested in the stability of voltage and current, and the stability of line path temperature.
  • the line temperature is closely related to the current on the path. When the current on the line path is too large, more heat will be generated on the path. When the heat is too high, it is easy to cause damage such as board burning or fire.
  • the purpose of the present invention is to provide a multi-channel power supply current sharing circuit and a control method, so as to control the safe current sharing of the multi-channel power supply power supply.
  • an embodiment of the present invention provides a multi-channel power supply current sharing circuit, including: a combined output terminal and at least two power supplies; wherein, any one of the at least two power supplies is correspondingly provided with a current sharing mode Group;
  • the current sharing module includes an NMOS transistor, a gate discharge circuit, a gate drive circuit and a gate control processor;
  • the source of the NMOS transistor is connected to the combined output terminal; the drain of the NMOS transistor is connected to the output terminal of the power supply corresponding to the current sharing module in the at least two power supplies;
  • the input end of the gate discharge circuit and the drive end of the gate drive circuit are both connected to the gate of the NMOS transistor;
  • the gate control processor is connected to the control terminal of the gate drive circuit; the gate control processor is further sampled and connected to the combined output terminal and the output terminal of the power supply corresponding to the current sharing module. .
  • the gate bleeder circuit includes: a first diode, a first resistor, a first capacitor and a first transistor;
  • the anode of the first diode is connected to the gate of the NMOS transistor; the cathode of the first diode is grounded through the first capacitor;
  • One end of the first resistor is connected to the gate of the NMOS transistor, and the opposite end of the first resistor is connected to the base of the first triode;
  • the emitter of the first triode is connected to the cathode of the first diode; the collector of the first triode is grounded.
  • the gate bleeder circuit includes: a voltage comparator, a second resistor, a second capacitor, and a second transistor;
  • the forward input terminal of the voltage comparator is connected to the reference voltage terminal; the reverse input terminal of the voltage comparator is connected to the gate of the NMOS transistor; the output terminal of the voltage comparator is connected to the second transistor the base;
  • the emitter of the second triode is connected to the gate of the NMOS transistor; the collector of the second triode is grounded through the parallel circuit formed by the second capacitor and the second resistor.
  • the current sharing module further includes: a third resistor, a fourth resistor, a fifth resistor and a sixth resistor;
  • the third resistor and the fourth resistor are connected in series between the output end of the power supply corresponding to the current sharing module and the ground;
  • the first sampling input terminal of the gate control processor is connected between the third resistor and the fourth resistor, so as to realize the sampling connection of the gate control processor to the power supply corresponding to the current sharing module. output;
  • the fifth resistor and the sixth resistor are connected in series between the combined output terminal and ground;
  • the second sampling input terminal of the gate control processor is connected between the fifth resistor and the sixth resistor, so as to realize the sampling connection of the gate control processor to the combined output terminal.
  • the gate drive circuit is a charge pump module.
  • the voltage comparator is an LM393 dual voltage comparator.
  • an embodiment of the present invention provides a multi-channel power supply current sharing control method, and the method is applied to the multi-channel power supply current sharing circuit according to any one of the first aspect, including:
  • the on-resistance of the NMOS transistor is adjusted
  • the NMOS transistor is turned off.
  • the obtaining the equivalent load current output by the current sharing module according to the sampled voltage of the power supply terminal and the sampled voltage of the merging terminal includes:
  • U 1 is the sampling voltage of the power supply terminal
  • U 2 is the sampling voltage of the merging terminal
  • adjusting the on-resistance of the NMOS transistor according to the magnitude relationship between the equivalent load current and the set current sharing value includes:
  • the on-resistance of the NMOS transistor is reduced.
  • the method further includes:
  • the electric energy at the driving end of the gate driving circuit is discharged by the gate discharge circuit.
  • the present invention has the following advantages and beneficial effects:
  • the multi-channel power supply is equipped with a current sharing module, and each current sharing module can adjust the switching state and on-resistance of the NMOS transistor according to the power supply voltage and the voltage of the combined output terminal, so as to realize the combined output of the power supply to the combined output terminal.
  • the current sharing control of the output current of the terminal avoids the potential safety hazards caused by the short circuit of the power supply, the high voltage of the combined output terminal and the fluctuation of the output current, thus realizing the safe current sharing control of the multi-channel power supply.
  • FIG. 1 is a schematic diagram of the connection of a multi-channel power supply current sharing circuit provided by an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a connection of a gate bleeder circuit provided by an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a connection of a gate bleeder circuit provided by an embodiment of the present invention.
  • FIG. 4 is a schematic connection diagram of a multi-channel power supply current sharing circuit with a sampling circuit provided by an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a connection of a gate driver circuit provided by an embodiment of the present invention.
  • FIG. 6 is a flowchart of a current sharing control method for power supply by multiple power sources according to an embodiment of the present invention.
  • 1 is a power supply
  • 11 is a module
  • 12 is an NMOS transistor
  • 13 is a gate discharge circuit
  • 14 is a gate drive circuit
  • 15 is a gate control processor
  • 2 is a combined power supply terminal.
  • FIG. 1 is a schematic diagram of the connection of the circuit, which specifically includes: a combined output end 2 and at least two power supplies 1 ;
  • a current sharing module 11 is correspondingly provided for any power supply of the power supply;
  • the current sharing module 11 includes an NMOS transistor 12, a gate discharge circuit 13, a gate driving circuit 14 and a gate control processor 15;
  • the source of the NMOS transistor 12 Connect the combined output terminal 2;
  • the drain of the NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor) transistor 12 is connected to the output terminal of the power supply 1 corresponding to the current sharing module 11 in the at least two power supplies;
  • the input end of the gate discharge circuit 13 and the drive end of the gate drive circuit 14 are both connected to the gate of the NMOS transistor 12;
  • the gate control processor 15 is connected to the control end of the gate drive circuit 14;
  • the gate control processor 15 also The combined output end 2 and the output end
  • the NMOS transistor 12 is used as the conduction channel between the power supply 1 and the combined output end 2, which can reduce conduction loss and facilitate the control of the opening degree of the channel.
  • a plurality of current sharing modules can be set at the same time, so as to realize the current sharing control of the multi-channel power supply.
  • the gate bleeder circuit 13 can quickly bleed off the voltage at the drive terminal of the gate driver circuit 14, thereby quickly turning off the NMOS transistor, so that when a short circuit occurs and the driver needs to be turned off quickly, the to protect the front-end circuit.
  • FIG. 2 shows a schematic connection diagram of a gate bleeder circuit provided in this embodiment, including: a first diode D1, a first resistor R1, a first capacitor C1 and a first transistor Q1; a first The anode of the diode D1 is connected to the gate of the NMOS transistor 12; the cathode of the first diode D1 is grounded through the first capacitor C1; one end of the first resistor R1 is connected to the gate of the NMOS transistor 12, and the opposite end of the first resistor R1 is connected to the gate of the NMOS transistor 12.
  • the base of a triode Q1; the emitter of the first triode Q1 is connected to the cathode of the first diode D1; the collector of the first triode Q1 is grounded.
  • the gate discharge circuit 13 acts rapidly due to the drop of the drive voltage, and discharges the charge of the drive to realize Quickly turn off the function of turning on the MOS; when the value of the first capacitor C1 is large, the circuit can also realize the slow-start function.
  • the gate driver circuit 14 outputs the driving voltage of the MOS, the voltage of the driving electrode is slowly increased, Reduce the impact of the driving voltage on the gate.
  • FIG. 3 shows a schematic diagram of the connection of a gate bleeder circuit provided in this embodiment, including: a voltage comparator A1, a second resistor R2, a second capacitor C2 and a second transistor Q2; a voltage comparator A1
  • the forward input terminal of the voltage comparator A1 is connected to the reference voltage terminal; the reverse input terminal of the voltage comparator A1 is connected to the gate of the NMOS transistor; the output terminal of the voltage comparator A1 is connected to the base of the second transistor Q2; the second transistor Q2
  • the emitter of the NMOS transistor is connected to the gate of the NMOS transistor; the collector of the second transistor Q2 is grounded through the parallel circuit formed by the second capacitor C2 and the second resistor R2.
  • the voltage comparator A1 When the gate driving circuit 14 cuts off the driving voltage of the MOS, the voltage of the driving terminal of the gate bleeder circuit 13 drops rapidly, and when it is less than the voltage of the reference voltage terminal, the voltage comparator A1 will output a high level, thereby turning on the second and third
  • the electrode transistor Q2 uses the parallel circuit formed by the second capacitor C2 and the second resistor R2 to quickly discharge the driving electrode voltage.
  • the voltage comparator is an LM393 dual voltage comparator.
  • the gate control processor 15 can collect the voltage at the power supply 1 and the voltage at the combined output terminal 2, as shown in FIG. Including: a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6; the third resistor R3 and the fourth resistor R4 are connected in series between the output end of the power supply 1 corresponding to the current sharing module 11 and the ground ; The first sampling input end of the gate control processor 15 is connected between the third resistance R3 and the fourth resistance R4, to realize that the gate control processor 15 is sampled and connected to the output end of the power supply 1 corresponding to the current sharing module 11; The fifth resistor R5 and the sixth resistor R6 are connected in series between the combined output terminal 2 and the ground; the second sampling input terminal of the gate control processor 15 is connected between the fifth resistor R5 and the sixth resistor R6 to realize the gate The control processor 15 is sample-connected to the combined output 2 .
  • the third resistor R3 and the fourth resistor R4 form a voltage divider circuit.
  • the gate control processor 15 can obtain the voltage of the power supply 1 corresponding to the current sharing module 11 by collecting the voltage between the third resistor R3 and the fourth resistor R4. voltage at the output.
  • the fifth resistor R5 and the sixth resistor R6 form a voltage divider circuit, and the gate control processor 15 can obtain the combined output terminal corresponding to the current sharing module 11 by collecting the voltage between the fifth resistor R5 and the sixth resistor R6 2 voltage.
  • the gate control processor 15 configures the equivalent internal resistance according to the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6, and then calculates the current output load current of the current sharing module 11 according to the sampled voltage , and according to the magnitude of the load current, the on-resistance control and the on-off control of the NMOS transistor 12 are performed.
  • the gate control processor 15 can be implemented by using electronic chips such as MCU and single chip with functions of sampling and control.
  • the gate drive circuit 14 is used to drive the NMOS transistor 12 to work according to the control signal output by the gate control processor 15.
  • the gate drive circuit can use a charge pump module.
  • the charge pump is a DC/DC converter (Direct current- Direct current converter, DC power-DC power converter), it is composed of the principle of charging and discharging the capacitor to realize the charge transfer. It can convert the input positive voltage into the corresponding negative voltage, and can also convert the input voltage into an integer multiple the output voltage.
  • the gate drive circuit 14 receives the gate control command issued by the gate control processor 15, the charge pump in the gate drive circuit 14 will generate the corresponding drive voltage and output it to the gate from its drive terminal to control the NMOS The switching state and on-resistance of the transistor.
  • FIG. 5 is a schematic diagram of the connection of a gate drive circuit provided by an embodiment of the present invention, including: a second diode D2, a first voltage regulator The diode D3, the second Zener diode D4, the seventh resistor R7 and the eighth resistor R8; the anode of the second diode D2 is connected to the drive terminal of the gate drive circuit 14; the cathode of the second diode D2 is connected to the NMOS transistor respectively 12 and the control terminal of the gate drive circuit 14; the seventh resistor R7 is connected in parallel with the second diode D2; the first Zener diode D3 and the second Zener diode D4 are connected in reverse series to the gate drive circuit 14 Between the driving terminal of the gate driver circuit 14 and the source of the NMOS transistor 12; the eighth resistor R8 is connected in series between the driving terminal of the gate driving circuit 14 and the source of the NMOS transistor 12; the source of the
  • the role of the seventh resistor R7 is to limit current and suppress parasitic oscillation
  • the eighth resistor R8 is to provide a discharge loop when the NMOS transistor 12 is turned off
  • the Zener diodes D3 and D4 are to protect the gate and source of the NMOS transistor 12.
  • the second diode D2 is to accelerate the turn-off of the NMOS transistor 12 .
  • FIG. 6 is a flowchart of a current sharing control method for multi-channel power supply provided by an embodiment of the present invention. The method embodiment is applied to the above-mentioned multi-channel power supply current sharing circuit, including:
  • Step 11 acquiring the combined terminal sampling voltage of the combined output terminal and the power supply terminal sampling voltage of the output terminal of the power supply corresponding to the current sharing module.
  • the sampling voltage of the combined terminal and the sampling voltage of the power supply terminal can be collected through a voltage divider circuit, and the voltage collection of different power supply terminals (such as 5V, 12V, 48V, and 54V, etc.) can be realized by reasonable matching of the voltage divider resistor.
  • a voltage sensor can also be used to directly measure and obtain the sampling voltage at the merging terminal and the sampling voltage at the power supply terminal.
  • Step 12 Obtain the equivalent load current output by the current sharing module according to the sampled voltage of the power supply terminal and the sampled voltage of the merging terminal.
  • the present invention also provides an optimal solution for obtaining the equivalent load current, specifically:
  • Step 21 Set the equivalent internal resistance r according to the third resistance, the fourth resistance, the fifth resistance and the sixth resistance.
  • the sampling voltage of the power supply terminal and the sampling voltage of the merging terminal can be restored to the bus voltage, thereby calculating the equivalent load current.
  • the accuracy of the resistance value of the equivalent internal resistance is different, and the accuracy of the current sharing control will also be different.
  • Step 22 calculate the equivalent load current I output by the current sharing module, and the specific calculation formula is:
  • U 1 is the sampling voltage of the power supply terminal
  • U 2 is the sampling voltage of the merging terminal
  • Step 13 Adjust the on-resistance of the NMOS transistor according to the magnitude relationship between the equivalent load current and the set current sharing value.
  • the present invention also provides a better control scheme, specifically:
  • Step 31 if the equivalent load current is greater than the set current sharing value, increase the on-resistance of the NMOS transistor.
  • the equivalent load current when the equivalent load current is large, it is necessary to perform current sharing control to reduce the size of the equivalent load current.
  • the on-resistance of the NMOS transistor is increased by reducing the driving voltage of the output of the gate driving circuit.
  • the power supply current capability is weakened, but it is in a state that can be re-conducted at any time.
  • Step 32 if the equivalent load current is less than the set current sharing value, reduce the on-resistance of the NMOS transistor.
  • the equivalent load current when the equivalent load current is small, current sharing control needs to be performed to increase the size of the equivalent load current.
  • the on-resistance of the NMOS transistor is reduced by increasing the output driving voltage of the gate driving circuit, so that the The power supply current capability is weakened, but it is in a state that can be re-conducted at any time.
  • Step 14 judging whether the difference between the sampling voltage of the power supply terminal and the sampling voltage of the combining terminal is greater than a set upper limit threshold or less than 0.
  • the difference between the sampling voltage at the power supply terminal and the sampling voltage at the merging terminal will increase rapidly and exceed the set upper limit threshold.
  • the output drive voltage of the gate drive circuit is cut off to turn off in time.
  • NMOS transistor to protect the front-end circuit.
  • the sampling voltage of the merging terminal will be greater than the sampling voltage of the power supply terminal, resulting in the difference between the sampling voltage of the power supply terminal and the sampling voltage of the merging terminal being less than 0.
  • Step 15 if yes, turn off the NMOS transistor.
  • the method further includes:
  • Step 41 using the gate discharge circuit to discharge the electric energy of the driving end of the gate drive circuit.
  • the multi-channel power supply is equipped with a current sharing module, and each current sharing module can adjust the switching state and on-resistance of the NMOS transistor according to the power supply voltage and the voltage of the combined output terminal, so as to realize the power supply direction.
  • the current sharing control of the output current of the combined output terminal avoids potential safety hazards caused by short circuit of the power supply, excessive voltage of the combined output terminal and fluctuation of the output current, thus realizing the safe current sharing control of the multi-channel power supply.

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Abstract

一种多路电源供电均流电路和控制方法。该电路中：NMOS晶体管的源极连接合并输出端；NMOS晶体管的漏极连接至少两个电源中与均流模组对应的电源的输出端；门极泄放电路的输入端和门极驱动电路的驱动端均连接NMOS晶体管的门极；门极控制处理器连接门极驱动电路的控制端；门极控制处理器还分别采样连接合并输出端和与均流模组对应的电源的输出端。本发明的均流模组能够根据电源电压以及合并输出端的电压来调整NMOS晶体管的开关状态以及导通阻抗，避免由于电源短路、合并输出端电压过高以及输出电流的波动而引起安全隐患，从而实现了对多路电源供电的安全均流控制。

Description

一种多路电源供电均流电路和控制方法
本申请要求于2020年09月07日提交中国专利局、申请号为202010928255.X、发明名称为“一种多路电源供电均流电路和控制方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及服务器电源技术领域，具体涉及一种多路电源供电均流电路和控制方法。
背景技术
伴随云计算、AI智能、大数据等新型互联网技术的发展，服务器的性能也越来越强大，各高精密芯片对电流的大小和电源的稳定性也越来越高。对电流的需求越来越大是为了获得更高的功率以及更高的性能。
当电流需求较大时，单个供电源的性能和成本就会增加，可以采用多个电源合并的方式进行供电，缓解单个供电电源压力的同时，当出现个例电源失效时增加了冗余数量，增强了供电可靠性。电源稳定性一般表现为电压和电流的稳定、线路路径温度的稳定。线路温度与路径上电流息息相关，当线路路径上的电流过大，在路径上产生的热量就会更多，当热量过高时就容易产生烧板或火灾等危害。
因此，如何实现对多路电源供电的安全均流控制，是目前亟需解决的技术问题。
发明内容
本发明的目的是提供一种多路电源供电均流电路和控制方法，以对多路电源供电的安全均流控制。
为实现上述目的，本发明实施例提供了以下方案：
第一方面，本发明实施例提供一种多路电源供电均流电路，包括：合并输出端和至少两个电源；其中，所述至少两个电源中的任一个电源均对应设置有均流模组；
所述均流模组包括NMOS晶体管、门极泄放电路、门极驱动电路和门极控制处理器；
所述NMOS晶体管的源极连接所述合并输出端；所述NMOS晶体管的漏极连接所述至少两个电源中与所述均流模组对应的电源的输出端；
所述门极泄放电路的输入端和所述门极驱动电路的驱动端均连接所述NMOS晶体管的门极；
所述门极控制处理器连接所述门极驱动电路的控制端；所述门极控制处理器还分别采样连接所述合并输出端和所述与所述均流模组对应的电源的输出端。
在一种可能的实施例中，所述门极泄放电路包括：第一二极管，第一电阻，第一电容和第一三极管；
所述第一二极管的正极连接所述NMOS晶体管的门极；所述第一二极管的负极通过所述第一电容接地；
所述第一电阻的一端连接所述NMOS晶体管的门极，其相对的另一端连接所述第一三极管的基极；
所述第一三极管的发射极连接所述第一二极管的负极；所述第一三极管的集电极接地。
在一种可能的实施例中，所述所述门极泄放电路包括：电压比较器、第二电阻、第二电容和第二三极管；
所述电压比较器的正向输入端连接参考电压端；所述电压比较器的反向输入端连接所述NMOS晶体管的门极；所述电压比较器的输出端连接所述第二三极管的基极；
所述第二三极管的发射极连接所述NMOS晶体管的门极；所述第二三极管的集电极通过所述第二电容和所述第二电阻构成的并联电路接地。
在一种可能的实施例中，所述均流模组还包括：第三电阻、第四电阻、第五电阻和第六电阻；
所述第三电阻和所述第四电阻串联在所述与所述均流模组对应的电源的输出端和地之间；
所述门极控制处理器的第一采样输入端连接在所述第三电阻和所述第 四电阻之间，以实现所述门极控制处理器采样连接所述均流模组对应的电源的输出端；
所述第五电阻和所述第六电阻串联在所述合并输出端和地之间；
所述门极控制处理器的第二采样输入端连接在所述第五电阻和所述第六电阻之间，以实现所述门极控制处理器采样连接所述合并输出端。
在一种可能的实施例中，所述门极驱动电路为电荷泵模组。
在一种可能的实施例中，所述电压比较器为LM393双电压比较器。
第二方面，本发明实施例提供一种多路电源供电均流控制方法，所述方法应用在如第一方面任一所述的多路电源供电均流电路中，包括：
获取合并输出端的合并端采样电压和与均流模组对应的电源的输出端的电源端采样电压；
根据所述电源端采样电压和所述合并端采样电压，获取所述均流模组输出的等效负载电流；
根据所述等效负载电流和设定电流均流值之间的大小关系，调整NMOS晶体管的导通阻抗；
判断所述电源端采样电压与所述合并端采样电压的差值是否大于设定上限阈值或小于0；
若是，则关断所述NMOS晶体管。
在一种可能的实施例中，所述根据所述电源端采样电压和所述合并端采样电压，获取所述均流模组输出的等效负载电流，包括：
根据第三电阻、第四电阻、第五电阻和第六电阻，设定等效内阻r；
计算所述均流模组输出的等效负载电流I，具体的计算公式为：
Figure PCTCN2021103370-appb-000001
其中，U 1为所述电源端采样电压，U 2为所述合并端采样电压。
在一种可能的实施例中，所述根据所述等效负载电流和设定电流均流值之间的大小关系，调整NMOS晶体管的导通阻抗，包括：
若所述等效负载电流大于所述设定电流均流值，则增大所述NMOS晶体管的导通阻抗；
若所述等效负载电流小于所述设定电流均流值，则减小所述NMOS晶 体管的导通阻抗。
在一种可能的实施例中，所述关断所述NMOS晶体管之后，所述方法还包括：
利用门极泄放电路泄放门极驱动电路的驱动端的电能。
本发明与现有技术相比，具有如下的优点和有益效果：
本发明中，为多路电源均配备有均流模组，每个均流模组能够根据电源电压以及合并输出端的电压来调整NMOS晶体管的开关状态以及导通阻抗，以实现该电源向合并输出端输出电流的均流控制，避免由于电源短路、合并输出端电压过高以及输出电流的波动而引起安全隐患，从而实现了对多路电源供电的安全均流控制。
附图说明
为了更清楚地说明本说明书实施例或现有技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本说明书的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种多路电源供电均流电路的连接示意图；
图2是本发明实施例提供的一种门极泄放电路的连接示意图；
图3是本发明实施例提供的一种门极泄放电路的连接示意图；
图4是本发明实施例提供的一种带有采样电路的多路电源供电均流电路的连接示意图；
图5是本发明实施例提供的一种门极驱动电路的连接示意图；
图6是本发明实施例提供的一种多路电源供电均流控制方法的流程图。
附图标记说明：1为电源，11为模组，12为NMOS晶体管，13为门极泄放电路，14为门极驱动电路，15为门极控制处理器，2为合并电源端。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整的描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例，基于本发明实施例，本领域普通技术人员所获得的所有其他实施例，都属于本发明实施例保护的范围。
本实施例提供一种多路电源供电均流电路，请参阅图1，图1为该电路的连接示意图，具体包括：合并输出端2和至少两个电源1；其中，至少两个电源1中的任一个电源均对应设置有均流模组11；均流模组11包括NMOS晶体管12、门极泄放电路13、门极驱动电路14和门极控制处理器15；NMOS晶体管12的源极连接合并输出端2；NMOS(N-Metal-Oxide-Semiconductor，N型金属-氧化物-半导体)晶体管12的漏极连接至少两个电源中与均流模组11对应的电源1的输出端；门极泄放电路13的输入端和门极驱动电路14的驱动端均连接NMOS晶体管12的门极；门极控制处理器15连接门极驱动电路14的控制端；门极控制处理器15还分别采样连接合并输出端2和与均流模组11对应的电源1的输出端。
本实施例采用NMOS晶体管12作为电源1与合并输出端2的导通通道，能够减小导通损耗，方便控制通道的打开程度。
本实施例中，可以同时设置多个均流模组，实现多路电源供电的均流控制。
本实施例中，门极泄放电路13能够快速泄放掉门极驱动电路14的驱动端的电压，从而迅速关断NMOS管，以在出现短路等状况需要快速关断驱动时，通过快速泄放以保护前级电路。
如图2所示为本实施例提供的一种门极泄放电路的连接示意图，包括：第一二极管D1，第一电阻R1，第一电容C1和第一三极管Q1；第一二极管D1的正极连接NMOS晶体管12的门极；第一二极管D1的负极通过第一电容C1接地；第一电阻R1的一端连接NMOS晶体管12的门极，其相对的另一端连接第一三极管Q1的基极；第一三极管Q1的发射极连接第一 二极管D1的负极；第一三极管Q1的集电极接地。
其中，当第一电容C1的值较小时，当门极驱动电路14切断MOS的驱动电压时，门极泄放电路13由于驱动极电压的跌落而迅速动作，泄放掉驱动极电荷量，实现快速关断导通MOS的功能；当第一电容C1的值较大时，该电路还能够实现缓起功能，当门极驱动电路14输出MOS的驱动电压时，缓慢升高驱动极的电压，减小驱动电压对门极的冲击。
如图3所示为本实施例提供的一种门极泄放电路的连接示意图，包括：电压比较器A1、第二电阻R2、第二电容C2和第二三极管Q2；电压比较器A1的正向输入端连接参考电压端；电压比较器A1的反向输入端连接NMOS晶体管的门极；电压比较器A1的输出端连接第二三极管Q2的基极；第二三极管Q2的发射极连接NMOS晶体管的门极；第二三极管Q2的集电极通过第二电容C2和第二电阻R2构成的并联电路接地。
当门极驱动电路14切断MOS的驱动电压时，门极泄放电路13的驱动端的电压迅速跌落，当小于参考电压端的电压时，电压比较器A1会输出高电平，从而导通第二三极管Q2，利用第二电容C2和第二电阻R2构成的并联电路迅速泄放驱动极电压。优选的，电压比较器为LM393双电压比较器。
门极控制处理器15能够采集电源1处的电压和合并输出端2的电压，如图4所示为本实施例提供的一种带有采样电路的多路电源供电均流电路的连接示意图，包括：第三电阻R3、第四电阻R4、第五电阻R5和第六电阻R6；第三电阻R3和第四电阻R4串联在与均流模组11对应的电源1的输出端和地之间；门极控制处理器15的第一采样输入端连接在第三电阻R3和第四电阻R4之间，以实现门极控制处理器15采样连接均流模组11对应的电源1的输出端；第五电阻R5和第六电阻R6串联在合并输出端2和地之间；门极控制处理器15的第二采样输入端连接在第五电阻R5和第六电阻R6之间，以实现门极控制处理器15采样连接合并输出端2。
第三电阻R3、第四电阻R4构成了分压电路，门极控制处理器15通过采集第三电阻R3与第四电阻R4之间的电压，可以获知与均流模组11对应的电源1的输出端的电压。
第五电阻R5和第六电阻R6构成了分压电路，门极控制处理器15通过采集第五电阻R5和第六电阻R6之间的电压，可以获知与均流模组11对应的合并输出端2的电压。
门极控制处理器15根据第三电阻R3、第四电阻R4、第五电阻R5和第六电阻R6，配置等效内阻，然后根据采样电压，计算出均流模组11当前输出的负载电流，并根据该负载电流的大小，对NMOS晶体管12进行导通阻抗控制以及导通关闭控制。
具体的，门极控制处理器15可以使用MCU、单片机等带有采样、控制等功能的电子芯片来实现。
门极驱动电路14用来根据门极控制处理器15输出的控制信号来驱动NMOS晶体管12工作，门极驱动电路可以采用电荷泵模组，电荷泵是一种DC/DC变换器(Direct current-Direct current converter，直流电源-直流电源变换器)，它是利用电容的充电、放电实现电荷转移的原理构成，可以将输入的正电压转换成相应的负电压，也可以把输入电压转换成整数倍的输出电压。当门极驱动电路14接收到门极控制处理器15发出门极控制指令，门极驱动电路14中的电荷泵就会生成相应的驱动电压，并从其驱动端输出给门极，以控制NMOS晶体管的开关状态以及导通阻抗。
当然，还可以使用其他形式的驱动电路来实现门极驱动的功能，图5是本发明实施例提供的一种门极驱动电路的连接示意图，包括：第二二极管D2、第一稳压二极管D3、第二稳压二极管D4、第七电阻R7和第八电阻R8；第二二极管D2的正极连接门极驱动电路14的驱动端；第二二极管D2的负极分别连接NMOS晶体管12的源极和门极驱动电路14的控制端；第七电阻R7与第二二极管D2并联连接；第一稳压二极管D3和第二稳压二极管D4反向串联在门极驱动电路14的驱动端和NMOS晶体管12的源极之间；第八电阻R8串联在门极驱动电路14的驱动端和NMOS晶体管12的源极之间；NMOS晶体管12的源极接地。
其中，第七电阻R7的作用是限流和抑制寄生振荡，第八电阻R8是为在NMOS晶体管12关断时提供放电回路，稳压二极管D3和D4是保护NMOS晶体管12的门极和源极，第二二极管D2是加速NMOS晶体管12 的关断。
如图6所示为本发明实施例提供的一种多路电源供电均流控制方法的流程图，该方法实施例应用在上文所述的多路电源供电均流电路中，包括：
步骤11，获取合并输出端的合并端采样电压和与均流模组对应的电源的输出端的电源端采样电压。
具体的，可以通过分压电路来采集合并端采样电压和电源端采样电压，通过合理的搭配分压电阻，可以实现对不同电源端(例如5V、12V、48V和54V等)的电压采集。
当然还可以利用电压传感器来直接测量获取合并端采样电压和电源端采样电压。
步骤12，根据所述电源端采样电压和所述合并端采样电压，获取所述均流模组输出的等效负载电流。
这里，本发明还给出了一种较优的获取等效负载电流的方案，具体为：
步骤21，根据第三电阻、第四电阻、第五电阻和第六电阻，设定等效内阻r。
具体的，通过合理的设置等效内阻，使电源端采样电压和合并端采样电压能够还原为母线电压，从而计算出等效负载电流。当然，等效内阻的阻值精度不同，均流控制的精度也会不同。
步骤22，计算所述均流模组输出的等效负载电流I，具体的计算公式为：
Figure PCTCN2021103370-appb-000002
其中，U 1为所述电源端采样电压，U 2为所述合并端采样电压。
步骤13，根据所述等效负载电流和设定电流均流值之间的大小关系，调整NMOS晶体管的导通阻抗。
这里，本发明还给出了一种较优的控制方案，具体为：
步骤31，若所述等效负载电流大于所述设定电流均流值，则增大所述NMOS晶体管的导通阻抗。
具体的，当等效负载电流较大时，需要进行均流控制，减小等效负载 电流的大小，本步骤通过降低门极驱动电路的输出的驱动电压，增大NMOS晶体管的导通阻抗，使该电源供应电流能力减弱，但处于随时可再导通状态。
步骤32，若所述等效负载电流小于所述设定电流均流值，则减小所述NMOS晶体管的导通阻抗。
具体的，当等效负载电流较小时，需要进行均流控制，增加等效负载电流的大小，本步骤通过提高门极驱动电路的输出的驱动电压，减小NMOS晶体管的导通阻抗，使该电源供应电流能力减弱，但处于随时可再导通状态。
步骤14，判断所述电源端采样电压与所述合并端采样电压的差值是否大于设定上限阈值或小于0。
具体的，当发生短路故障时，电源端采样电压与合并端采样电压的差值会迅速升高，并超过设定上限阈值，此时通过切断门极驱动电路的输出的驱动电压，及时关断NMOS晶体管，实现对前端电路的保护。
具体的，线路发生异常时，合并端采样电压会大于电源端采样电压，导致电源端采样电压与合并端采样电压的差值小于0，此时需要迅速切断门极驱动电路的输出的驱动电压，及时关断NMOS晶体管，实现对前端电路的保护。
步骤15，若是，则关断所述NMOS晶体管。
具体的，所述关断所述NMOS晶体管之后，所述方法还包括：
步骤41，利用门极泄放电路泄放门极驱动电路的驱动端的电能。
本发明实施例中提供的技术方案，至少具有如下技术效果或优点：
本发明实施例中，为多路电源均配备有均流模组，每个均流模组能够根据电源电压以及合并输出端的电压来调整NMOS晶体管的开关状态以及导通阻抗，以实现该电源向合并输出端输出电流的均流控制，避免由于电源短路、合并输出端电压过高以及输出电流的波动而引起安全隐患，从而实现了对多路电源供电的安全均流控制。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造概念，则可对这些实施例作出另外的变更和修改。所以，所附 权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包括这些改动和变型在内。

Claims (10)

  1. 一种多路电源供电均流电路，其特征在于，包括：合并输出端和至少两个电源；其中，所述至少两个电源中的任一个电源均对应设置有均流模组；
    所述均流模组包括NMOS晶体管、门极泄放电路、门极驱动电路和门极控制处理器；
    所述NMOS晶体管的源极连接所述合并输出端；所述NMOS晶体管的漏极连接所述至少两个电源中与所述均流模组对应的电源的输出端；
    所述门极泄放电路的输入端和所述门极驱动电路的驱动端均连接所述NMOS晶体管的门极；
    所述门极控制处理器连接所述门极驱动电路的控制端；所述门极控制处理器还分别采样连接所述合并输出端和所述与所述均流模组对应的电源的输出端。
  2. 根据权利要求1所述的多路电源供电均流电路，其特征在于，所述门极泄放电路包括：第一二极管，第一电阻，第一电容和第一三极管；
    所述第一二极管的正极连接所述NMOS晶体管的门极；所述第一二极管的负极通过所述第一电容接地；
    所述第一电阻的一端连接所述NMOS晶体管的门极，其相对的另一端连接所述第一三极管的基极；
    所述第一三极管的发射极连接所述第一二极管的负极；所述第一三极管的集电极接地。
  3. 根据权利要求1所述的多路电源供电均流电路，其特征在于，所述门极泄放电路包括：电压比较器、第二电阻、第二电容和第二三极管；
    所述电压比较器的正向输入端连接参考电压端；所述电压比较器的反向输入端连接所述NMOS晶体管的门极；所述电压比较器的输出端连接所述第二三极管的基极；
    所述第二三极管的发射极连接所述NMOS晶体管的门极；所述第二三极管的集电极通过所述第二电容和所述第二电阻构成的并联电路接地。
  4. 根据权利要求1所述的多路电源供电均流电路，其特征在于，所述 均流模组还包括：第三电阻、第四电阻、第五电阻和第六电阻；
    所述第三电阻和所述第四电阻串联在所述与所述均流模组对应的电源的输出端和地之间；
    所述门极控制处理器的第一采样输入端连接在所述第三电阻和所述第四电阻之间，以实现所述门极控制处理器采样连接所述均流模组对应的电源的输出端；
    所述第五电阻和所述第六电阻串联在所述合并输出端和地之间；
    所述门极控制处理器的第二采样输入端连接在所述第五电阻和所述第六电阻之间，以实现所述门极控制处理器采样连接所述合并输出端。
  5. 根据权利要求4所述的多路电源供电均流电路，其特征在于，所述门极驱动电路为电荷泵模组。
  6. 根据权利要求3所述的多路电源供电均流电路，其特征在于，所述电压比较器为LM393双电压比较器。
  7. 一种多路电源供电均流控制方法，其特征在于，所述方法应用在如权利要求1至6任一所述的多路电源供电均流电路中，包括：
    获取合并输出端的合并端采样电压和与均流模组对应的电源的输出端的电源端采样电压；
    根据所述电源端采样电压和所述合并端采样电压，获取所述均流模组输出的等效负载电流；
    根据所述等效负载电流和设定电流均流值之间的大小关系，调整NMOS晶体管的导通阻抗；
    判断所述电源端采样电压与所述合并端采样电压的差值是否大于设定上限阈值或小于0；
    若是，则关断所述NMOS晶体管。
  8. 根据权利要求7所述的多路电源供电均流控制方法，其特征在于，所述根据所述电源端采样电压和所述合并端采样电压，获取所述均流模组输出的等效负载电流，包括：
    根据第三电阻、第四电阻、第五电阻和第六电阻，设定等效内阻r；
    计算所述均流模组输出的等效负载电流I，具体的计算公式为：
    Figure PCTCN2021103370-appb-100001
    其中，U 1为所述电源端采样电压，U 2为所述合并端采样电压。
  9. 根据权利要求7所述的多路电源供电均流控制方法，其特征在于，所述根据所述等效负载电流和设定电流均流值之间的大小关系，调整NMOS晶体管的导通阻抗，包括：
    若所述等效负载电流大于所述设定电流均流值，则增大所述NMOS晶体管的导通阻抗；
    若所述等效负载电流小于所述设定电流均流值，则减小所述NMOS晶体管的导通阻抗。
  10. 根据权利要求7所述的多路电源供电均流控制方法，其特征在于，所述关断所述NMOS晶体管之后，所述方法还包括：
    利用门极泄放电路泄放门极驱动电路的驱动端的电能。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115561662A (zh) * 2022-09-26 2023-01-03 上海芯聆半导体科技有限公司 电源检测电路、电源电路、功放集成电路和音响设备

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112181037B (zh) * 2020-09-07 2023-02-28 苏州浪潮智能科技有限公司 一种多路电源供电均流电路和控制方法
CN113242035B (zh) * 2021-05-08 2023-06-02 上海数明半导体有限公司 基于电容隔离的驱动器电路以及电子设备
CN119602780A (zh) * 2024-11-20 2025-03-11 武汉大全能源技术股份有限公司 一种正压电平转换为负压电平的系统及方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050275372A1 (en) * 2004-06-14 2005-12-15 Crowell Jonathan C Power controller for managing arrays of smart battery packs
CN103731016A (zh) * 2013-12-18 2014-04-16 国网上海市电力公司 一种电源输出用均流电路及其应用
CN106233598A (zh) * 2014-05-30 2016-12-14 松下知识产权经营株式会社 电源装置
CN110768649A (zh) * 2018-07-26 2020-02-07 台达电子工业股份有限公司 功率半导体开关的门极电路及门极驱动电路
CN112181037A (zh) * 2020-09-07 2021-01-05 苏州浪潮智能科技有限公司 一种多路电源供电均流电路和控制方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050275372A1 (en) * 2004-06-14 2005-12-15 Crowell Jonathan C Power controller for managing arrays of smart battery packs
CN103731016A (zh) * 2013-12-18 2014-04-16 国网上海市电力公司 一种电源输出用均流电路及其应用
CN106233598A (zh) * 2014-05-30 2016-12-14 松下知识产权经营株式会社 电源装置
CN110768649A (zh) * 2018-07-26 2020-02-07 台达电子工业股份有限公司 功率半导体开关的门极电路及门极驱动电路
CN112181037A (zh) * 2020-09-07 2021-01-05 苏州浪潮智能科技有限公司 一种多路电源供电均流电路和控制方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115561662A (zh) * 2022-09-26 2023-01-03 上海芯聆半导体科技有限公司 电源检测电路、电源电路、功放集成电路和音响设备

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