WO2022048083A1

WO2022048083A1 - Magnetic random access memory device and method for manufacturing same

Info

Publication number: WO2022048083A1
Application number: PCT/CN2020/140879
Authority: WO
Inventors: 申力杰; 张栋山
Original assignee: 浙江驰拓科技有限公司
Priority date: 2020-09-07
Filing date: 2020-12-29
Publication date: 2022-03-10
Also published as: CN111933790A

Abstract

A magnetic random access memory device and a method for manufacturing same. The device comprises: a substrate, on which a first interlayer dielectric layer and bottom electrode contact parts, which extendingly pass through the first interlayer dielectric layer, are formed; a connection structure above each bottom electrode contact part, the connection structures each comprising a first metal electrode, which is disposed horizontally and is in contact with the bottom electrode contact part, and a second metal electrode, which is located on the first metal electrode, and the cross-sectional width of the second metal electrode being smaller than the cross-sectional width of the first metal electrode; and a magnetic tunnel junction device above each second metal electrode, the cross-sectional width of the magnetic tunnel junction devices being greater than the cross-sectional width of the second metal electrodes. Different types of MTJ etching processes can be satisfied without reducing the size of a through hole on a bottom part, and the processes can be easily implemented.

Description

Magnetic random access memory device and method of making the same

technical field

The present invention relates to the technical field of semiconductor devices, in particular to a magnetic random access memory device and a manufacturing method thereof.

Background technique

In recent years, Magnetic Random Access Memory (MRAM) using the magnetoresistance effect of Magnetic Tunnel Junction (MTJ) is considered to be the future solid-state non-volatile memory, which has high-speed read and write, large capacity and low energy consumption. Features. The MRAM device includes a logic region and a storage region, the logic region is mainly a switching device, the storage region is mainly an MTJ device, and the MTJ device includes a bottom electrode, an MTJ cell and a top electrode.

At present, in the preparation process of MRAM devices, through holes (which can be called bottom through holes) are first opened in the dielectric layer under the bottom electrode and filled with metal (usually copper) to form the interconnect structure of the bottom electrode, and then sequentially deposited The bottom electrode layer and the MTJ structure layer are formed by one photolithography and etching to form the bottom electrode and the MTJ unit. However, as the size of MTJ devices continues to shrink, when etching the MTJ structure layer, especially when a large over-etching or sidewall cleaning process is required, in order to prevent the metal filled in the bottom via from sputtering to the MTJ The sidewall causes the MTJ to be short-circuited. The usual practice is to make the bottom through hole correspondingly smaller. Although this method can meet the conditions of the existing process, the small size of the bottom through hole is very difficult for lithography and etching. Strict requirements are difficult to achieve, and the process cost is bound to increase.

SUMMARY OF THE INVENTION

In view of this, the present invention provides a magnetic random access memory device and a manufacturing method thereof, which can meet different types of MTJ etching processes without reducing the size of the bottom through hole, and reduce the large amount of damage during the MTJ etching process. Short circuit problems caused by over-etching or sidewall cleaning.

In a first aspect, the present invention provides a magnetic random access memory device, comprising:

a substrate, on which a first interlayer dielectric layer is formed;

a bottom electrode contact extending through the first interlayer dielectric layer;

a connection structure above each of the bottom electrode contacts, the connection structure comprising a horizontally disposed first metal electrode in contact with the bottom electrode contact and a second metal electrode on the first metal electrode, The cross-sectional width of the second metal electrode is smaller than the cross-sectional width of the first metal electrode;

A magnetic tunnel junction device above each of the second metal electrodes, the cross-sectional width of the magnetic tunnel junction device is greater than that of the second metal electrode.

Optionally, the second metal electrode is a vertical structure with a height greater than a cross-sectional width.

Optionally, the magnetic tunnel junction device includes a sequentially stacked bottom electrode, a magnetic tunnel junction unit, and a metal hard mask.

Optionally, the second metal electrode is surrounded by a second interlayer dielectric layer.

Optionally, a third interlayer dielectric layer surrounds the second interlayer dielectric layer and the first metal electrode.

Optionally, the material of the first metal electrode is one of tungsten nitride, titanium nitride and tantalum nitride.

Optionally, the material of the second metal electrode is one of tungsten, titanium and tantalum.

Optionally, an etch stop layer is formed on the substrate, and the etch stop layer is located under the first interlayer dielectric layer.

In a second aspect, the present invention provides a method for manufacturing a magnetic random access memory device, comprising:

providing a substrate on which a first interlayer dielectric layer is formed and forming a bottom electrode contact extending through the first interlayer dielectric layer;

A connection structure is formed on each of the bottom electrode contacts, and the connection structure includes a horizontally disposed first metal electrode in contact with the bottom electrode contact portion and a second metal electrode located on the first metal electrode, The cross-sectional width of the second metal electrode is smaller than the cross-sectional width of the first metal electrode;

A magnetic tunnel junction device is formed on each of the second metal electrodes, and the cross-sectional width of the magnetic tunnel junction device is larger than that of the second metal electrode.

Optionally, wherein forming a connection structure on each of the bottom electrode contact portions includes:

depositing a first metal electrode layer and a second metal electrode layer in sequence;

A mask pattern of the second metal electrode is obtained by a photolithography process, and the second metal electrode layer is etched with the obtained mask pattern to form a second metal electrode;

depositing a second interlayer dielectric layer to surround the second metal electrode;

Etching the second interlayer dielectric layer and the first metal electrode layer until the upper surface of the first interlayer dielectric layer is exposed to obtain an island-like structure arranged in isolation;

depositing a third interlayer dielectric layer to surround the island structure;

A planarization process is performed until the top of the second metal electrode is exposed.

Optionally, in the etching of the second interlayer dielectric layer and the first metal electrode layer, the etching process used is dry etching, reactive ion etching or wet etching.

Optionally, for the deposition of the second interlayer dielectric layer and the deposition of the third interlayer dielectric layer, the deposition process used is plasma enhanced chemical vapor deposition, physical vapor deposition or electron beam evaporation process.

Optionally, wherein forming a magnetic tunnel junction device on each of the second metal electrodes includes:

depositing a bottom electrode layer and a magnetic tunnel junction structure layer;

forming a patterned metal hard mask on the magnetic tunnel junction structure layer;

Using the metal hard mask as an etching mask, the magnetic tunnel junction structure layer, the bottom electrode layer, the second interlayer dielectric layer and the third interlayer dielectric layer are etched.

The present invention provides a magnetic random access memory device and a manufacturing method thereof. A connection structure is formed above the bottom electrode contact portion and below the MTJ bottom electrode. The connection structure includes a first metal electrode and a second metal electrode, and the second metal electrode has The advantages of flexible and adjustable height and diameter can well match various types of MTJ etching processes, especially suitable for processes with large over-etching or sidewall cleaning during MTJ etching, which can reduce the cost of MTJ etching process. The problem of short circuit in the device is improved, and the yield of the device is improved. And it is also easier to implement in the process.

Description of drawings

FIG. 1 is a schematic cross-sectional structural diagram of a magnetic random access memory device according to an embodiment of the present invention;

2 to 10 are schematic cross-sectional structural diagrams corresponding to each step of a method for manufacturing a magnetic random access memory device according to an embodiment of the present invention.

detailed description

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under" the other layer/element.

FIG. 1 shows a schematic cross-sectional structure diagram of a magnetic random access memory device according to an example embodiment.

Referring to FIG. 1 , a magnetic random access memory device may be formed on a provided substrate 100 . Specifically, an etch stop layer 101 , a first interlayer dielectric layer 102 , a bottom electrode contact portion 103 extending through the etch stop layer 101 and the first interlayer dielectric layer 102 are formed on the substrate 100 . Connection structures 104 over the bottom electrode contact 103 and a magnetic tunnel junction device (MTJ device) 105 over each connection structure 104 .

The substrate 100 may include semiconductor materials such as silicon, germanium, and silicon germanium, on which various types of circuit patterns, such as transistors, underlying metal wiring, and the like, are pre-formed. The etching stop layer 101 is used as a stop layer for the etching process when the via hole is formed subsequently, and is generally silicon nitride (SiN). The first interlayer dielectric layer 102 is formed on the etch stop layer 101 and may include silicon oxide or a low-k dielectric material with a dielectric constant lower than that of silicon oxide (ie, less than about 3.9), such as polyethyl silicate (TEOS) .

Bottom electrode contacts 103 may be filled in openings extending through the etch stop layer 101 and the first interlayer dielectric layer 102 . The bottom electrode contact portion 103 includes a metal with low resistance, such as tungsten, copper, aluminum, etc., copper is usually used. In order to prevent the diffusion of copper, there is a diffusion barrier layer (not shown in the figure) under the metal, such as TaN, Ta and so on. The bottom electrode contact 103 may contact the metal wiring on the substrate 100 .

The connection structure 104 may include a first metal electrode 1041 and a second metal electrode 1042. The first metal electrode 1041 is horizontally disposed on the bottom electrode contact portion 103 and in contact with the bottom electrode contact portion 103. The cross-sectional width of the first metal electrode 1041 is larger than that of the bottom electrode contact portion 103. The cross-sectional width of the electrode contact portion 103. The second metal electrode 1042 is disposed on the first metal electrode 1041 and extends vertically upward from the upper surface of the first metal electrode 1041. The second metal electrode 1042 can be cylindrical or cylindrical, usually The cross-sectional width gradually decreases from bottom to top, and the cross-sectional width of the second metal electrode 1042 is smaller than that of the first metal electrode 1041 . The first metal electrode 1041 and the second metal electrode 1042 use different metal materials, for example, the first metal electrode 1041 can be metal nitride, such as tungsten nitride, titanium nitride, and tantalum nitride. The second metal electrode 1042 may be a metal such as tungsten, titanium, tantalum, and the like. A second interlayer dielectric layer 1043 surrounds the second metal electrode 1042 , and the edge of the second interlayer dielectric layer 1043 is flush with the edge of the first metal electrode 1041 . The third interlayer dielectric layer 1044 surrounds the second interlayer dielectric layer 1043 and the first metal electrode 1041 to form a structure isolated from each other. The materials of the second interlayer dielectric layer 1043 and the third interlayer dielectric layer 1044 may be the same or different, and are usually low-k dielectric materials such as polyethyl silicate (TEOS).

The MTJ device 105 may include a sequentially stacked bottom electrode 1051 , an MTJ cell 1052 and a metal hard mask 1053 formed by one etching. The cross-sectional width of the MTJ device 105 is greater than the cross-sectional width of the second metal electrode 1042 . The bottom electrode 1051 may include tantalum nitride, tantalum, titanium nitride, titanium, or the like. The MTJ unit 1052 is a stacked structure including at least a free layer, a barrier layer, and a reference layer.

By applying the magnetic random access memory device provided by the embodiment of the present invention, a connection structure including a first metal electrode and a second metal electrode is added between the bottom electrode contact portion and the bottom electrode of the MTJ device, and the size of the second metal electrode can be It is very small. When forming a magnetic tunnel junction device over the second metal electrode, even if a large over-etching or sidewall cleaning process is used, regardless of the size of the bottom via, the metal of the bottom via will not be sputtered. The sidewall of the MTJ device reduces the short circuit problem of the device during the MTJ etching process and improves the device yield. And it is also easier to implement in the process.

2 to 10 illustrate cross-sectional structural views of some stages of a method of fabricating a magnetic random access memory device according to example embodiments.

Referring to FIG. 2, a substrate 200 is provided, an etch stop layer 201 and a first interlayer dielectric layer 202 are sequentially formed by deposition on the substrate 200, and an etch stop layer 201 and the first interlayer dielectric layer 202 are formed extending through the etch stop layer 201 and the first interlayer dielectric layer 202. bottom electrode contact 203.

The substrate 200 has been previously formed with various types of circuit patterns, such as transistors, underlying metal wirings, and the like. The etching stop layer 201 generally uses silicon nitride (SiN); the first interlayer dielectric layer 202 generally uses polyethyl silicate (TEOS).

An etch mask is formed on the first interlayer dielectric layer 202 , and the etch mask can be used to anisotropically etch the first interlayer dielectric layer 202 and the etch stop layer 201 , so as to form a surface that exposes the upper surface of the substrate 200 . The first opening. The height of the first opening is generally controlled at 100 nm, and should not be too high. The anisotropic etching process may include a chemical etching process, such as a reactive ion etching (RIE) process.

A diffusion barrier layer (not shown) is formed on the inner surface of the first opening and the upper surface of the first interlayer dielectric layer 202 , and a bottom conductive layer is formed on the diffusion barrier layer to fill the first opening. The diffusion barrier layer and the bottom conductive layer are then planarized until the upper surface of the first interlayer dielectric layer is exposed, thereby forming a bottom electrode contact 203 within the first opening. The diffusion barrier layer can be Ta or TaN, and the bottom conductive layer can be copper (Cu).

Referring to FIG. 3 , a first metal electrode layer 204 and a second metal electrode layer 205 are sequentially deposited on the bottom electrode contact portion 203 . The thickness is preferably 100 nm, and the thickness is adjustable depending on the process. The first metal electrode layer 204 and the second metal electrode layer 205 use different metal materials to obtain controllable etching endpoint control. For example, the first metal electrode layer 204 preferably uses metal nitrides such as tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), and the like. The second metal electrode layer 205 preferably uses a corresponding metal, such as tungsten, titanium, tantalum and other metals, that is to say, the first metal electrode layer/second metal electrode layer can be, for example, a combination of TaN/Ta, a combination of TiN/Ti such as Structure. The materials used in the two can be interchanged up and down.

Referring to FIG. 4 , an etching mask pattern is formed on the second metal electrode layer 205 using a photolithography process, and the second metal electrode layer 205 is etched by using the etching mask pattern to form a second metal electrode 205a. The formed second metal electrode 205a may be cylindrical, and the diameter gradually increases from top to bottom. The first metal electrode layer 204 can prevent upward sputtering of the bottom metal (eg, Cu) during the etching process. It is worth noting that when the second metal electrode layer 205 is etched, only the second metal electrode layer 205 is etched and the optical emission spectroscopy (OES) system is used to reasonably stop the etching end point at the first metal electrode layer 204. upper surface. Since the first metal electrode layer 204 and the second metal electrode layer 205 use different metal materials, an optical emission spectroscopy (OES) system can be used to perform appropriate endpoint judgment during etching.

Referring to FIG. 5, a second interlayer dielectric layer 206 is deposited around the formed second metal electrode 205a. The second interlayer dielectric layer 206 is a material with low dielectric constant. Preferably, the second interlayer dielectric layer 206 uses polyethyl silicate (TEOS). The second interlayer dielectric layer 206 is preferably deposited by plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) or electron beam evaporation.

Referring to FIG. 6 , the second interlayer dielectric layer 206 and the first metal electrode layer 204 are continuously etched until the upper surface of the first interlayer dielectric layer 203 is exposed to form an independent island-like structure. Each island structure includes a first metal electrode 204a formed, a second metal electrode 205a located on the first metal electrode 204a, and an interlayer dielectric layer 206a surrounding the second metal electrode 205a. The edge of a metal electrode 204a is flush. The used etching process is dry etching, reactive ion etching or wet etching. Wherein, the determination of the etching end point is still performed by using an optical emission spectroscopy (OES) system, so that the first metal electrode layer 204 is completely etched and the bottom through hole is not contacted.

Referring to FIG. 7 , a third interlayer dielectric layer 207 is deposited, and the third interlayer dielectric layer 207 completely surrounds the previously formed island-like structure. The third interlayer dielectric layer 207 and the second interlayer dielectric layer 206 may use the same or different materials. Similarly, the third interlayer dielectric layer 207 is preferably deposited by plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) or electron beam evaporation.

Referring to FIG. 8 , a planarization process is performed, while the second interlayer dielectric layer 206a and the third interlayer dielectric layer 207 are flattened, and the top of the second metal electrode 205a is exposed. A planarization process, including chemical mechanical polishing, or other processes such as reactive ion etching, removes a portion of the third interlayer dielectric layer and a portion of the second interlayer dielectric layer to expose the second metal electrode 205a.

Referring to FIG. 9 , a bottom electrode layer 208 , a magnetic tunnel junction structure layer 209 are sequentially deposited on the flat surface above the formed second metal electrode 205 a , and a patterned metal hard mask 210 a is formed over the magnetic tunnel junction structure layer 209 . Preferably, the bottom electrode layer 208 is tantalum nitride (TaN). The material of the metal hard mask 210a may also be composed of one or more layers of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W) or ruthenium (Ru). material composition.

Referring to FIG. 10 , etching is performed using the metal hard mask 210 a as an etching mask, and the magnetic tunnel junction structure layer, the bottom electrode layer, the second interlayer dielectric layer and the third interlayer dielectric layer are etched. The bottom electrode 208a, the magnetic tunnel junction unit 209a and the metal hard mask 210a formed after etching constitute an independent magnetic tunnel junction device. In particular, when etching the magnetic tunnel junction structure layer 209, a large over-etching can be used, and due to the existence of the second metal electrode 205a, the metal in the bottom through hole will not be sputtered to the magnetic field during the etching process. sidewall of the tunnel junction.

By applying the manufacturing method of the magnetic random access memory device provided by the embodiment of the present invention, without reducing the size of the bottom through hole, it can meet different types of MTJ etching processes, and reduce the large over-etching or large over-etching during the MTJ etching process. Short circuit problems caused by sidewall cleaning.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

A magnetic random access memory device, comprising:

a substrate, on which a first interlayer dielectric layer is formed;

a bottom electrode contact extending through the first interlayer dielectric layer;

a connection structure above each of the bottom electrode contacts, the connection structure comprising a horizontally disposed first metal electrode in contact with the bottom electrode contact and a second metal electrode on the first metal electrode, The cross-sectional width of the second metal electrode is smaller than the cross-sectional width of the first metal electrode;

A magnetic tunnel junction device above each of the second metal electrodes, the cross-sectional width of the magnetic tunnel junction device is greater than that of the second metal electrode.
The magnetic random access memory device of claim 1, wherein the second metal electrode is a vertical structure with a height greater than a cross-sectional width.
The magnetic random access memory device of claim 1, wherein the magnetic tunnel junction device comprises a sequentially stacked bottom electrode, a magnetic tunnel junction unit, and a metal hard mask.
The magnetic random access memory device according to claim 1, wherein the second metal electrode is surrounded by a second interlayer dielectric layer.
The magnetic random access memory device according to claim 4, wherein the second interlayer dielectric layer and the first metal electrode are surrounded by a third interlayer dielectric layer.
The magnetic random access memory device according to claim 1, wherein the material of the first metal electrode is one of tungsten nitride, titanium nitride and tantalum nitride.
The magnetic random access memory device according to claim 1, wherein the material of the second metal electrode is one of tungsten, titanium and tantalum.
The magnetic random access memory device according to claim 1, wherein an etch stop layer is formed on the substrate, and the etch stop layer is located under the first interlayer dielectric layer.
A method for manufacturing a magnetic random access memory device, comprising:

providing a substrate on which a first interlayer dielectric layer is formed and forming a bottom electrode contact extending through the first interlayer dielectric layer;

A connection structure is formed on each of the bottom electrode contacts, and the connection structure includes a horizontally disposed first metal electrode in contact with the bottom electrode contact portion and a second metal electrode located on the first metal electrode, The cross-sectional width of the second metal electrode is smaller than the cross-sectional width of the first metal electrode;

A magnetic tunnel junction device is formed on each of the second metal electrodes, and the cross-sectional width of the magnetic tunnel junction device is larger than that of the second metal electrode.
9. The method of claim 9, wherein forming a connection structure on each of the bottom electrode contacts comprises:

depositing a first metal electrode layer and a second metal electrode layer in sequence;

A mask pattern of the second metal electrode is obtained by a photolithography process, and the second metal electrode layer is etched with the obtained mask pattern to form a second metal electrode;

depositing a second interlayer dielectric layer to surround the second metal electrode;

Etching the second interlayer dielectric layer and the first metal electrode layer until the upper surface of the first interlayer dielectric layer is exposed to obtain an island-like structure arranged in isolation;

depositing a third interlayer dielectric layer to surround the island structure;

A planarization process is performed until the top of the second metal electrode is exposed.
The method according to claim 10, wherein the etching process of the second interlayer dielectric layer and the first metal electrode layer is dry etching, reactive ion etching or wet etching. Etching.
The method according to claim 10, wherein the deposition of the second interlayer dielectric layer and the deposition of the third interlayer dielectric layer are performed by plasma enhanced chemical vapor deposition, physical vapor deposition or electron deposition. Beam evaporation process.
9. The method of claim 9, wherein forming a magnetic tunnel junction device on each of the second metal electrodes comprises:

depositing a bottom electrode layer and a magnetic tunnel junction structure layer;

forming a patterned metal hard mask on the magnetic tunnel junction structure layer;

Using the metal hard mask as an etching mask, the magnetic tunnel junction structure layer, the bottom electrode layer, the second interlayer dielectric layer and the third interlayer dielectric layer are etched.