TWI791214B - Integrated circuit device and method for fabricating the same - Google Patents

Abstract

In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

Description

Integrated circuit element and its manufacturing method

Embodiments of the disclosure relate to an integrated circuit device and a manufacturing method thereof.

In the manufacture of integrated circuits (ICs), components are formed on a wafer and connected by conductive interconnect layers. These conductive interconnect layers may be formed during so-called mid-line (MOL) or back-end-of-line (BEOL). Mid-line and back-end processes are similar in that they both form openings in the dielectric layer (eg, contact holes, trenches, or vias in the dielectric layer) and then fill these openings with conductive material. Mid-end process differs from back-end process in that mid-end process usually occurs early in the manufacturing process and can refer to a process in which contacts are made directly above or adjacent to device structures such as gate electrodes or source/drain regions; while back-end Processing typically occurs late in the manufacturing process and may refer to processes that form continuous metallization layers and vias over contacts formed in mid-process.

The disclosure provides an integrated circuit device including a transistor structure, a lower interlayer dielectric layer, and a gate capping layer. The transistor structure is disposed on the substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. The lower interlayer dielectric layer is disposed on the pair of source/drain regions and surrounds the gate electrode, and the gate electrode is recessed from the top of the lower interlayer dielectric layer. Gate The capping layer is disposed on the gate electrode, wherein the gate capping layer has a top surface aligned with the top surface of the lower interlayer dielectric layer.

The present disclosure provides an integrated circuit device including a transistor structure, a gate capping layer, a lower etch stop layer, and lower source/drain contacts. The transistor structure is disposed on the substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. The gate covering layer is disposed on the gate electrode. The lower etch stop layer lines the sidewalls of the gate electrode and the gate capping layer. A lower source/drain contact is provided on the opposite side of the etch stop layer below the gate electrode and reaches on the source/drain region of the pair of source/drain regions.

The present disclosure provides a method of manufacturing an integrated circuit device, the method comprising forming a transistor structure on a substrate, the transistor structure comprising a pair of source/drain regions and a gate between the pair of source/drain regions pole electrode; form a lower etch stop layer and a lower interlayer dielectric layer on the pair of source/drain regions, and surround the gate electrode; recess the gate electrode, and form a gate capping precursor layer on the recessed gate electrode; form a lower source/drain contact on one of the pair of source/drain regions; replace the gate capping precursor layer with a gate capping layer having a thickness less than the dielectric constant of the dielectric constant of the gate capping precursor layer; forming an upper ILD layer over the lower ILD layer and the gate capping layer; and forming a gate contact through the upper ILD layer and the gate capping layer layer, and reaches the gate electrode.

101: Transistor structure

102: Substrate

103: source/drain region

104: gate electrode

105: gate dielectric layer

106: side wall spacer

108: lower etch stop layer

110: lower interlayer dielectric layer

114a: first contact covering layer

114a': first contact covering precursor layer

114b: second contact covering layer

116:Gate cover layer

116': gate covering precursor layer

118: opening

120: Lower source/drain contact

122: opening

124: Source/drain capping layer

126: upper etch stop layer

128: upper interlayer dielectric layer

130: opening

132: opening

134: opening

136: opening

137: Upper source/drain contact

138: metal core

139: Gate electrode contact

141: body contact

141a: Part I

141b: Part II

142: Lower contact structure

142a: First Lower Contact Structure

142b: second lower contact structure

144: upper contact structure

144a: first upper contact structure

144b: second upper contact structure

152: action

154: action

156: action

158: action

160: action

162: action

400: Section View

404: Dummy gate

500:Section View

600: Section view

700: Section view

800: Section view

900: Section view

1000: Section view

1100: Section view

1200: Section view

1300: Section view

1400: Section view

1500: Sectional view

1600: Section view

1700: Sectional view

1800: method

1802: action

1804: action

1806: action

1808: action

1810: action

1812: action

1814: action

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It is noted that, in accordance with the standard practice in the industry, many features are not drawn to scale. In fact, each can be increased or decreased arbitrarily Dimensions of features for clarity of discussion.

1A-1E show various cross-sectional views of some additional embodiments of integrated circuit devices with contact covering layers.

2 is a perspective view of some embodiments of an integrated circuit device with a contact cover layer.

3A-3G are a series of cross-sectional views and flow diagrams illustrating some embodiments of methods of forming integrated circuit devices with contact covering layers.

4-17 are cross-sectional views illustrating some embodiments of methods of forming integrated circuit devices with contact covering layers.

18 is a flowchart illustrating some embodiments of a method of forming an integrated circuit device with a contact cover layer.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are of course only examples and not limitations. For example, in the description, the process of forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, or may include an embodiment in which additional features are formed on the first feature and the second feature. Between the features, so that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference symbols and/or letters in various instances. This repetition is for the purposes of brevity and clarity and does not inherently dictate the relationship between the various embodiments and/or configurations discussed.

In addition, terms of spatial relationship may be used here, such as "beneath", "below", "lower", "Above," "upper," and similar terms, are used to briefly describe the relationship of one element or feature to another (other) element or feature as depicted in the drawing . The terms of these spatial relationships are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. A device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be construed accordingly.

In a mid-line-of-line (MOL) interconnect structure, contact and interconnection vias and metal lines play important roles in both transistor and circuit performance. As dimensions continue to shrink, the distance between various contact and interconnect features shrinks, along with leakage current and parasitic capacitance, becoming key limiting factors for device performance. It is desirable to reduce or prevent leakage currents in contacts and other conductive features, while limiting increases in resistance and capacitance.

Accordingly, the present disclosure relates to integrated circuit devices and related fabrication methods having improved mid-line interconnect structures to protect contacts, reduce contact resistance, and also improve parasitic capacitance. Therefore, the reliability of the device is improved, and the manufacturing process is simplified. In some embodiments, the integrated circuit device includes a transistor structure disposed on a substrate, and the transistor structure includes a pair of source/drain regions disposed on the substrate, and a pair of source/drain regions located on the pair of source/drain regions. between the gate electrodes. A lower interlayer dielectric layer (ILD) is disposed above the pair of source/drain regions and surrounds the gate electrode. The gate electrode may be recessed from the top surface of the lower interlayer dielectric layer. The gate capping layer may be disposed on the recessed gate electrode and may have a top surface aligned or coplanar with the top surface of the underlying interlayer dielectric layer. By recessing the gate electrode and providing a gate cover, the gate electrode is isolated and protected from adjacent conductive features, thereby reducing or eliminating leakage problems. In some embodiments, The gate capping layer comprises an oxide material or a low-κ dielectric material, thereby keeping the parasitic capacitance small. In some further embodiments, the integrated circuit device further includes a lower source/drain contact disposed on the first source/drain region of the pair of source/drain regions. The lower source/drain contacts may also be recessed from the top. A source/drain capping layer may be provided over the recessed underlying source/drain contacts to protect and isolate the underlying source/drain contacts from adjacent conductive features. Therefore, leakage problems can be further reduced or eliminated. The source/drain capping layer comprises the same or different dielectric material as the gate capping layer.

1A-1E illustrate various cross-sectional views of integrated circuit devices according to some embodiments. As shown in FIGS. 1A to 1E , in some embodiments, a transistor structure 101 is disposed on a substrate 102 . In various embodiments, the substrate 102 can be any type of semiconductor body (for example, silicon, silicon germanium, silicon-on-insulator, etc.), such as a semiconductor wafer and/or one or more dies on the wafer, and Any other type of semiconductor layer, epitaxial layer, or dielectric layer associated therewith. The transistor structure 101 may be a logic element including a gate electrode 104 separated from the substrate 102 by a gate dielectric layer 105 . A pair of source/drain regions 103 are disposed on opposite sides of the gate electrode 104 in the substrate 102 . The transistor structure 101 can be a single-gate planar device or a multi-gate device, such as a FinFET device. The transistor structure 101 can also be other elements, such as gate all-around (GAA) elements, Ω (omega)-shaped gate elements, or π (pi)-shaped gate elements, as well as strained semiconductor elements, silicon-on-insulator (SOI) ) devices, partially depleted silicon-on-insulator (PD-SOI) devices, fully depleted silicon-on-insulator (FD-SOI) devices, or other suitable devices.

The contacts are respectively coupled to gate electrode 104 , source/drain regions 103 , body contact regions, or other active regions of transistor structure 101 . In some embodiments, the contact may include a lower contact structure 142 surrounded by a lower interlayer dielectric (ILD) layer 110 and/or surrounded by an upper interlayer dielectric (ILD) layer 128 and disposed on the lower ILD layer 110 The above contact structure 144 . Contacts may include metal cores 138 and barrier layers not shown. In some embodiments, metal core 138 includes or consists of tungsten, cobalt, ruthenium, titanium nitride, tantalum nitride, or other suitable metals. The barrier layer acts as an adhesive and a barrier layer to bond the metal core, thereby preventing void formation and preventing the metal core 138 from diffusing into the lower ILD layer 110 and/or the upper ILD layer 128 . In some embodiments, the barrier layer has a thickness of about 2 nm to about 10 nm. The lower etch stop layer 108 may be disposed along and lining the sidewalls of the lower ILD layer 110 .

In some embodiments, the upper etch stop layer 126 may be disposed between the upper ILD layer 128 and the lower ILD layer 110 . The lower etch stop layer 108 and the upper etch stop layer 126 may comprise a different dielectric material than the lower ILD layer 110 and the upper ILD layer 128 , respectively. For example, the lower etch stop layer 108 and the upper etch stop layer 126 may respectively comprise silicon nitride or silicon carbide, and may have a thickness of about 3 nm to about 10 nm.

In some embodiments, the gate electrode 104 is recessed from the top of the lower ILD layer 110 . The gate capping layer 116 is disposed on the gate electrode 104 . The gate capping layer 116 may have a top surface aligned or coplanar with the top surface of the lower ILD layer 110 . For example, the recessed gate electrode 104 may have a thickness of about 10 nm to about 20 nm. The gate capping layer 116 may have approximately 20nm to about 40nm thickness. In some embodiments, the gate capping layer 116 includes silicon dioxide or a low-κ dielectric material. Silicon dioxide has a dielectric constant of about 3.9, while low-κ dielectric materials have a dielectric constant of less than 3. For example, the gate capping layer 116 may comprise a carbon-doped oxide composed of silicon, carbon, oxygen, and hydrogen (silicon carbon oxyhydroxide (SiCOH), low hydrogen silicon oxycarbide nitride (SiOCN), Silicon oxycarbide (SiOC), or other suitable low-κ dielectric constant. Compared to using a semiconductor or dielectric material with a higher dielectric constant, such as silicon, which has a dielectric constant of about 11.7, or silicon nitride, which has a dielectric constant of about 7 to about 8, the relative A small dielectric constant helps reduce the parasitic capacitance of integrated circuit components.

In some embodiments, the lower contact structure 142 includes a lower source/drain contact 120 disposed on the source/drain region of the pair of source/drain regions 103 . In some embodiments, the lower source/drain contacts 120 fill in the trenches between the sidewalls of the lower etch stop layer 108 and directly contact the sidewalls of the lower etch stop layer 108 .

In some embodiments, the upper contact structure 144 includes an upper source/drain contact 137 passing through the upper ILD layer 128 onto the source/drain region of the source/drain region pair 103 . In some alternative embodiments, the upper source/drain contact 137 may be disposed on the lower source/drain contact 120 and electrically coupled to the source/drain region 103 through the lower source/drain contact 120 on the source/drain region. In some embodiments, the upper contact structure 144 further includes a gate electrode contact 139 disposed beside the upper source/drain contact 137 and passing through the upper ILD layer 128 . The gate electrode contact 139 can pass through the gate capping layer 116 to be electrically coupled to the gate electrode 104 . Gate electrode 104 may contain A stack of metal layers including a work function metal disposed on the core gate metal. Gate electrode contact 139 may comprise or consist of the same material as upper source/drain contact 137 . The upper contact structure 144 may also include a body contact 141 including a first portion 141a electrically coupled to one of the source/drain regions 103 through the lower source/drain 120 and electrically coupled to the gate electrode 104. The second part 141b. In some embodiments, body contact 141 comprises or consists of the same material as upper source/drain contact 137 and gate electrode contact 139 .

Upper contact structures 144, such as upper source/drain contacts 137, gate electrode contacts 139, and body contacts 141, may be provided between underlying conductive features, such as gate electrodes 104 and lower source/drain contacts 120, respectively. Concave on top surface to improve landing and reduce contact resistance. The upper contact structures 144 may each have lateral dimensions that approximate those of the underlying conductive features to achieve low resistance. For example, the bottom lateral dimension of upper source/drain contact 137 may be substantially equal to, for example, larger or smaller than the top lateral dimension of lower source/drain contact 120 in the range of about 3 nm to about 5 nm. The bottom lateral dimension of gate electrode contact 139 may be substantially equal to, for example, greater or less than the top lateral dimension of gate electrode 104 in the range of about 3 nm to about 5 nm. The slope angle of the upper source/drain contact 137 and the gate electrode contact 139 from the side of the integrated circuit device may be about 86° to about 89°. As a result, in a limited space, the lower contact structure 142 can be configured to be effectively isolated from the upper contact structure 144 while maximizing the lateral dimension to prevent leakage problems while minimizing resistance.

As shown in Figure 1A and Figure 1C, in some embodiments, the lower source The pole/drain contact 120 has a top surface that is aligned or coplanar with the top surface of the lower etch stop layer 108 . The upper etch stop layer 126 can be directly disposed on the gate capping layer 116 and the lower source/drain contacts 120 .

As shown in FIGS. 1B, 1D, and 1E, in some alternative embodiments, the lower source/drain contact 120 is recessed from the lower etch stop layer 108, and the source/drain capping layer 124 is disposed in the recessed source/drain contacts 120 below. The source/drain capping layer 124 may have a top surface aligned or coplanar with the top surface of the gate capping layer 116 , which may further be aligned or coplanar with the top surface of the lower etch stop layer 108 . For example, the recessed source/drain contact 120 may have a thickness of about 30 nm to 60 nm. The source/drain capping layer 124 may have a thickness of about 5 nm to about 25 nm. In some embodiments, the source/drain capping layer 124 may have sidewall surfaces in direct contact with the upper source/drain contact 137 and a bottom surface in direct contact with the lower source/drain contact 120 . For example, the source/drain capping layer 124 may include or consist of silicon nitride, silicon carbide, combinations thereof, or the like. In some embodiments, the source/drain capping layer 124 may have a thickness of about 5 nm to about 25 nm. The height of the source/drain contact 120 and the recessed gate electrode 104 under the recess, and the thickness of the gate capping layer 116 and the source/drain capping layer 124 can be varied. For example, as shown in FIGS. 1B and 1D , the source/drain contact 120 may be higher than the gate electrode 104 under the recess, and the source/drain capping layer 124 may be thinner than the gate capping layer 116 . Alternatively, as shown in FIG. 1E , the recessed source/drain contact 120 may be lower than the gate electrode 104 , and the source/drain capping layer 124 may be thicker than the gate capping layer 116 .

In some embodiments, the upper etch stop layer 126 is disposed on the gate capping layer 116 and source/drain capping layer 124 . The bottom surface of the upper etch stop layer 126 can contact the gate capping layer 116 and the source/drain capping layer 124 . For example, the upper etch stop layer 126 may include or consist of aluminum oxide, silicon nitride, or other suitable dielectric materials. In some embodiments, the upper interlayer dielectric layer 128 may include or be made of, for example, plasma-enhanced chemical vapor deposition oxide, flowable chemical vapor deposition oxide, tetraethoxysilane (TEOS) oxide, undoped Silicon glass, or doped silica such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and/or or other suitable dielectric materials. In some examples, the upper ILD layer 128 may include the same dielectric material as the lower ILD layer 110 . In this example, upper etch stop layer 126 may comprise a non-oxide dielectric material such as silicon nitride. In some examples, upper etch stop layer 126 has a thickness of about 3 nm to about 20 nm, and upper interlayer dielectric layer 128 has a thickness of about 5 nm to about 40 nm.

In some embodiments, the sidewall spacer 106 is disposed beside the gate electrode 104 . As shown in FIGS. 1A and 1B , the sidewall spacer 106 may have a top surface that is aligned or coplanar with the top surface of the gate electrode 104 . The gate capping layer 116 can be disposed on both the gate electrode 104 and the sidewall spacers 106 . Alternatively, the sidewall spacer 106 may have a top surface higher than that of the gate electrode 104 . As shown in FIGS. 1C and 1D , the top surfaces of the sidewall spacers 106 may be aligned or coplanar with the top surfaces of the lower etch stop layer 108 . The gate capping layer 116 may be disposed between upper portions of the sidewall spacers 106 . As shown in FIG. 1E , the top surface of the sidewall spacer 106 can also be located between the recessed gate electrode 104 and the lower surface. between the top surfaces of the etch stop layer 108 . The gate capping layer 116 may be disposed between upper portions of the sidewall spacers 106 and extend above the top surfaces of the sidewall spacers 106 .

FIG. 2 is a perspective view of an integrated circuit element with a contact cover layer according to some additional embodiments. In some embodiments, the integrated circuit device includes a FinFET device, a nanowire device, or other gate all around (GAA) device. The substrate 102 may include a lower base and a plurality of upper pillars erected from the lower base. The pillars extend along the length of the channel and are arranged parallel to each other. The epitaxial semiconductor layer can be disposed on a plurality of upper pillars of the substrate 102, and can include a highly doped portion on the opposite side as the source/drain region 103, and an intervening source/drain region as the channel region. Lowly doped or undoped portions between regions 103 . A conductive layer serving as the gate electrode 104 can be provided on the channel region, can be separated from the channel region by a gate dielectric layer, and can be configured to control current flow in the channel region. The gate electrode 104 may extend along a channel width direction perpendicular to the channel length direction. The gate electrode 104 may extend to surround the sidewalls surrounding the channel region. As discussed with respect to the figures above, in some embodiments, a gate capping layer 116 is disposed on the gate electrode 104 . The gate capping layer 116 may have a top surface that is aligned or coplanar with the top surface of the lower etch stop layer 108 . In other embodiments, the source/drain capping layer 124 is disposed on the lower source/drain contact 120 . The source/drain capping layer 124 may have a top surface that is aligned or coplanar with the top surface of the lower etch stop layer 108 . The upper source/drain contact 137 can pass through the upper ILD layer 128 and the source/drain capping layer 124 to reach the lower source/drain contact 120 . The gate electrode contact 139 may pass through the upper ILD layer 128 and the gate capping layer 116, and reach the gate electrode 104 . The body contact 141 can pass through the gate capping layer 116 and the source/drain capping layer 124 and electrically couple the gate electrode 104 and the lower source/drain contact 120 .

3A-3G are a series of cross-sectional views and flow diagrams illustrating some embodiments of methods of forming integrated circuits with contact covering layers. As shown in action 152 of FIG. 3A and FIG. 3G , in some embodiments, a first lower contact structure 142 a is formed on the substrate 102 . The first lower contact structure 142a can be a device feature or a mid-line contact feature, such as the gate electrode 104 or the lower source/drain contact 120 shown in the above figures. The lower etch stop layer 108 and the lower interlayer dielectric layer 110 can be formed lining the upper surface of the substrate 102 and the sidewalls of the first lower contact structure 142a before or after the formation of the first lower contact structure 142a.

As shown in action 154 of FIGS. 3B and 3G , in some embodiments, the first lower contact structure 142a is recessed. Then, a first contact capping precursor layer 114a' is formed on the concave upper surface of the first lower contact structure 142a. The first contact capping precursor layer 114a' may comprise a different semiconductor or dielectric material than the underlying ILD layer 110. The first contact capping precursor layer 114a' can be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

As shown in action 156 of FIGS. 3C and 3G , in some embodiments, a second lower contact structure 142b is formed next to the first lower contact structure 142a provided with the first contact capping precursor layer 114a'. In some embodiments, the lower interlayer dielectric layer 110 and the lower interlayer dielectric layer 110 are partially or completely removed by using the first contact capping precursor layer 114a' as a mask and protection layer. Lateral portions of stop layer 108 are etched beneath layer 110 to form openings. The lower ILD layer 110 may be removed by an etch process that is selective to the lower ILD layer 110 compared to the lower etch stop layer 108 and the first contact capping precursor layer 114a'. During the removal of the lower ILD layer 110, the first contact capping precursor layer 114a' protects the first lower contact structure 142a from being exposed. Then, the opening of the second lower contact structure 142 b between the vertical portions of the lower etch stop layer 108 is filled. The second lower contact structure 142b can be a mid-line contact feature or a device feature, such as the source/drain contact 120 or the gate electrode 104 in the above figure.

As shown in FIG. 3D and act 158 of FIG. 3G, in some embodiments, the first contact capping precursor is replaced with the first contact capping layer 114a having a dielectric constant less than the dielectric constant of the first contact capping precursor layer 114a'. Layer 114a'. For example, the first contact capping layer 114a may include or consist of a low-κ dielectric material with a dielectric constant less than 3.9. Thereby, the parasitic capacitance associated with the first contact capping layer 114a can be reduced compared to using the first contact capping precursor layer 114a'.

3E and FIG. 3G as shown in action 160, instead of embodiments where the second lower contact structure 142b has a plane aligned or coplanar with the top surface of the lower etch stop layer 108, in some embodiments, the recessed second The lower contact structure 142b goes under the top of the lower etch stop layer 108 . Then, a second contact capping layer 114b is formed on the concave upper surface of the second lower contact structure 142b. The second contact capping layer 114b protects the underlying second lower contact structure 142b during subsequent manufacturing steps, for example preventing leakage currents caused by the fabrication of the upper contact structure on the second lower contact structure 142b. give an example For example, the second contact capping layer 114b may include or consist of silicon nitride, silicon carbide, combinations thereof, or the like. In some alternative embodiments, the second contact capping layer 114b may be replaced by a dielectric material with a lower dielectric constant, such as a low-κ dielectric material with a dielectric constant less than 3. Thereby, the parasitic capacitance related to the second contact covering layer 114b can be reduced.

As shown in action 162 of FIG. 3F and FIG. 3G , in some embodiments, a first upper contact structure 144a may be formed through the first contact capping layer 114a and onto the first lower contact structure 142a. A second upper contact structure 144b may be formed through the second contact capping layer 114b and onto the second lower contact structure 142b.

4-17 show cross-sectional views 400-1700 of some embodiments of a method of forming an integrated circuit with a contact covering layer. Although FIGS. 4-17 are described with respect to one approach, it will be understood that the structures disclosed in FIGS. 4-17 are not limited to such an approach, but may exist independently of structures unrelated to this approach.

As shown in FIGS. 4 and 5 , the transistor structure 101 is formed on a substrate 102 and surrounded by a lower interlayer dielectric layer 110 . The transistor structure 101 has a gate dielectric layer 105 on a substrate 102, a gate electrode 104 on the gate dielectric layer 105, and a gate electrode 104 in the substrate 102 on opposite sides of the gate electrode 104. A pair of source/drain regions 103 (see FIG. 5 ). The gate electrode 104 can be a polysilicon gate or a metal gate. The gate dielectric layer 105 may comprise or consist of a silicon dioxide layer or a high kappa dielectric material such as hafnium dioxide with a dielectric constant greater than 7.

In some embodiments, a gate replacement process can be used to form Transistor structure 101. As shown in FIG. 4 , firstly, a dummy gate 404 is formed and patterned on a substrate. The sidewall spacer 106 is formed beside the dummy gate 404 to line or cover the sidewall of the dummy gate 404 . A pair of source/drain electrodes 103 are formed on opposite sides of the sidewall spacers 106 in the substrate 102 . In various embodiments, the sidewall spacers 106 comprise silicon dioxide, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, combinations thereof, or other suitable dielectric materials. In some embodiments, the sidewall spacer 106 may comprise multiple layers, such as a main spacer, a liner layer, and the like. For example, sidewall spacers 106 may be formed to have a top surface that is substantially coplanar with the top surface of dummy gate 404 by depositing a dielectric material over dummy gate 404 and etching back the dielectric material perpendicularly.

As shown in FIG. 5 , a dielectric layer is deposited on the transistor structure 101 , and then a planarization process is performed to form a lower interlayer dielectric layer 110 . In some embodiments, before forming the lower interlayer dielectric layer 110 , a lower etch stop layer 108 is formed to line the upper surface of the substrate and extend upward along the sidewall spacers 106 . The lower etch stop layer 108 can be formed by a deposition process, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). The lower ILD layer 110 may be deposited by a sub-atmospheric chemical vapor deposition (SACVD) process, flowable chemical vapor deposition, or other suitable deposition techniques. The lower etch stop layer 108 and the dielectric layer may be planarized to have top surfaces substantially coplanar with top surfaces of the sidewall spacers 106 by a chemical mechanical planarization (CMP) process. For example, the dielectric layer forming the lower interlayer dielectric layer 110 may include, for example, tetraethoxysilane (TEOS) oxide, undoped silicon glass, or doped silicon dioxide, such as borophosphosilicate glass ( BPSG), Fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silica glass (BSG) materials, and/or other suitable dielectric materials. For example, the lower interlayer dielectric layer 110 has a thickness of about 40 nm to about 80 nm.

Regarding the gate replacement process, the dummy gate 404 in FIG. 4 can be removed and replaced with a gate electrode 104 made of metal. After the dummy gate 404 is removed, the gate dielectric layer 105 may also be formed. A stack of metal material may be filled in the gate opening, and then the excess portion on the lower ILD layer 110 is removed by a planarization process to form the gate electrode 104 . Depending on the device, the stack of metal materials may include or consist of titanium nitride, tantalum nitride, titanium aluminum, and aluminum. Other materials can also be used for the gate electrode 104 .

As shown in FIG. 6 , in some embodiments, the gate electrode 104 is recessed. For example, a patterning process is firstly performed to form the mask layer 112 on the lower interlayer dielectric layer 110 , leaving the gate electrode exposed. Then, an etching process is performed on the gate electrode 104 to lower the top surface of the gate electrode 104 to a position lower than the top surface of the lower interlayer dielectric layer. Alternatively, the etch process can be highly selective to the gate electrode 104 without using a mask layer. In some embodiments, the etching process includes anisotropic etching such as vertical dry etching, and as shown in the figure, the recessed top surface of the gate electrode 104 is substantially flat. In some alternative embodiments, the etching process includes isotropic etching such as wet etching, although not shown in the drawings, the concave top surface of the gate electrode 104 may be concave in shape. In some embodiments, the sidewall spacers 106 may be lowered together with the gate electrode 104 . Depending on the selectivity of the etchant, the sidewall spacers 106 can be altered to have For example, it is lower than, equal to, or higher than the top surface of the gate electrode 104 , as shown in FIGS. 1A to 1E . The gate electrode recess process can expose the sidewall above the lower etch stop layer 108 . This etching process controls the thickness of the gate electrode 104 and thus tunes the effective work function of the gate electrode 104 to a desired value.

As shown in FIG. 7 , in some embodiments, a gate capping precursor layer 116' is formed on the recessed gate electrode 104 to serve as a protective layer to protect the gate electrode 104 from subsequent process steps. In some embodiments, gate capping precursor layer 116' may be deposited and then planarized to be aligned or coplanar with the top surface of lower ILD layer 110 and/or lower etch stop layer 108. The gate capping precursor layer 116' may include or consist of silicon or silicon nitride or metal oxides.

As shown in FIG. 8 , an opening 118 is formed through the lower ILD layer 110 and the underlying etch stop layer 108 below the lower ILD layer 110 . In some examples, openings 118 provide access to source/drain regions 103, and/or body contact regions. For example, opening 118 may be formed by a suitable combination of lithographic patterning and etching (eg, wet or dry etching) processes.

As shown in FIG. 9 , in some embodiments, a lower source/drain contact 120 is filled in the opening 118 and formed on the source/drain region 103 . In some embodiments, the self-aligned lower source/drain contact 120 can be formed by completely removing the lower ILD layer 110, and thus the lower source/drain contact 120 can directly contact the lower etch stop layer. 108 side walls. The gate capping precursor layer 116' covers and protects the gate electrode 104 during the formation of the opening 118 and the lower source/drain contact 120. In some examples, the lower source/drain contacts 120 may comprise cobalt, or other suitable materials such as tungsten, Copper, ruthenium, aluminum, rhodium, molybdenum, tantalum, titanium. Lower source/drain contacts 120 may also include an adhesive or a barrier layer to aid in bonding and/or prevent diffusion. Following deposition of the lower source/drain contacts 120, a chemical mechanical planarization (CMP) process may be performed to remove excess material from the lower source/drain contacts 120 and planarize the top surface of the workpiece. A metallization process can be performed before forming the lower source/drain contact 120 to form a semiconductor metal compound film (such as silicide, germanide, germanium silicide) on the lower source/drain contact 120 and the source/drain The interface of the exposed portion of the upper surface of region 103 thus provides a low resistance contact.

As shown in FIG. 10, in some embodiments, the gate capping precursor layer 116' is removed and replaced with a gate capping layer 116 with a lower dielectric constant, thereby reducing parasitic capacitance. The gate capping layer 116 may comprise silicon dioxide or a low-κ dielectric material with a dielectric constant less than 3.9. For example, the gate capping layer 116 may comprise a carbon-doped oxide composed of silicon, carbon, oxygen, and hydrogen (silicon oxycarbon hydroxide (SiCOH), low hydrogen silicon oxycarbide (SiOCN), carbon Silicon oxide (SiOC), or other suitable low-κ dielectric materials.

As shown in FIG. 11 , in some embodiments, the lower source/drain contact 120 is recessed, and thus an opening 122 is formed in the upper portion of the lower etch stop layer 108 . An etch process is performed on the lower source/drain contact 120 to lower the top surface of the lower source/drain contact 120 below the top surface of the lower etch stop layer 108 . In some embodiments, the etching process includes anisotropic etching such as vertical dry etching, and as shown in the drawings, the recessed top surface of the lower source/drain contact 120 is substantially planar. In some alternative embodiments, the etch process includes an isotropic etch such as a wet etch, although not shown in the drawings, the recessing of the lower source/drain contacts 120 The top surface may be concave in shape.

As shown in FIG. 12 , a source/drain capping layer 124 is formed to fill the opening 122 in the portion above the lower source/drain contact 120 . In some embodiments, the source/drain capping layer 124 may be formed by depositing a dielectric material followed by a chemical mechanical planarization process. The source/drain capping layer 124 may have a top surface that is aligned or coplanar with the top surfaces of the gate capping layer 116 and/or the lower etch stop layer 108 . The source/drain capping layer 124 provides protection and isolation for the lower source/drain contact 120 .

As shown in FIG. 13 , an upper etch stop layer 126 is formed on the gate capping layer 116 , and an upper interlayer dielectric layer 128 is formed on the upper etch stop layer 126 . For example, the upper etch stop layer 126 may include or consist of aluminum oxide, silicon nitride, or zirconium oxide. Other suitable dielectric materials can also be used to etch the stop layer 126 thereon. In some embodiments, the upper interlayer dielectric layer 128 may comprise a material such as tetraethoxysilane (TEOS) oxide, undoped silicon glass, or doped silicon dioxide such as borophosphosilicate glass (BPSG ), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and/or other suitable dielectric materials. Therefore, in some examples, the upper ILD layer 128 may be substantially the same as the lower ILD layer 110 . In various embodiments, through a sub-atmospheric chemical vapor deposition (SACVD) process, a flowable chemical vapor deposition process, an atomic layer deposition process, a plasma enhanced chemical vapor deposition process, or other suitable deposition techniques, The upper etch stop layer 126 and the upper interlayer dielectric layer 128 are deposited. In some examples, upper etch stop layer 126 has a thickness of about 5 nm to about 20 nm, and upper interlayer dielectric layer 128 has a thickness of about 20 nm to about 40 nm. Spend.

As shown in FIGS. 14-16 , a plurality of openings 130 , 132 , 134 , and 136 are formed to reach the gate capping layer 116 or the source/drain capping layer 124 , and then fill the openings with a core metal material. In some embodiments, the core metal material can be tungsten, cobalt, ruthenium, titanium nitride, tantalum nitride, or other suitable metals. These openings 130 , 132 , 134 , and 136 may be formed individually or in some combination in any order, and may all be formed before simultaneously filling the core metal material. The height of the under-recessed source/drain contact 120 and the recessed gate electrode 104, and the thickness of the gate capping layer 116 and the source/drain capping layer 124 can be varied according to subsequent manufacturing steps. For example, as shown, the lower source/drain contact 120 can be less recessed than the gate electrode 104, and the source/drain capping layer 124 can be formed thinner than the gate capping layer 116 so that when formed The openings 134 and 136 can better protect the gate electrode 104 when passing through the source/drain capping layer 124 . Alternatively, if the openings 134 and 136 are formed first, although not shown, the lower source/drain contact 120 can be much recessed and lower than the gate electrode 104 so that when the openings are formed The source/drain regions 103 are better protected when 130 and 132 pass through the gate capping layer 116 . The openings 130 , 132 , 134 , and 136 can be respectively formed through a multi-step etching process to improve etching selectivity and provide overetching control.

For example, referring to FIG. 14 , openings 130 and 132 as a first pattern can be formed by performing a first etch with a high etch rate on the upper ILD layer 128 and stopping at the upper etch stop layer 126 . Then, a second etch is performed to slowly etch the upper etch stop layer 126 and the gate The capping layer 116, and thus the gate electrode 104 is exposed with a suitable overetch. Alternatively, the opening 130 may be formed by performing a first etch with a higher etch rate on the upper ILD layer 128 and upper etch stop layer and stopping at the gate capping layer 116 . Then, a second etch is performed to etch through the gate capping layer 116 and thus expose the gate electrode 104 . Openings 130 and 132 may also be formed by a suitable combination of lithographic patterning and etching (eg, wet or dry etching) processes.

Similarly, referring to FIG. 15 , the openings 134 and 136 as the second pattern can be formed by performing a first etch with a high etch rate on the upper interlayer dielectric layer 128 and stopping at the upper etch stop layer 126 . Then, a second etch is performed to slowly etch the upper etch stop layer 126 and the source/drain capping layer 124 and thus expose the lower source/drain contact 120 with a suitable overetch. Openings 134 and 136 may also be formed by a suitable combination of lithographic patterning and etching (eg, wet or dry etching) processes.

As shown in FIG. 16 , openings 132 and 136 are combined by etching through upper ILD layer 128 and upper etch stop layer 126 between openings 132 and 136 to form a third pattern. In some embodiments, the patterning process (for example, for the fabrication of the plurality of openings) may include a multi-step etching process to individually etch the upper interlayer dielectric layer 128 and the upper etch stop layer 126, so as to improve the etch selectivity and Provides overetch control.

As shown in FIG. 17 , one or more metal layers are formed in the openings 130 , 132 , 134 , and 136 . In some examples, body contact 141 provides direct contact between gate electrode 104 and adjacent source, drain, and/or body regions. The upper source/drain contact 137 passes through the lower source/drain contact 120 provides access to source/drain regions in substrate 102 and gate electrode contact 139 provides access to gate electrode 104 . As discussed above, the source/drain capping layer 124 isolates and protects the lower source/drain contact 120 . Gate capping layer 116 isolates and protects gate electrode 104 . By arranging gate capping layer 116, upper etch stop layer 126, source/drain capping layer 124 on lower source/drain contact 120, and gate capping layer on gate electrode 104 as disclosed Layer 116 can integrate the fabrication process of upper source/drain contacts 137 with the formation of gate electrode contacts 139 and body contacts 141 . In some embodiments, the fabrication of the metal layer includes forming the metal core 138 and the barrier layer not shown in the figure through a deposition process.

18 is a flowchart illustrating some embodiments of a method of forming an integrated wafer with an interconnect structure of an intermixing barrier layer.

Where method 1800 is illustrated or described below as a series of acts or events, it is to be understood that the order in which these acts or events are depicted is not limiting. For example, some acts may be in different order and/or concurrently with other acts or events than those shown and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or implementations described herein. Additionally, one or more actions described herein may be performed in one or more individual actions and/or stages.

In act 1802, a transistor structure is formed and surrounded by a lower ILD layer. The transistor structure includes a gate electrode formed on a substrate and a pair of source/drain regions disposed on opposite sides of the gate electrode. A sidewall spacer is formed beside the gate electrode and lining or covering the sidewall of the gate electrode. In some embodiments, a first etch stop layer is formed lining the upper surface of the source/drain region, and extend along the gate electrode. The gate electrode can be formed by a gate replacement process that removes the gate precursor and replaces the gate precursor with a high-κ dielectric material and metal gate material. 4 and 5 illustrate cross-sectional views 400 and 500 of some implementations corresponding to act 1802 .

In act 1804, in some embodiments, the gate electrode is recessed, and a gate capping precursor layer is formed on the recessed upper surface of the gate electrode. In some embodiments, the gate capping precursor layer includes or consists of silicon, silicon nitride, or metal oxides. 6 and 7 illustrate cross-sectional views 600 and 700 of some implementations corresponding to act 1804 .

In act 1806, lower source/drain contacts are formed onto the source/drain regions of the transistor structure in the substrate. In some embodiments, the opening is formed by partially or completely removing the lower etch stop layer when a gate capping precursor layer is provided. A conductive material is then filled into the opening as a lower source/drain contact. The gate capping precursor layer protects the underlying gate electrode from being exposed during fabrication of the lower source/drain contacts. 8 and 9 illustrate cross-sectional views 800 and 900 of some implementations corresponding to act 1806 .

In act 1808, in some embodiments, the gate capping precursor layer is replaced with a gate capping layer having a lower dielectric constant. In some embodiments, the gate capping layer comprises or consists of silicon dioxide or a low-κ dielectric material with a dielectric constant less than 3.9. Therefore, the parasitic capacitance related to the gate cover layer can be reduced, thereby improving device performance. FIG. 10 illustrates a cross-sectional view 1000 of some implementations corresponding to act 1808 .

In act 1810, in some embodiments, the source may be recessed and forming a source/drain capping layer on the lower source/drain contact to fill the opening in the portion above the lower etch stop layer. In some embodiments, the source/drain capping layer can be formed by depositing a dielectric material followed by a chemical mechanical planarization process. 11 and 12 illustrate cross-sectional views 1100 and 1200 of some embodiments corresponding to act 1810 .

In act 1812, an upper ILD layer is formed on the gate capping layer and the source/drain capping layer. The upper etch stop layer can be formed before the formation of the upper ILD layer. FIG. 13 illustrates a cross-sectional view 1300 of some implementations corresponding to act 1812 .

In action 1814, a plurality of openings are formed through the upper ILD layer and the upper etch stop layer, and further through the gate capping layer and the source/drain capping layer to expose the gate electrode and the lower source/drain capping layer. drain contact. These openings are then filled with a metal material to form contacts for gate electrodes, source/drain regions, body contact regions, and/or other device features. In some embodiments, the metal material includes tungsten, cobalt, ruthenium, titanium nitride, tantalum nitride, or other suitable materials. 14-17 illustrate cross-sectional views 1400-1700 of some implementations corresponding to act 1814 .

Accordingly, the present disclosure relates to a novel integrated circuit device comprising a gate capping layer on a recessed gate electrode, a source/drain capping layer on a recessed source/drain contact, or Both to protect and prevent leakage current. The gate capping layer and/or the source/drain capping layer may comprise a dielectric material with a relatively small dielectric constant (eg, a low-κ dielectric material with a dielectric constant less than 3.9), thereby minimizing parasitic capacitance.

Accordingly, in some embodiments, the present disclosure relates to an integrated circuit components. The transistor structure is disposed on the substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower interlayer dielectric (ILD) layer is disposed on the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from the top of the lower interlayer dielectric layer. The gate covering layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with the top surface of the underlying interlayer dielectric layer.

According to some embodiments, the gate capping layer includes a low-κ dielectric material. According to some embodiments, the integrated circuit device further includes an upper interlayer dielectric layer disposed on the gate capping layer and the lower interlayer dielectric layer, and a gate electrode contact is disposed in the upper interlayer dielectric layer and the gate capping layer, and reach the gate electrode. According to some embodiments, the integrated circuit device further includes a lower source/drain contact on the source/drain region of the pair of source/drain regions, a source/drain capping layer on the lower source/drain region. The drain contact, and the upper source/drain contact penetrate through the interlayer dielectric layer and the source/drain capping layer, and reach the lower source/drain contact. According to some embodiments, the source/drain capping layer includes silicon carbide or silicon nitride. According to some embodiments, the gate capping layer and the source/drain capping layer have top surfaces aligned with each other. According to some embodiments, the integrated circuit device further includes a lower etch stop layer lining sidewalls of the lower ILD layer, wherein the lower etch stop layer contacts sidewalls of the lower source/drain contacts. According to some embodiments, the lower etch stop layer has a top surface aligned with a top surface of the gate capping layer and a top surface of the source/drain capping layer. According to some embodiments, the integrated circuit device further includes an upper etch stop layer disposed between the upper interlayer dielectric layer and the lower interlayer dielectric layer, wherein the bottom surface of the upper etch stop layer and the gate capping layer and the source/drain capping layer contact. According to some embodiments, the integrated circuit component further includes body contacts, the body contacts comprising It includes a first part and a second part, wherein the first part penetrates the upper interlayer dielectric layer and the gate capping layer, and wherein the second part penetrates the upper interlayer dielectric layer and the source/drain capping layer.

In other embodiments, the disclosure relates to an integrated circuit device. The transistor structure is disposed on the substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. The gate covering layer is disposed on the gate electrode. The lower etch stop layer lines the sidewalls of the gate electrode and the gate capping layer. A lower source/drain contact is provided on the opposite side of the etch stop layer below the gate electrode and reaches on the first source/drain region of the pair of source/drain regions.

According to some embodiments, the integrated circuit device further includes a source/drain cap layer disposed on the lower source/drain contact. According to some embodiments, the integrated circuit device further includes an upper interlayer dielectric layer disposed on the gate capping layer, the lower etch stop layer, and the source/drain capping layer. According to some embodiments, the integrated circuit device further includes an upper source/drain contact penetrating through the upper interlayer dielectric layer and the source/drain capping layer, and reaching on the lower source/drain contact. According to some embodiments, the integrated circuit device further includes a gate electrode contact penetrating through the upper interlayer dielectric layer and the gate capping layer, and reaching on the gate electrode. According to some embodiments, the integrated circuit device further includes a body contact, the body contact includes a first portion and a second portion, wherein the first portion penetrates the upper interlayer dielectric layer and the gate capping layer, and wherein the second portion penetrates between the In the upper interlayer dielectric layer and the source/drain capping layer. According to some embodiments, the integrated circuit device further includes a sidewall spacer disposed between the gate electrode and the lower etch stop layer. According to some embodiments, the integrated circuit device further includes an upper etch stop layer disposed on the gate capping layer, the lower etch stop layer, and the sidewall spacers.

In still other embodiments, the present disclosure relates to a method of forming an integrated circuit device. The method comprises forming a transistor structure on a substrate, the transistor structure comprising a pair of source/drain regions and a gate electrode between the pair of source/drain regions; A dielectric (ILD) layer is on the pair of source/drain regions and surrounds the gate electrode. The method further includes recessing the gate electrode, forming a gate capping precursor layer on the recessed gate electrode, and forming a lower source/drain contact to one source/drain of the pair of source/drain regions on the polar region. The method further includes replacing the gate capping precursor layer with a gate capping layer having a dielectric constant less than that of the gate capping precursor layer; and forming an upper interlayer dielectric layer on a lower interlayer dielectric layer with gate overlay on. The method further includes forming a gate contact through the upper ILD layer and the gate capping layer and onto the gate electrode.

According to some embodiments, the method of forming an integrated circuit device further includes forming a source/drain capping layer on the lower source/drain contact and forming an upper source/drain contact before forming the upper interlayer dielectric layer Pass through the upper ILD layer and the source/drain capping layer, and reach the lower source/drain contact.

The foregoing disclosure summarizes features of several embodiments, so those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis to design or modify other processes and structures to achieve the same objectives and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also understand that this equal structure does not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and changes herein without departing from the spirit and scope of the present disclosure.

102: Substrate

103: source/drain region

104: gate electrode

106: side wall spacer

108: lower etch stop layer

116:Gate cover layer

120: Lower source/drain contact

124: Source/drain cover layer

126: upper etch stop layer

128: upper interlayer dielectric layer

137: Upper source/drain contact

139: Gate electrode contact

141: body contact

Claims (10)

An integrated circuit element, comprising: a transistor structure disposed on a substrate, and comprising a pair of source/drain regions and a gate electrode located between the pair of source/drain regions; a dielectric (ILD) layer disposed on the pair of source/drain regions and surrounding the gate electrode recessed from the top of the lower interlayer dielectric layer; and a gate capping layer, On the gate electrode; wherein the gate capping layer has a top surface aligned with a top surface of the lower interlayer dielectric layer, and wherein the gate capping layer comprises a low-κ dielectric material. The integrated circuit device as claimed in claim 1, wherein the low-κ dielectric material has a dielectric constant less than 3. The integrated circuit device as described in claim 1, further comprising: an upper interlayer dielectric layer disposed on the gate cover layer and the lower interlayer dielectric layer; and a gate electrode contact penetrated on the upper interlayer dielectric layer The interlayer dielectric layer is in contact with the gate capping layer and reaches on the gate electrode. The integrated circuit device as claimed in claim 3, further comprising: a source/drain contact disposed on one of the pair of source/drain regions; a source/drain overlay layer disposed on the lower source/drain contact; and An upper source/drain contact passes through the upper interlayer dielectric layer and the source/drain capping layer, and reaches the lower source/drain contact. The integrated circuit device as claimed in claim 4, further comprising: a body contact including a first portion and a second portion, wherein the first portion penetrates the upper interlayer dielectric layer and the gate capping layer, And wherein the second portion penetrates the upper interlayer dielectric layer and the source/drain capping layer. An integrated circuit device, comprising: a transistor structure disposed on a substrate, and comprising a pair of source/drain regions and a gate electrode located between the pair of source/drain regions; a gate an electrode capping layer disposed on the gate electrode; a lower etch stop layer lining the gate electrode and a plurality of sidewalls of the gate capping layer; and a lower source/drain contact disposed opposite the gate electrode One side of the lower etch stop layer of the electrode reaches on one of the source/drain regions of the pair of source/drain regions. The integrated circuit device as claimed in claim 6, further comprising a source/drain capping layer disposed on the lower source/drain contact. The integrated circuit device as described in claim 7, further comprising an upper interlayer dielectric layer disposed on the gate capping layer, the lower etch stop layer, and and on the source/drain capping layer. A method of manufacturing an integrated circuit device, comprising: forming a transistor structure on a substrate, the transistor structure including a pair of source/drain regions and a gate between the pair of source/drain regions electrode electrode; forming an etch stop layer and an interlayer dielectric (ILD) layer on the pair of source/drain regions and surrounding the gate electrode; recessing the gate electrode and forming a gate covering precursor layer on the recessed gate electrode; form a source/drain contact on one of the pair of source/drain regions; replace the gate capping precursor with a gate capping layer an object layer, the gate capping layer having a dielectric constant less than that of the gate capping precursor layer; forming an upper interlayer dielectric layer on the lower interlayer dielectric layer and the gate capping layer; and A gate contact is formed through the upper ILD layer and the gate capping layer and onto the gate electrode. The method as claimed in claim 9, further comprising: before forming the upper interlayer dielectric layer, forming a source/drain capping layer on the lower source/drain contact; and forming an upper source/drain A pole contact passes through the upper ILD layer and the source/drain capping layer and onto the lower source/drain contact.

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